Jacob Lifshay b4650f1bff WIP adding extern modules to simulator		2025-03-19 20:48:21 -07:00
..
sim/expected	WIP adding extern modules to simulator	2025-03-19 20:48:21 -07:00
ui	support #[hdl] type aliases	2024-10-30 20:47:10 -07:00
formal.rs	add module exercising formal verification of memories	2024-12-08 17:13:26 -03:00
hdl_types.rs	support #[hdl] type aliases	2024-10-30 20:47:10 -07:00
module.rs	add #[hdl(cmp_eq)] to implement HdlPartialEq automatically	2025-02-16 20:48:16 -08:00
sim.rs	sim: fix "label address not set" bug when the last Assignment is conditional	2025-01-15 19:04:40 -08:00
ui.rs	initial public commit	2024-06-10 23:09:13 -07:00