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connect_const.txt
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sim: simple memory test works!
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2024-12-12 19:47:57 -08:00 |
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connect_const_reset.txt
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sim: simple memory test works!
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2024-12-12 19:47:57 -08:00 |
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connect_const_reset.vcd
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tests/sim: split expected output text into separate files
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2024-12-05 18:17:13 -08:00 |
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counter_async.txt
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sim: simple memory test works!
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2024-12-12 19:47:57 -08:00 |
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counter_async.vcd
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tests/sim: split expected output text into separate files
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2024-12-05 18:17:13 -08:00 |
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counter_sync.txt
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sim: simple memory test works!
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2024-12-12 19:47:57 -08:00 |
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counter_sync.vcd
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tests/sim: split expected output text into separate files
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2024-12-05 18:17:13 -08:00 |
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enums.txt
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sim: add SimValue and reading/writing more than just a scalar
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2024-12-18 01:39:35 -08:00 |
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enums.vcd
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sim: add SimValue and reading/writing more than just a scalar
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2024-12-18 01:39:35 -08:00 |
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memories.txt
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sim: simple memory test works!
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2024-12-12 19:47:57 -08:00 |
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memories.vcd
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sim: simple memory test works!
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2024-12-12 19:47:57 -08:00 |
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memories2.txt
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tests/sim: add test for memory rw port
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2024-12-12 20:50:41 -08:00 |
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memories2.vcd
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tests/sim: add test for memory rw port
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2024-12-12 20:50:41 -08:00 |
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memories3.txt
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add more memory tests
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2024-12-13 15:04:48 -08:00 |
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memories3.vcd
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add more memory tests
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2024-12-13 15:04:48 -08:00 |
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mod1.txt
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sim: simple memory test works!
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2024-12-12 19:47:57 -08:00 |
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mod1.vcd
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tests/sim: split expected output text into separate files
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2024-12-05 18:17:13 -08:00 |
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shift_register.txt
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sim: simple memory test works!
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2024-12-12 19:47:57 -08:00 |
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shift_register.vcd
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tests/sim: split expected output text into separate files
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2024-12-05 18:17:13 -08:00 |
