History

Jacob Lifshay 9128a84284 Merge remote-tracking branch 'origin/master' into adding-simulator		2024-11-26 21:28:22 -08:00
..
examples	change register names to end in `_reg` by convention	2024-10-06 18:50:09 -07:00
src	Merge remote-tracking branch 'origin/master' into adding-simulator	2024-11-26 21:28:22 -08:00
tests	writing VCD for combinatorial circuits works!	2024-11-20 22:53:54 -08:00
build.rs	WIP: use HdlOption[the_type_var] or UInt[123 + n] for creating types	2024-08-21 22:27:21 -07:00
Cargo.toml	simulator WIP: use petgraph for topological sort over assignments	2024-11-20 22:53:54 -08:00
LICENSE.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
Notices.txt	prep for eventual publishing	2024-07-11 22:39:00 -07:00
README.md	prep for eventual publishing	2024-07-11 22:39:00 -07:00
visit_types.json	make ClockDomain and Reg generic over reset type	2024-11-26 20:47:03 -08:00

README.md

Fayalite

Fayalite is a library for designing digital hardware -- a hardware description language (HDL) embedded in the Rust programming language. Fayalite's semantics are based on FIRRTL as interpreted by LLVM CIRCT.