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fayalite/crates/fayalite/tests/sim/expected
2026-04-30 19:12:20 -07:00
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array_rw.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
array_rw.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
conditional_assignment_last.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
conditional_assignment_last.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
connect_const.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
connect_const_reset.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
connect_const_reset.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
counter_async.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
counter_async.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
counter_sync.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
counter_sync.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
duplicate_names.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
duplicate_names.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
enums.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
enums.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
extern_module.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
extern_module.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
extern_module2.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
extern_module2.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
last_connect.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
last_connect.vcd add test that simulator handles last-connect semantics properly 2026-03-24 23:29:30 -07:00
many_memories.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
many_memories.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
memories.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
memories.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
memories2.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
memories2.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
memories3.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
memories3.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
mod1.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
mod1.vcd change vcd output to have module contents under instance's name, more closely matching how it works in verilog 2026-03-26 18:21:14 -07:00
phantom_const.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
phantom_const.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
queue_1_false_false.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_1_false_false.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_1_false_true.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_1_false_true.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_1_true_false.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_1_true_false.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_1_true_true.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_1_true_true.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_2_false_false.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_2_false_false.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_2_false_true.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_2_false_true.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_2_true_false.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_2_true_false.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_2_true_true.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_2_true_true.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_3_false_false.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_3_false_false.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_3_false_true.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_3_false_true.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_3_true_false.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_3_true_false.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_3_true_true.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_3_true_true.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_4_false_false.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_4_false_false.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_4_false_true.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_4_false_true.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_4_true_false.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_4_true_false.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
queue_4_true_true.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
queue_4_true_true.vcd add simulator tests for queue() 2026-03-24 23:30:15 -07:00
ripple_counter.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
ripple_counter.vcd change vcd output to have module contents under instance's name, more closely matching how it works in verilog 2026-03-26 18:21:14 -07:00
shift_register.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
shift_register.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
sim_fork_join.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
sim_fork_join.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
sim_fork_join_scope.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
sim_fork_join_scope.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
sim_only_connects.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
sim_only_connects.vcd change vcd output to have module contents under instance's name, more closely matching how it works in verilog 2026-03-26 18:21:14 -07:00
sim_read_past.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
sim_read_past.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
sim_resettable_counter_async.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
sim_resettable_counter_async.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
sim_resettable_counter_async_immediate_reset.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
sim_resettable_counter_async_immediate_reset.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
sim_resettable_counter_sync.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
sim_resettable_counter_sync.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00
sim_resettable_counter_sync_immediate_reset.txt sim: Speed up updating traces by tracking which traces are written to 2026-04-30 19:12:20 -07:00
sim_resettable_counter_sync_immediate_reset.vcd change VCD id generation to be based on hashing the path, making them better for git diff 2026-02-23 20:05:10 -08:00