forked from libre-chip/fayalite
1694 lines
No EOL
71 KiB
Text
1694 lines
No EOL
71 KiB
Text
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 11,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Enum {
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HdlNone,
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HdlSome,
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},
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},
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SlotDebugData {
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name: "",
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ty: Enum {
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HdlNone,
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HdlSome,
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},
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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|
SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<3>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<3>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 36,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::rw.addr",
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ty: UInt<3>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::rw.en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::rw.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr",
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ty: UInt<3>,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata",
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ty: Enum {
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HdlNone,
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HdlSome(Bool),
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},
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode",
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ty: Bool,
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata",
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ty: Enum {
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HdlNone,
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HdlSome(Bool),
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},
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},
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SlotDebugData {
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name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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|
SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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|
SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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|
SlotDebugData {
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name: "",
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ty: Enum {
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HdlNone,
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HdlSome(Bool),
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},
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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|
SlotDebugData {
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name: "",
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|
ty: Enum {
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HdlNone,
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HdlSome(Bool),
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},
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},
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|
SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: ".0",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: ".1",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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|
SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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|
SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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|
SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<2>,
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},
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SlotDebugData {
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name: "",
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ty: Enum {
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HdlNone,
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HdlSome(Bool),
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},
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},
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],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 1,
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debug_data: [
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(),
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],
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layout_data: [
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MemoryData {
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array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
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data: [
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// len = 0x5
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[0x0]: 0x3,
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[0x1]: 0x3,
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[0x2]: 0x3,
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[0x3]: 0x3,
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[0x4]: 0x3,
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],
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},
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],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:13:1
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0: Copy {
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dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool },
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src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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1: SliceInt {
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dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
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src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> },
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start: 1,
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len: 1,
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},
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2: Copy {
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dest: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
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},
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3: Const {
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dest: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
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value: 0x1,
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},
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4: Copy {
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dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
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src: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
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},
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5: Copy {
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dest: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".1", ty: Bool },
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src: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
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},
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6: Copy {
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dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
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src: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".1", ty: Bool },
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},
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7: Shl {
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dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
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lhs: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
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rhs: 1,
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},
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8: Or {
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dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
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lhs: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
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rhs: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
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},
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9: CastToUInt {
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dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
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src: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
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dest_width: 2,
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},
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10: Copy {
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dest: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
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src: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
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},
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11: SliceInt {
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dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
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src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> },
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start: 0,
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len: 1,
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},
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12: Copy {
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dest: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
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},
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13: Const {
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dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
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value: 0x0,
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},
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14: Copy {
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dest: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
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src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
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},
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// at: module-XXXXXXXXXX.rs:10:1
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15: Copy {
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dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
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src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
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},
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// at: module-XXXXXXXXXX.rs:11:1
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16: BranchIfZero {
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target: 18,
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value: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:12:1
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17: Copy {
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dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
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src: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
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},
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// at: module-XXXXXXXXXX.rs:9:1
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18: Copy {
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dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool },
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src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:7:1
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19: Copy {
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dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock },
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src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.clk", ty: Clock },
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},
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// at: module-XXXXXXXXXX.rs:6:1
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20: Copy {
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dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool },
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src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.en", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:5:1
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21: Copy {
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dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> },
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src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.addr", ty: UInt<3> },
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},
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// at: module-XXXXXXXXXX.rs:3:1
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22: BranchIfSmallZero {
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target: 26,
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value: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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23: BranchIfSmallNonZero {
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target: 26,
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value: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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24: MemoryReadUInt {
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dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
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memory: StatePartIndex<Memories>(0), // (MemoryData {
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// array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
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// data: [
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// // len = 0x5
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// [0x0]: 0x0,
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// [0x1]: 0x1,
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// [0x2]: 0x0,
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// [0x3]: 0x3,
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// [0x4]: 0x0,
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// ],
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// }) (),
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addr: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
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stride: 2,
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start: 0,
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width: 2,
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},
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25: Branch {
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target: 27,
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},
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26: Const {
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dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
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value: 0x0,
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},
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27: IsNonZeroDestIsSmall {
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|
dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool },
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},
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28: CastBigToArrayIndex {
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dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
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src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> },
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},
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|
29: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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|
src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool },
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},
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|
30: IsNonZeroDestIsSmall {
|
|
dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock },
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|
},
|
|
31: AndSmall {
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|
dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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|
rhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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|
},
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|
// at: module-XXXXXXXXXX.rs:1:1
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|
32: Copy {
|
|
dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
|
src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
|
|
},
|
|
33: SliceInt {
|
|
dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
src: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
|
start: 1,
|
|
len: 1,
|
|
},
|
|
34: Copy {
|
|
dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:4:1
|
|
35: AndBigWithSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
|
|
lhs: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
|
|
rhs: 0x1,
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
36: Copy {
|
|
dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
|
src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
|
|
},
|
|
37: SliceInt {
|
|
dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
|
start: 1,
|
|
len: 1,
|
|
},
|
|
38: Copy {
|
|
dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:8:1
|
|
39: Copy {
|
|
dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata", ty: UInt<2> },
|
|
src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:4:1
|
|
40: AndBigWithSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
|
|
lhs: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
|
|
rhs: 0x1,
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:3:1
|
|
41: BranchIfSmallZero {
|
|
target: 51,
|
|
value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
42: CopySmall {
|
|
dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
|
|
src: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
|
|
},
|
|
43: CopySmall {
|
|
dest: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
44: Copy {
|
|
dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
|
|
src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
|
|
},
|
|
45: Copy {
|
|
dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool },
|
|
},
|
|
46: CopySmall {
|
|
dest: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
src: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
47: BranchIfSmallZero {
|
|
target: 51,
|
|
value: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
48: BranchIfSmallZero {
|
|
target: 51,
|
|
value: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
49: BranchIfZero {
|
|
target: 51,
|
|
value: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
50: MemoryWriteUInt {
|
|
value: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
|
|
memory: StatePartIndex<Memories>(0), // (MemoryData {
|
|
// array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
|
|
// data: [
|
|
// // len = 0x5
|
|
// [0x0]: 0x0,
|
|
// [0x1]: 0x1,
|
|
// [0x2]: 0x0,
|
|
// [0x3]: 0x3,
|
|
// [0x4]: 0x0,
|
|
// ],
|
|
// }) (),
|
|
addr: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
|
|
stride: 2,
|
|
start: 0,
|
|
width: 2,
|
|
},
|
|
51: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
52: Return,
|
|
],
|
|
..
|
|
},
|
|
pc: 52,
|
|
memory_write_log: [],
|
|
memories: StatePart {
|
|
value: [
|
|
MemoryData {
|
|
array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
|
|
data: [
|
|
// len = 0x5
|
|
[0x0]: 0x0,
|
|
[0x1]: 0x1,
|
|
[0x2]: 0x0,
|
|
[0x3]: 0x3,
|
|
[0x4]: 0x0,
|
|
],
|
|
},
|
|
],
|
|
},
|
|
small_slots: StatePart {
|
|
value: [
|
|
0,
|
|
0,
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
],
|
|
},
|
|
big_slots: StatePart {
|
|
value: [
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
1,
|
|
0,
|
|
1,
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
1,
|
|
1,
|
|
1,
|
|
],
|
|
},
|
|
},
|
|
io: Instance {
|
|
name: <simulator>::memories2,
|
|
instantiated: Module {
|
|
name: memories2,
|
|
..
|
|
},
|
|
},
|
|
uninitialized_inputs: {},
|
|
io_targets: {
|
|
Instance {
|
|
name: <simulator>::memories2,
|
|
instantiated: Module {
|
|
name: memories2,
|
|
..
|
|
},
|
|
}.rw: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<3>,
|
|
/* offset = 3 */
|
|
en: Bool,
|
|
/* offset = 4 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 5 */
|
|
rdata: UInt<2>,
|
|
/* offset = 7 */
|
|
wmode: Bool,
|
|
/* offset = 8 */
|
|
wdata: UInt<2>,
|
|
/* offset = 10 */
|
|
wmask: Bool,
|
|
},
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 7,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(memories2: memories2).memories2::rw.addr",
|
|
ty: UInt<3>,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(memories2: memories2).memories2::rw.en",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(memories2: memories2).memories2::rw.clk",
|
|
ty: Clock,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata",
|
|
ty: UInt<2>,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode",
|
|
ty: Bool,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata",
|
|
ty: UInt<2>,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask",
|
|
ty: Bool,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Bundle {
|
|
fields: [
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(0),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: UInt<3>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: UInt<3>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(1),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: Bool,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Bool,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(2),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(3),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: UInt<2>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: UInt<2>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(4),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: Bool,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Bool,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(5),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: UInt<2>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: UInt<2>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
CompiledBundleField {
|
|
offset: TypeIndex {
|
|
small_slots: StatePartIndex<SmallSlots>(0),
|
|
big_slots: StatePartIndex<BigSlots>(6),
|
|
},
|
|
ty: CompiledTypeLayout {
|
|
ty: Bool,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Bool,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
},
|
|
],
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 7 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::memories2,
|
|
instantiated: Module {
|
|
name: memories2,
|
|
..
|
|
},
|
|
}.rw.addr: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: UInt<3>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: UInt<3>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::memories2,
|
|
instantiated: Module {
|
|
name: memories2,
|
|
..
|
|
},
|
|
}.rw.clk: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::memories2,
|
|
instantiated: Module {
|
|
name: memories2,
|
|
..
|
|
},
|
|
}.rw.en: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Bool,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Bool,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::memories2,
|
|
instantiated: Module {
|
|
name: memories2,
|
|
..
|
|
},
|
|
}.rw.rdata: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: UInt<2>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: UInt<2>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::memories2,
|
|
instantiated: Module {
|
|
name: memories2,
|
|
..
|
|
},
|
|
}.rw.wdata: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: UInt<2>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: UInt<2>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::memories2,
|
|
instantiated: Module {
|
|
name: memories2,
|
|
..
|
|
},
|
|
}.rw.wmask: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Bool,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Bool,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
Instance {
|
|
name: <simulator>::memories2,
|
|
instantiated: Module {
|
|
name: memories2,
|
|
..
|
|
},
|
|
}.rw.wmode: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Bool,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "",
|
|
ty: Bool,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
|
|
},
|
|
write: None,
|
|
},
|
|
},
|
|
made_initial_step: true,
|
|
needs_settle: false,
|
|
trace_decls: TraceModule {
|
|
name: "memories2",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "rw",
|
|
child: TraceBundle {
|
|
name: "rw",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(0),
|
|
name: "addr",
|
|
ty: UInt<3>,
|
|
flow: Source,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(1),
|
|
name: "en",
|
|
flow: Source,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(2),
|
|
name: "clk",
|
|
flow: Source,
|
|
},
|
|
TraceUInt {
|
|
location: TraceScalarId(3),
|
|
name: "rdata",
|
|
ty: UInt<2>,
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(4),
|
|
name: "wmode",
|
|
flow: Source,
|
|
},
|
|
TraceUInt {
|
|
location: TraceScalarId(5),
|
|
name: "wdata",
|
|
ty: UInt<2>,
|
|
flow: Source,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(6),
|
|
name: "wmask",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<3>,
|
|
/* offset = 3 */
|
|
en: Bool,
|
|
/* offset = 4 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 5 */
|
|
rdata: UInt<2>,
|
|
/* offset = 7 */
|
|
wmode: Bool,
|
|
/* offset = 8 */
|
|
wdata: UInt<2>,
|
|
/* offset = 10 */
|
|
wmask: Bool,
|
|
},
|
|
flow: Source,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<3>,
|
|
/* offset = 3 */
|
|
en: Bool,
|
|
/* offset = 4 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 5 */
|
|
rdata: UInt<2>,
|
|
/* offset = 7 */
|
|
wmode: Bool,
|
|
/* offset = 8 */
|
|
wdata: UInt<2>,
|
|
/* offset = 10 */
|
|
wmask: Bool,
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceMem {
|
|
id: TraceMemoryId(0),
|
|
name: "mem",
|
|
stride: 2,
|
|
element_type: TraceEnumWithFields {
|
|
name: "mem",
|
|
discriminant: TraceEnumDiscriminant {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 5,
|
|
stride: 2,
|
|
start: 0,
|
|
len: 1,
|
|
},
|
|
name: "$tag",
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Duplex,
|
|
},
|
|
non_empty_fields: [
|
|
TraceBool {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 5,
|
|
stride: 2,
|
|
start: 1,
|
|
len: 1,
|
|
},
|
|
name: "HdlSome",
|
|
flow: Duplex,
|
|
},
|
|
],
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Duplex,
|
|
},
|
|
ports: [
|
|
TraceMemPort {
|
|
name: "rw0",
|
|
bundle: TraceBundle {
|
|
name: "rw0",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(7),
|
|
name: "addr",
|
|
ty: UInt<3>,
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(8),
|
|
name: "en",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(9),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceEnumWithFields {
|
|
name: "rdata",
|
|
discriminant: TraceEnumDiscriminant {
|
|
location: TraceScalarId(10),
|
|
name: "$tag",
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Source,
|
|
},
|
|
non_empty_fields: [
|
|
TraceBool {
|
|
location: TraceScalarId(11),
|
|
name: "HdlSome",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(12),
|
|
name: "wmode",
|
|
flow: Sink,
|
|
},
|
|
TraceEnumWithFields {
|
|
name: "wdata",
|
|
discriminant: TraceEnumDiscriminant {
|
|
location: TraceScalarId(13),
|
|
name: "$tag",
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Sink,
|
|
},
|
|
non_empty_fields: [
|
|
TraceBool {
|
|
location: TraceScalarId(14),
|
|
name: "HdlSome",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(15),
|
|
name: "wmask",
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<3>,
|
|
/* offset = 3 */
|
|
en: Bool,
|
|
/* offset = 4 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 5 */
|
|
rdata: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
/* offset = 7 */
|
|
wmode: Bool,
|
|
/* offset = 8 */
|
|
wdata: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
/* offset = 10 */
|
|
wmask: Bool,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<3>,
|
|
/* offset = 3 */
|
|
en: Bool,
|
|
/* offset = 4 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 5 */
|
|
rdata: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
/* offset = 7 */
|
|
wmode: Bool,
|
|
/* offset = 8 */
|
|
wdata: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
/* offset = 10 */
|
|
wmask: Bool,
|
|
},
|
|
},
|
|
],
|
|
array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
|
|
},
|
|
],
|
|
},
|
|
traces: [
|
|
SimTrace {
|
|
id: TraceScalarId(0),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(0),
|
|
ty: UInt<3>,
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(1),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(1),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(2),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(2),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(3),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(3),
|
|
ty: UInt<2>,
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(4),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(4),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(5),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(5),
|
|
ty: UInt<2>,
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(6),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(6),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(7),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(7),
|
|
ty: UInt<3>,
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(8),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(8),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(9),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(9),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(10),
|
|
kind: EnumDiscriminant {
|
|
index: StatePartIndex<SmallSlots>(0),
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(11),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(16),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(12),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(11),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(13),
|
|
kind: EnumDiscriminant {
|
|
index: StatePartIndex<SmallSlots>(1),
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(14),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(19),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(15),
|
|
kind: BigBool {
|
|
index: StatePartIndex<BigSlots>(13),
|
|
},
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
],
|
|
trace_memories: {
|
|
StatePartIndex<Memories>(0): TraceMem {
|
|
id: TraceMemoryId(0),
|
|
name: "mem",
|
|
stride: 2,
|
|
element_type: TraceEnumWithFields {
|
|
name: "mem",
|
|
discriminant: TraceEnumDiscriminant {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 5,
|
|
stride: 2,
|
|
start: 0,
|
|
len: 1,
|
|
},
|
|
name: "$tag",
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Duplex,
|
|
},
|
|
non_empty_fields: [
|
|
TraceBool {
|
|
location: TraceMemoryLocation {
|
|
id: TraceMemoryId(0),
|
|
depth: 5,
|
|
stride: 2,
|
|
start: 1,
|
|
len: 1,
|
|
},
|
|
name: "HdlSome",
|
|
flow: Duplex,
|
|
},
|
|
],
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Duplex,
|
|
},
|
|
ports: [
|
|
TraceMemPort {
|
|
name: "rw0",
|
|
bundle: TraceBundle {
|
|
name: "rw0",
|
|
fields: [
|
|
TraceUInt {
|
|
location: TraceScalarId(7),
|
|
name: "addr",
|
|
ty: UInt<3>,
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(8),
|
|
name: "en",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(9),
|
|
name: "clk",
|
|
flow: Sink,
|
|
},
|
|
TraceEnumWithFields {
|
|
name: "rdata",
|
|
discriminant: TraceEnumDiscriminant {
|
|
location: TraceScalarId(10),
|
|
name: "$tag",
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Source,
|
|
},
|
|
non_empty_fields: [
|
|
TraceBool {
|
|
location: TraceScalarId(11),
|
|
name: "HdlSome",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Source,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(12),
|
|
name: "wmode",
|
|
flow: Sink,
|
|
},
|
|
TraceEnumWithFields {
|
|
name: "wdata",
|
|
discriminant: TraceEnumDiscriminant {
|
|
location: TraceScalarId(13),
|
|
name: "$tag",
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Sink,
|
|
},
|
|
non_empty_fields: [
|
|
TraceBool {
|
|
location: TraceScalarId(14),
|
|
name: "HdlSome",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
flow: Sink,
|
|
},
|
|
TraceBool {
|
|
location: TraceScalarId(15),
|
|
name: "wmask",
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<3>,
|
|
/* offset = 3 */
|
|
en: Bool,
|
|
/* offset = 4 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 5 */
|
|
rdata: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
/* offset = 7 */
|
|
wmode: Bool,
|
|
/* offset = 8 */
|
|
wdata: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
/* offset = 10 */
|
|
wmask: Bool,
|
|
},
|
|
flow: Sink,
|
|
},
|
|
ty: Bundle {
|
|
/* offset = 0 */
|
|
addr: UInt<3>,
|
|
/* offset = 3 */
|
|
en: Bool,
|
|
/* offset = 4 */
|
|
clk: Clock,
|
|
#[hdl(flip)] /* offset = 5 */
|
|
rdata: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
/* offset = 7 */
|
|
wmode: Bool,
|
|
/* offset = 8 */
|
|
wdata: Enum {
|
|
HdlNone,
|
|
HdlSome(Bool),
|
|
},
|
|
/* offset = 10 */
|
|
wmask: Bool,
|
|
},
|
|
},
|
|
],
|
|
array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
|
|
},
|
|
},
|
|
trace_writers: [
|
|
Running(
|
|
VcdWriter {
|
|
finished_init: true,
|
|
timescale: 1 ps,
|
|
..
|
|
},
|
|
),
|
|
],
|
|
instant: 22 μs,
|
|
clocks_triggered: [
|
|
StatePartIndex<SmallSlots>(3),
|
|
],
|
|
..
|
|
} |