forked from libre-chip/fayalite
14 lines
190 B
Text
14 lines
190 B
Text
$timescale 1 ps $end
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$scope module conditional_assignment_last $end
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$var wire 1 ! i $end
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$var wire 1 " w $end
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$upscope $end
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$enddefinitions $end
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$dumpvars
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0!
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1"
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$end
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#1000000
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1!
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0"
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#2000000
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