forked from libre-chip/fayalite
46 lines
1.5 KiB
TOML
46 lines
1.5 KiB
TOML
# SPDX-License-Identifier: LGPL-3.0-or-later
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# See Notices.txt for copyright information
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[workspace]
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resolver = "2"
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members = ["crates/*"]
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[workspace.package]
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version = "0.3.0"
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license = "LGPL-3.0-or-later"
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edition = "2024"
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repository = "https://git.libre-chip.org/libre-chip/fayalite"
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keywords = ["hdl", "hardware", "semiconductors", "firrtl", "fpga"]
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categories = ["simulation", "development-tools", "compilers"]
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rust-version = "1.89.0"
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[workspace.dependencies]
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fayalite-proc-macros = { version = "=0.3.0", path = "crates/fayalite-proc-macros" }
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fayalite-proc-macros-impl = { version = "=0.3.0", path = "crates/fayalite-proc-macros-impl" }
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fayalite-visit-gen = { version = "=0.3.0", path = "crates/fayalite-visit-gen" }
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base16ct = "0.2.0"
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base64 = "0.22.1"
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bitvec = { version = "1.0.1", features = ["serde"] }
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blake3 = { version = "1.5.4", features = ["serde"] }
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clap = { version = "4.5.9", features = ["derive", "env", "string"] }
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clap_complete = "4.5.58"
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ctor = "0.2.8"
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eyre = "0.6.12"
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hashbrown = "0.15.2"
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indexmap = { version = "2.5.0", features = ["serde"] }
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jobslot = "0.2.23"
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num-bigint = "0.4.6"
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num-traits = "0.2.16"
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ordered-float = { version = "5.1.0", features = ["serde"] }
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petgraph = "0.8.1"
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prettyplease = "0.2.20"
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proc-macro2 = "1.0.83"
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quote = "1.0.36"
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serde = { version = "1.0.202", features = ["derive"] }
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serde_json = { version = "1.0.117", features = ["preserve_order"] }
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sha2 = "0.10.8"
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syn = { version = "2.0.93", features = ["full", "fold", "visit", "extra-traits"] }
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tempfile = "3.10.1"
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thiserror = "1.0.61"
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trybuild = "1.0"
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vec_map = "0.8.2"
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which = "6.0.1"
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