fayalite/crates/fayalite/tests/sim/expected/ripple_counter.vcd

$timescale 1 ps $end
$scope module ripple_counter $end
$var wire 1 ! clk $end
$var wire 6 " o $end
$scope struct bits $end
$var wire 1 # \[0] $end
$var wire 1 $ \[1] $end
$var wire 1 % \[2] $end
$var wire 1 & \[3] $end
$var wire 1 ' \[4] $end
$var wire 1 ( \[5] $end
$upscope $end
$var reg 1 ) bit_reg_0 $end
$scope struct bit_reg_1 $end
$var wire 1 , clk $end
$var wire 1 - o $end
$upscope $end
$scope module sw_reg $end
$var wire 1 * clk $end
$var wire 1 + o $end
$upscope $end
$var reg 1 . bit_reg_2 $end
$scope struct bit_reg_3 $end
$var wire 1 1 clk $end
$var wire 1 2 o $end
$upscope $end
$scope module sw_reg_2 $end
$var wire 1 / clk $end
$var wire 1 0 o $end
$upscope $end
$var reg 1 3 bit_reg_4 $end
$scope struct bit_reg_5 $end
$var wire 1 6 clk $end
$var wire 1 7 o $end
$upscope $end
$scope module sw_reg_3 $end
$var wire 1 4 clk $end
$var wire 1 5 o $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
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$end
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