Jacob Lifshay 3ed7827485 sim: WIP adding memory support		2024-12-05 21:35:23 -08:00
..
sim/expected	sim: WIP adding memory support	2024-12-05 21:35:23 -08:00
ui	support #[hdl] type aliases	2024-10-30 20:47:10 -07:00
formal.rs	Add test module exercising formal verification.	2024-11-20 18:29:39 -03:00
hdl_types.rs	support #[hdl] type aliases	2024-10-30 20:47:10 -07:00
module.rs	deduce_resets works!	2024-11-27 23:24:11 -08:00
sim.rs	tests/sim: split expected output text into separate files	2024-12-05 18:17:13 -08:00
ui.rs	initial public commit	2024-06-10 23:09:13 -07:00