forked from libre-chip/fayalite
9730 lines
No EOL
610 KiB
Text
9730 lines
No EOL
610 KiB
Text
Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartLayout<SmallSlots> {
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len: 9,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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big_slots: StatePartLayout<BigSlots> {
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len: 48,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[0]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[1]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[2]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[0]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[1]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[2]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[0]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[1]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[2]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[0]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[1]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[2]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[0]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[1]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[2]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[0]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[1]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[2]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[0]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[1]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[2]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[0]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[1]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[2]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[0]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[1]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[2]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[0]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[1]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[2]",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[0]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[1]",
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ty: UInt<8>,
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},
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SlotDebugData {
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name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]",
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ty: UInt<8>,
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},
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],
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..
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},
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sim_only_slots: StatePartLayout<SimOnlySlots> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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memories: StatePartLayout<Memories> {
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len: 0,
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debug_data: [],
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layout_data: [],
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..
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:2:1
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0: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock },
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},
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1: AndSmall {
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dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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rhs: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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},
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2: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock },
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},
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3: AndSmall {
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dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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rhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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},
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4: IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock },
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},
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5: AndSmall {
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dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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rhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
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},
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6: BranchIfSmallZero {
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target: 10,
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value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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7: Copy {
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dest: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]", ty: Clock },
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src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock },
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},
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8: Copy {
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dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]", ty: Clock },
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src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock },
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},
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9: Copy {
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dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]", ty: Clock },
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src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock },
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},
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// at: module-XXXXXXXXXX.rs:3:1
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10: BranchIfSmallZero {
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target: 14,
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value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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11: Copy {
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dest: StatePartIndex<BigSlots>(15), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[0]", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> },
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},
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12: Copy {
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dest: StatePartIndex<BigSlots>(16), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[1]", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> },
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},
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13: Copy {
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dest: StatePartIndex<BigSlots>(17), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[2]", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> },
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},
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// at: module-XXXXXXXXXX.rs:4:1
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14: BranchIfSmallZero {
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target: 18,
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value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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15: Copy {
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dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[0]", ty: Clock },
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src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock },
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},
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16: Copy {
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dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[1]", ty: Clock },
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src: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock },
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},
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17: Copy {
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dest: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[2]", ty: Clock },
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src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock },
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},
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// at: module-XXXXXXXXXX.rs:5:1
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18: BranchIfSmallZero {
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target: 22,
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value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
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},
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19: Copy {
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dest: StatePartIndex<BigSlots>(21), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[0]", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> },
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},
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20: Copy {
|
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dest: StatePartIndex<BigSlots>(22), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[1]", ty: UInt<8> },
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src: StatePartIndex<BigSlots>(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> },
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},
|
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21: Copy {
|
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dest: StatePartIndex<BigSlots>(23), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[2]", ty: UInt<8> },
|
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src: StatePartIndex<BigSlots>(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> },
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},
|
|
// at: module-XXXXXXXXXX.rs:2:1
|
|
22: BranchIfSmallZero {
|
|
target: 26,
|
|
value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
23: Copy {
|
|
dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[0]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock },
|
|
},
|
|
24: Copy {
|
|
dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[1]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock },
|
|
},
|
|
25: Copy {
|
|
dest: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[2]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:3:1
|
|
26: BranchIfSmallZero {
|
|
target: 30,
|
|
value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
27: Copy {
|
|
dest: StatePartIndex<BigSlots>(27), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[0]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> },
|
|
},
|
|
28: Copy {
|
|
dest: StatePartIndex<BigSlots>(28), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[1]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> },
|
|
},
|
|
29: Copy {
|
|
dest: StatePartIndex<BigSlots>(29), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[2]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:4:1
|
|
30: BranchIfSmallZero {
|
|
target: 34,
|
|
value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
31: Copy {
|
|
dest: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[0]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock },
|
|
},
|
|
32: Copy {
|
|
dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[1]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock },
|
|
},
|
|
33: Copy {
|
|
dest: StatePartIndex<BigSlots>(32), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[2]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:5:1
|
|
34: BranchIfSmallZero {
|
|
target: 38,
|
|
value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
35: Copy {
|
|
dest: StatePartIndex<BigSlots>(33), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[0]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> },
|
|
},
|
|
36: Copy {
|
|
dest: StatePartIndex<BigSlots>(34), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[1]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> },
|
|
},
|
|
37: Copy {
|
|
dest: StatePartIndex<BigSlots>(35), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[2]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:2:1
|
|
38: BranchIfSmallZero {
|
|
target: 42,
|
|
value: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
39: Copy {
|
|
dest: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[0]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock },
|
|
},
|
|
40: Copy {
|
|
dest: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[1]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock },
|
|
},
|
|
41: Copy {
|
|
dest: StatePartIndex<BigSlots>(38), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[2]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:3:1
|
|
42: BranchIfSmallZero {
|
|
target: 46,
|
|
value: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
43: Copy {
|
|
dest: StatePartIndex<BigSlots>(39), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[0]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> },
|
|
},
|
|
44: Copy {
|
|
dest: StatePartIndex<BigSlots>(40), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[1]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> },
|
|
},
|
|
45: Copy {
|
|
dest: StatePartIndex<BigSlots>(41), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[2]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:4:1
|
|
46: BranchIfSmallZero {
|
|
target: 50,
|
|
value: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
47: Copy {
|
|
dest: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[0]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock },
|
|
},
|
|
48: Copy {
|
|
dest: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[1]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock },
|
|
},
|
|
49: Copy {
|
|
dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[2]", ty: Clock },
|
|
src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:5:1
|
|
50: BranchIfSmallZero {
|
|
target: 54,
|
|
value: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
},
|
|
51: Copy {
|
|
dest: StatePartIndex<BigSlots>(45), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[0]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> },
|
|
},
|
|
52: Copy {
|
|
dest: StatePartIndex<BigSlots>(46), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[1]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> },
|
|
},
|
|
53: Copy {
|
|
dest: StatePartIndex<BigSlots>(47), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]", ty: UInt<8> },
|
|
src: StatePartIndex<BigSlots>(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> },
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:2:1
|
|
54: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
55: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
56: XorSmallImmediate {
|
|
dest: StatePartIndex<SmallSlots>(6), // (0x1 1) SlotDebugData { name: "", ty: Bool },
|
|
lhs: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
|
|
rhs: 0x1,
|
|
},
|
|
// at: module-XXXXXXXXXX.rs:1:1
|
|
57: Return,
|
|
],
|
|
..
|
|
},
|
|
pc: 57,
|
|
memory_write_log: [],
|
|
memories: StatePart {
|
|
value: [],
|
|
},
|
|
small_slots: StatePart {
|
|
value: [
|
|
1 (modified),
|
|
0 (modified),
|
|
0 (modified),
|
|
1 (modified),
|
|
0 (modified),
|
|
0 (modified),
|
|
1 (modified),
|
|
0 (modified),
|
|
0 (modified),
|
|
],
|
|
},
|
|
big_slots: StatePart {
|
|
value: [
|
|
0 (modified),
|
|
0,
|
|
0,
|
|
49 (modified),
|
|
50 (modified),
|
|
50 (modified),
|
|
0 (modified),
|
|
1 (modified),
|
|
0 (modified),
|
|
49 (modified),
|
|
49 (modified),
|
|
50 (modified),
|
|
1 (modified),
|
|
0 (modified),
|
|
0 (modified),
|
|
48 (modified),
|
|
49 (modified),
|
|
49 (modified),
|
|
0 (modified),
|
|
0 (modified),
|
|
1 (modified),
|
|
48 (modified),
|
|
49 (modified),
|
|
48 (modified),
|
|
0 (modified),
|
|
1 (modified),
|
|
0 (modified),
|
|
49 (modified),
|
|
49 (modified),
|
|
50 (modified),
|
|
0 (modified),
|
|
0 (modified),
|
|
1 (modified),
|
|
49 (modified),
|
|
49 (modified),
|
|
49 (modified),
|
|
0 (modified),
|
|
0 (modified),
|
|
1 (modified),
|
|
49 (modified),
|
|
50 (modified),
|
|
50 (modified),
|
|
0 (modified),
|
|
1 (modified),
|
|
0 (modified),
|
|
49 (modified),
|
|
49 (modified),
|
|
50 (modified),
|
|
],
|
|
},
|
|
sim_only_slots: StatePart {
|
|
value: [],
|
|
},
|
|
},
|
|
io: Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
},
|
|
main_module: SimulationModuleState {
|
|
base_targets: [
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.clocks,
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.outputs,
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.past_clocks,
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.past_outputs,
|
|
],
|
|
uninitialized_ios: {},
|
|
io_targets: {
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.clocks,
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.clocks[0],
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.clocks[1],
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.clocks[2],
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.outputs,
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.outputs[0],
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.outputs[1],
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.outputs[2],
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.past_clocks,
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.past_clocks[0],
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.past_clocks[1],
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.past_clocks[2],
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.past_outputs,
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.past_outputs[0],
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.past_outputs[1],
|
|
Instance {
|
|
name: <simulator>::sim_read_past,
|
|
instantiated: Module {
|
|
name: sim_read_past,
|
|
..
|
|
},
|
|
}.past_outputs[2],
|
|
},
|
|
did_initial_settle: true,
|
|
clocks_for_past: {},
|
|
},
|
|
extern_modules: [
|
|
SimulationExternModuleState {
|
|
module_state: SimulationModuleState {
|
|
base_targets: [
|
|
ModuleIO {
|
|
name: sim_read_past::clocks,
|
|
is_input: true,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::past_clocks,
|
|
is_input: false,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::past_outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
},
|
|
],
|
|
uninitialized_ios: {},
|
|
io_targets: {
|
|
ModuleIO {
|
|
name: sim_read_past::clocks,
|
|
is_input: true,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::clocks,
|
|
is_input: true,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
}[0],
|
|
ModuleIO {
|
|
name: sim_read_past::clocks,
|
|
is_input: true,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
}[1],
|
|
ModuleIO {
|
|
name: sim_read_past::clocks,
|
|
is_input: true,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
}[2],
|
|
ModuleIO {
|
|
name: sim_read_past::outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
}[0],
|
|
ModuleIO {
|
|
name: sim_read_past::outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
}[1],
|
|
ModuleIO {
|
|
name: sim_read_past::outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
}[2],
|
|
ModuleIO {
|
|
name: sim_read_past::past_clocks,
|
|
is_input: false,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::past_clocks,
|
|
is_input: false,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
}[0],
|
|
ModuleIO {
|
|
name: sim_read_past::past_clocks,
|
|
is_input: false,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
}[1],
|
|
ModuleIO {
|
|
name: sim_read_past::past_clocks,
|
|
is_input: false,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
}[2],
|
|
ModuleIO {
|
|
name: sim_read_past::past_outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::past_outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
}[0],
|
|
ModuleIO {
|
|
name: sim_read_past::past_outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
}[1],
|
|
ModuleIO {
|
|
name: sim_read_past::past_outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
}[2],
|
|
},
|
|
did_initial_settle: true,
|
|
clocks_for_past: {
|
|
CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
write: None,
|
|
}: SimulationExternModuleClockForPast {
|
|
current_to_past_map: {
|
|
CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Array<Clock, 3>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 3,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]",
|
|
ty: Clock,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]",
|
|
ty: Clock,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Array {
|
|
elements_non_empty: [
|
|
CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
],
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 3 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
write: None,
|
|
}: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Array<Clock, 3>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 3,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]",
|
|
ty: Clock,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]",
|
|
ty: Clock,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Array {
|
|
elements_non_empty: [
|
|
CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
],
|
|
},
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 12, len: 3 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
write: Some(
|
|
(
|
|
CompiledTypeLayout {
|
|
ty: Array<Clock, 3>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 3,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]",
|
|
ty: Clock,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]",
|
|
ty: Clock,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Array {
|
|
elements_non_empty: [
|
|
CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
],
|
|
},
|
|
},
|
|
TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 3 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
),
|
|
),
|
|
},
|
|
CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Array<Clock, 3>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 3,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]",
|
|
ty: Clock,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]",
|
|
ty: Clock,
|
|
},
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
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|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
write: Some(
|
|
(
|
|
CompiledTypeLayout {
|
|
ty: UInt<8>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]",
|
|
ty: UInt<8>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 10, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
),
|
|
),
|
|
},
|
|
CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: UInt<8>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]",
|
|
ty: UInt<8>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 11, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
write: None,
|
|
}: CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: UInt<8>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]",
|
|
ty: UInt<8>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 9, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 47, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
write: Some(
|
|
(
|
|
CompiledTypeLayout {
|
|
ty: UInt<8>,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]",
|
|
ty: UInt<8>,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 11, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
),
|
|
),
|
|
},
|
|
},
|
|
},
|
|
},
|
|
},
|
|
sim: ExternModuleSimulation {
|
|
generator: SimGeneratorFn {
|
|
args: (
|
|
ModuleIO {
|
|
name: sim_read_past::clocks,
|
|
is_input: true,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::past_clocks,
|
|
is_input: false,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::past_outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
},
|
|
),
|
|
f: ...,
|
|
},
|
|
sim_io_to_generator_map: {
|
|
ModuleIO {
|
|
name: sim_read_past::clocks,
|
|
is_input: true,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
}: ModuleIO {
|
|
name: sim_read_past::clocks,
|
|
is_input: true,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
}: ModuleIO {
|
|
name: sim_read_past::outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::past_clocks,
|
|
is_input: false,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
}: ModuleIO {
|
|
name: sim_read_past::past_clocks,
|
|
is_input: false,
|
|
ty: Array<Clock, 3>,
|
|
..
|
|
},
|
|
ModuleIO {
|
|
name: sim_read_past::past_outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
}: ModuleIO {
|
|
name: sim_read_past::past_outputs,
|
|
is_input: false,
|
|
ty: Array<UInt<8>, 3>,
|
|
..
|
|
},
|
|
},
|
|
source_location: SourceLocation(
|
|
module-XXXXXXXXXX.rs:6:1,
|
|
),
|
|
},
|
|
running_generator: Some(
|
|
...,
|
|
),
|
|
},
|
|
],
|
|
trace_decls: TraceModule {
|
|
name: "sim_read_past",
|
|
children: [
|
|
TraceModuleIO {
|
|
name: "clocks",
|
|
child: TraceArray {
|
|
name: "clocks",
|
|
elements: [
|
|
TraceClock {
|
|
location: TraceScalarId(0),
|
|
name: "[0]",
|
|
flow: Source,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(1),
|
|
name: "[1]",
|
|
flow: Source,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(2),
|
|
name: "[2]",
|
|
flow: Source,
|
|
},
|
|
],
|
|
ty: Array<Clock, 3>,
|
|
flow: Source,
|
|
},
|
|
ty: Array<Clock, 3>,
|
|
flow: Source,
|
|
},
|
|
TraceModuleIO {
|
|
name: "outputs",
|
|
child: TraceArray {
|
|
name: "outputs",
|
|
elements: [
|
|
TraceUInt {
|
|
location: TraceScalarId(3),
|
|
name: "[0]",
|
|
ty: UInt<8>,
|
|
flow: Sink,
|
|
},
|
|
TraceUInt {
|
|
location: TraceScalarId(4),
|
|
name: "[1]",
|
|
ty: UInt<8>,
|
|
flow: Sink,
|
|
},
|
|
TraceUInt {
|
|
location: TraceScalarId(5),
|
|
name: "[2]",
|
|
ty: UInt<8>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Array<UInt<8>, 3>,
|
|
flow: Sink,
|
|
},
|
|
ty: Array<UInt<8>, 3>,
|
|
flow: Sink,
|
|
},
|
|
TraceModuleIO {
|
|
name: "past_clocks",
|
|
child: TraceArray {
|
|
name: "past_clocks",
|
|
elements: [
|
|
TraceClock {
|
|
location: TraceScalarId(6),
|
|
name: "[0]",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(7),
|
|
name: "[1]",
|
|
flow: Sink,
|
|
},
|
|
TraceClock {
|
|
location: TraceScalarId(8),
|
|
name: "[2]",
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Array<Clock, 3>,
|
|
flow: Sink,
|
|
},
|
|
ty: Array<Clock, 3>,
|
|
flow: Sink,
|
|
},
|
|
TraceModuleIO {
|
|
name: "past_outputs",
|
|
child: TraceArray {
|
|
name: "past_outputs",
|
|
elements: [
|
|
TraceUInt {
|
|
location: TraceScalarId(9),
|
|
name: "[0]",
|
|
ty: UInt<8>,
|
|
flow: Sink,
|
|
},
|
|
TraceUInt {
|
|
location: TraceScalarId(10),
|
|
name: "[1]",
|
|
ty: UInt<8>,
|
|
flow: Sink,
|
|
},
|
|
TraceUInt {
|
|
location: TraceScalarId(11),
|
|
name: "[2]",
|
|
ty: UInt<8>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
ty: Array<UInt<8>, 3>,
|
|
flow: Sink,
|
|
},
|
|
ty: Array<UInt<8>, 3>,
|
|
flow: Sink,
|
|
},
|
|
],
|
|
},
|
|
traces: [
|
|
SimTrace {
|
|
id: TraceScalarId(0),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(0),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(1),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(1),
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(2),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(2),
|
|
},
|
|
maybe_changed: true,
|
|
state: 0x0,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(3),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(3),
|
|
ty: UInt<8>,
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x31,
|
|
last_state: 0x31,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(4),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(4),
|
|
ty: UInt<8>,
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x32,
|
|
last_state: 0x32,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(5),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(5),
|
|
ty: UInt<8>,
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x32,
|
|
last_state: 0x32,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(6),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(6),
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(7),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(7),
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x1,
|
|
last_state: 0x1,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(8),
|
|
kind: BigClock {
|
|
index: StatePartIndex<BigSlots>(8),
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x0,
|
|
last_state: 0x0,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(9),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(9),
|
|
ty: UInt<8>,
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x31,
|
|
last_state: 0x31,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(10),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(10),
|
|
ty: UInt<8>,
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x31,
|
|
last_state: 0x31,
|
|
},
|
|
SimTrace {
|
|
id: TraceScalarId(11),
|
|
kind: BigUInt {
|
|
index: StatePartIndex<BigSlots>(11),
|
|
ty: UInt<8>,
|
|
},
|
|
maybe_changed: false,
|
|
state: 0x32,
|
|
last_state: 0x32,
|
|
},
|
|
],
|
|
trace_memories: {},
|
|
trace_writers: [
|
|
Running(
|
|
VcdWriter {
|
|
finished_init: true,
|
|
timescale: 1 ps,
|
|
..
|
|
},
|
|
),
|
|
],
|
|
clocks_triggered: [
|
|
StatePartIndex<SmallSlots>(1),
|
|
StatePartIndex<SmallSlots>(4),
|
|
StatePartIndex<SmallSlots>(7),
|
|
],
|
|
event_queue: EventQueue(EventQueueData {
|
|
instant: 648 μs,
|
|
events: {},
|
|
}),
|
|
waiting_sensitivity_sets_by_address: {
|
|
SensitivitySet {
|
|
id: 198,
|
|
values: {
|
|
CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
write: None,
|
|
}: OpaqueSimValue {
|
|
bits: 0x0_u1,
|
|
sim_only_values: [],
|
|
},
|
|
},
|
|
changed: Cell {
|
|
value: false,
|
|
},
|
|
..
|
|
},
|
|
},
|
|
waiting_sensitivity_sets_by_compiled_value: {
|
|
CompiledValue {
|
|
layout: CompiledTypeLayout {
|
|
ty: Clock,
|
|
layout: TypeLayout {
|
|
small_slots: StatePartLayout<SmallSlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
..
|
|
},
|
|
big_slots: StatePartLayout<BigSlots> {
|
|
len: 1,
|
|
debug_data: [
|
|
SlotDebugData {
|
|
name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]",
|
|
ty: Clock,
|
|
},
|
|
],
|
|
..
|
|
},
|
|
sim_only_slots: StatePartLayout<SimOnlySlots> {
|
|
len: 0,
|
|
debug_data: [],
|
|
layout_data: [],
|
|
..
|
|
},
|
|
},
|
|
body: Scalar,
|
|
},
|
|
range: TypeIndexRange {
|
|
small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
|
|
big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
|
|
sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
|
|
},
|
|
write: None,
|
|
}: (
|
|
OpaqueSimValue {
|
|
bits: 0x0_u1,
|
|
sim_only_values: [],
|
|
},
|
|
{
|
|
SensitivitySet {
|
|
id: 198,
|
|
..
|
|
},
|
|
},
|
|
),
|
|
},
|
|
..
|
|
} |