Simulation { state: State { insns: Insns { state_layout: StateLayout { ty: TypeLayout { small_slots: StatePartLayout { len: 4, debug_data: [ SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, ], .. }, big_slots: StatePartLayout { len: 10, debug_data: [ SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock, }, SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset, }, SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4>, }, SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4>, }, SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4>, }, SlotDebugData { name: "", ty: UInt<4>, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: UInt<1>, }, SlotDebugData { name: "", ty: UInt<5>, }, SlotDebugData { name: "", ty: UInt<4>, }, ], .. }, sim_only_slots: StatePartLayout { len: 0, debug_data: [], .. }, }, memories: StatePartLayout { len: 0, debug_data: [], layout_data: [], .. }, }, insns: [ // at: module-XXXXXXXXXX.rs:1:1 0: Const { dest: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, value: 0x1, }, 1: Copy { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, }, // at: module-XXXXXXXXXX.rs:3:1 2: IsNonZeroDestIsSmall { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, }, // at: module-XXXXXXXXXX.rs:1:1 3: Const { dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, value: 0x3, }, // at: module-XXXXXXXXXX.rs:3:1 4: BranchIfZero { target: 6, value: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, 5: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:1:1 6: Add { dest: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, rhs: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 7: CastToUInt { dest: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, // at: module-XXXXXXXXXX.rs:4:1 8: Copy { dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, src: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:6:1 9: Copy { dest: StatePartIndex(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:3:1 10: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, }, 11: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 12: BranchIfSmallNonZero { target: 16, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 13: BranchIfSmallZero { target: 17, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 14: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, }, 15: Branch { target: 17, }, 16: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, 17: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 18: Return, ], .. }, pc: 18, memory_write_log: [], memories: StatePart { value: [], }, small_slots: StatePart { value: [ 0, 0, 1, 0, ], }, big_slots: StatePart { value: [ 1, 0, 3, 3, 4, 3, 0, 1, 4, 4, ], }, sim_only_slots: StatePart { value: [], }, }, io: Instance { name: ::counter, instantiated: Module { name: counter, .. }, }, main_module: SimulationModuleState { base_targets: [ Instance { name: ::counter, instantiated: Module { name: counter, .. }, }.cd, Instance { name: ::counter, instantiated: Module { name: counter, .. }, }.count, ], uninitialized_ios: {}, io_targets: { Instance { name: ::counter, instantiated: Module { name: counter, .. }, }.cd, Instance { name: ::counter, instantiated: Module { name: counter, .. }, }.cd.clk, Instance { name: ::counter, instantiated: Module { name: counter, .. }, }.cd.rst, Instance { name: ::counter, instantiated: Module { name: counter, .. }, }.count, }, did_initial_settle: true, }, extern_modules: [], state_ready_to_run: false, trace_decls: TraceModule { name: "counter", children: [ TraceModuleIO { name: "cd", child: TraceBundle { name: "cd", fields: [ TraceClock { location: TraceScalarId(0), name: "clk", flow: Source, }, TraceAsyncReset { location: TraceScalarId(1), name: "rst", flow: Source, }, ], ty: Bundle { /* offset = 0 */ clk: Clock, /* offset = 1 */ rst: AsyncReset, }, flow: Source, }, ty: Bundle { /* offset = 0 */ clk: Clock, /* offset = 1 */ rst: AsyncReset, }, flow: Source, }, TraceModuleIO { name: "count", child: TraceUInt { location: TraceScalarId(2), name: "count", ty: UInt<4>, flow: Sink, }, ty: UInt<4>, flow: Sink, }, TraceReg { name: "count_reg", child: TraceUInt { location: TraceScalarId(3), name: "count_reg", ty: UInt<4>, flow: Duplex, }, ty: UInt<4>, }, ], }, traces: [ SimTrace { id: TraceScalarId(0), kind: BigClock { index: StatePartIndex(0), }, state: 0x1, last_state: 0x1, }, SimTrace { id: TraceScalarId(1), kind: BigAsyncReset { index: StatePartIndex(1), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(2), kind: BigUInt { index: StatePartIndex(2), ty: UInt<4>, }, state: 0x3, last_state: 0x2, }, SimTrace { id: TraceScalarId(3), kind: BigUInt { index: StatePartIndex(3), ty: UInt<4>, }, state: 0x3, last_state: 0x3, }, ], trace_memories: {}, trace_writers: [ Running( VcdWriter { finished_init: true, timescale: 1 ps, .. }, ), ], instant: 66 μs, clocks_triggered: [ StatePartIndex(1), ], .. }