Simulation { state: State { insns: Insns { state_layout: StateLayout { ty: TypeLayout { small_slots: StatePartLayout { len: 11, debug_data: [ SlotDebugData { name: "", ty: Enum { HdlNone, HdlSome, }, }, SlotDebugData { name: "", ty: Enum { HdlNone, HdlSome, }, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: UInt<3>, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: UInt<3>, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, ], .. }, big_slots: StatePartLayout { len: 36, debug_data: [ SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.addr", ty: UInt<3>, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.en", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.clk", ty: Clock, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata", ty: UInt<2>, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2>, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3>, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum { HdlNone, HdlSome(Bool), }, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum { HdlNone, HdlSome(Bool), }, }, SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool, }, SlotDebugData { name: "", ty: UInt<2>, }, SlotDebugData { name: "", ty: UInt<1>, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: UInt<2>, }, SlotDebugData { name: "", ty: UInt<1>, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Enum { HdlNone, HdlSome(Bool), }, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: UInt<2>, }, SlotDebugData { name: "", ty: Enum { HdlNone, HdlSome(Bool), }, }, SlotDebugData { name: "", ty: UInt<1>, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: ".0", ty: UInt<1>, }, SlotDebugData { name: ".1", ty: Bool, }, SlotDebugData { name: "", ty: UInt<1>, }, SlotDebugData { name: "", ty: UInt<1>, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: UInt<1>, }, SlotDebugData { name: "", ty: UInt<2>, }, SlotDebugData { name: "", ty: UInt<2>, }, SlotDebugData { name: "", ty: UInt<2>, }, SlotDebugData { name: "", ty: Enum { HdlNone, HdlSome(Bool), }, }, ], .. }, }, memories: StatePartLayout { len: 1, debug_data: [ (), ], layout_data: [ MemoryData { array_type: Array, data: [ // len = 0x5 [0x0]: 0x3, [0x1]: 0x3, [0x2]: 0x3, [0x3]: 0x3, [0x4]: 0x3, ], }, ], .. }, }, insns: [ // at: module-XXXXXXXXXX.rs:13:1 0: Copy { dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 1: SliceInt { dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> }, start: 1, len: 1, }, 2: Copy { dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, 3: Const { dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, value: 0x1, }, 4: Copy { dest: StatePartIndex(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, src: StatePartIndex(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, 5: Copy { dest: StatePartIndex(27), // (0x0) SlotDebugData { name: ".1", ty: Bool }, src: StatePartIndex(30), // (0x0) SlotDebugData { name: "", ty: Bool }, }, 6: Copy { dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(27), // (0x0) SlotDebugData { name: ".1", ty: Bool }, }, 7: Shl { dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, lhs: StatePartIndex(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 1, }, 8: Or { dest: StatePartIndex(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, lhs: StatePartIndex(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, }, 9: CastToUInt { dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, src: StatePartIndex(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, dest_width: 2, }, 10: Copy { dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, src: StatePartIndex(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, }, 11: SliceInt { dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> }, start: 0, len: 1, }, 12: Copy { dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, 13: Const { dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, value: 0x0, }, 14: Copy { dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, src: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, }, // at: module-XXXXXXXXXX.rs:10:1 15: Copy { dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} }, src: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, }, // at: module-XXXXXXXXXX.rs:11:1 16: BranchIfZero { target: 18, value: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:12:1 17: Copy { dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} }, src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, }, // at: module-XXXXXXXXXX.rs:9:1 18: Copy { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool }, src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:7:1 19: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock }, src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.clk", ty: Clock }, }, // at: module-XXXXXXXXXX.rs:6:1 20: Copy { dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.en", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:5:1 21: Copy { dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> }, src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.addr", ty: UInt<3> }, }, // at: module-XXXXXXXXXX.rs:3:1 22: BranchIfSmallZero { target: 26, value: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 23: BranchIfSmallNonZero { target: 26, value: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 24: MemoryReadUInt { dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} }, memory: StatePartIndex(0), // (MemoryData { // array_type: Array, // data: [ // // len = 0x5 // [0x0]: 0x0, // [0x1]: 0x1, // [0x2]: 0x0, // [0x3]: 0x3, // [0x4]: 0x0, // ], // }) (), addr: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, stride: 2, start: 0, width: 2, }, 25: Branch { target: 27, }, 26: Const { dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} }, value: 0x0, }, 27: IsNonZeroDestIsSmall { dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool }, }, 28: CastBigToArrayIndex { dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> }, }, 29: IsNonZeroDestIsSmall { dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool }, }, 30: IsNonZeroDestIsSmall { dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock }, }, 31: AndSmall { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 32: Copy { dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, src: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} }, }, 33: SliceInt { dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 1, len: 1, }, 34: Copy { dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: module-XXXXXXXXXX.rs:4:1 35: AndBigWithSmallImmediate { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, lhs: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 36: Copy { dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, src: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} }, }, 37: SliceInt { dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 1, len: 1, }, 38: Copy { dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, // at: module-XXXXXXXXXX.rs:8:1 39: Copy { dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata", ty: UInt<2> }, src: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, }, // at: module-XXXXXXXXXX.rs:4:1 40: AndBigWithSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, lhs: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:3:1 41: BranchIfSmallZero { target: 51, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 42: CopySmall { dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, src: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, }, 43: CopySmall { dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 44: Copy { dest: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, src: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} }, }, 45: Copy { dest: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool }, }, 46: CopySmall { dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 47: BranchIfSmallZero { target: 51, value: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 48: BranchIfSmallZero { target: 51, value: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, 49: BranchIfZero { target: 51, value: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: Bool }, }, 50: MemoryWriteUInt { value: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} }, memory: StatePartIndex(0), // (MemoryData { // array_type: Array, // data: [ // // len = 0x5 // [0x0]: 0x0, // [0x1]: 0x1, // [0x2]: 0x0, // [0x3]: 0x3, // [0x4]: 0x0, // ], // }) (), addr: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> }, stride: 2, start: 0, width: 2, }, 51: XorSmallImmediate { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 52: Return, ], .. }, pc: 52, memory_write_log: [], memories: StatePart { value: [ MemoryData { array_type: Array, data: [ // len = 0x5 [0x0]: 0x0, [0x1]: 0x1, [0x2]: 0x0, [0x3]: 0x3, [0x4]: 0x0, ], }, ], }, small_slots: StatePart { value: [ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, ], }, big_slots: StatePart { value: [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, ], }, }, io: Instance { name: ::memories2, instantiated: Module { name: memories2, .. }, }, main_module: SimulationModuleState { base_targets: [ Instance { name: ::memories2, instantiated: Module { name: memories2, .. }, }.rw, ], uninitialized_ios: {}, io_targets: { Instance { name: ::memories2, instantiated: Module { name: memories2, .. }, }.rw, Instance { name: ::memories2, instantiated: Module { name: memories2, .. }, }.rw.addr, Instance { name: ::memories2, instantiated: Module { name: memories2, .. }, }.rw.clk, Instance { name: ::memories2, instantiated: Module { name: memories2, .. }, }.rw.en, Instance { name: ::memories2, instantiated: Module { name: memories2, .. }, }.rw.rdata, Instance { name: ::memories2, instantiated: Module { name: memories2, .. }, }.rw.wdata, Instance { name: ::memories2, instantiated: Module { name: memories2, .. }, }.rw.wmask, Instance { name: ::memories2, instantiated: Module { name: memories2, .. }, }.rw.wmode, }, did_initial_settle: true, }, extern_modules: [], state_ready_to_run: false, trace_decls: TraceModule { name: "memories2", children: [ TraceModuleIO { name: "rw", child: TraceBundle { name: "rw", fields: [ TraceUInt { location: TraceScalarId(0), name: "addr", ty: UInt<3>, flow: Source, }, TraceBool { location: TraceScalarId(1), name: "en", flow: Source, }, TraceClock { location: TraceScalarId(2), name: "clk", flow: Source, }, TraceUInt { location: TraceScalarId(3), name: "rdata", ty: UInt<2>, flow: Sink, }, TraceBool { location: TraceScalarId(4), name: "wmode", flow: Source, }, TraceUInt { location: TraceScalarId(5), name: "wdata", ty: UInt<2>, flow: Source, }, TraceBool { location: TraceScalarId(6), name: "wmask", flow: Source, }, ], ty: Bundle { /* offset = 0 */ addr: UInt<3>, /* offset = 3 */ en: Bool, /* offset = 4 */ clk: Clock, #[hdl(flip)] /* offset = 5 */ rdata: UInt<2>, /* offset = 7 */ wmode: Bool, /* offset = 8 */ wdata: UInt<2>, /* offset = 10 */ wmask: Bool, }, flow: Source, }, ty: Bundle { /* offset = 0 */ addr: UInt<3>, /* offset = 3 */ en: Bool, /* offset = 4 */ clk: Clock, #[hdl(flip)] /* offset = 5 */ rdata: UInt<2>, /* offset = 7 */ wmode: Bool, /* offset = 8 */ wdata: UInt<2>, /* offset = 10 */ wmask: Bool, }, flow: Source, }, TraceMem { id: TraceMemoryId(0), name: "mem", stride: 2, element_type: TraceEnumWithFields { name: "mem", discriminant: TraceEnumDiscriminant { location: TraceMemoryLocation { id: TraceMemoryId(0), depth: 5, stride: 2, start: 0, len: 1, }, name: "$tag", ty: Enum { HdlNone, HdlSome(Bool), }, flow: Duplex, }, non_empty_fields: [ TraceBool { location: TraceMemoryLocation { id: TraceMemoryId(0), depth: 5, stride: 2, start: 1, len: 1, }, name: "HdlSome", flow: Duplex, }, ], ty: Enum { HdlNone, HdlSome(Bool), }, flow: Duplex, }, ports: [ TraceMemPort { name: "rw0", bundle: TraceBundle { name: "rw0", fields: [ TraceUInt { location: TraceScalarId(7), name: "addr", ty: UInt<3>, flow: Sink, }, TraceBool { location: TraceScalarId(8), name: "en", flow: Sink, }, TraceClock { location: TraceScalarId(9), name: "clk", flow: Sink, }, TraceEnumWithFields { name: "rdata", discriminant: TraceEnumDiscriminant { location: TraceScalarId(10), name: "$tag", ty: Enum { HdlNone, HdlSome(Bool), }, flow: Source, }, non_empty_fields: [ TraceBool { location: TraceScalarId(11), name: "HdlSome", flow: Source, }, ], ty: Enum { HdlNone, HdlSome(Bool), }, flow: Source, }, TraceBool { location: TraceScalarId(12), name: "wmode", flow: Sink, }, TraceEnumWithFields { name: "wdata", discriminant: TraceEnumDiscriminant { location: TraceScalarId(13), name: "$tag", ty: Enum { HdlNone, HdlSome(Bool), }, flow: Sink, }, non_empty_fields: [ TraceBool { location: TraceScalarId(14), name: "HdlSome", flow: Source, }, ], ty: Enum { HdlNone, HdlSome(Bool), }, flow: Sink, }, TraceBool { location: TraceScalarId(15), name: "wmask", flow: Sink, }, ], ty: Bundle { /* offset = 0 */ addr: UInt<3>, /* offset = 3 */ en: Bool, /* offset = 4 */ clk: Clock, #[hdl(flip)] /* offset = 5 */ rdata: Enum { HdlNone, HdlSome(Bool), }, /* offset = 7 */ wmode: Bool, /* offset = 8 */ wdata: Enum { HdlNone, HdlSome(Bool), }, /* offset = 10 */ wmask: Bool, }, flow: Sink, }, ty: Bundle { /* offset = 0 */ addr: UInt<3>, /* offset = 3 */ en: Bool, /* offset = 4 */ clk: Clock, #[hdl(flip)] /* offset = 5 */ rdata: Enum { HdlNone, HdlSome(Bool), }, /* offset = 7 */ wmode: Bool, /* offset = 8 */ wdata: Enum { HdlNone, HdlSome(Bool), }, /* offset = 10 */ wmask: Bool, }, }, ], array_type: Array, }, ], }, traces: [ SimTrace { id: TraceScalarId(0), kind: BigUInt { index: StatePartIndex(0), ty: UInt<3>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(1), kind: BigBool { index: StatePartIndex(1), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(2), kind: BigClock { index: StatePartIndex(2), }, state: 0x0, last_state: 0x1, }, SimTrace { id: TraceScalarId(3), kind: BigUInt { index: StatePartIndex(3), ty: UInt<2>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(4), kind: BigBool { index: StatePartIndex(4), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(5), kind: BigUInt { index: StatePartIndex(5), ty: UInt<2>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(6), kind: BigBool { index: StatePartIndex(6), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(7), kind: BigUInt { index: StatePartIndex(7), ty: UInt<3>, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(8), kind: BigBool { index: StatePartIndex(8), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(9), kind: BigClock { index: StatePartIndex(9), }, state: 0x0, last_state: 0x1, }, SimTrace { id: TraceScalarId(10), kind: EnumDiscriminant { index: StatePartIndex(0), ty: Enum { HdlNone, HdlSome(Bool), }, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(11), kind: BigBool { index: StatePartIndex(16), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(12), kind: BigBool { index: StatePartIndex(11), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(13), kind: EnumDiscriminant { index: StatePartIndex(1), ty: Enum { HdlNone, HdlSome(Bool), }, }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(14), kind: BigBool { index: StatePartIndex(19), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(15), kind: BigBool { index: StatePartIndex(13), }, state: 0x0, last_state: 0x0, }, ], trace_memories: { StatePartIndex(0): TraceMem { id: TraceMemoryId(0), name: "mem", stride: 2, element_type: TraceEnumWithFields { name: "mem", discriminant: TraceEnumDiscriminant { location: TraceMemoryLocation { id: TraceMemoryId(0), depth: 5, stride: 2, start: 0, len: 1, }, name: "$tag", ty: Enum { HdlNone, HdlSome(Bool), }, flow: Duplex, }, non_empty_fields: [ TraceBool { location: TraceMemoryLocation { id: TraceMemoryId(0), depth: 5, stride: 2, start: 1, len: 1, }, name: "HdlSome", flow: Duplex, }, ], ty: Enum { HdlNone, HdlSome(Bool), }, flow: Duplex, }, ports: [ TraceMemPort { name: "rw0", bundle: TraceBundle { name: "rw0", fields: [ TraceUInt { location: TraceScalarId(7), name: "addr", ty: UInt<3>, flow: Sink, }, TraceBool { location: TraceScalarId(8), name: "en", flow: Sink, }, TraceClock { location: TraceScalarId(9), name: "clk", flow: Sink, }, TraceEnumWithFields { name: "rdata", discriminant: TraceEnumDiscriminant { location: TraceScalarId(10), name: "$tag", ty: Enum { HdlNone, HdlSome(Bool), }, flow: Source, }, non_empty_fields: [ TraceBool { location: TraceScalarId(11), name: "HdlSome", flow: Source, }, ], ty: Enum { HdlNone, HdlSome(Bool), }, flow: Source, }, TraceBool { location: TraceScalarId(12), name: "wmode", flow: Sink, }, TraceEnumWithFields { name: "wdata", discriminant: TraceEnumDiscriminant { location: TraceScalarId(13), name: "$tag", ty: Enum { HdlNone, HdlSome(Bool), }, flow: Sink, }, non_empty_fields: [ TraceBool { location: TraceScalarId(14), name: "HdlSome", flow: Source, }, ], ty: Enum { HdlNone, HdlSome(Bool), }, flow: Sink, }, TraceBool { location: TraceScalarId(15), name: "wmask", flow: Sink, }, ], ty: Bundle { /* offset = 0 */ addr: UInt<3>, /* offset = 3 */ en: Bool, /* offset = 4 */ clk: Clock, #[hdl(flip)] /* offset = 5 */ rdata: Enum { HdlNone, HdlSome(Bool), }, /* offset = 7 */ wmode: Bool, /* offset = 8 */ wdata: Enum { HdlNone, HdlSome(Bool), }, /* offset = 10 */ wmask: Bool, }, flow: Sink, }, ty: Bundle { /* offset = 0 */ addr: UInt<3>, /* offset = 3 */ en: Bool, /* offset = 4 */ clk: Clock, #[hdl(flip)] /* offset = 5 */ rdata: Enum { HdlNone, HdlSome(Bool), }, /* offset = 7 */ wmode: Bool, /* offset = 8 */ wdata: Enum { HdlNone, HdlSome(Bool), }, /* offset = 10 */ wmask: Bool, }, }, ], array_type: Array, }, }, trace_writers: [ Running( VcdWriter { finished_init: true, timescale: 1 ps, .. }, ), ], instant: 22 μs, clocks_triggered: [ StatePartIndex(3), ], .. }