Simulation { state: State { insns: Insns { state_layout: StateLayout { ty: TypeLayout { small_slots: StatePartAllocationLayout { len: 4, debug_data: [ SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, ], .. }, big_slots: StatePartAllocationLayout { len: 13, debug_data: [ SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool, }, SlotDebugData { name: "", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool, }, ], .. }, }, memories: StatePartAllocationLayout { len: 0, debug_data: [], layout_data: [], .. }, }, insns: [ // at: module-XXXXXXXXXX.rs:13:1 Copy { dest: StatePartIndex(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool }, src: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:12:1 Copy { dest: StatePartIndex(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, src: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:10:1 Copy { dest: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, src: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:8:1 Copy { dest: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, src: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:6:1 Copy { dest: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, src: StatePartIndex(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:5:1 IsNonZeroDestIsSmall { dest: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:1:1 Const { dest: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, value: 0, }, // at: module-XXXXXXXXXX.rs:5:1 IsNonZeroDestIsSmall { dest: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, }, AndSmall { dest: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, }, BranchIfSmallZero { target: 14, value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, }, BranchIfSmallNonZero { target: 13, value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, }, Copy { dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, src: StatePartIndex(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, }, Branch { target: 14, }, Copy { dest: StatePartIndex(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:7:1 BranchIfSmallZero { target: 19, value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, }, BranchIfSmallNonZero { target: 18, value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, }, Copy { dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, src: StatePartIndex(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, }, Branch { target: 19, }, Copy { dest: StatePartIndex(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:9:1 BranchIfSmallZero { target: 24, value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, }, BranchIfSmallNonZero { target: 23, value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, }, Copy { dest: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, src: StatePartIndex(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, }, Branch { target: 24, }, Copy { dest: StatePartIndex(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 BranchIfSmallZero { target: 29, value: StatePartIndex(1), // SlotDebugData { name: "", ty: Bool }, }, BranchIfSmallNonZero { target: 28, value: StatePartIndex(3), // SlotDebugData { name: "", ty: Bool }, }, Copy { dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, src: StatePartIndex(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, }, Branch { target: 29, }, Copy { dest: StatePartIndex(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, src: StatePartIndex(6), // SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:5:1 NotSmall { dest: StatePartIndex(0), // SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(2), // SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 Return, ], .. }, pc: 30, memories: StatePart { value: [], }, small_slots: StatePart { value: [ 18446744073709551614, 0, 1, 0, ], }, big_slots: StatePart { value: [ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ], }, }, io: Instance { name: ::shift_register, instantiated: Module { name: shift_register, .. }, }, uninitialized_inputs: {}, io_targets: { Instance { name: ::shift_register, instantiated: Module { name: shift_register, .. }, }.cd: CompiledValue { layout: CompiledTypeLayout { ty: Bundle { /* offset = 0 */ clk: Clock, /* offset = 1 */ rst: SyncReset, }, layout: TypeLayout { small_slots: StatePartAllocationLayout { len: 0, debug_data: [], .. }, big_slots: StatePartAllocationLayout { len: 2, debug_data: [ SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock, }, SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset, }, ], .. }, }, body: Bundle { fields: [ CompiledBundleField { offset: TypeIndex { small_slots: StatePartIndex(0), big_slots: StatePartIndex(0), }, ty: CompiledTypeLayout { ty: Clock, layout: TypeLayout { small_slots: StatePartAllocationLayout { len: 0, debug_data: [], .. }, big_slots: StatePartAllocationLayout { len: 1, debug_data: [ SlotDebugData { name: "", ty: Clock, }, ], .. }, }, body: Scalar, }, }, CompiledBundleField { offset: TypeIndex { small_slots: StatePartIndex(0), big_slots: StatePartIndex(1), }, ty: CompiledTypeLayout { ty: SyncReset, layout: TypeLayout { small_slots: StatePartAllocationLayout { len: 0, debug_data: [], .. }, big_slots: StatePartAllocationLayout { len: 1, debug_data: [ SlotDebugData { name: "", ty: SyncReset, }, ], .. }, }, body: Scalar, }, }, ], }, }, range: TypeIndexRange { small_slots: StatePartIndexRange { start: 0, len: 0 }, big_slots: StatePartIndexRange { start: 0, len: 2 }, }, write: None, }, Instance { name: ::shift_register, instantiated: Module { name: shift_register, .. }, }.cd.clk: CompiledValue { layout: CompiledTypeLayout { ty: Clock, layout: TypeLayout { small_slots: StatePartAllocationLayout { len: 0, debug_data: [], .. }, big_slots: StatePartAllocationLayout { len: 1, debug_data: [ SlotDebugData { name: "", ty: Clock, }, ], .. }, }, body: Scalar, }, range: TypeIndexRange { small_slots: StatePartIndexRange { start: 0, len: 0 }, big_slots: StatePartIndexRange { start: 0, len: 1 }, }, write: None, }, Instance { name: ::shift_register, instantiated: Module { name: shift_register, .. }, }.cd.rst: CompiledValue { layout: CompiledTypeLayout { ty: SyncReset, layout: TypeLayout { small_slots: StatePartAllocationLayout { len: 0, debug_data: [], .. }, big_slots: StatePartAllocationLayout { len: 1, debug_data: [ SlotDebugData { name: "", ty: SyncReset, }, ], .. }, }, body: Scalar, }, range: TypeIndexRange { small_slots: StatePartIndexRange { start: 0, len: 0 }, big_slots: StatePartIndexRange { start: 1, len: 1 }, }, write: None, }, Instance { name: ::shift_register, instantiated: Module { name: shift_register, .. }, }.d: CompiledValue { layout: CompiledTypeLayout { ty: Bool, layout: TypeLayout { small_slots: StatePartAllocationLayout { len: 0, debug_data: [], .. }, big_slots: StatePartAllocationLayout { len: 1, debug_data: [ SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool, }, ], .. }, }, body: Scalar, }, range: TypeIndexRange { small_slots: StatePartIndexRange { start: 0, len: 0 }, big_slots: StatePartIndexRange { start: 2, len: 1 }, }, write: None, }, Instance { name: ::shift_register, instantiated: Module { name: shift_register, .. }, }.q: CompiledValue { layout: CompiledTypeLayout { ty: Bool, layout: TypeLayout { small_slots: StatePartAllocationLayout { len: 0, debug_data: [], .. }, big_slots: StatePartAllocationLayout { len: 1, debug_data: [ SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool, }, ], .. }, }, body: Scalar, }, range: TypeIndexRange { small_slots: StatePartIndexRange { start: 0, len: 0 }, big_slots: StatePartIndexRange { start: 3, len: 1 }, }, write: None, }, }, made_initial_step: true, needs_settle: false, trace_decls: TraceModule { name: "shift_register", children: [ TraceModuleIO { name: "cd", child: TraceBundle { name: "cd", fields: [ TraceClock { id: TraceScalarId(0), name: "clk", flow: Source, }, TraceSyncReset { id: TraceScalarId(1), name: "rst", flow: Source, }, ], ty: Bundle { /* offset = 0 */ clk: Clock, /* offset = 1 */ rst: SyncReset, }, flow: Source, }, ty: Bundle { /* offset = 0 */ clk: Clock, /* offset = 1 */ rst: SyncReset, }, flow: Source, }, TraceModuleIO { name: "d", child: TraceBool { id: TraceScalarId(2), name: "d", flow: Source, }, ty: Bool, flow: Source, }, TraceModuleIO { name: "q", child: TraceBool { id: TraceScalarId(3), name: "q", flow: Sink, }, ty: Bool, flow: Sink, }, TraceReg { name: "reg0", child: TraceBool { id: TraceScalarId(4), name: "reg0", flow: Duplex, }, ty: Bool, }, TraceReg { name: "reg1", child: TraceBool { id: TraceScalarId(5), name: "reg1", flow: Duplex, }, ty: Bool, }, TraceReg { name: "reg2", child: TraceBool { id: TraceScalarId(6), name: "reg2", flow: Duplex, }, ty: Bool, }, TraceReg { name: "reg3", child: TraceBool { id: TraceScalarId(7), name: "reg3", flow: Duplex, }, ty: Bool, }, ], }, traces: [ SimTrace { id: TraceScalarId(0), kind: BigClock { index: StatePartIndex(0), }, state: 0x1, last_state: 0x1, }, SimTrace { id: TraceScalarId(1), kind: BigSyncReset { index: StatePartIndex(1), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(2), kind: BigBool { index: StatePartIndex(2), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(3), kind: BigBool { index: StatePartIndex(3), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(4), kind: BigBool { index: StatePartIndex(4), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(5), kind: BigBool { index: StatePartIndex(7), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(6), kind: BigBool { index: StatePartIndex(9), }, state: 0x0, last_state: 0x0, }, SimTrace { id: TraceScalarId(7), kind: BigBool { index: StatePartIndex(11), }, state: 0x0, last_state: 0x0, }, ], trace_writers: [ Running( VcdWriter { finished_init: true, timescale: 1 ps, .. }, ), ], instant: 66 μs, clocks_triggered: [ StatePartIndex(1), ], }