diff --git a/README.md b/README.md index 18cd78c3..8e7f275a 100644 --- a/README.md +++ b/README.md @@ -12,7 +12,7 @@ Fayalite is a library for designing digital hardware -- a hardware description l [Blinky example]: crates/fayalite/examples/blinky.rs -This uses the container image containing all the external programs and files that Fayalite needs to build for FPGAs, the sources for the container image are in +This uses the container image containing all the external programs and files that Fayalite needs to build for FPGAs, the sources for the container image are in https://git.libre-chip.org/libre-chip/fayalite-deps Steps: diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs index e8dc51bf..09189bd9 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs @@ -87,11 +87,7 @@ impl ParsedBundle { no_static: _, no_runtime_generics: _, cmp_eq: _, - ref get, } = options.body; - if let Some((get, ..)) = get { - errors.error(get, "#[hdl(get(...))] is not allowed on structs"); - } let mut fields = match fields { syn::Fields::Named(fields) => fields, syn::Fields::Unnamed(fields) => { @@ -449,7 +445,6 @@ impl ToTokens for ParsedBundle { no_static, no_runtime_generics, cmp_eq, - get: _, } = &options.body; let target = get_target(target, ident); let mut item_attrs = attrs.clone(); diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs index 885cf871..47a5df10 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs @@ -159,14 +159,10 @@ impl ParsedEnum { no_static: _, no_runtime_generics: _, cmp_eq, - ref get, } = options.body; if let Some((cmp_eq,)) = cmp_eq { errors.error(cmp_eq, "#[hdl(cmp_eq)] is not yet implemented for enums"); } - if let Some((get, ..)) = get { - errors.error(get, "#[hdl(get(...))] is not allowed on enums"); - } attrs.retain(|attr| { if attr.path().is_ident("repr") { errors.error(attr, "#[repr] is not supported on #[hdl] enums"); @@ -229,7 +225,6 @@ impl ToTokens for ParsedEnum { no_static, no_runtime_generics, cmp_eq: _, // TODO: implement cmp_eq for enums - get: _, } = &options.body; let target = get_target(target, ident); let mut struct_attrs = attrs.clone(); diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs index 0fa2222d..d4a035bd 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs @@ -3,264 +3,29 @@ use crate::{ Errors, HdlAttr, hdl_type_common::{ - ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, - PhantomConstGetBound, TypesParser, WrappedInConst, common_derives, get_target, known_items, + ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, TypesParser, + get_target, }, kw, }; use proc_macro2::TokenStream; -use quote::{ToTokens, format_ident, quote_spanned}; -use syn::{ - Attribute, Expr, Fields, GenericParam, Generics, Ident, ItemStruct, ItemType, Token, Type, - TypeGroup, TypeParam, TypeParen, Visibility, parse_quote_spanned, punctuated::Pair, - token::Paren, -}; +use quote::ToTokens; +use syn::{Attribute, Generics, Ident, ItemType, Token, Type, Visibility, parse_quote_spanned}; #[derive(Clone, Debug)] -pub(crate) struct PhantomConstAccessorTypeParam { - attrs: Vec, - ident: Ident, - colon_token: Token![:], - phantom_const_get_bound: PhantomConstGetBound, - plus_token: Option, -} - -impl From for TypeParam { - fn from(value: PhantomConstAccessorTypeParam) -> Self { - let PhantomConstAccessorTypeParam { - attrs, - ident, - colon_token, - phantom_const_get_bound, - plus_token, - } = value; - TypeParam { - attrs, - ident, - colon_token: Some(colon_token), - bounds: FromIterator::from_iter([Pair::new( - phantom_const_get_bound.into(), - plus_token, - )]), - eq_token: None, - default: None, - } - } -} - -impl From for GenericParam { - fn from(value: PhantomConstAccessorTypeParam) -> Self { - TypeParam::from(value).into() - } -} - -impl PhantomConstAccessorTypeParam { - fn parse_opt(generic_param: GenericParam) -> Option { - let GenericParam::Type(TypeParam { - attrs, - ident, - colon_token, - bounds, - eq_token: None, - default: None, - }) = generic_param - else { - return None; - }; - let colon_token = colon_token.unwrap_or(Token![:](ident.span())); - let mut bounds = bounds.into_pairs(); - let (bound, plus_token) = bounds.next()?.into_tuple(); - let phantom_const_get_bound = PhantomConstGetBound::parse_type_param_bound(bound) - .ok()? - .ok()?; - let None = bounds.next() else { - return None; - }; - Some(Self { - attrs, - ident, - colon_token, - phantom_const_get_bound, - plus_token, - }) - } -} - -#[derive(Clone, Debug)] -pub(crate) struct PhantomConstAccessorGenerics { - lt_token: Token![<], - type_param: PhantomConstAccessorTypeParam, - comma_token: Option, - gt_token: Token![>], -} - -impl From for Generics { - fn from(value: PhantomConstAccessorGenerics) -> Self { - let PhantomConstAccessorGenerics { - lt_token, - type_param, - comma_token, - gt_token, - } = value; - Generics { - lt_token: Some(lt_token), - params: FromIterator::from_iter([Pair::new(type_param.into(), comma_token)]), - gt_token: Some(gt_token), - where_clause: None, - } - } -} - -impl<'a> From<&'a PhantomConstAccessorGenerics> for Generics { - fn from(value: &'a PhantomConstAccessorGenerics) -> Self { - value.clone().into() - } -} - -impl PhantomConstAccessorGenerics { - fn parse_opt(generics: Generics) -> Option { - let Generics { - lt_token, - params, - gt_token, - where_clause: None, - } = generics - else { - return None; - }; - let mut params = params.into_pairs(); - let (generic_param, comma_token) = params.next()?.into_tuple(); - let type_param = PhantomConstAccessorTypeParam::parse_opt(generic_param)?; - let span = type_param.ident.span(); - let lt_token = lt_token.unwrap_or(Token![<](span)); - let gt_token = gt_token.unwrap_or(Token![>](span)); - let None = params.next() else { - return None; - }; - Some(Self { - lt_token, - type_param, - comma_token, - gt_token, - }) - } -} - -#[derive(Clone, Debug)] -pub(crate) enum ParsedTypeAlias { - TypeAlias { - attrs: Vec, - options: HdlAttr, - vis: Visibility, - type_token: Token![type], - ident: Ident, - generics: MaybeParsed, - eq_token: Token![=], - ty: MaybeParsed, - semi_token: Token![;], - }, - PhantomConstAccessor { - attrs: Vec, - options: HdlAttr, - get: (kw::get, Paren, Expr), - vis: Visibility, - type_token: Token![type], - ident: Ident, - generics: PhantomConstAccessorGenerics, - eq_token: Token![=], - ty: Type, - ty_is_dyn_size: Option, - semi_token: Token![;], - }, +pub(crate) struct ParsedTypeAlias { + pub(crate) attrs: Vec, + pub(crate) options: HdlAttr, + pub(crate) vis: Visibility, + pub(crate) type_token: Token![type], + pub(crate) ident: Ident, + pub(crate) generics: MaybeParsed, + pub(crate) eq_token: Token![=], + pub(crate) ty: MaybeParsed, + pub(crate) semi_token: Token![;], } impl ParsedTypeAlias { - fn ty_is_dyn_size(ty: &Type) -> Option { - match ty { - Type::Group(TypeGroup { - group_token: _, - elem, - }) => Self::ty_is_dyn_size(elem), - Type::Paren(TypeParen { - paren_token: _, - elem, - }) => Self::ty_is_dyn_size(elem), - Type::Path(syn::TypePath { qself: None, path }) => { - known_items::DynSize::parse_path(path.clone()).ok() - } - _ => None, - } - } - fn parse_phantom_const_accessor( - item: ItemType, - mut errors: Errors, - options: HdlAttr, - get: (kw::get, Paren, Expr), - ) -> syn::Result { - let ItemType { - attrs, - vis, - type_token, - ident, - generics, - eq_token, - ty, - semi_token, - } = item; - let ItemOptions { - outline_generated: _, - ref target, - custom_bounds, - no_static, - no_runtime_generics, - cmp_eq, - get: _, - } = options.body; - if let Some((no_static,)) = no_static { - errors.error(no_static, "no_static is not valid on type aliases"); - } - if let Some((target, ..)) = target { - errors.error( - target, - "target is not implemented on PhantomConstGet type aliases", - ); - } - if let Some((no_runtime_generics,)) = no_runtime_generics { - errors.error( - no_runtime_generics, - "no_runtime_generics is not implemented on PhantomConstGet type aliases", - ); - } - if let Some((cmp_eq,)) = cmp_eq { - errors.error(cmp_eq, "cmp_eq is not valid on type aliases"); - } - if let Some((custom_bounds,)) = custom_bounds { - errors.error( - custom_bounds, - "custom_bounds is not implemented on PhantomConstGet type aliases", - ); - } - let Some(generics) = PhantomConstAccessorGenerics::parse_opt(generics) else { - errors.error(ident, "#[hdl(get(...))] type alias must be of the form:\ntype MyTypeGetter> = RetType;"); - errors.finish()?; - unreachable!(); - }; - errors.finish()?; - let ty_is_dyn_size = Self::ty_is_dyn_size(&ty); - Ok(Self::PhantomConstAccessor { - attrs, - options, - get, - vis, - type_token, - ident, - generics, - eq_token, - ty: *ty, - ty_is_dyn_size, - semi_token, - }) - } fn parse(item: ItemType) -> syn::Result { let ItemType { mut attrs, @@ -286,25 +51,7 @@ impl ParsedTypeAlias { no_static, no_runtime_generics: _, cmp_eq, - ref mut get, } = options.body; - if let Some(get) = get.take() { - return Self::parse_phantom_const_accessor( - ItemType { - attrs, - vis, - type_token, - ident, - generics, - eq_token, - ty, - semi_token, - }, - errors, - options, - get, - ); - } if let Some((no_static,)) = no_static { errors.error(no_static, "no_static is not valid on type aliases"); } @@ -320,7 +67,7 @@ impl ParsedTypeAlias { }; let ty = TypesParser::maybe_run(generics.as_ref(), *ty, &mut errors); errors.finish()?; - Ok(Self::TypeAlias { + Ok(Self { attrs, options, vis, @@ -336,155 +83,54 @@ impl ParsedTypeAlias { impl ToTokens for ParsedTypeAlias { fn to_tokens(&self, tokens: &mut TokenStream) { - match self { - Self::TypeAlias { - attrs, - options, - vis, - type_token, - ident, - generics, - eq_token, - ty, - semi_token, - } => { - let ItemOptions { - outline_generated: _, - target, - custom_bounds: _, - no_static: _, - no_runtime_generics, - cmp_eq: _, - get: _, - } = &options.body; - let target = get_target(target, ident); - let mut type_attrs = attrs.clone(); - type_attrs.push(parse_quote_spanned! {ident.span()=> - #[allow(type_alias_bounds)] - }); - ItemType { - attrs: type_attrs, - vis: vis.clone(), - type_token: *type_token, - ident: ident.clone(), - generics: generics.into(), - eq_token: *eq_token, - ty: Box::new(ty.clone().into()), - semi_token: *semi_token, - } - .to_tokens(tokens); - if let (MaybeParsed::Parsed(generics), MaybeParsed::Parsed(ty), None) = - (generics, ty, no_runtime_generics) - { - generics.make_runtime_generics(tokens, vis, ident, &target, |context| { - ty.make_hdl_type_expr(context) - }) - } - } - Self::PhantomConstAccessor { - attrs, - options, - get: (_get_kw, _get_paren, get_expr), - vis, - type_token, - ident, - generics, - eq_token, - ty, - ty_is_dyn_size, - semi_token, - } => { - let ItemOptions { - outline_generated: _, - target: _, - custom_bounds: _, - no_static: _, - no_runtime_generics: _, - cmp_eq: _, - get: _, - } = &options.body; - let span = ident.span(); - let mut type_attrs = attrs.clone(); - type_attrs.push(parse_quote_spanned! {span=> - #[allow(type_alias_bounds)] - }); - let type_param_ident = &generics.type_param.ident; - let syn_generics = Generics::from(generics); - ItemType { - attrs: type_attrs, - vis: vis.clone(), - type_token: *type_token, - ident: ident.clone(), - generics: syn_generics.clone(), - eq_token: *eq_token, - ty: parse_quote_spanned! {span=> - <#ty as ::fayalite::phantom_const::ReturnSelfUnchanged<#type_param_ident>>::Type - }, - semi_token: *semi_token, - } - .to_tokens(tokens); - let generics_accumulation_ident = - format_ident!("__{}__GenericsAccumulation", ident); - ItemStruct { - attrs: vec![ - common_derives(span), - parse_quote_spanned! {span=> - #[allow(non_camel_case_types)] - }, - ], - vis: vis.clone(), - struct_token: Token![struct](span), - ident: generics_accumulation_ident.clone(), - generics: Generics::default(), - fields: Fields::Unnamed(parse_quote_spanned! {span=> - (()) - }), - semi_token: Some(Token![;](span)), - } - .to_tokens(tokens); - quote_spanned! {span=> - #[allow(non_upper_case_globals, dead_code)] - #vis const #ident: #generics_accumulation_ident = #generics_accumulation_ident(()); - } - .to_tokens(tokens); - let mut wrapped_in_const = WrappedInConst::new(tokens, span); - let tokens = wrapped_in_const.inner(); - let (impl_generics, _type_generics, where_clause) = syn_generics.split_for_impl(); - let phantom_const_get_ty = &generics.type_param.phantom_const_get_bound.ty; - let index_output = if let Some(ty_is_dyn_size) = ty_is_dyn_size { - known_items::usize(ty_is_dyn_size.span).to_token_stream() - } else { - ty.to_token_stream() - }; - quote_spanned! {span=> - #[allow(non_upper_case_globals)] - #[automatically_derived] - impl #impl_generics ::fayalite::__std::ops::Index<#type_param_ident> - for #generics_accumulation_ident - #where_clause - { - type Output = #index_output; - - fn index(&self, __param: #type_param_ident) -> &Self::Output { - ::fayalite::phantom_const::type_alias_phantom_const_get_helper::<#phantom_const_get_ty, #index_output>( - __param, - #get_expr, - ) - } - } - } - .to_tokens(tokens); - } + let Self { + attrs, + options, + vis, + type_token, + ident, + generics, + eq_token, + ty, + semi_token, + } = self; + let ItemOptions { + outline_generated: _, + target, + custom_bounds: _, + no_static: _, + no_runtime_generics, + cmp_eq: _, + } = &options.body; + let target = get_target(target, ident); + let mut type_attrs = attrs.clone(); + type_attrs.push(parse_quote_spanned! {ident.span()=> + #[allow(type_alias_bounds)] + }); + ItemType { + attrs: type_attrs, + vis: vis.clone(), + type_token: *type_token, + ident: ident.clone(), + generics: generics.into(), + eq_token: *eq_token, + ty: Box::new(ty.clone().into()), + semi_token: *semi_token, + } + .to_tokens(tokens); + if let (MaybeParsed::Parsed(generics), MaybeParsed::Parsed(ty), None) = + (generics, ty, no_runtime_generics) + { + generics.make_runtime_generics(tokens, vis, ident, &target, |context| { + ty.make_hdl_type_expr(context) + }) } } } pub(crate) fn hdl_type_alias_impl(item: ItemType) -> syn::Result { let item = ParsedTypeAlias::parse(item)?; - let outline_generated = match &item { - ParsedTypeAlias::TypeAlias { options, .. } - | ParsedTypeAlias::PhantomConstAccessor { options, .. } => options.body.outline_generated, - }; + let outline_generated = item.options.body.outline_generated; let mut contents = item.to_token_stream(); if outline_generated.is_some() { contents = crate::outline_generated(contents, "hdl-type-alias-"); diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs index f5b353e0..1206f11c 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs @@ -8,9 +8,9 @@ use syn::{ AngleBracketedGenericArguments, Attribute, Block, ConstParam, Expr, ExprBlock, ExprGroup, ExprIndex, ExprParen, ExprPath, ExprTuple, Field, FieldMutability, Fields, FieldsNamed, FieldsUnnamed, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index, ItemStruct, - Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound, Turbofish, - Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath, TypeTuple, - Visibility, WhereClause, WherePredicate, + Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, Turbofish, Type, + TypeGenerics, TypeGroup, TypeParam, TypeParen, TypePath, TypeTuple, Visibility, WhereClause, + WherePredicate, parse::{Parse, ParseStream}, parse_quote, parse_quote_spanned, punctuated::{Pair, Punctuated}, @@ -27,7 +27,6 @@ crate::options! { NoStatic(no_static), NoRuntimeGenerics(no_runtime_generics), CmpEq(cmp_eq), - Get(get, Expr), } } @@ -2046,7 +2045,6 @@ pub(crate) mod known_items { impl_known_item!(::fayalite::int::Size); impl_known_item!(::fayalite::int::UInt); impl_known_item!(::fayalite::int::UIntType); - impl_known_item!(::fayalite::phantom_const::PhantomConstGet); impl_known_item!(::fayalite::reset::ResetType); impl_known_item!(::fayalite::ty::CanonicalType); impl_known_item!(::fayalite::ty::StaticType); @@ -2065,174 +2063,6 @@ pub(crate) mod known_items { ); } -#[derive(Clone, Debug)] -pub(crate) struct PhantomConstGetBound { - pub(crate) phantom_const_get: known_items::PhantomConstGet, - pub(crate) colon2_token: Option, - pub(crate) lt_token: Token![<], - pub(crate) ty: Type, - pub(crate) comma_token: Option, - pub(crate) gt_token: Token![>], -} - -impl PhantomConstGetBound { - pub(crate) fn parse_path_with_arguments(path: Path) -> syn::Result> { - match known_items::PhantomConstGet::parse_path_with_arguments(path) { - Ok((phantom_const_get, arguments)) => { - Self::parse_path_and_arguments(phantom_const_get, arguments).map(Ok) - } - Err(path) => Ok(Err(path)), - } - } - pub(crate) fn parse_path_and_arguments( - phantom_const_get: known_items::PhantomConstGet, - arguments: PathArguments, - ) -> syn::Result { - let error = |arguments: PathArguments, message: &str| { - let mut path = phantom_const_get.path.clone(); - path.segments.last_mut().expect("known to exist").arguments = arguments; - syn::Error::new_spanned(path, message) - }; - match arguments { - PathArguments::None => Err(error(arguments, "missing generics for PhantomConstGet")), - PathArguments::AngleBracketed(AngleBracketedGenericArguments { - colon2_token, - lt_token, - args, - gt_token, - }) => { - let error = |args: Punctuated, message| { - error( - PathArguments::AngleBracketed(AngleBracketedGenericArguments { - colon2_token, - lt_token, - args, - gt_token, - }), - message, - ) - }; - let mut args = args.into_pairs().peekable(); - let Some((generic_argument, comma_token)) = args.next().map(Pair::into_tuple) - else { - return Err(error( - Default::default(), - "PhantomConstGet takes a type argument but no generic arguments were supplied", - )); - }; - if args.peek().is_some() { - return Err(error( - [Pair::new(generic_argument, comma_token)] - .into_iter() - .chain(args) - .collect(), - "PhantomConstGet takes a single type argument but too many generic arguments were supplied", - )); - }; - let GenericArgument::Type(ty) = generic_argument else { - return Err(error( - Punctuated::from_iter([Pair::new(generic_argument, comma_token)]), - "PhantomConstGet requires a type argument", - )); - }; - Ok(Self { - phantom_const_get, - colon2_token, - lt_token, - ty, - comma_token, - gt_token, - }) - } - PathArguments::Parenthesized(_) => Err(error( - arguments, - "parenthetical generics are not valid for PhantomConstGet", - )), - } - } - pub(crate) fn parse_type_param_bound( - bound: TypeParamBound, - ) -> syn::Result> { - let TypeParamBound::Trait(TraitBound { - paren_token: None, - modifier: syn::TraitBoundModifier::None, - lifetimes: None, - path, - }) = bound - else { - return Ok(Err(bound)); - }; - Ok(match Self::parse_path_with_arguments(path)? { - Ok(v) => Ok(v), - Err(path) => Err(TypeParamBound::Trait(TraitBound { - paren_token: None, - modifier: syn::TraitBoundModifier::None, - lifetimes: None, - path, - })), - }) - } -} - -impl ToTokens for PhantomConstGetBound { - fn to_tokens(&self, tokens: &mut TokenStream) { - let Self { - phantom_const_get, - colon2_token, - lt_token, - ty, - comma_token, - gt_token, - } = self; - phantom_const_get.to_tokens(tokens); - colon2_token.to_tokens(tokens); - lt_token.to_tokens(tokens); - ty.to_tokens(tokens); - comma_token.to_tokens(tokens); - gt_token.to_tokens(tokens); - } -} - -impl From for Path { - fn from(value: PhantomConstGetBound) -> Self { - let PhantomConstGetBound { - phantom_const_get, - colon2_token, - lt_token, - ty, - comma_token, - gt_token, - } = value; - let mut path = phantom_const_get.path; - path.segments.last_mut().expect("known to exist").arguments = - PathArguments::AngleBracketed(AngleBracketedGenericArguments { - colon2_token, - lt_token, - args: FromIterator::from_iter([Pair::new(GenericArgument::Type(ty), comma_token)]), - gt_token, - }); - path - } -} - -impl From for TraitBound { - fn from(value: PhantomConstGetBound) -> Self { - let path = Path::from(value); - TraitBound { - paren_token: None, - modifier: syn::TraitBoundModifier::None, - lifetimes: None, - path, - } - } -} - -impl From for TypeParamBound { - fn from(value: PhantomConstGetBound) -> Self { - TraitBound::from(value).into() - } -} - macro_rules! impl_bounds { ( #[struct = $struct_type:ident] @@ -2240,10 +2070,6 @@ macro_rules! impl_bounds { $( $Variant:ident, )* - $( - #[has_body] - $VariantHasBody:ident($variant_has_body_ty:ty), - )* $( #[unknown] $Unknown:ident, @@ -2253,7 +2079,6 @@ macro_rules! impl_bounds { #[derive(Clone, Debug)] $vis enum $enum_type { $($Variant(known_items::$Variant),)* - $($VariantHasBody($variant_has_body_ty),)* $($Unknown(syn::TypeParamBound),)? } @@ -2263,42 +2088,31 @@ macro_rules! impl_bounds { } })* - $(impl From<$variant_has_body_ty> for $enum_type { - fn from(v: $variant_has_body_ty) -> Self { - Self::$VariantHasBody(v) - } - })* - impl ToTokens for $enum_type { fn to_tokens(&self, tokens: &mut TokenStream) { match self { $(Self::$Variant(v) => v.to_tokens(tokens),)* - $(Self::$VariantHasBody(v) => v.to_tokens(tokens),)* $(Self::$Unknown(v) => v.to_tokens(tokens),)? } } } impl $enum_type { - $vis fn parse_path_with_arguments(path: Path) -> syn::Result> { + $vis fn parse_path(path: Path) -> Result { #![allow(unreachable_code)] $(let path = match known_items::$Variant::parse_path(path) { - Ok(v) => return Ok(Ok(Self::$Variant(v))), + Ok(v) => return Ok(Self::$Variant(v)), Err(path) => path, };)* - $(let path = match <$variant_has_body_ty>::parse_path_with_arguments(path)? { - Ok(v) => return Ok(Ok(Self::$VariantHasBody(v))), - Err(path) => path, - };)* - $(return Ok(Ok(Self::$Unknown(syn::TraitBound { + $(return Ok(Self::$Unknown(syn::TraitBound { paren_token: None, modifier: syn::TraitBoundModifier::None, lifetimes: None, path, - }.into())));)? - Ok(Err(path)) + }.into()));)? + Err(path) } - $vis fn parse_type_param_bound(mut type_param_bound: syn::TypeParamBound) -> syn::Result> { + $vis fn parse_type_param_bound(mut type_param_bound: syn::TypeParamBound) -> Result { #![allow(unreachable_code)] if let syn::TypeParamBound::Trait(mut trait_bound) = type_param_bound { if let syn::TraitBound { @@ -2307,24 +2121,24 @@ macro_rules! impl_bounds { lifetimes: None, path: _, } = trait_bound { - match Self::parse_path_with_arguments(trait_bound.path)? { - Ok(retval) => return Ok(Ok(retval)), + match Self::parse_path(trait_bound.path) { + Ok(retval) => return Ok(retval), Err(path) => trait_bound.path = path, } } type_param_bound = trait_bound.into(); } - $(return Ok(Ok(Self::$Unknown(type_param_bound)));)? - Ok(Err(type_param_bound)) + $(return Ok(Self::$Unknown(type_param_bound));)? + Err(type_param_bound) } } impl Parse for $enum_type { fn parse(input: ParseStream) -> syn::Result { - Self::parse_type_param_bound(input.parse()?)? + Self::parse_type_param_bound(input.parse()?) .map_err(|type_param_bound| syn::Error::new_spanned( type_param_bound, - format_args!("expected one of: {}", [$(stringify!($Variant),)* $(stringify!($VariantHasBody)),*].join(", ")), + format_args!("expected one of: {}", [$(stringify!($Variant)),*].join(", ")), )) } } @@ -2333,7 +2147,6 @@ macro_rules! impl_bounds { #[allow(non_snake_case)] $vis struct $struct_type { $($vis $Variant: Option,)* - $($vis $VariantHasBody: Option<$variant_has_body_ty>,)* $($vis $Unknown: Vec,)? } @@ -2346,11 +2159,6 @@ macro_rules! impl_bounds { separator = Some(::default()); v.to_tokens(tokens); })* - $(if let Some(v) = &self.$VariantHasBody { - separator.to_tokens(tokens); - separator = Some(::default()); - v.to_tokens(tokens); - })* $(for v in &self.$Unknown { separator.to_tokens(tokens); separator = Some(::default()); @@ -2364,7 +2172,6 @@ macro_rules! impl_bounds { #[allow(non_snake_case)] $vis struct Iter { $($Variant: Option,)* - $($VariantHasBody: Option<$variant_has_body_ty>,)* $($Unknown: std::vec::IntoIter,)? } @@ -2375,7 +2182,6 @@ macro_rules! impl_bounds { fn into_iter(self) -> Self::IntoIter { Iter { $($Variant: self.$Variant,)* - $($VariantHasBody: self.$VariantHasBody,)* $($Unknown: self.$Unknown.into_iter(),)? } } @@ -2390,11 +2196,6 @@ macro_rules! impl_bounds { return Some($enum_type::$Variant(value)); } )* - $( - if let Some(value) = self.$VariantHasBody.take() { - return Some($enum_type::$VariantHasBody(value)); - } - )* $( if let Some(value) = self.$Unknown.next() { return Some($enum_type::$Unknown(value)); @@ -2410,11 +2211,6 @@ macro_rules! impl_bounds { init = f(init, $enum_type::$Variant(value)); } )* - $( - if let Some(value) = self.$VariantHasBody.take() { - init = f(init, $enum_type::$VariantHasBody(value)); - } - )* $( if let Some(value) = self.$Unknown.next() { init = f(init, $enum_type::$Unknown(value)); @@ -2431,9 +2227,6 @@ macro_rules! impl_bounds { $($enum_type::$Variant(v) => { self.$Variant = Some(v); })* - $($enum_type::$VariantHasBody(v) => { - self.$VariantHasBody = Some(v); - })* $($enum_type::$Unknown(v) => { self.$Unknown.push(v); })? @@ -2455,9 +2248,6 @@ macro_rules! impl_bounds { $(if let Some(v) = v.$Variant { self.$Variant = Some(v); })* - $(if let Some(v) = v.$VariantHasBody { - self.$VariantHasBody = Some(v); - })* $(self.$Unknown.extend(v.$Unknown);)* }); } @@ -2512,8 +2302,6 @@ impl_bounds! { Size, StaticType, Type, - #[has_body] - PhantomConstGet(PhantomConstGetBound), #[unknown] Unknown, } @@ -2529,8 +2317,6 @@ impl_bounds! { ResetType, StaticType, Type, - #[has_body] - PhantomConstGet(PhantomConstGetBound), #[unknown] Unknown, } @@ -2546,7 +2332,6 @@ impl From for ParsedBound { ParsedTypeBound::ResetType(v) => ParsedBound::ResetType(v), ParsedTypeBound::StaticType(v) => ParsedBound::StaticType(v), ParsedTypeBound::Type(v) => ParsedBound::Type(v), - ParsedTypeBound::PhantomConstGet(v) => ParsedBound::PhantomConstGet(v), ParsedTypeBound::Unknown(v) => ParsedBound::Unknown(v), } } @@ -2562,7 +2347,6 @@ impl From for ParsedBounds { ResetType, StaticType, Type, - PhantomConstGet, Unknown, } = value; Self { @@ -2575,7 +2359,6 @@ impl From for ParsedBounds { Size: None, StaticType, Type, - PhantomConstGet, Unknown, } } @@ -2612,10 +2395,6 @@ impl ParsedTypeBound { ParsedTypeBound::Type(known_items::Type(span)), ]), Self::Type(v) => ParsedTypeBounds::from_iter([ParsedTypeBound::from(v)]), - Self::PhantomConstGet(v) => ParsedTypeBounds::from_iter([ - ParsedTypeBound::from(v), - ParsedTypeBound::Type(known_items::Type(span)), - ]), Self::Unknown(v) => ParsedTypeBounds::from_iter([ParsedTypeBound::Unknown(v)]), } } @@ -2651,7 +2430,6 @@ impl From for ParsedBounds { Size, StaticType: None, Type: None, - PhantomConstGet: None, Unknown: vec![], } } @@ -2754,9 +2532,6 @@ impl ParsedBound { Self::Size(v) => ParsedBoundCategory::SizeType(ParsedSizeTypeBound::Size(v)), Self::StaticType(v) => ParsedBoundCategory::Type(ParsedTypeBound::StaticType(v)), Self::Type(v) => ParsedBoundCategory::Type(ParsedTypeBound::Type(v)), - Self::PhantomConstGet(v) => { - ParsedBoundCategory::Type(ParsedTypeBound::PhantomConstGet(v)) - } Self::Unknown(v) => ParsedBoundCategory::Unknown(v), } } @@ -3642,8 +3417,7 @@ impl ParsedGenerics { | ParsedTypeBound::BundleType(_) | ParsedTypeBound::EnumType(_) | ParsedTypeBound::IntType(_) - | ParsedTypeBound::ResetType(_) - | ParsedTypeBound::PhantomConstGet(_) => { + | ParsedTypeBound::ResetType(_) => { errors.error(bound, "bounds on mask types are not implemented"); } ParsedTypeBound::StaticType(bound) => { diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs index 13ec7a2e..13336fa2 100644 --- a/crates/fayalite-proc-macros-impl/src/lib.rs +++ b/crates/fayalite-proc-macros-impl/src/lib.rs @@ -76,7 +76,6 @@ mod kw { custom_keyword!(connect_inexact); custom_keyword!(custom_bounds); custom_keyword!(flip); - custom_keyword!(get); custom_keyword!(hdl); custom_keyword!(hdl_module); custom_keyword!(incomplete_wire); diff --git a/crates/fayalite/src/build/external.rs b/crates/fayalite/src/build/external.rs index 1a904144..e4251a48 100644 --- a/crates/fayalite/src/build/external.rs +++ b/crates/fayalite/src/build/external.rs @@ -12,7 +12,7 @@ use crate::{ }; use base64::{Engine, prelude::BASE64_URL_SAFE_NO_PAD}; use clap::builder::OsStringValueParser; -use eyre::{Context, ensure, eyre}; +use eyre::{Context, bail, ensure, eyre}; use serde::{ Deserialize, Deserializer, Serialize, Serializer, de::{DeserializeOwned, Error}, @@ -26,7 +26,6 @@ use std::{ io::Write, marker::PhantomData, path::{Path, PathBuf}, - process::ExitStatus, sync::OnceLock, }; @@ -366,17 +365,13 @@ impl ExternalJobCaching { .stdin(std::process::Stdio::null()); Ok(cmd) } - pub fn run( + pub fn run eyre::Result<()>>( self, command_line: Interned<[Interned]>, input_file_paths: impl IntoIterator>, output_file_paths: impl IntoIterator> + Clone, run_fn: F, - exit_status_to_error: impl FnOnce(ExitStatus) -> eyre::Report, - ) -> eyre::Result<()> - where - F: FnOnce(std::process::Command) -> eyre::Result>, - { + ) -> eyre::Result<()> { let mut hasher = JobCacheHasher::default(); hasher.hash_iter(command_line.iter(), |hasher, arg| { hasher.hash_sized_os_str(arg) @@ -424,26 +419,7 @@ impl ExternalJobCaching { }) .expect("spawn shouldn't fail"); run_fn(cmd) - })?; - if let Err(exit_status) = result { - // check if the user may have terminated it or something, don't cache the failure - let user_maybe_terminated; - #[cfg(unix)] - { - user_maybe_terminated = std::os::unix::process::ExitStatusExt::signal(&exit_status) - .is_some() - || exit_status.code().is_none_or(|code| code > 1); - } - #[cfg(not(unix))] - { - user_maybe_terminated = !exit_status.success(); - } - if user_maybe_terminated { - let _ = std::fs::remove_file(self.cache_json_path); - return Err(exit_status_to_error(exit_status)); - } - } - let result = result.map_err(exit_status_to_error); + }); ExternalJobCacheV2 { version: ExternalJobCacheVersion::CURRENT, inputs_hash, @@ -468,26 +444,16 @@ impl ExternalJobCaching { .write_to_file(self.cache_json_path)?; result } - pub fn run_maybe_cached( + pub fn run_maybe_cached eyre::Result<()>>( this: Option, command_line: Interned<[Interned]>, input_file_paths: impl IntoIterator>, output_file_paths: impl IntoIterator> + Clone, run_fn: F, - exit_status_to_error: impl FnOnce(ExitStatus) -> eyre::Report, - ) -> eyre::Result<()> - where - F: FnOnce(std::process::Command) -> eyre::Result>, - { + ) -> eyre::Result<()> { match this { - Some(this) => this.run( - command_line, - input_file_paths, - output_file_paths, - run_fn, - exit_status_to_error, - ), - None => run_fn(Self::make_command(command_line)?)?.map_err(exit_status_to_error), + Some(this) => this.run(command_line, input_file_paths, output_file_paths, run_fn), + None => run_fn(Self::make_command(command_line)?), } } } @@ -1153,12 +1119,10 @@ impl JobKind for ExternalCommandJobKind { } let status = acquired_job.run_command(cmd, |cmd| cmd.status())?; if !status.success() { - Ok(Err(status)) - } else { - Ok(Ok(())) + bail!("running {command_line:?} failed: {status}") } + Ok(()) }, - |status| eyre!("running {command_line:?} failed: {status}"), )?; Ok(job .output_paths() diff --git a/crates/fayalite/src/build/graph.rs b/crates/fayalite/src/build/graph.rs index bed88295..d81b282f 100644 --- a/crates/fayalite/src/build/graph.rs +++ b/crates/fayalite/src/build/graph.rs @@ -703,12 +703,8 @@ impl JobGraph { } let mut running_jobs = HashMap::default(); let (finished_jobs_sender, finished_jobs_receiver) = mpsc::channel(); - let mut next_finished_job = None; loop { - if let Some(finished_job) = next_finished_job - .take() - .or_else(|| finished_jobs_receiver.try_recv().ok()) - { + while let Some(finished_job) = finished_jobs_receiver.try_recv().ok() { let Some(RunningJob { job, thread }) = running_jobs.remove(&finished_job) else { unreachable!(); @@ -740,7 +736,6 @@ impl JobGraph { } } } - continue; } if let Some(WaitingJobState { job_node_id, @@ -796,15 +791,12 @@ impl JobGraph { .expect("failed to spawn thread for job"), }, ); - continue; } if running_jobs.is_empty() { assert!(item_name_to_waiting_jobs_map.is_empty()); assert!(ready_jobs.is_empty()); return Ok(()); } - // nothing to do yet, block to avoid busy waiting - next_finished_job = finished_jobs_receiver.recv().ok(); } }) } diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs index 96ee1f71..326d44bb 100644 --- a/crates/fayalite/src/lib.rs +++ b/crates/fayalite/src/lib.rs @@ -4,18 +4,6 @@ // TODO: enable: // #![warn(missing_docs)] -#![deny( - rustdoc::bare_urls, - rustdoc::broken_intra_doc_links, - rustdoc::invalid_codeblock_attributes, - rustdoc::invalid_html_tags, - rustdoc::invalid_rust_codeblocks, - rustdoc::private_doc_tests, - rustdoc::private_intra_doc_links, - rustdoc::redundant_explicit_links, - rustdoc::unescaped_backticks -)] - //! [Main Documentation][_docs] extern crate self as fayalite; @@ -86,135 +74,6 @@ macro_rules! __cfg_expansion_helper { pub use fayalite_proc_macros::hdl_module; #[doc(inline)] -/// The `#[hdl]` attribute is supported on several different kinds of [Rust Items](https://doc.rust-lang.org/reference/items.html): -/// -/// # Functions and Methods -/// Enable's the stuff that you can use inside a [module's body](crate::_docs::modules::module_bodies), -/// but without being a module or changing the function's signature. -/// The only exception is that you can't use stuff that requires the automatically-provided `m` variable. -/// -/// # Structs -// TODO: expand on struct docs -/// e.g.: -/// ``` -/// # use fayalite::prelude::*; -/// # #[hdl] -/// # pub struct OtherStruct {} -/// #[hdl] -/// pub struct MyStruct { -/// #[hdl(flip)] -/// pub a: UInt<5>, -/// pub b: Bool, -/// #[hdl(flip)] -/// pub c: OtherStruct, -/// } -/// ``` -/// -/// # Enums -// TODO: expand on enum docs -/// e.g.: -/// ``` -/// # use fayalite::prelude::*; -/// # #[hdl] -/// # pub struct MyStruct {} -/// #[hdl] -/// pub enum MyEnum { -/// A(UInt<3>), -/// B, -/// C(MyStruct), -/// } -/// ``` -/// -/// # Type Aliases -/// -/// There's three different ways you can create a type alias: -/// -/// # Normal Type Alias -/// -/// This works exactly how you'd expect: -/// ``` -/// # use fayalite::prelude::*; -/// # #[hdl] -/// # pub struct MyStruct { -/// # v: T, -/// # } -/// #[hdl] -/// pub type MyType = MyStruct; -/// -/// // you can then use Fayalite's standard syntax for creating dynamic types at runtime: -/// -/// let ty = MyType[UInt[3]]; -/// assert_eq!(ty, MyStruct[UInt[3]]); -/// ``` -/// -/// # Type Alias that gets a [`Type`] from a [`PhantomConst`] -/// -/// This allows you to use some computed property of a [`PhantomConst`] to get a [`Type`] that you can use in other #[hdl] types. -/// -/// ``` -/// # use fayalite::{intern::Intern, prelude::*}; -/// #[derive(Clone, PartialEq, Eq, Hash, Debug, serde::Serialize, serde::Deserialize)] -/// pub struct Config { -/// pub foo: usize, -/// pub bar: Bundle, -/// } -/// -/// // the expression inside `get` is called with `Interned` and returns `Array` -/// #[hdl(get(|config| Array[config.bar][config.foo]))] -/// pub type GetMyArray> = Array; -/// -/// // you can then use it in other types: -/// -/// #[hdl(no_static)] -/// pub struct WrapMyArray> { -/// pub my_array: GetMyArray

, -/// } -/// -/// // you can then use Fayalite's standard syntax for creating dynamic types at runtime: -/// let bar = Bundle::new(Default::default()); -/// let config = PhantomConst::new(Config { foo: 12, bar }.intern_sized()); -/// let ty = WrapMyArray[config]; -/// assert_eq!(ty.my_array, Array[bar][12]); -/// ``` -/// -/// # Type Alias that gets a [`Size`] from a [`PhantomConst`] -/// -/// This allows you to use some computed property of a [`PhantomConst`] to get a [`Size`] that you can use in other #[hdl] types. -/// -/// ``` -/// # use fayalite::{intern::Intern, prelude::*}; -/// # #[derive(Clone, PartialEq, Eq, Hash, Debug, serde::Serialize, serde::Deserialize)] -/// # pub struct ConfigItem {} -/// # impl ConfigItem { -/// # pub fn new() -> Self { -/// # Self {} -/// # } -/// # } -/// #[derive(Clone, PartialEq, Eq, Hash, Debug, serde::Serialize, serde::Deserialize)] -/// pub struct Config { -/// pub items: Vec, -/// } -/// -/// // the expression inside `get` is called with `Interned` and returns `usize` (not DynSize) -/// #[hdl(get(|config| config.items.len()))] -/// pub type GetItemsLen> = DynSize; // must be DynSize -/// -/// // you can then use it in other types: -/// -/// #[hdl(no_static)] -/// pub struct FlagPerItem> { -/// pub flags: ArrayType>, -/// } -/// -/// // you can then use Fayalite's standard syntax for creating dynamic types at runtime: -/// let config = PhantomConst::new(Config { items: vec![ConfigItem::new(); 5] }.intern_sized()); -/// let ty = FlagPerItem[config]; -/// assert_eq!(ty.flags, Array[Bool][5]); -/// ``` -/// -/// [`PhantomConst`]: crate::phantom_const::PhantomConst -/// [`Size`]: crate::int::Size -/// [`Type`]: crate::ty::Type pub use fayalite_proc_macros::hdl; pub use bitvec; diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs index 9f251665..b8520560 100644 --- a/crates/fayalite/src/phantom_const.rs +++ b/crates/fayalite/src/phantom_const.rs @@ -415,71 +415,3 @@ impl ToSimValueWithType for Phanto SimValue::into_canonical(SimValue::from_value(Self::from_canonical(ty), *self)) } } - -mod sealed { - pub trait Sealed {} -} - -pub trait PhantomConstGet: sealed::Sealed { - fn get(&self) -> Interned; -} - -impl>> - sealed::Sealed for This -{ -} - -impl>> - PhantomConstGet for This -{ - fn get(&self) -> Interned { - This::Target::get(&**self) - } -} - -macro_rules! impl_phantom_const_get { - ( - impl PhantomConstGet<$T:ident> for $ty:ty { - fn $get:ident(&$get_self:ident) -> _ $get_body:block - } - ) => { - impl<$T: ?Sized + PhantomConstValue> sealed::Sealed<$T> for $ty {} - - impl<$T: ?Sized + PhantomConstValue> PhantomConstGet<$T> for $ty { - fn $get(&$get_self) -> Interned<$T> $get_body - } - }; -} - -impl_phantom_const_get! { - impl PhantomConstGet for PhantomConst { - fn get(&self) -> _ { - PhantomConst::get(*self) - } - } -} - -impl_phantom_const_get! { - impl PhantomConstGet for Expr> { - fn get(&self) -> _ { - PhantomConst::get(Expr::ty(*self)) - } - } -} - -#[doc(hidden)] -pub trait ReturnSelfUnchanged { - type Type: ?Sized; -} - -impl ReturnSelfUnchanged for This { - type Type = This; -} - -#[doc(hidden)] -pub fn type_alias_phantom_const_get_helper( - param: impl PhantomConstGet, - get: impl FnOnce(Interned) -> R, -) -> &'static R { - Interned::into_inner(get(param.get()).intern_sized()) -} diff --git a/crates/fayalite/src/prelude.rs b/crates/fayalite/src/prelude.rs index 4cc173e8..5bb4b772 100644 --- a/crates/fayalite/src/prelude.rs +++ b/crates/fayalite/src/prelude.rs @@ -27,7 +27,7 @@ pub use crate::{ Instance, Module, ModuleBuilder, annotate, connect, connect_any, incomplete_wire, instance, memory, memory_array, memory_with_init, reg_builder, wire, }, - phantom_const::{PhantomConst, PhantomConstGet}, + phantom_const::PhantomConst, platform::{DynPlatform, Platform, PlatformIOBuilder, peripherals}, reg::Reg, reset::{AsyncReset, Reset, SyncReset, ToAsyncReset, ToReset, ToSyncReset}, diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 35da3367..fabe6d8c 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -48,7 +48,7 @@ use num_traits::{Signed, Zero}; use std::{ any::Any, borrow::Cow, - cell::{Cell, RefCell}, + cell::RefCell, collections::BTreeMap, fmt, future::{Future, IntoFuture}, @@ -57,9 +57,8 @@ use std::{ pin::Pin, ptr, rc::Rc, - sync::{Arc, Mutex}, + sync::Arc, task::Poll, - usize, }; pub mod compiler; @@ -1263,11 +1262,149 @@ impl SimulationModuleState { } } +#[derive(Copy, Clone, Debug)] +enum WaitTarget { + Settle, + Instant(SimInstant), + Change { key: ChangeKey, value: ChangeValue }, +} + +#[derive(Clone)] +struct EarliestWaitTargets { + settle: bool, + instant: Option, + changes: HashMap, SimValue>, +} + +impl fmt::Debug for EarliestWaitTargets { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_set().entries(self.iter()).finish() + } +} + +impl Default for EarliestWaitTargets { + fn default() -> Self { + Self { + settle: false, + instant: None, + changes: HashMap::default(), + } + } +} + +impl EarliestWaitTargets { + fn settle() -> Self { + Self { + settle: true, + instant: None, + changes: HashMap::default(), + } + } + fn instant(instant: SimInstant) -> Self { + Self { + settle: false, + instant: Some(instant), + changes: HashMap::default(), + } + } + fn len(&self) -> usize { + self.settle as usize + self.instant.is_some() as usize + self.changes.len() + } + fn is_empty(&self) -> bool { + self.len() == 0 + } + fn clear(&mut self) { + let Self { + settle, + instant, + changes, + } = self; + *settle = false; + *instant = None; + changes.clear(); + } + fn insert( + &mut self, + value: impl std::borrow::Borrow, ChangeValue>>, + ) where + ChangeValue: std::borrow::Borrow>, + { + let value = value.borrow(); + match value { + WaitTarget::Settle => self.settle = true, + WaitTarget::Instant(instant) => { + if self.instant.is_none_or(|v| v > *instant) { + self.instant = Some(*instant); + } + } + WaitTarget::Change { key, value } => { + self.changes + .entry(*key) + .or_insert_with(|| value.borrow().clone()); + } + } + } + fn convert_earlier_instants_to_settle(&mut self, instant: SimInstant) { + if self.instant.is_some_and(|v| v <= instant) { + self.settle = true; + self.instant = None; + } + } + fn iter<'a>( + &'a self, + ) -> impl Clone + + Iterator, &'a SimValue>> + + 'a { + self.settle + .then_some(WaitTarget::Settle) + .into_iter() + .chain(self.instant.map(|instant| WaitTarget::Instant(instant))) + .chain( + self.changes + .iter() + .map(|(&key, value)| WaitTarget::Change { key, value }), + ) + } +} + +impl>> + Extend, ChangeValue>> for EarliestWaitTargets +{ + fn extend, ChangeValue>>>( + &mut self, + iter: T, + ) { + iter.into_iter().for_each(|v| self.insert(v)) + } +} + +impl<'a, ChangeValue: std::borrow::Borrow>> + Extend<&'a WaitTarget, ChangeValue>> for EarliestWaitTargets +{ + fn extend, ChangeValue>>>( + &mut self, + iter: T, + ) { + iter.into_iter().for_each(|v| self.insert(v)) + } +} + +impl FromIterator for EarliestWaitTargets +where + Self: Extend, +{ + fn from_iter>(iter: T) -> Self { + let mut retval = Self::default(); + retval.extend(iter); + retval + } +} + struct SimulationExternModuleState { module_state: SimulationModuleState, sim: ExternModuleSimulation, running_generator: Option + 'static>>>, - waker: Arc, + wait_targets: EarliestWaitTargets, } impl fmt::Debug for SimulationExternModuleState { @@ -1276,7 +1413,7 @@ impl fmt::Debug for SimulationExternModuleState { module_state, sim, running_generator, - waker: _, + wait_targets, } = self; f.debug_struct("SimulationExternModuleState") .field("module_state", module_state) @@ -1285,6 +1422,7 @@ impl fmt::Debug for SimulationExternModuleState { "running_generator", &running_generator.as_ref().map(|_| DebugAsDisplay("...")), ) + .field("wait_targets", wait_targets) .finish() } } @@ -1351,255 +1489,28 @@ impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadFn { } } -#[derive(Copy, Clone, PartialEq, Eq, Debug)] -enum EventKind { - State, - ExternModule(usize), -} +struct GeneratorWaker; -impl PartialOrd for EventKind { - fn partial_cmp(&self, other: &Self) -> Option { - Some(self.cmp(other)) - } -} - -impl Ord for EventKind { - fn cmp(&self, other: &Self) -> std::cmp::Ordering { - match (self, other) { - (Self::State, Self::State) => std::cmp::Ordering::Equal, - (Self::State, Self::ExternModule(_)) => std::cmp::Ordering::Less, - (Self::ExternModule(_), Self::State) => std::cmp::Ordering::Greater, - (Self::ExternModule(this), Self::ExternModule(other)) => this.cmp(other), - } - } -} - -#[derive(Copy, Clone, PartialEq, Eq, Debug)] -struct Event { - instant: SimInstant, - kind: EventKind, -} - -impl PartialOrd for Event { - fn partial_cmp(&self, other: &Self) -> Option { - Some(self.cmp(other)) - } -} - -impl Ord for Event { - fn cmp(&self, other: &Self) -> std::cmp::Ordering { - let Self { instant, kind } = other; - self.instant.cmp(instant).then(self.kind.cmp(kind)) - } -} - -struct HashableWaker(std::task::Waker); - -impl Clone for HashableWaker { - fn clone(&self) -> Self { - Self(self.0.clone()) - } - - fn clone_from(&mut self, source: &Self) { - self.0.clone_from(&source.0); - } -} - -impl PartialEq for HashableWaker { - fn eq(&self, other: &Self) -> bool { - self.0.will_wake(&other.0) - } -} - -impl Eq for HashableWaker {} - -impl Hash for HashableWaker { - fn hash(&self, state: &mut H) { - self.0.data().hash(state); - let vtable: *const std::task::RawWakerVTable = self.0.vtable(); - vtable.hash(state); - } -} - -struct EventQueueData { - instant: SimInstant, - events: BTreeMap>, -} - -impl fmt::Debug for EventQueueData { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - struct EventsDebug<'a>(&'a BTreeMap>); - impl fmt::Debug for EventsDebug<'_> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let mut debug_map = f.debug_map(); - for (k, v) in self.0 { - debug_map.entry(&format_args!("{k:?}"), &v.len()); - } - debug_map.finish() - } - } - let Self { instant, events } = self; - f.debug_struct("EventQueueData") - .field("instant", instant) - .field("events", &EventsDebug(events)) - .finish() - } -} - -struct EventQueueFirstEntry<'a>( - std::collections::btree_map::OccupiedEntry<'a, Event, HashSet>, -); - -impl<'a> EventQueueFirstEntry<'a> { - fn key(&self) -> &Event { - self.0.key() - } - fn remove(self) -> HashSet { - self.0.remove() - } -} - -impl EventQueueData { - fn new(instant: SimInstant) -> Self { - Self { - instant, - events: BTreeMap::new(), - } - } - fn instant(&self) -> SimInstant { - self.instant - } - fn set_instant(&mut self, instant: SimInstant) { - self.instant = instant; - } - fn add_event(&mut self, mut event: Event, waker: Option) { - event.instant = event.instant.max(self.instant); - self.events - .entry(event) - .or_default() - .extend(waker.map(HashableWaker)); - } - fn add_event_for_now(&mut self, kind: EventKind, waker: Option) { - self.add_event( - Event { - instant: self.instant, - kind, - }, - waker, - ); - } - fn first_entry(&mut self) -> Option> { - self.events.first_entry().map(EventQueueFirstEntry) - } - fn peek_first_event(&self) -> Option { - Some(*self.events.first_key_value()?.0) - } - fn peek_first_event_for_now(&self) -> Option { - self.peek_first_event() - .filter(|event| event.instant <= self.instant) - } -} - -struct EventQueue(Mutex); - -impl fmt::Debug for EventQueue { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.write_str("EventQueue(")?; - if let Ok(data) = self.0.try_lock() { - (*data).fmt(f)?; - } else { - f.write_str("")?; - } - f.write_str(")") - } -} - -impl EventQueue { - fn new(data: EventQueueData) -> Self { - Self(Mutex::new(data)) - } - fn lock(&self) -> std::sync::MutexGuard<'_, EventQueueData> { - self.0.lock().expect("not poisoned") - } - fn add_event_for_now(&self, kind: EventKind, waker: Option) { - self.lock().add_event_for_now(kind, waker); - } - fn peek_first_event_for_now(&self) -> Option { - self.lock().peek_first_event_for_now() - } -} - -struct ExternModuleGeneratorWaker { - event_queue: std::sync::Weak, - module_index: usize, -} - -impl std::task::Wake for ExternModuleGeneratorWaker { +impl std::task::Wake for GeneratorWaker { fn wake(self: Arc) { - self.wake_by_ref(); - } - fn wake_by_ref(self: &Arc) { - if let Some(event_queue) = self.event_queue.upgrade() { - event_queue.add_event_for_now(EventKind::ExternModule(self.module_index), None); - } + panic!("can't await other kinds of futures in function passed to ExternalModuleSimulation"); } } -struct SensitivitySet { - debug_id: u64, - compiled_values: HashSet>>, - values: Vec<( - Rc>, - Rc>, - )>, - waker: RefCell, - changed: Cell, +#[derive(Default)] +struct ReadyToRunSet { + state_ready_to_run: bool, + extern_modules_ready_to_run: Vec, } -struct SensitivitySetJustId<'a>(&'a SensitivitySet); - -impl fmt::Debug for SensitivitySetJustId<'_> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - self.0.debug_fmt(true, f) - } -} - -impl fmt::Debug for SensitivitySet { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - self.debug_fmt(false, f) - } -} - -impl SensitivitySet { - fn debug_fmt(&self, just_id: bool, f: &mut fmt::Formatter<'_>) -> fmt::Result { +impl ReadyToRunSet { + fn clear(&mut self) { let Self { - debug_id, - compiled_values: _, - values, - waker: _, - changed, + state_ready_to_run, + extern_modules_ready_to_run, } = self; - struct DebugValues<'a>( - &'a [( - Rc>, - Rc>, - )], - ); - impl<'a> fmt::Debug for DebugValues<'a> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_map() - .entries(self.0.iter().map(|(k, v)| (k, v))) - .finish() - } - } - let mut debug_struct = f.debug_struct("SensitivitySet"); - debug_struct.field("id", debug_id); - if !just_id { - debug_struct - .field("values", &DebugValues(values)) - .field("changed", changed); - } - debug_struct.finish_non_exhaustive() + *state_ready_to_run = false; + extern_modules_ready_to_run.clear(); } } @@ -1608,22 +1519,15 @@ struct SimulationImpl { io: Expr, main_module: SimulationModuleState, extern_modules: Box<[SimulationExternModuleState]>, + state_ready_to_run: bool, trace_decls: TraceModule, traces: SimTraces]>>, - trace_memories: BTreeMap, TraceMem>, + trace_memories: HashMap, TraceMem>, trace_writers: Vec>, + instant: SimInstant, clocks_triggered: Interned<[StatePartIndex]>, breakpoints: Option, - event_queue: Arc, - next_sensitivity_set_debug_id: u64, - waiting_sensitivity_sets_by_compiled_value: HashMap< - Rc>, - ( - Rc>, - HashMap<*const SensitivitySet, Rc>, - ), - >, - waiting_sensitivity_sets_by_address: HashMap<*const SensitivitySet, Rc>, + generator_waker: std::task::Waker, } impl fmt::Debug for SimulationImpl { @@ -1632,70 +1536,6 @@ impl fmt::Debug for SimulationImpl { } } -struct DebugSensitivitySetsByAddress<'a> { - sensitivity_sets: &'a HashMap<*const SensitivitySet, Rc>, - just_id: bool, -} - -impl<'a> fmt::Debug for DebugSensitivitySetsByAddress<'a> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - sensitivity_sets, - just_id, - } = *self; - let mut values: Vec<_> = sensitivity_sets.values().collect(); - values.sort_by_key(|v| v.debug_id); - if just_id { - f.debug_set() - .entries( - values - .iter() - .map(|sensitivity_set| SensitivitySetJustId(sensitivity_set)), - ) - .finish() - } else { - f.debug_set().entries(values).finish() - } - } -} - -struct DebugSensitivitySetsByCompiledValue<'a>( - &'a HashMap< - Rc>, - ( - Rc>, - HashMap<*const SensitivitySet, Rc>, - ), - >, -); - -impl<'a> fmt::Debug for DebugSensitivitySetsByCompiledValue<'a> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let mut values: Vec<_> = self - .0 - .iter() - .map(|(compiled_value, (sim_value, sensitivity_sets))| { - ( - DebugAsDisplay(if f.alternate() { - format!("{compiled_value:#?}") - } else { - format!("{compiled_value:?}") - }), - ( - sim_value, - DebugSensitivitySetsByAddress { - sensitivity_sets, - just_id: true, - }, - ), - ) - }) - .collect(); - values.sort_by(|l, r| l.0.0.cmp(&r.0.0)); - f.debug_map().entries(values).finish() - } -} - impl SimulationImpl { fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { @@ -1703,58 +1543,38 @@ impl SimulationImpl { io: self_io, main_module, extern_modules, + state_ready_to_run, trace_decls, traces, trace_memories, trace_writers, + instant, clocks_triggered, breakpoints: _, - event_queue, - next_sensitivity_set_debug_id: _, - waiting_sensitivity_sets_by_compiled_value, - waiting_sensitivity_sets_by_address, + generator_waker: _, } = self; f.debug_struct("Simulation") .field("state", state) .field("io", io.unwrap_or(self_io)) .field("main_module", main_module) .field("extern_modules", extern_modules) + .field("state_ready_to_run", state_ready_to_run) .field("trace_decls", trace_decls) .field("traces", traces) .field("trace_memories", trace_memories) .field("trace_writers", trace_writers) + .field("instant", instant) .field("clocks_triggered", clocks_triggered) - .field("event_queue", event_queue) - .field( - "waiting_sensitivity_sets_by_address", - &DebugSensitivitySetsByAddress { - sensitivity_sets: waiting_sensitivity_sets_by_address, - just_id: false, - }, - ) - .field( - "waiting_sensitivity_sets_by_compiled_value", - &DebugSensitivitySetsByCompiledValue(waiting_sensitivity_sets_by_compiled_value), - ) .finish_non_exhaustive() } fn new(compiled: Compiled) -> Self { let io_target = Target::from(compiled.io); - let mut event_queue = EventQueueData::new(SimInstant::START); - event_queue.add_event_for_now(EventKind::State, None); - for module_index in 0..compiled.extern_modules.len() { - event_queue.add_event_for_now(EventKind::ExternModule(module_index), None); - } - let event_queue = Arc::new(EventQueue::new(event_queue)); - let extern_modules = Box::from_iter(compiled.extern_modules.iter().enumerate().map( - |( - module_index, - &CompiledExternModule { - module_io_targets, - module_io, - simulation, - }, - )| { + let extern_modules = Box::from_iter(compiled.extern_modules.iter().map( + |&CompiledExternModule { + module_io_targets, + module_io, + simulation, + }| { SimulationExternModuleState { module_state: SimulationModuleState::new( module_io_targets @@ -1764,10 +1584,7 @@ impl SimulationImpl { ), sim: simulation, running_generator: None, - waker: Arc::new(ExternModuleGeneratorWaker { - event_queue: Arc::downgrade(&event_queue), - module_index, - }), + wait_targets: EarliestWaitTargets::settle(), } }, )); @@ -1792,6 +1609,7 @@ impl SimulationImpl { }), ), extern_modules, + state_ready_to_run: true, trace_decls: compiled.base_module.trace_decls, traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map( |&SimTrace { @@ -1804,14 +1622,12 @@ impl SimulationImpl { last_state: kind.make_state(), }, ))), - trace_memories: BTreeMap::from_iter(compiled.trace_memories.iter().copied()), + trace_memories: HashMap::from_iter(compiled.trace_memories.iter().copied()), trace_writers: vec![], + instant: SimInstant::START, clocks_triggered: compiled.clocks_triggered, breakpoints: None, - event_queue, - next_sensitivity_set_debug_id: 0, - waiting_sensitivity_sets_by_compiled_value: HashMap::default(), - waiting_sensitivity_sets_by_address: HashMap::default(), + generator_waker: Arc::new(GeneratorWaker).into(), } } fn write_traces( @@ -1966,170 +1782,137 @@ impl SimulationImpl { } #[track_caller] fn advance_time(this_ref: &Rc>, duration: SimDuration) { - Self::run_until(this_ref, &mut |instant| instant.checked_add(duration)); + let run_target = this_ref.borrow().instant + duration; + Self::run_until(this_ref, run_target); } - fn wake_after_change(&mut self, sensitivity_set: Rc) { - let None = self - .waiting_sensitivity_sets_by_address - .insert(Rc::as_ptr(&sensitivity_set), sensitivity_set.clone()) - else { - // already added - return; - }; - let SensitivitySet { - debug_id: _, - compiled_values: _, - values, - waker: _, - changed: _, - } = &*sensitivity_set; - for (compiled_value, sim_value) in values { - self.waiting_sensitivity_sets_by_compiled_value - .entry(compiled_value.clone()) - .or_insert_with(|| (sim_value.clone(), HashMap::default())) - .1 - .insert(Rc::as_ptr(&sensitivity_set), sensitivity_set.clone()); + /// clears `targets` + #[must_use] + fn yield_wait<'a>( + this: Rc>, + module_index: usize, + targets: &'a mut EarliestWaitTargets, + ) -> impl Future + 'a { + struct MyGenerator<'a> { + sim: Rc>, + yielded_at_all: bool, + module_index: usize, + targets: &'a mut EarliestWaitTargets, } - } - fn cancel_wake_after_change(&mut self, sensitivity_set: &Rc) { - let Some(_) = self - .waiting_sensitivity_sets_by_address - .remove(&Rc::as_ptr(&sensitivity_set)) - else { - return; - }; - let SensitivitySet { - debug_id: _, - compiled_values: _, - values, - waker: _, - changed: _, - } = &**sensitivity_set; - for (compiled_value, _) in values { - if let hashbrown::hash_map::Entry::Occupied(mut entry) = self - .waiting_sensitivity_sets_by_compiled_value - .entry(compiled_value.clone()) - { - entry.get_mut().1.remove(&Rc::as_ptr(&sensitivity_set)); - if entry.get().1.is_empty() { - entry.remove(); + impl Future for MyGenerator<'_> { + type Output = (); + + fn poll( + mut self: Pin<&mut Self>, + cx: &mut std::task::Context<'_>, + ) -> Poll { + let this = &mut *self; + let mut sim = this.sim.borrow_mut(); + let sim = &mut *sim; + assert!( + cx.waker().will_wake(&sim.generator_waker), + "can't use ExternModuleSimulationState's methods outside of ExternModuleSimulation" + ); + this.targets.convert_earlier_instants_to_settle(sim.instant); + if this.targets.is_empty() { + this.targets.settle = true; } + if this.targets.settle { + if this.yielded_at_all { + this.targets.clear(); + return Poll::Ready(()); + } + } + sim.extern_modules[this.module_index] + .wait_targets + .extend(this.targets.iter()); + this.targets.clear(); + this.yielded_at_all = true; + Poll::Pending } } - } - fn try_wake_at_instant( - &mut self, - module_index: usize, - instant: &mut dyn FnMut(SimInstant) -> Option, - waker: std::task::Waker, - ) -> Result<(), std::task::Waker> { - let mut event_queue = self.event_queue.lock(); - let Some(instant) = instant(event_queue.instant()) else { - return Err(waker); - }; - event_queue.add_event( - Event { - instant, - kind: EventKind::ExternModule(module_index), - }, - Some(waker), - ); - Ok(()) + MyGenerator { + sim: this, + yielded_at_all: false, + module_index, + targets, + } } async fn yield_advance_time_or_settle( - this: &RefCell, + this: Rc>, module_index: usize, duration: Option, ) { - let mut target_instant = None; - std::future::poll_fn(|cx| { - match this.borrow_mut().try_wake_at_instant( - module_index, - &mut |instant| match target_instant { - Some(target_instant) => { - // already waited at least once - if instant < target_instant { - Some(target_instant) - } else { - None - } - } - None => { - target_instant = instant.checked_add(duration.unwrap_or(SimDuration::ZERO)); - target_instant - } - }, - cx.waker().clone(), - ) { - Ok(()) => Poll::Pending, - Err(_waker) => { - if target_instant.is_none() { - // don't panic in try_wait_at_instant to avoid poisoning the lock - panic!("SimInstant overflow"); - } - Poll::Ready(()) - } - } - }) - .await + let mut targets = duration.map_or(EarliestWaitTargets::settle(), |duration| { + EarliestWaitTargets::instant(this.borrow().instant + duration) + }); + Self::yield_wait(this, module_index, &mut targets).await; } - async fn yield_wait_for_changes( - this: &RefCell, - module_index: usize, - sensitivity_set: SensitivitySet, - timeout: Option, - ) { - if let Some(timeout) = timeout { - if timeout == SimDuration::ZERO { - return Self::yield_advance_time_or_settle(this, module_index, None).await; + fn is_extern_module_ready_to_run(&mut self, module_index: usize) -> Option { + let module = &self.extern_modules[module_index]; + let mut retval = None; + for wait_target in module.wait_targets.iter() { + retval = match (wait_target, retval) { + (WaitTarget::Settle, _) => Some(self.instant), + (WaitTarget::Instant(instant), _) if instant <= self.instant => Some(self.instant), + (WaitTarget::Instant(instant), None) => Some(instant), + (WaitTarget::Instant(instant), Some(retval)) => Some(instant.min(retval)), + (WaitTarget::Change { key, value }, retval) => { + if Self::value_changed(&mut self.state, key, SimValue::opaque(value)) { + Some(self.instant) + } else { + retval + } + } + }; + if retval == Some(self.instant) { + break; } } - let sensitivity_set = Rc::new(sensitivity_set); - let mut timeout_instant = None; - std::future::poll_fn(|cx| { - if sensitivity_set.changed.get() { - return Poll::Ready(()); - } - sensitivity_set.waker.borrow_mut().clone_from(cx.waker()); - let mut this = this.borrow_mut(); - this.wake_after_change(sensitivity_set.clone()); - if let Some(timeout) = timeout { - match this.try_wake_at_instant( - module_index, - &mut |instant| match timeout_instant { - Some(timeout_instant) => { - if instant < timeout_instant { - Some(timeout_instant) - } else { - None - } - } - None => { - timeout_instant = instant.checked_add(timeout); - timeout_instant - } - }, - cx.waker().clone(), - ) { - Ok(()) => Poll::Pending, - Err(_waker) => { - if timeout_instant.is_none() { - // don't panic in try_wait_at_instant to avoid poisoning the lock - panic!("SimInstant overflow"); - } - Poll::Ready(()) - } + retval + } + fn get_ready_to_run_set(&mut self, ready_to_run_set: &mut ReadyToRunSet) -> Option { + ready_to_run_set.clear(); + let mut retval = None; + if self.state_ready_to_run { + ready_to_run_set.state_ready_to_run = true; + retval = Some(self.instant); + } + for module_index in 0..self.extern_modules.len() { + let Some(instant) = self.is_extern_module_ready_to_run(module_index) else { + continue; + }; + if let Some(retval) = &mut retval { + match instant.cmp(retval) { + std::cmp::Ordering::Less => ready_to_run_set.clear(), + std::cmp::Ordering::Equal => {} + std::cmp::Ordering::Greater => continue, } } else { - Poll::Pending + retval = Some(instant); } - }) - .await; - this.borrow_mut().cancel_wake_after_change(&sensitivity_set); + ready_to_run_set + .extern_modules_ready_to_run + .push(module_index); + } + retval + } + fn set_instant_no_sim(&mut self, instant: SimInstant) { + self.instant = instant; + self.for_each_trace_writer_storing_error(|this, mut trace_writer_state| { + match &mut trace_writer_state { + TraceWriterState::Decls(_) | TraceWriterState::Init(_) => unreachable!(), + TraceWriterState::Running(trace_writer) => { + trace_writer.change_time_to(this.instant)?; + } + TraceWriterState::Errored(_) => {} + } + Ok(trace_writer_state) + }); } #[must_use] #[track_caller] - fn run_state_settle_cycle(&mut self) { + fn run_state_settle_cycle(&mut self) -> bool { + self.state_ready_to_run = false; self.state.setup_call(0); if self.breakpoints.is_some() { loop { @@ -2160,197 +1943,138 @@ impl SimulationImpl { .iter() .any(|i| self.state.small_slots[*i] != 0) { - self.event_queue.add_event_for_now(EventKind::State, None); + self.state_ready_to_run = true; + true + } else { + false } } #[track_caller] - fn run_extern_module(this_ref: &Rc>, module_index: usize) { - let mut this = this_ref.borrow_mut(); - let extern_module = &mut this.extern_modules[module_index]; - let waker = std::task::Waker::from(extern_module.waker.clone()); - let mut generator = if !extern_module.module_state.did_initial_settle { - let sim = extern_module.sim; - drop(this); - Box::into_pin(sim.run(ExternModuleSimulationState { - sim_impl: this_ref.clone(), - module_index, - })) - } else if let Some(generator) = extern_module.running_generator.take() { - drop(this); - generator - } else { - return; - }; - let generator = match generator - .as_mut() - .poll(&mut std::task::Context::from_waker(&waker)) - { - Poll::Ready(()) => None, - Poll::Pending => Some(generator), - }; - this = this_ref.borrow_mut(); - this.extern_modules[module_index] - .module_state - .did_initial_settle = true; - if !this.extern_modules[module_index] - .module_state - .uninitialized_ios - .is_empty() - { - panic!( - "extern module didn't initialize all outputs before \ - waiting, settling, or reading any inputs: {}", - this.extern_modules[module_index].sim.source_location - ); - } - this.extern_modules[module_index].running_generator = generator; - } - fn check_waiting_sensitivity_sets(&mut self) { - if let Some(Event { - instant: _, - kind: EventKind::State, - }) = self.event_queue.peek_first_event_for_now() - { - return; - } - let mut triggered = HashMap::<*const SensitivitySet, Rc>::default(); - for (compiled_value, (sim_value, sensitivity_sets)) in - &self.waiting_sensitivity_sets_by_compiled_value - { - if Self::value_changed( - &mut self.state, - **compiled_value, - SimValue::opaque(sim_value), - ) { - triggered.extend(sensitivity_sets.iter().map(|(&k, v)| (k, v.clone()))); - } - } - for sensitivity_set in triggered.into_values() { - sensitivity_set.changed.set(true); - sensitivity_set.waker.borrow().wake_by_ref(); - self.cancel_wake_after_change(&sensitivity_set); - } - } - fn write_traces_after_event(&mut self) { - if let Some(Event { - instant: _, - kind: EventKind::State, - }) = self.event_queue.peek_first_event_for_now() - { - return; - } - if self.main_module.did_initial_settle { - self.read_traces::(); - } else { - self.read_traces::(); - } - self.state.memory_write_log.sort_unstable(); - self.state.memory_write_log.dedup(); - self.main_module.did_initial_settle = true; - self.for_each_trace_writer_storing_error(|this, trace_writer_state| { - Ok(match trace_writer_state { - TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running( - this.init_trace_writer(trace_writer_decls.write_decls( - this.trace_decls, - this.traces.0.len(), - this.trace_memories.len(), - )?)?, - ), - TraceWriterState::Init(trace_writer) => { - TraceWriterState::Running(this.init_trace_writer(trace_writer)?) - } - TraceWriterState::Running(trace_writer) => { - TraceWriterState::Running(this.update_trace_writer(trace_writer)?) - } - TraceWriterState::Errored(e) => TraceWriterState::Errored(e), - }) - }); - self.state.memory_write_log.clear(); - } - fn write_traces_change_time_to(&mut self, new_instant: SimInstant) { - self.for_each_trace_writer_storing_error(|_this, mut trace_writer_state| { - match &mut trace_writer_state { - TraceWriterState::Decls(_) | TraceWriterState::Init(_) => unreachable!(), - TraceWriterState::Running(trace_writer) => { - trace_writer.change_time_to(new_instant)?; - } - TraceWriterState::Errored(_) => {} - } - Ok(trace_writer_state) - }); - } - #[track_caller] - fn run_until( + fn run_extern_modules_cycle( this_ref: &Rc>, - run_target: &mut dyn FnMut(SimInstant) -> Option, + generator_waker: &std::task::Waker, + extern_modules_ready_to_run: &[usize], ) { let mut this = this_ref.borrow_mut(); + for module_index in extern_modules_ready_to_run.iter().copied() { + let extern_module = &mut this.extern_modules[module_index]; + extern_module.wait_targets.clear(); + let mut generator = if !extern_module.module_state.did_initial_settle { + let sim = extern_module.sim; + drop(this); + Box::into_pin(sim.run(ExternModuleSimulationState { + sim_impl: this_ref.clone(), + module_index, + wait_for_changes_wait_targets: EarliestWaitTargets::default(), + })) + } else if let Some(generator) = extern_module.running_generator.take() { + drop(this); + generator + } else { + continue; + }; + let generator = match generator + .as_mut() + .poll(&mut std::task::Context::from_waker(generator_waker)) + { + Poll::Ready(()) => None, + Poll::Pending => Some(generator), + }; + this = this_ref.borrow_mut(); + this.extern_modules[module_index] + .module_state + .did_initial_settle = true; + if !this.extern_modules[module_index] + .module_state + .uninitialized_ios + .is_empty() + { + panic!( + "extern module didn't initialize all outputs before \ + waiting, settling, or reading any inputs: {}", + this.extern_modules[module_index].sim.source_location + ); + } + this.extern_modules[module_index].running_generator = generator; + } + } + /// clears `targets` + #[track_caller] + fn run_until(this_ref: &Rc>, run_target: SimInstant) { + let mut this = this_ref.borrow_mut(); + let mut ready_to_run_set = ReadyToRunSet::default(); + let generator_waker = this.generator_waker.clone(); assert!( this.main_module.uninitialized_ios.is_empty(), "didn't initialize all inputs", ); - this.check_waiting_sensitivity_sets(); - let mut event_queue = this.event_queue.lock(); - let Some(run_target) = run_target(event_queue.instant()) else { - drop(event_queue); - panic!("SimInstant overflowed"); - }; - let run_target = run_target.max(event_queue.instant()); + let run_target = run_target.max(this.instant); let mut settle_cycle = 0; + let mut run_extern_modules = true; loop { - if settle_cycle >= 100000 { - drop(event_queue); - panic!("settle(): took too many steps"); - } + assert!(settle_cycle < 100000, "settle(): took too many steps"); settle_cycle += 1; - let event_queue_instant = event_queue.instant(); - let Some(first_entry) = event_queue.first_entry() else { - let changed_time = event_queue_instant != run_target; - event_queue.set_instant(run_target); - drop(event_queue); - if changed_time { - this.write_traces_change_time_to(run_target); - } - return; + let next_wait_target = match this.get_ready_to_run_set(&mut ready_to_run_set) { + Some(next_wait_target) if next_wait_target <= run_target => next_wait_target, + _ => break, }; - let Event { - instant: event_instant, - kind: event_kind, - } = *first_entry.key(); - if event_instant <= event_queue_instant { - let wakers = first_entry.remove(); - drop(event_queue); - for HashableWaker(waker) in wakers { - waker.wake(); - } - match event_kind { - EventKind::State => this.run_state_settle_cycle(), - EventKind::ExternModule(module_index) => { - drop(this); - Self::run_extern_module(this_ref, module_index); - this = this_ref.borrow_mut(); - } - } - this.write_traces_after_event(); - this.check_waiting_sensitivity_sets(); - } else { - let new_instant = event_instant.min(run_target); - let changed_time = event_queue_instant != new_instant; - event_queue.set_instant(new_instant); - drop(event_queue); - if changed_time { - this.write_traces_change_time_to(new_instant); - } - if event_instant > run_target { - return; + if next_wait_target > this.instant { + settle_cycle = 0; + this.set_instant_no_sim(next_wait_target); + } + if run_extern_modules { + drop(this); + Self::run_extern_modules_cycle( + this_ref, + &generator_waker, + &ready_to_run_set.extern_modules_ready_to_run, + ); + this = this_ref.borrow_mut(); + } + if ready_to_run_set.state_ready_to_run { + if this.run_state_settle_cycle() { + // wait for clocks to settle before running extern modules again + run_extern_modules = false; + } else { + run_extern_modules = true; } } - event_queue = this.event_queue.lock(); + if this.main_module.did_initial_settle { + this.read_traces::(); + } else { + this.read_traces::(); + } + this.state.memory_write_log.sort_unstable(); + this.state.memory_write_log.dedup(); + this.main_module.did_initial_settle = true; + this.for_each_trace_writer_storing_error(|this, trace_writer_state| { + Ok(match trace_writer_state { + TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running( + this.init_trace_writer(trace_writer_decls.write_decls( + this.trace_decls, + this.traces.0.len(), + this.trace_memories.len(), + )?)?, + ), + TraceWriterState::Init(trace_writer) => { + TraceWriterState::Running(this.init_trace_writer(trace_writer)?) + } + TraceWriterState::Running(trace_writer) => { + TraceWriterState::Running(this.update_trace_writer(trace_writer)?) + } + TraceWriterState::Errored(e) => TraceWriterState::Errored(e), + }) + }); + this.state.memory_write_log.clear(); + } + if run_target > this.instant { + this.set_instant_no_sim(run_target); } } #[track_caller] fn settle(this_ref: &Rc>) { - Self::run_until(this_ref, &mut Some); + let run_target = this_ref.borrow().instant; + Self::run_until(this_ref, run_target); } fn get_module(&self, which_module: WhichModule) -> &SimulationModuleState { match which_module { @@ -2382,7 +2106,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(io, which_module); - self.event_queue.add_event_for_now(EventKind::State, None); + self.state_ready_to_run = true; match compiled_value.range.len().as_single() { Some(TypeLenSingle::SmallSlot) => { self.state.small_slots[compiled_value.range.small_slots.start] = value as _; @@ -2414,7 +2138,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(Expr::canonical(io), which_module); - self.event_queue.add_event_for_now(EventKind::State, None); + self.state_ready_to_run = true; let value: BigInt = value.into(); match compiled_value.range.len().as_single() { Some(TypeLenSingle::SmallSlot) => { @@ -2654,7 +2378,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(io, which_module); - self.event_queue.add_event_for_now(EventKind::State, None); + self.state_ready_to_run = true; assert_eq!(Expr::ty(io), SimValue::ty(value)); Self::read_write_sim_value_helper( &mut self.state, @@ -2702,7 +2426,7 @@ impl SimulationImpl { } } async fn yield_settle_if_needed( - this_ref: &RefCell, + this_ref: &Rc>, module_index: usize, v: MaybeNeedsSettle, ) -> O @@ -2711,7 +2435,7 @@ impl SimulationImpl { { match v { MaybeNeedsSettle::NeedsSettle(v) => { - Self::yield_advance_time_or_settle(this_ref, module_index, None).await; + Self::yield_advance_time_or_settle(this_ref.clone(), module_index, None).await; v.call(&mut this_ref.borrow_mut().state) } MaybeNeedsSettle::NoSettleNeeded(v) => v, @@ -3062,6 +2786,7 @@ impl Simulation { pub struct ExternModuleSimulationState { sim_impl: Rc>, module_index: usize, + wait_for_changes_wait_targets: EarliestWaitTargets, } impl fmt::Debug for ExternModuleSimulationState { @@ -3069,6 +2794,7 @@ impl fmt::Debug for ExternModuleSimulationState { let Self { sim_impl: _, module_index, + wait_for_changes_wait_targets: _, } = self; f.debug_struct("ExternModuleSimulationState") .field("sim_impl", &DebugAsDisplay("...")) @@ -3079,11 +2805,12 @@ impl fmt::Debug for ExternModuleSimulationState { impl ExternModuleSimulationState { pub async fn settle(&mut self) { - SimulationImpl::yield_advance_time_or_settle(&self.sim_impl, self.module_index, None).await + SimulationImpl::yield_advance_time_or_settle(self.sim_impl.clone(), self.module_index, None) + .await } pub async fn advance_time(&mut self, duration: SimDuration) { SimulationImpl::yield_advance_time_or_settle( - &self.sim_impl, + self.sim_impl.clone(), self.module_index, Some(duration), ) @@ -3094,17 +2821,7 @@ impl ExternModuleSimulationState { iter: I, timeout: Option, ) { - let mut sim_impl = self.sim_impl.borrow_mut(); - let mut sensitivity_set = SensitivitySet { - debug_id: sim_impl.next_sensitivity_set_debug_id, - compiled_values: HashSet::default(), - values: Vec::new(), - waker: RefCell::new(std::task::Waker::noop().clone()), - changed: Cell::new(false), - }; - sim_impl.next_sensitivity_set_debug_id = - sim_impl.next_sensitivity_set_debug_id.wrapping_add(1); - drop(sim_impl); + self.wait_for_changes_wait_targets.clear(); let which_module = WhichModule::Extern { module_index: self.module_index, }; @@ -3112,18 +2829,19 @@ impl ExternModuleSimulationState { let io = Expr::canonical(io.to_expr()); let (key, value) = self.sim_impl.borrow_mut().read(io, which_module); let value = self.settle_if_needed(value).await; - let key = Rc::new(key); - if sensitivity_set.compiled_values.insert(key.clone()) { - sensitivity_set.values.push((key, Rc::new(value))); - } + self.wait_for_changes_wait_targets + .insert(WaitTarget::Change { key, value }); } - SimulationImpl::yield_wait_for_changes( - &self.sim_impl, + if let Some(timeout) = timeout { + self.wait_for_changes_wait_targets.instant = + Some(self.sim_impl.borrow().instant + timeout); + } + SimulationImpl::yield_wait( + self.sim_impl.clone(), self.module_index, - sensitivity_set, - timeout, + &mut self.wait_for_changes_wait_targets, ) - .await + .await; } pub async fn wait_for_clock_edge(&mut self, clk: impl ToExpr) { let clk = clk.to_expr(); @@ -3140,19 +2858,6 @@ impl ExternModuleSimulationState { { SimulationImpl::yield_settle_if_needed(&self.sim_impl, self.module_index, v).await } - pub async fn fork_join(&mut self, futures: F) -> F::Output { - F::fork_join(futures, self).await - } - fn forked_state(&self) -> Self { - let Self { - ref sim_impl, - module_index, - } = *self; - Self { - sim_impl: sim_impl.clone(), - module_index, - } - } impl_simulation_methods!( async_await = (async, await), track_caller = (), @@ -3160,114 +2865,6 @@ impl ExternModuleSimulationState { ); } -struct ForkJoinImpl<'a> { - futures: Vec + 'a>>>, -} - -impl Future for ForkJoinImpl<'_> { - type Output = (); - fn poll(self: Pin<&mut Self>, cx: &mut std::task::Context<'_>) -> Poll { - let Self { futures } = self.get_mut(); - futures.retain_mut(|future| future.as_mut().poll(cx).is_pending()); - if futures.is_empty() { - Poll::Ready(()) - } else { - Poll::Pending - } - } -} - -pub trait ForkJoin { - type Output; - #[allow(async_fn_in_trait, reason = "no auto traits needed")] - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output; -} - -impl O, O, const N: usize> ForkJoin for [F; N] { - type Output = [O; N]; - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { - let mut temp = [const { None }; N]; - ForkJoinImpl { - futures: this - .into_iter() - .zip(&mut temp) - .map(|(future, temp)| -> Pin + '_>> { - Box::pin(async { *temp = Some(future(sim_state.forked_state()).await) }) - }) - .collect(), - } - .await; - temp.map(|output| output.expect("set to Some above")) - } -} - -impl O, O> ForkJoin for Vec { - type Output = Vec; - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { - let mut temp = Vec::with_capacity(this.len()); - for _ in 0..this.len() { - temp.push(None); - } - ForkJoinImpl { - futures: this - .into_iter() - .zip(&mut temp) - .map(|(future, temp)| -> Pin + '_>> { - Box::pin(async { *temp = Some(future(sim_state.forked_state()).await) }) - }) - .collect(), - } - .await; - temp.into_iter() - .map(|output| output.expect("set to Some above")) - .collect() - } -} - -impl O, O> ForkJoin for Box<[F]> { - type Output = Box<[O]>; - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { - Vec::fork_join(this.into(), sim_state) - .await - .into_boxed_slice() - } -} - -impl ForkJoin for Box { - type Output = Box; - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { - Box::new(T::fork_join(*this, sim_state).await) - } -} - -macro_rules! impl_fork_join_tuples { - (@impl $(($f:ident: $F:ident => $o:ident: $O:ident)),*) => { - impl<$($F: AsyncFnOnce(ExternModuleSimulationState) -> $O, $O,)*> ForkJoin for ($($F,)*) { - type Output = ($($O,)*); - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { - #![allow(unused_variables)] - let ($($f,)*) = this; - $(let mut $o = None;)* - ForkJoinImpl { - futures: vec![ - $(Box::pin(async { $o = Some($f(sim_state.forked_state()).await) }),)* - ], - }.await; - ($($o.expect("set to Some above"),)*) - } - } - }; - (($($first:tt)*) $(, $rest:tt)* $(,)?) => { - impl_fork_join_tuples!(@impl ($($first)*) $(, $rest)*); - impl_fork_join_tuples!($($rest),*); - }; - () => { - impl_fork_join_tuples!(@impl); - }; -} - -impl_fork_join_tuples!((f0: F0 => o0: O0), (f1: F1 => o1: O1), (f2: F2 => o2: O2), (f3: F3 => o3: O3), (f4: F4 => o4: O4), (f5: F5 => o5: O5), (f6: F6 => o6: O6), (f7: F7 => o7: O7), (f8: F8 => o8: O8), (f9: F9 => o9: O9), (f10: F10 => o10: O10), (f11: F11 => o11: O11),); - pub trait ExternModuleSimGenerator: Clone + Eq + Hash + Any + Send + Sync + fmt::Debug { fn run<'a>(&'a self, sim: ExternModuleSimulationState) -> impl IntoFuture + 'a; } diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs index 148cb642..8802fd4b 100644 --- a/crates/fayalite/tests/hdl_types.rs +++ b/crates/fayalite/tests/hdl_types.rs @@ -4,6 +4,7 @@ use fayalite::{ bundle::BundleType, enum_::EnumType, int::{BoolOrIntType, IntType}, + phantom_const::PhantomConst, prelude::*, ty::StaticType, }; @@ -196,21 +197,3 @@ check_bounds!(CheckBoundsTTT2<#[a, Type] A: BundleType +, #[b, Type] B: Type +, check_bounds!(CheckBoundsTTT3<#[a, Type] A: EnumType +, #[b, Type] B: Type +, #[c, Type] C: Type +>); check_bounds!(CheckBoundsTTT4<#[a, Type] A: IntType +, #[b, Type] B: Type +, #[c, Type] C: Type +>); check_bounds!(CheckBoundsTTT5<#[a, Type] A: StaticType +, #[b, Type] B: Type +, #[c, Type] C: Type +>); - -#[derive(Clone, PartialEq, Eq, Hash, Debug, serde::Serialize, serde::Deserialize)] -pub struct MyPhantomConstInner { - pub a: usize, - pub b: UInt, -} - -#[hdl(outline_generated, get(|v| v.a))] -pub type GetA> = DynSize; - -#[hdl(outline_generated, get(|v| v.b))] -pub type GetB> = UInt; - -#[hdl(outline_generated, no_static)] -pub struct MyTypeWithPhantomConstParameter> { - pub a: ArrayType>, - pub b: HdlOption>, -} diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index b055ffa0..b9c6a80b 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -3,7 +3,7 @@ use fayalite::{ memory::{ReadStruct, ReadWriteStruct, WriteStruct}, - module::{instance_with_loc, memory_with_init_and_loc, reg_builder_with_loc}, + module::{instance_with_loc, reg_builder_with_loc}, prelude::*, reset::ResetType, sim::vcd::VcdWriterDecls, @@ -1261,310 +1261,6 @@ fn test_memories3() { } } -#[hdl_module(outline_generated)] -pub fn many_memories() { - #[hdl] - let r: Array>, 8> = m.input(); - #[hdl] - let w: Array>, 8> = m.input(); - for (mem_index, (r, w)) in r.into_iter().zip(w).enumerate() { - let mut mem = memory_with_init_and_loc( - &format!("mem_{mem_index}"), - (0..16) - .map(|bit_index| mem_index.pow(5).to_expr()[bit_index]) - .collect::>(), - SourceLocation::caller(), - ); - connect_any(mem.new_read_port(), r); - connect_any(mem.new_write_port(), w); - } -} - -#[hdl] -#[test] -fn test_many_memories() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(many_memories()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - for r in sim.io().r { - sim.write_clock(r.clk, false); - } - for w in sim.io().w { - sim.write_clock(w.clk, false); - } - #[hdl(cmp_eq)] - struct IO { - r_addr: UInt<4>, - r_en: Bool, - r_data: Array, - w_addr: UInt<4>, - w_en: Bool, - w_data: Array, - w_mask: Array, - } - let io_cycles = [ - #[hdl(sim)] - IO { - r_addr: 0_hdl_u4, - r_en: false, - r_data: [false; 8], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [false; 8], - }, - #[hdl(sim)] - IO { - r_addr: 0_hdl_u4, - r_en: true, - r_data: [false, true, false, true, false, true, false, true], - w_addr: 0_hdl_u4, - w_en: true, - w_data: [true; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 0_hdl_u4, - r_en: true, - r_data: [true; 8], - w_addr: 0_hdl_u4, - w_en: true, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 0_hdl_u4, - r_en: true, - r_data: [false; 8], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 1_hdl_u4, - r_en: true, - r_data: [false, false, false, true, false, false, false, true], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 2_hdl_u4, - r_en: true, - r_data: [false, false, false, false, false, true, false, true], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 3_hdl_u4, - r_en: true, - r_data: [false, false, false, false, false, false, false, false], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 4_hdl_u4, - r_en: true, - r_data: [false, false, false, true, false, true, false, false], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 5_hdl_u4, - r_en: true, - r_data: [false, false, true, true, false, true, true, true], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 6_hdl_u4, - r_en: true, - r_data: [false, false, false, true, false, false, true, false], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 7_hdl_u4, - r_en: true, - r_data: [false, false, false, true, false, false, false, true], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 8_hdl_u4, - r_en: true, - r_data: [false, false, false, false, false, false, false, true], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 9_hdl_u4, - r_en: true, - r_data: [false, false, false, false, false, false, true, false], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 0xA_hdl_u4, - r_en: true, - r_data: [false, false, false, false, true, true, true, false], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 0xB_hdl_u4, - r_en: true, - r_data: [false, false, false, false, false, true, true, false], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 0xC_hdl_u4, - r_en: true, - r_data: [false, false, false, false, false, false, true, false], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 0xD_hdl_u4, - r_en: true, - r_data: [false, false, false, false, false, false, false, false], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 0xE_hdl_u4, - r_en: true, - r_data: [false, false, false, false, false, false, false, true], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - #[hdl(sim)] - IO { - r_addr: 0xF_hdl_u4, - r_en: true, - r_data: [false, false, false, false, false, false, false, false], - w_addr: 0_hdl_u4, - w_en: false, - w_data: [false; 8], - w_mask: [true; 8], - }, - ]; - for (cycle, expected) in io_cycles.into_iter().enumerate() { - #[hdl(sim)] - let IO { - r_addr, - r_en, - r_data: _, - w_addr, - w_en, - w_data, - w_mask, - } = expected; - for (((r, w), w_data), w_mask) in sim - .io() - .r - .into_iter() - .zip(sim.io().w) - .zip(w_data.iter()) - .zip(w_mask.iter()) - { - sim.write(r.addr, &r_addr); - sim.write(r.en, &r_en); - sim.write(w.addr, &w_addr); - sim.write(w.en, &w_en); - sim.write(w.data, w_data); - sim.write(w.mask, w_mask); - } - let io = #[hdl(sim)] - IO { - r_addr, - r_en, - r_data: std::array::from_fn(|i| sim.read(sim.io().r[i].data)), - w_addr, - w_en, - w_data, - w_mask, - }; - assert_eq!( - expected, - io, - "vcd:\n{}\ncycle: {cycle}", - String::from_utf8(writer.take()).unwrap(), - ); - sim.advance_time(SimDuration::from_micros(1)); - for r in sim.io().r { - sim.write_clock(r.clk, true); - } - for w in sim.io().w { - sim.write_clock(w.clk, true); - } - sim.advance_time(SimDuration::from_micros(1)); - for r in sim.io().r { - sim.write_clock(r.clk, false); - } - for w in sim.io().w { - sim.write_clock(w.clk, false); - } - } - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/many_memories.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/many_memories.txt") { - panic!(); - } -} - #[hdl_module(outline_generated)] pub fn duplicate_names() { #[hdl] @@ -2026,85 +1722,3 @@ fn test_sim_only_connects() { panic!(); } } - -#[hdl_module(outline_generated, extern)] -pub fn sim_fork_join() -where - ConstUsize: KnownSize, -{ - #[hdl] - let clocks: Array = m.input(); - #[hdl] - let outputs: Array, N> = m.output(); - m.extern_module_simulation_fn((clocks, outputs), |(clocks, outputs), mut sim| async move { - sim.write(outputs, [0u8; N]).await; - loop { - sim.fork_join( - clocks - .into_iter() - .zip(outputs) - .map(|(clock, output)| { - move |mut sim: ExternModuleSimulationState| async move { - sim.wait_for_clock_edge(clock).await; - let v = sim - .read_bool_or_int(output) - .await - .to_bigint() - .try_into() - .expect("known to be in range"); - sim.write(output, 1u8.wrapping_add(v)).await; - } - }) - .collect::>(), - ) - .await; - } - }); -} - -#[test] -fn test_sim_fork_join() { - let _n = SourceLocation::normalize_files_for_tests(); - const N: usize = 3; - let mut sim = Simulation::new(sim_fork_join::()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - sim.write(sim.io().clocks, [false; N]); - let mut clocks_triggered = [false; N]; - let mut expected = [0u8; N]; - for i0 in 0..N { - for i1 in 0..N { - for i2 in 0..N { - for i3 in 0..N { - let indexes = [i0, i1, i2, i3]; - for i in indexes { - sim.advance_time(SimDuration::from_micros(1)); - sim.write(sim.io().clocks[i], true); - sim.advance_time(SimDuration::from_micros(1)); - sim.write(sim.io().clocks[i], false); - if !clocks_triggered[i] { - expected[i] = expected[i].wrapping_add(1); - } - clocks_triggered[i] = true; - if clocks_triggered == [true; N] { - clocks_triggered = [false; N]; - } - let output = sim.read(sim.io().outputs); - assert_eq!(output, expected.to_sim_value(), "indexes={indexes:?} i={i}"); - } - } - } - } - } - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/sim_fork_join.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/sim_fork_join.txt") { - panic!(); - } -} diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt index 2f25f359..12e86f30 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.txt +++ b/crates/fayalite/tests/sim/expected/array_rw.txt @@ -828,6 +828,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "array_rw", children: [ @@ -1698,12 +1699,7 @@ Simulation { }, ), ], + instant: 34 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 34 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt index 47997e5b..58b2d20f 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt @@ -124,6 +124,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "conditional_assignment_last", children: [ @@ -176,12 +177,7 @@ Simulation { }, ), ], + instant: 2 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 2 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt index ac6c052b..182ed84f 100644 --- a/crates/fayalite/tests/sim/expected/connect_const.txt +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -100,6 +100,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "connect_const", children: [ @@ -129,12 +130,7 @@ Simulation { ], trace_memories: {}, trace_writers: [], + instant: 0 s, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 0 s, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt index 999f414c..f56a6b4e 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -143,6 +143,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "connect_const_reset", children: [ @@ -196,12 +197,7 @@ Simulation { }, ), ], + instant: 1 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 1 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index 7a43720e..8c8809ab 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -263,6 +263,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "counter", children: [ @@ -328,7 +329,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x0, + last_state: 0x1, }, SimTrace { id: TraceScalarId(1), @@ -354,7 +355,7 @@ Simulation { ty: UInt<4>, }, state: 0x3, - last_state: 0x2, + last_state: 0x3, }, ], trace_memories: {}, @@ -367,14 +368,9 @@ Simulation { }, ), ], + instant: 66 μs, clocks_triggered: [ StatePartIndex(1), ], - event_queue: EventQueue(EventQueueData { - instant: 66 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_async.vcd b/crates/fayalite/tests/sim/expected/counter_async.vcd index dab690f5..a4b2ee91 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.vcd +++ b/crates/fayalite/tests/sim/expected/counter_async.vcd @@ -26,192 +26,192 @@ b11 $ 0! #3000000 1! -b100 # b100 $ +b100 # #4000000 0! #5000000 1! -b101 # b101 $ +b101 # #6000000 0! #7000000 1! -b110 # b110 $ +b110 # #8000000 0! #9000000 1! -b111 # b111 $ +b111 # #10000000 0! #11000000 1! -b1000 # b1000 $ +b1000 # #12000000 0! #13000000 1! -b1001 # b1001 $ +b1001 # #14000000 0! #15000000 1! -b1010 # b1010 $ +b1010 # #16000000 0! #17000000 1! -b1011 # b1011 $ +b1011 # #18000000 0! #19000000 1! -b1100 # b1100 $ +b1100 # #20000000 0! #21000000 1! -b1101 # b1101 $ +b1101 # #22000000 0! #23000000 1! -b1110 # b1110 $ +b1110 # #24000000 0! #25000000 1! -b1111 # b1111 $ +b1111 # #26000000 0! #27000000 1! -b0 # b0 $ +b0 # #28000000 0! #29000000 1! -b1 # b1 $ +b1 # #30000000 0! #31000000 1! -b10 # b10 $ +b10 # #32000000 0! #33000000 1! -b11 # b11 $ +b11 # #34000000 0! #35000000 1! -b100 # b100 $ +b100 # #36000000 0! #37000000 1! -b101 # b101 $ +b101 # #38000000 0! #39000000 1! -b110 # b110 $ +b110 # #40000000 0! #41000000 1! -b111 # b111 $ +b111 # #42000000 0! #43000000 1! -b1000 # b1000 $ +b1000 # #44000000 0! #45000000 1! -b1001 # b1001 $ +b1001 # #46000000 0! #47000000 1! -b1010 # b1010 $ +b1010 # #48000000 0! #49000000 1! -b1011 # b1011 $ +b1011 # #50000000 0! #51000000 1! -b1100 # b1100 $ +b1100 # #52000000 0! #53000000 1! -b1101 # b1101 $ +b1101 # #54000000 0! #55000000 1! -b1110 # b1110 $ +b1110 # #56000000 0! #57000000 1! -b1111 # b1111 $ +b1111 # #58000000 0! #59000000 1! -b0 # b0 $ +b0 # #60000000 0! #61000000 1! -b1 # b1 $ +b1 # #62000000 0! #63000000 1! -b10 # b10 $ +b10 # #64000000 0! #65000000 1! -b11 # b11 $ +b11 # #66000000 diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index b96ce5fd..1d975b3d 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -244,6 +244,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "counter", children: [ @@ -309,7 +310,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x0, + last_state: 0x1, }, SimTrace { id: TraceScalarId(1), @@ -335,7 +336,7 @@ Simulation { ty: UInt<4>, }, state: 0x3, - last_state: 0x2, + last_state: 0x3, }, ], trace_memories: {}, @@ -348,14 +349,9 @@ Simulation { }, ), ], + instant: 66 μs, clocks_triggered: [ StatePartIndex(1), ], - event_queue: EventQueue(EventQueueData { - instant: 66 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_sync.vcd b/crates/fayalite/tests/sim/expected/counter_sync.vcd index 9504a30a..bf6249e4 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.vcd +++ b/crates/fayalite/tests/sim/expected/counter_sync.vcd @@ -16,199 +16,199 @@ b0 $ $end #1000000 1! -b11 # b11 $ +b11 # 0" #2000000 0! #3000000 1! -b100 # b100 $ +b100 # #4000000 0! #5000000 1! -b101 # b101 $ +b101 # #6000000 0! #7000000 1! -b110 # b110 $ +b110 # #8000000 0! #9000000 1! -b111 # b111 $ +b111 # #10000000 0! #11000000 1! -b1000 # b1000 $ +b1000 # #12000000 0! #13000000 1! -b1001 # b1001 $ +b1001 # #14000000 0! #15000000 1! -b1010 # b1010 $ +b1010 # #16000000 0! #17000000 1! -b1011 # b1011 $ +b1011 # #18000000 0! #19000000 1! -b1100 # b1100 $ +b1100 # #20000000 0! #21000000 1! -b1101 # b1101 $ +b1101 # #22000000 0! #23000000 1! -b1110 # b1110 $ +b1110 # #24000000 0! #25000000 1! -b1111 # b1111 $ +b1111 # #26000000 0! #27000000 1! -b0 # b0 $ +b0 # #28000000 0! #29000000 1! -b1 # b1 $ +b1 # #30000000 0! #31000000 1! -b10 # b10 $ +b10 # #32000000 0! #33000000 1! -b11 # b11 $ +b11 # #34000000 0! #35000000 1! -b100 # b100 $ +b100 # #36000000 0! #37000000 1! -b101 # b101 $ +b101 # #38000000 0! #39000000 1! -b110 # b110 $ +b110 # #40000000 0! #41000000 1! -b111 # b111 $ +b111 # #42000000 0! #43000000 1! -b1000 # b1000 $ +b1000 # #44000000 0! #45000000 1! -b1001 # b1001 $ +b1001 # #46000000 0! #47000000 1! -b1010 # b1010 $ +b1010 # #48000000 0! #49000000 1! -b1011 # b1011 $ +b1011 # #50000000 0! #51000000 1! -b1100 # b1100 $ +b1100 # #52000000 0! #53000000 1! -b1101 # b1101 $ +b1101 # #54000000 0! #55000000 1! -b1110 # b1110 $ +b1110 # #56000000 0! #57000000 1! -b1111 # b1111 $ +b1111 # #58000000 0! #59000000 1! -b0 # b0 $ +b0 # #60000000 0! #61000000 1! -b1 # b1 $ +b1 # #62000000 0! #63000000 1! -b10 # b10 $ +b10 # #64000000 0! #65000000 1! -b11 # b11 $ +b11 # #66000000 diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt index e127210b..4c54aa85 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.txt +++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt @@ -104,6 +104,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "duplicate_names", children: [ @@ -159,12 +160,7 @@ Simulation { }, ), ], + instant: 1 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 1 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index eeef867d..4850a215 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1456,6 +1456,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "enums", children: [ @@ -1743,7 +1744,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x0, + last_state: 0x1, }, SimTrace { id: TraceScalarId(1), @@ -1923,14 +1924,9 @@ Simulation { }, ), ], + instant: 16 μs, clocks_triggered: [ StatePartIndex(3), ], - event_queue: EventQueue(EventQueueData { - instant: 16 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt index 03349409..e09a7671 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.txt +++ b/crates/fayalite/tests/sim/expected/extern_module.txt @@ -186,8 +186,14 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Instant( + 20.500000000000 μs, + ), + }, }, ], + state_ready_to_run: false, trace_decls: TraceModule { name: "extern_module", children: [ @@ -241,14 +247,7 @@ Simulation { }, ), ], + instant: 20 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 20 μs, - events: { - Event { instant: 20.500000000000 μs, kind: ExternModule(0) }: 1, - }, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module.vcd b/crates/fayalite/tests/sim/expected/extern_module.vcd index 5d6a0bc9..e026a50c 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.vcd +++ b/crates/fayalite/tests/sim/expected/extern_module.vcd @@ -6,9 +6,8 @@ $upscope $end $enddefinitions $end $dumpvars 0! -0" -$end 1" +$end #500000 #1500000 0" diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt index 3d7cfaef..1023b2ba 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.txt +++ b/crates/fayalite/tests/sim/expected/extern_module2.txt @@ -234,8 +234,55 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + }, + }, }, ], + state_ready_to_run: false, trace_decls: TraceModule { name: "extern_module2", children: [ @@ -309,113 +356,7 @@ Simulation { }, ), ], + instant: 60 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 60 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 59, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 59, - .. - }, - }, - ), - }, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module2.vcd b/crates/fayalite/tests/sim/expected/extern_module2.vcd index 42045679..464f4bd4 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.vcd +++ b/crates/fayalite/tests/sim/expected/extern_module2.vcd @@ -8,9 +8,8 @@ $enddefinitions $end $dumpvars 1! 0" -b0 # -$end b1001000 # +$end #1000000 1" b1100101 # diff --git a/crates/fayalite/tests/sim/expected/many_memories.txt b/crates/fayalite/tests/sim/expected/many_memories.txt deleted file mode 100644 index f311cf7e..00000000 --- a/crates/fayalite/tests/sim/expected/many_memories.txt +++ /dev/null @@ -1,7786 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 96, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: UInt<4>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - big_slots: StatePartLayout { - len: 160, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].mask", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].mask", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].mask", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].mask", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].mask", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].mask", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].mask", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].mask", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.mask", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.mask", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.mask", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.mask", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.mask", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.mask", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.mask", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.data", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.mask", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 8, - debug_data: [ - (), - (), - (), - (), - (), - (), - (), - (), - ], - layout_data: [ - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x0, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x0, - [0x6]: 0x0, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x0, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x1, - [0x1]: 0x0, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x0, - [0x6]: 0x0, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x0, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x0, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x1, - [0x6]: 0x0, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x0, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x1, - [0x1]: 0x1, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x1, - [0x5]: 0x1, - [0x6]: 0x1, - [0x7]: 0x1, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x0, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x0, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x0, - [0x6]: 0x0, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x1, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x1, - [0x1]: 0x0, - [0x2]: 0x1, - [0x3]: 0x0, - [0x4]: 0x1, - [0x5]: 0x1, - [0x6]: 0x0, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x1, - [0xb]: 0x1, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x0, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x1, - [0x6]: 0x1, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x1, - [0xa]: 0x1, - [0xb]: 0x1, - [0xc]: 0x1, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x1, - [0x1]: 0x1, - [0x2]: 0x1, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x1, - [0x6]: 0x0, - [0x7]: 0x1, - [0x8]: 0x1, - [0x9]: 0x0, - [0xa]: 0x0, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x1, - [0xf]: 0x0, - ], - }, - ], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:8:1 - 0: Copy { - dest: StatePartIndex(153), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.addr", ty: UInt<4> }, - src: StatePartIndex(67), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].addr", ty: UInt<4> }, - }, - 1: Copy { - dest: StatePartIndex(154), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.en", ty: Bool }, - src: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].en", ty: Bool }, - }, - 2: Copy { - dest: StatePartIndex(155), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.clk", ty: Clock }, - src: StatePartIndex(69), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].clk", ty: Clock }, - }, - 3: Copy { - dest: StatePartIndex(156), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.data", ty: Bool }, - src: StatePartIndex(70), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].data", ty: Bool }, - }, - 4: Copy { - dest: StatePartIndex(157), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.mask", ty: Bool }, - src: StatePartIndex(71), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[7].mask", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 5: Copy { - dest: StatePartIndex(151), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.clk", ty: Clock }, - src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].clk", ty: Clock }, - }, - 6: Copy { - dest: StatePartIndex(150), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.en", ty: Bool }, - src: StatePartIndex(29), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].en", ty: Bool }, - }, - 7: Copy { - dest: StatePartIndex(149), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.addr", ty: UInt<4> }, - src: StatePartIndex(28), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].addr", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 8: Copy { - dest: StatePartIndex(142), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.addr", ty: UInt<4> }, - src: StatePartIndex(62), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].addr", ty: UInt<4> }, - }, - 9: Copy { - dest: StatePartIndex(143), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.en", ty: Bool }, - src: StatePartIndex(63), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].en", ty: Bool }, - }, - 10: Copy { - dest: StatePartIndex(144), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.clk", ty: Clock }, - src: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].clk", ty: Clock }, - }, - 11: Copy { - dest: StatePartIndex(145), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.data", ty: Bool }, - src: StatePartIndex(65), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].data", ty: Bool }, - }, - 12: Copy { - dest: StatePartIndex(146), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.mask", ty: Bool }, - src: StatePartIndex(66), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[6].mask", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 13: Copy { - dest: StatePartIndex(140), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.clk", ty: Clock }, - src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].clk", ty: Clock }, - }, - 14: Copy { - dest: StatePartIndex(139), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.en", ty: Bool }, - src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].en", ty: Bool }, - }, - 15: Copy { - dest: StatePartIndex(138), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.addr", ty: UInt<4> }, - src: StatePartIndex(24), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].addr", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 16: Copy { - dest: StatePartIndex(131), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.addr", ty: UInt<4> }, - src: StatePartIndex(57), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].addr", ty: UInt<4> }, - }, - 17: Copy { - dest: StatePartIndex(132), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.en", ty: Bool }, - src: StatePartIndex(58), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].en", ty: Bool }, - }, - 18: Copy { - dest: StatePartIndex(133), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.clk", ty: Clock }, - src: StatePartIndex(59), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].clk", ty: Clock }, - }, - 19: Copy { - dest: StatePartIndex(134), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.data", ty: Bool }, - src: StatePartIndex(60), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].data", ty: Bool }, - }, - 20: Copy { - dest: StatePartIndex(135), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.mask", ty: Bool }, - src: StatePartIndex(61), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[5].mask", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 21: Copy { - dest: StatePartIndex(129), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.clk", ty: Clock }, - src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].clk", ty: Clock }, - }, - 22: Copy { - dest: StatePartIndex(128), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.en", ty: Bool }, - src: StatePartIndex(21), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].en", ty: Bool }, - }, - 23: Copy { - dest: StatePartIndex(127), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.addr", ty: UInt<4> }, - src: StatePartIndex(20), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].addr", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 24: Copy { - dest: StatePartIndex(120), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.addr", ty: UInt<4> }, - src: StatePartIndex(52), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].addr", ty: UInt<4> }, - }, - 25: Copy { - dest: StatePartIndex(121), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.en", ty: Bool }, - src: StatePartIndex(53), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].en", ty: Bool }, - }, - 26: Copy { - dest: StatePartIndex(122), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.clk", ty: Clock }, - src: StatePartIndex(54), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].clk", ty: Clock }, - }, - 27: Copy { - dest: StatePartIndex(123), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.data", ty: Bool }, - src: StatePartIndex(55), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].data", ty: Bool }, - }, - 28: Copy { - dest: StatePartIndex(124), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.mask", ty: Bool }, - src: StatePartIndex(56), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[4].mask", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 29: Copy { - dest: StatePartIndex(118), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.clk", ty: Clock }, - src: StatePartIndex(18), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].clk", ty: Clock }, - }, - 30: Copy { - dest: StatePartIndex(117), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.en", ty: Bool }, - src: StatePartIndex(17), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].en", ty: Bool }, - }, - 31: Copy { - dest: StatePartIndex(116), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.addr", ty: UInt<4> }, - src: StatePartIndex(16), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].addr", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 32: Copy { - dest: StatePartIndex(109), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.addr", ty: UInt<4> }, - src: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].addr", ty: UInt<4> }, - }, - 33: Copy { - dest: StatePartIndex(110), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.en", ty: Bool }, - src: StatePartIndex(48), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].en", ty: Bool }, - }, - 34: Copy { - dest: StatePartIndex(111), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.clk", ty: Clock }, - src: StatePartIndex(49), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].clk", ty: Clock }, - }, - 35: Copy { - dest: StatePartIndex(112), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.data", ty: Bool }, - src: StatePartIndex(50), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].data", ty: Bool }, - }, - 36: Copy { - dest: StatePartIndex(113), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.mask", ty: Bool }, - src: StatePartIndex(51), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[3].mask", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 37: Copy { - dest: StatePartIndex(107), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.clk", ty: Clock }, - src: StatePartIndex(14), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].clk", ty: Clock }, - }, - 38: Copy { - dest: StatePartIndex(106), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.en", ty: Bool }, - src: StatePartIndex(13), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].en", ty: Bool }, - }, - 39: Copy { - dest: StatePartIndex(105), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.addr", ty: UInt<4> }, - src: StatePartIndex(12), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].addr", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 40: Copy { - dest: StatePartIndex(98), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.addr", ty: UInt<4> }, - src: StatePartIndex(42), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].addr", ty: UInt<4> }, - }, - 41: Copy { - dest: StatePartIndex(99), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.en", ty: Bool }, - src: StatePartIndex(43), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].en", ty: Bool }, - }, - 42: Copy { - dest: StatePartIndex(100), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.clk", ty: Clock }, - src: StatePartIndex(44), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].clk", ty: Clock }, - }, - 43: Copy { - dest: StatePartIndex(101), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.data", ty: Bool }, - src: StatePartIndex(45), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].data", ty: Bool }, - }, - 44: Copy { - dest: StatePartIndex(102), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.mask", ty: Bool }, - src: StatePartIndex(46), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[2].mask", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 45: Copy { - dest: StatePartIndex(96), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.clk", ty: Clock }, - src: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].clk", ty: Clock }, - }, - 46: Copy { - dest: StatePartIndex(95), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.en", ty: Bool }, - src: StatePartIndex(9), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].en", ty: Bool }, - }, - 47: Copy { - dest: StatePartIndex(94), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.addr", ty: UInt<4> }, - src: StatePartIndex(8), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].addr", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 48: Copy { - dest: StatePartIndex(87), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.addr", ty: UInt<4> }, - src: StatePartIndex(37), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].addr", ty: UInt<4> }, - }, - 49: Copy { - dest: StatePartIndex(88), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.en", ty: Bool }, - src: StatePartIndex(38), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].en", ty: Bool }, - }, - 50: Copy { - dest: StatePartIndex(89), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.clk", ty: Clock }, - src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].clk", ty: Clock }, - }, - 51: Copy { - dest: StatePartIndex(90), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.data", ty: Bool }, - src: StatePartIndex(40), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].data", ty: Bool }, - }, - 52: Copy { - dest: StatePartIndex(91), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.mask", ty: Bool }, - src: StatePartIndex(41), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[1].mask", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 53: Copy { - dest: StatePartIndex(85), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.clk", ty: Clock }, - src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].clk", ty: Clock }, - }, - 54: Copy { - dest: StatePartIndex(84), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.en", ty: Bool }, - src: StatePartIndex(5), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].en", ty: Bool }, - }, - 55: Copy { - dest: StatePartIndex(83), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.addr", ty: UInt<4> }, - src: StatePartIndex(4), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].addr", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:8:1 - 56: Copy { - dest: StatePartIndex(76), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.addr", ty: UInt<4> }, - src: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].addr", ty: UInt<4> }, - }, - 57: Copy { - dest: StatePartIndex(77), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.en", ty: Bool }, - src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].en", ty: Bool }, - }, - 58: Copy { - dest: StatePartIndex(78), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.clk", ty: Clock }, - src: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].clk", ty: Clock }, - }, - 59: Copy { - dest: StatePartIndex(79), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.data", ty: Bool }, - src: StatePartIndex(35), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].data", ty: Bool }, - }, - 60: Copy { - dest: StatePartIndex(80), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.mask", ty: Bool }, - src: StatePartIndex(36), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::w[0].mask", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 61: Copy { - dest: StatePartIndex(74), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.clk", ty: Clock }, - src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].clk", ty: Clock }, - }, - 62: Copy { - dest: StatePartIndex(73), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.en", ty: Bool }, - src: StatePartIndex(1), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].en", ty: Bool }, - }, - 63: Copy { - dest: StatePartIndex(72), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.addr", ty: UInt<4> }, - src: StatePartIndex(0), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].addr", ty: UInt<4> }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 64: CastBigToArrayIndex { - dest: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(153), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.addr", ty: UInt<4> }, - }, - 65: IsNonZeroDestIsSmall { - dest: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(154), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.en", ty: Bool }, - }, - 66: IsNonZeroDestIsSmall { - dest: StatePartIndex(91), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(155), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.clk", ty: Clock }, - }, - 67: AndSmall { - dest: StatePartIndex(90), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(91), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(89), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 68: CastBigToArrayIndex { - dest: StatePartIndex(88), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(149), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.addr", ty: UInt<4> }, - }, - 69: IsNonZeroDestIsSmall { - dest: StatePartIndex(87), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(150), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.en", ty: Bool }, - }, - 70: BranchIfSmallZero { - target: 73, - value: StatePartIndex(87), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 71: MemoryReadUInt { - dest: StatePartIndex(152), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data", ty: Bool }, - memory: StatePartIndex(7), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x1, - // [0x2]: 0x1, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x1, - // [0x6]: 0x0, - // [0x7]: 0x1, - // [0x8]: 0x1, - // [0x9]: 0x0, - // [0xa]: 0x0, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x1, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(88), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 72: Branch { - target: 74, - }, - 73: Const { - dest: StatePartIndex(152), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data", ty: Bool }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 74: Copy { - dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[7].data", ty: Bool }, - src: StatePartIndex(152), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.data", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 75: IsNonZeroDestIsSmall { - dest: StatePartIndex(86), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(151), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::r0.clk", ty: Clock }, - }, - 76: AndSmall { - dest: StatePartIndex(85), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(86), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(84), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 77: CastBigToArrayIndex { - dest: StatePartIndex(81), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(142), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.addr", ty: UInt<4> }, - }, - 78: IsNonZeroDestIsSmall { - dest: StatePartIndex(80), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(143), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.en", ty: Bool }, - }, - 79: IsNonZeroDestIsSmall { - dest: StatePartIndex(79), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(144), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.clk", ty: Clock }, - }, - 80: AndSmall { - dest: StatePartIndex(78), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(79), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(77), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 81: CastBigToArrayIndex { - dest: StatePartIndex(76), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(138), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.addr", ty: UInt<4> }, - }, - 82: IsNonZeroDestIsSmall { - dest: StatePartIndex(75), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(139), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.en", ty: Bool }, - }, - 83: BranchIfSmallZero { - target: 86, - value: StatePartIndex(75), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 84: MemoryReadUInt { - dest: StatePartIndex(141), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data", ty: Bool }, - memory: StatePartIndex(6), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x1, - // [0x6]: 0x1, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x1, - // [0xa]: 0x1, - // [0xb]: 0x1, - // [0xc]: 0x1, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(76), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 85: Branch { - target: 87, - }, - 86: Const { - dest: StatePartIndex(141), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data", ty: Bool }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 87: Copy { - dest: StatePartIndex(27), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[6].data", ty: Bool }, - src: StatePartIndex(141), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.data", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 88: IsNonZeroDestIsSmall { - dest: StatePartIndex(74), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(140), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::r0.clk", ty: Clock }, - }, - 89: AndSmall { - dest: StatePartIndex(73), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(74), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(72), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 90: CastBigToArrayIndex { - dest: StatePartIndex(69), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(131), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.addr", ty: UInt<4> }, - }, - 91: IsNonZeroDestIsSmall { - dest: StatePartIndex(68), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(132), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.en", ty: Bool }, - }, - 92: IsNonZeroDestIsSmall { - dest: StatePartIndex(67), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(133), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.clk", ty: Clock }, - }, - 93: AndSmall { - dest: StatePartIndex(66), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(67), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(65), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 94: CastBigToArrayIndex { - dest: StatePartIndex(64), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(127), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.addr", ty: UInt<4> }, - }, - 95: IsNonZeroDestIsSmall { - dest: StatePartIndex(63), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(128), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.en", ty: Bool }, - }, - 96: BranchIfSmallZero { - target: 99, - value: StatePartIndex(63), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 97: MemoryReadUInt { - dest: StatePartIndex(130), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data", ty: Bool }, - memory: StatePartIndex(5), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x1, - // [0x3]: 0x0, - // [0x4]: 0x1, - // [0x5]: 0x1, - // [0x6]: 0x0, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x1, - // [0xb]: 0x1, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(64), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 98: Branch { - target: 100, - }, - 99: Const { - dest: StatePartIndex(130), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data", ty: Bool }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 100: Copy { - dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[5].data", ty: Bool }, - src: StatePartIndex(130), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.data", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 101: IsNonZeroDestIsSmall { - dest: StatePartIndex(62), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(129), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::r0.clk", ty: Clock }, - }, - 102: AndSmall { - dest: StatePartIndex(61), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(62), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(60), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 103: CastBigToArrayIndex { - dest: StatePartIndex(57), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(120), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.addr", ty: UInt<4> }, - }, - 104: IsNonZeroDestIsSmall { - dest: StatePartIndex(56), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(121), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.en", ty: Bool }, - }, - 105: IsNonZeroDestIsSmall { - dest: StatePartIndex(55), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(122), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.clk", ty: Clock }, - }, - 106: AndSmall { - dest: StatePartIndex(54), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(55), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(53), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 107: CastBigToArrayIndex { - dest: StatePartIndex(52), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(116), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.addr", ty: UInt<4> }, - }, - 108: IsNonZeroDestIsSmall { - dest: StatePartIndex(51), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(117), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.en", ty: Bool }, - }, - 109: BranchIfSmallZero { - target: 112, - value: StatePartIndex(51), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 110: MemoryReadUInt { - dest: StatePartIndex(119), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.data", ty: Bool }, - memory: StatePartIndex(4), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x0, - // [0x6]: 0x0, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x1, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(52), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 111: Branch { - target: 113, - }, - 112: Const { - dest: StatePartIndex(119), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.data", ty: Bool }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 113: Copy { - dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[4].data", ty: Bool }, - src: StatePartIndex(119), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.data", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 114: IsNonZeroDestIsSmall { - dest: StatePartIndex(50), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(118), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::r0.clk", ty: Clock }, - }, - 115: AndSmall { - dest: StatePartIndex(49), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(50), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(48), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 116: CastBigToArrayIndex { - dest: StatePartIndex(45), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(109), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.addr", ty: UInt<4> }, - }, - 117: IsNonZeroDestIsSmall { - dest: StatePartIndex(44), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(110), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.en", ty: Bool }, - }, - 118: IsNonZeroDestIsSmall { - dest: StatePartIndex(43), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(111), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.clk", ty: Clock }, - }, - 119: AndSmall { - dest: StatePartIndex(42), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(43), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(41), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 120: CastBigToArrayIndex { - dest: StatePartIndex(40), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(105), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.addr", ty: UInt<4> }, - }, - 121: IsNonZeroDestIsSmall { - dest: StatePartIndex(39), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(106), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.en", ty: Bool }, - }, - 122: BranchIfSmallZero { - target: 125, - value: StatePartIndex(39), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 123: MemoryReadUInt { - dest: StatePartIndex(108), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.data", ty: Bool }, - memory: StatePartIndex(3), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x1, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x1, - // [0x5]: 0x1, - // [0x6]: 0x1, - // [0x7]: 0x1, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x0, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(40), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 124: Branch { - target: 126, - }, - 125: Const { - dest: StatePartIndex(108), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.data", ty: Bool }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 126: Copy { - dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[3].data", ty: Bool }, - src: StatePartIndex(108), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.data", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 127: IsNonZeroDestIsSmall { - dest: StatePartIndex(38), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(107), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::r0.clk", ty: Clock }, - }, - 128: AndSmall { - dest: StatePartIndex(37), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(38), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(36), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 129: CastBigToArrayIndex { - dest: StatePartIndex(33), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(98), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.addr", ty: UInt<4> }, - }, - 130: IsNonZeroDestIsSmall { - dest: StatePartIndex(32), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(99), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.en", ty: Bool }, - }, - 131: IsNonZeroDestIsSmall { - dest: StatePartIndex(31), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(100), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.clk", ty: Clock }, - }, - 132: AndSmall { - dest: StatePartIndex(30), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(31), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(29), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 133: CastBigToArrayIndex { - dest: StatePartIndex(28), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(94), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.addr", ty: UInt<4> }, - }, - 134: IsNonZeroDestIsSmall { - dest: StatePartIndex(27), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(95), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.en", ty: Bool }, - }, - 135: BranchIfSmallZero { - target: 138, - value: StatePartIndex(27), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 136: MemoryReadUInt { - dest: StatePartIndex(97), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.data", ty: Bool }, - memory: StatePartIndex(2), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x1, - // [0x6]: 0x0, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x0, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(28), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 137: Branch { - target: 139, - }, - 138: Const { - dest: StatePartIndex(97), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.data", ty: Bool }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 139: Copy { - dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[2].data", ty: Bool }, - src: StatePartIndex(97), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.data", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 140: IsNonZeroDestIsSmall { - dest: StatePartIndex(26), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(96), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::r0.clk", ty: Clock }, - }, - 141: AndSmall { - dest: StatePartIndex(25), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(26), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(24), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 142: CastBigToArrayIndex { - dest: StatePartIndex(21), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(87), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.addr", ty: UInt<4> }, - }, - 143: IsNonZeroDestIsSmall { - dest: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(88), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.en", ty: Bool }, - }, - 144: IsNonZeroDestIsSmall { - dest: StatePartIndex(19), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(89), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.clk", ty: Clock }, - }, - 145: AndSmall { - dest: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(19), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(17), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 146: CastBigToArrayIndex { - dest: StatePartIndex(16), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(83), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.addr", ty: UInt<4> }, - }, - 147: IsNonZeroDestIsSmall { - dest: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(84), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.en", ty: Bool }, - }, - 148: BranchIfSmallZero { - target: 151, - value: StatePartIndex(15), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 149: MemoryReadUInt { - dest: StatePartIndex(86), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.data", ty: Bool }, - memory: StatePartIndex(1), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x0, - // [0x6]: 0x0, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x0, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(16), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 150: Branch { - target: 152, - }, - 151: Const { - dest: StatePartIndex(86), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.data", ty: Bool }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 152: Copy { - dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[1].data", ty: Bool }, - src: StatePartIndex(86), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.data", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 153: IsNonZeroDestIsSmall { - dest: StatePartIndex(14), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(85), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::r0.clk", ty: Clock }, - }, - 154: AndSmall { - dest: StatePartIndex(13), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(14), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 155: CastBigToArrayIndex { - dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(76), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.addr", ty: UInt<4> }, - }, - 156: IsNonZeroDestIsSmall { - dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(77), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.en", ty: Bool }, - }, - 157: IsNonZeroDestIsSmall { - dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(78), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.clk", ty: Clock }, - }, - 158: AndSmall { - dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 159: CastBigToArrayIndex { - dest: StatePartIndex(4), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(72), // (0xf) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.addr", ty: UInt<4> }, - }, - 160: IsNonZeroDestIsSmall { - dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(73), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.en", ty: Bool }, - }, - 161: BranchIfSmallZero { - target: 164, - value: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 162: MemoryReadUInt { - dest: StatePartIndex(75), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.data", ty: Bool }, - memory: StatePartIndex(0), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x0, - // [0x6]: 0x0, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x0, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(4), // (0xf 15) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 163: Branch { - target: 165, - }, - 164: Const { - dest: StatePartIndex(75), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.data", ty: Bool }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 165: Copy { - dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::r[0].data", ty: Bool }, - src: StatePartIndex(75), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.data", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 166: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(74), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::r0.clk", ty: Clock }, - }, - 167: AndSmall { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 168: BranchIfSmallZero { - target: 169, - value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 169: BranchIfSmallZero { - target: 177, - value: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 170: CopySmall { - dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - }, - 171: CopySmall { - dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 172: Copy { - dest: StatePartIndex(81), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(79), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.data", ty: Bool }, - }, - 173: Copy { - dest: StatePartIndex(82), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(80), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_0::w1.mask", ty: Bool }, - }, - 174: BranchIfSmallZero { - target: 177, - value: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 175: BranchIfZero { - target: 177, - value: StatePartIndex(82), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 176: MemoryWriteUInt { - value: StatePartIndex(81), // (0x0) SlotDebugData { name: "", ty: Bool }, - memory: StatePartIndex(0), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x0, - // [0x6]: 0x0, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x0, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 177: BranchIfSmallZero { - target: 178, - value: StatePartIndex(13), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 178: BranchIfSmallZero { - target: 186, - value: StatePartIndex(18), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 179: CopySmall { - dest: StatePartIndex(22), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(21), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - }, - 180: CopySmall { - dest: StatePartIndex(23), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(20), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 181: Copy { - dest: StatePartIndex(92), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(90), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.data", ty: Bool }, - }, - 182: Copy { - dest: StatePartIndex(93), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(91), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_1::w1.mask", ty: Bool }, - }, - 183: BranchIfSmallZero { - target: 186, - value: StatePartIndex(23), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 184: BranchIfZero { - target: 186, - value: StatePartIndex(93), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 185: MemoryWriteUInt { - value: StatePartIndex(92), // (0x0) SlotDebugData { name: "", ty: Bool }, - memory: StatePartIndex(1), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x0, - // [0x6]: 0x0, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x0, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(22), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 186: BranchIfSmallZero { - target: 187, - value: StatePartIndex(25), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 187: BranchIfSmallZero { - target: 195, - value: StatePartIndex(30), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 188: CopySmall { - dest: StatePartIndex(34), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(33), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - }, - 189: CopySmall { - dest: StatePartIndex(35), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(32), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 190: Copy { - dest: StatePartIndex(103), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(101), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.data", ty: Bool }, - }, - 191: Copy { - dest: StatePartIndex(104), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(102), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_2::w1.mask", ty: Bool }, - }, - 192: BranchIfSmallZero { - target: 195, - value: StatePartIndex(35), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 193: BranchIfZero { - target: 195, - value: StatePartIndex(104), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 194: MemoryWriteUInt { - value: StatePartIndex(103), // (0x0) SlotDebugData { name: "", ty: Bool }, - memory: StatePartIndex(2), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x1, - // [0x6]: 0x0, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x0, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(34), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 195: BranchIfSmallZero { - target: 196, - value: StatePartIndex(37), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 196: BranchIfSmallZero { - target: 204, - value: StatePartIndex(42), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 197: CopySmall { - dest: StatePartIndex(46), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(45), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - }, - 198: CopySmall { - dest: StatePartIndex(47), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(44), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 199: Copy { - dest: StatePartIndex(114), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(112), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.data", ty: Bool }, - }, - 200: Copy { - dest: StatePartIndex(115), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(113), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_3::w1.mask", ty: Bool }, - }, - 201: BranchIfSmallZero { - target: 204, - value: StatePartIndex(47), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 202: BranchIfZero { - target: 204, - value: StatePartIndex(115), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 203: MemoryWriteUInt { - value: StatePartIndex(114), // (0x0) SlotDebugData { name: "", ty: Bool }, - memory: StatePartIndex(3), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x1, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x1, - // [0x5]: 0x1, - // [0x6]: 0x1, - // [0x7]: 0x1, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x0, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(46), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 204: BranchIfSmallZero { - target: 205, - value: StatePartIndex(49), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 205: BranchIfSmallZero { - target: 213, - value: StatePartIndex(54), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 206: CopySmall { - dest: StatePartIndex(58), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(57), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - }, - 207: CopySmall { - dest: StatePartIndex(59), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(56), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 208: Copy { - dest: StatePartIndex(125), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(123), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.data", ty: Bool }, - }, - 209: Copy { - dest: StatePartIndex(126), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(124), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_4::w1.mask", ty: Bool }, - }, - 210: BranchIfSmallZero { - target: 213, - value: StatePartIndex(59), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 211: BranchIfZero { - target: 213, - value: StatePartIndex(126), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 212: MemoryWriteUInt { - value: StatePartIndex(125), // (0x0) SlotDebugData { name: "", ty: Bool }, - memory: StatePartIndex(4), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x0, - // [0x6]: 0x0, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x1, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(58), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 213: BranchIfSmallZero { - target: 214, - value: StatePartIndex(61), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 214: BranchIfSmallZero { - target: 222, - value: StatePartIndex(66), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 215: CopySmall { - dest: StatePartIndex(70), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(69), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - }, - 216: CopySmall { - dest: StatePartIndex(71), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(68), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 217: Copy { - dest: StatePartIndex(136), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(134), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.data", ty: Bool }, - }, - 218: Copy { - dest: StatePartIndex(137), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(135), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_5::w1.mask", ty: Bool }, - }, - 219: BranchIfSmallZero { - target: 222, - value: StatePartIndex(71), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 220: BranchIfZero { - target: 222, - value: StatePartIndex(137), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 221: MemoryWriteUInt { - value: StatePartIndex(136), // (0x0) SlotDebugData { name: "", ty: Bool }, - memory: StatePartIndex(5), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x1, - // [0x3]: 0x0, - // [0x4]: 0x1, - // [0x5]: 0x1, - // [0x6]: 0x0, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x0, - // [0xa]: 0x1, - // [0xb]: 0x1, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(70), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 222: BranchIfSmallZero { - target: 223, - value: StatePartIndex(73), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 223: BranchIfSmallZero { - target: 231, - value: StatePartIndex(78), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 224: CopySmall { - dest: StatePartIndex(82), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(81), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - }, - 225: CopySmall { - dest: StatePartIndex(83), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(80), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 226: Copy { - dest: StatePartIndex(147), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(145), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.data", ty: Bool }, - }, - 227: Copy { - dest: StatePartIndex(148), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(146), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_6::w1.mask", ty: Bool }, - }, - 228: BranchIfSmallZero { - target: 231, - value: StatePartIndex(83), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 229: BranchIfZero { - target: 231, - value: StatePartIndex(148), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 230: MemoryWriteUInt { - value: StatePartIndex(147), // (0x0) SlotDebugData { name: "", ty: Bool }, - memory: StatePartIndex(6), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x0, - // [0x2]: 0x0, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x1, - // [0x6]: 0x1, - // [0x7]: 0x0, - // [0x8]: 0x0, - // [0x9]: 0x1, - // [0xa]: 0x1, - // [0xb]: 0x1, - // [0xc]: 0x1, - // [0xd]: 0x0, - // [0xe]: 0x0, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(82), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 231: BranchIfSmallZero { - target: 232, - value: StatePartIndex(85), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 232: BranchIfSmallZero { - target: 240, - value: StatePartIndex(90), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 233: CopySmall { - dest: StatePartIndex(94), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - src: StatePartIndex(93), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - }, - 234: CopySmall { - dest: StatePartIndex(95), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(92), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 235: Copy { - dest: StatePartIndex(158), // (0x0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(156), // (0x0) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.data", ty: Bool }, - }, - 236: Copy { - dest: StatePartIndex(159), // (0x1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(157), // (0x1) SlotDebugData { name: "InstantiatedModule(many_memories: many_memories).many_memories::mem_7::w1.mask", ty: Bool }, - }, - 237: BranchIfSmallZero { - target: 240, - value: StatePartIndex(95), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 238: BranchIfZero { - target: 240, - value: StatePartIndex(159), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, - 239: MemoryWriteUInt { - value: StatePartIndex(158), // (0x0) SlotDebugData { name: "", ty: Bool }, - memory: StatePartIndex(7), // (MemoryData { - // array_type: Array, - // data: [ - // // len = 0x10 - // [0x0]: 0x0, - // [0x1]: 0x1, - // [0x2]: 0x1, - // [0x3]: 0x0, - // [0x4]: 0x0, - // [0x5]: 0x1, - // [0x6]: 0x0, - // [0x7]: 0x1, - // [0x8]: 0x1, - // [0x9]: 0x0, - // [0xa]: 0x0, - // [0xb]: 0x0, - // [0xc]: 0x0, - // [0xd]: 0x0, - // [0xe]: 0x1, - // [0xf]: 0x0, - // ], - // }) (), - addr: StatePartIndex(94), // (0x0 0) SlotDebugData { name: "", ty: UInt<4> }, - stride: 1, - start: 0, - width: 1, - }, - 240: XorSmallImmediate { - dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 241: XorSmallImmediate { - dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 242: XorSmallImmediate { - dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(14), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 243: XorSmallImmediate { - dest: StatePartIndex(17), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(19), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 244: XorSmallImmediate { - dest: StatePartIndex(24), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(26), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 245: XorSmallImmediate { - dest: StatePartIndex(29), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(31), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 246: XorSmallImmediate { - dest: StatePartIndex(36), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(38), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 247: XorSmallImmediate { - dest: StatePartIndex(41), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(43), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 248: XorSmallImmediate { - dest: StatePartIndex(48), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(50), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 249: XorSmallImmediate { - dest: StatePartIndex(53), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(55), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 250: XorSmallImmediate { - dest: StatePartIndex(60), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(62), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 251: XorSmallImmediate { - dest: StatePartIndex(65), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(67), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 252: XorSmallImmediate { - dest: StatePartIndex(72), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(74), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 253: XorSmallImmediate { - dest: StatePartIndex(77), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(79), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 254: XorSmallImmediate { - dest: StatePartIndex(84), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(86), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 255: XorSmallImmediate { - dest: StatePartIndex(89), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(91), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 256: Return, - ], - .. - }, - pc: 256, - memory_write_log: [], - memories: StatePart { - value: [ - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x0, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x0, - [0x6]: 0x0, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x0, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x0, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x0, - [0x6]: 0x0, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x0, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x0, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x1, - [0x6]: 0x0, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x0, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x1, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x1, - [0x5]: 0x1, - [0x6]: 0x1, - [0x7]: 0x1, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x0, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x0, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x0, - [0x6]: 0x0, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x1, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x0, - [0x2]: 0x1, - [0x3]: 0x0, - [0x4]: 0x1, - [0x5]: 0x1, - [0x6]: 0x0, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x0, - [0xa]: 0x1, - [0xb]: 0x1, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x0, - [0x2]: 0x0, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x1, - [0x6]: 0x1, - [0x7]: 0x0, - [0x8]: 0x0, - [0x9]: 0x1, - [0xa]: 0x1, - [0xb]: 0x1, - [0xc]: 0x1, - [0xd]: 0x0, - [0xe]: 0x0, - [0xf]: 0x0, - ], - }, - MemoryData { - array_type: Array, - data: [ - // len = 0x10 - [0x0]: 0x0, - [0x1]: 0x1, - [0x2]: 0x1, - [0x3]: 0x0, - [0x4]: 0x0, - [0x5]: 0x1, - [0x6]: 0x0, - [0x7]: 0x1, - [0x8]: 0x1, - [0x9]: 0x0, - [0xa]: 0x0, - [0xb]: 0x0, - [0xc]: 0x0, - [0xd]: 0x0, - [0xe]: 0x1, - [0xf]: 0x0, - ], - }, - ], - }, - small_slots: StatePart { - value: [ - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - ], - }, - big_slots: StatePart { - value: [ - 15, - 1, - 0, - 0, - 15, - 1, - 0, - 0, - 15, - 1, - 0, - 0, - 15, - 1, - 0, - 0, - 15, - 1, - 0, - 0, - 15, - 1, - 0, - 0, - 15, - 1, - 0, - 0, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 1, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[0], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[0].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[0].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[0].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[0].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[1], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[1].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[1].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[1].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[1].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[2], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[2].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[2].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[2].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[2].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[3], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[3].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[3].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[3].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[3].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[4], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[4].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[4].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[4].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[4].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[5], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[5].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[5].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[5].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[5].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[6], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[6].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[6].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[6].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[6].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[7], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[7].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[7].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[7].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.r[7].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[0], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[0].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[0].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[0].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[0].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[0].mask, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[1], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[1].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[1].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[1].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[1].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[1].mask, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[2], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[2].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[2].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[2].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[2].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[2].mask, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[3], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[3].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[3].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[3].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[3].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[3].mask, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[4], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[4].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[4].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[4].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[4].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[4].mask, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[5], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[5].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[5].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[5].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[5].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[5].mask, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[6], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[6].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[6].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[6].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[6].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[6].mask, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[7], - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[7].addr, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[7].clk, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[7].data, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[7].en, - Instance { - name: ::many_memories, - instantiated: Module { - name: many_memories, - .. - }, - }.w[7].mask, - }, - did_initial_settle: true, - }, - extern_modules: [], - trace_decls: TraceModule { - name: "many_memories", - children: [ - TraceModuleIO { - name: "r", - child: TraceArray { - name: "r", - elements: [ - TraceBundle { - name: "[0]", - fields: [ - TraceUInt { - location: TraceScalarId(0), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(1), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(2), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(3), - name: "data", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[1]", - fields: [ - TraceUInt { - location: TraceScalarId(4), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(5), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(6), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(7), - name: "data", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[2]", - fields: [ - TraceUInt { - location: TraceScalarId(8), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(9), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(10), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(11), - name: "data", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[3]", - fields: [ - TraceUInt { - location: TraceScalarId(12), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(13), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(14), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(15), - name: "data", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[4]", - fields: [ - TraceUInt { - location: TraceScalarId(16), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(17), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(18), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(19), - name: "data", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[5]", - fields: [ - TraceUInt { - location: TraceScalarId(20), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(21), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(22), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(23), - name: "data", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[6]", - fields: [ - TraceUInt { - location: TraceScalarId(24), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(25), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(26), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(27), - name: "data", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[7]", - fields: [ - TraceUInt { - location: TraceScalarId(28), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(29), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(30), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(31), - name: "data", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Source, - }, - ], - ty: Array, en: Bool, clk: Clock, #[hdl(flip)] data: Bool}, 8>, - flow: Source, - }, - ty: Array, en: Bool, clk: Clock, #[hdl(flip)] data: Bool}, 8>, - flow: Source, - }, - TraceModuleIO { - name: "w", - child: TraceArray { - name: "w", - elements: [ - TraceBundle { - name: "[0]", - fields: [ - TraceUInt { - location: TraceScalarId(32), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(33), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(34), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(35), - name: "data", - flow: Source, - }, - TraceBool { - location: TraceScalarId(36), - name: "mask", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[1]", - fields: [ - TraceUInt { - location: TraceScalarId(37), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(38), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(39), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(40), - name: "data", - flow: Source, - }, - TraceBool { - location: TraceScalarId(41), - name: "mask", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[2]", - fields: [ - TraceUInt { - location: TraceScalarId(42), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(43), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(44), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(45), - name: "data", - flow: Source, - }, - TraceBool { - location: TraceScalarId(46), - name: "mask", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[3]", - fields: [ - TraceUInt { - location: TraceScalarId(47), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(48), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(49), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(50), - name: "data", - flow: Source, - }, - TraceBool { - location: TraceScalarId(51), - name: "mask", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[4]", - fields: [ - TraceUInt { - location: TraceScalarId(52), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(53), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(54), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(55), - name: "data", - flow: Source, - }, - TraceBool { - location: TraceScalarId(56), - name: "mask", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[5]", - fields: [ - TraceUInt { - location: TraceScalarId(57), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(58), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(59), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(60), - name: "data", - flow: Source, - }, - TraceBool { - location: TraceScalarId(61), - name: "mask", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[6]", - fields: [ - TraceUInt { - location: TraceScalarId(62), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(63), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(64), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(65), - name: "data", - flow: Source, - }, - TraceBool { - location: TraceScalarId(66), - name: "mask", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Source, - }, - TraceBundle { - name: "[7]", - fields: [ - TraceUInt { - location: TraceScalarId(67), - name: "addr", - ty: UInt<4>, - flow: Source, - }, - TraceBool { - location: TraceScalarId(68), - name: "en", - flow: Source, - }, - TraceClock { - location: TraceScalarId(69), - name: "clk", - flow: Source, - }, - TraceBool { - location: TraceScalarId(70), - name: "data", - flow: Source, - }, - TraceBool { - location: TraceScalarId(71), - name: "mask", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Source, - }, - ], - ty: Array, en: Bool, clk: Clock, data: Bool, mask: Bool}, 8>, - flow: Source, - }, - ty: Array, en: Bool, clk: Clock, data: Bool, mask: Bool}, 8>, - flow: Source, - }, - TraceMem { - id: TraceMemoryId(0), - name: "mem_0", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(0), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_0", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(72), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(73), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(74), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(75), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(76), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(77), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(78), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(79), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(80), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - TraceMem { - id: TraceMemoryId(1), - name: "mem_1", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(1), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_1", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(81), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(82), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(83), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(84), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(85), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(86), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(87), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(88), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(89), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - TraceMem { - id: TraceMemoryId(2), - name: "mem_2", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(2), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_2", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(90), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(91), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(92), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(93), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(94), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(95), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(96), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(97), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(98), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - TraceMem { - id: TraceMemoryId(3), - name: "mem_3", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(3), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_3", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(99), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(100), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(101), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(102), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(103), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(104), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(105), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(106), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(107), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - TraceMem { - id: TraceMemoryId(4), - name: "mem_4", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(4), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_4", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(108), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(109), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(110), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(111), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(112), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(113), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(114), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(115), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(116), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - TraceMem { - id: TraceMemoryId(5), - name: "mem_5", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(5), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_5", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(117), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(118), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(119), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(120), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(121), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(122), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(123), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(124), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(125), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - TraceMem { - id: TraceMemoryId(6), - name: "mem_6", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(6), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_6", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(126), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(127), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(128), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(129), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(130), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(131), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(132), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(133), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(134), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - TraceMem { - id: TraceMemoryId(7), - name: "mem_7", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(7), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_7", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(135), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(136), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(137), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(138), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(139), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(140), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(141), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(142), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(143), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigUInt { - index: StatePartIndex(0), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigBool { - index: StatePartIndex(1), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigClock { - index: StatePartIndex(2), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigBool { - index: StatePartIndex(3), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(4), - kind: BigUInt { - index: StatePartIndex(4), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(5), - kind: BigBool { - index: StatePartIndex(5), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(6), - kind: BigClock { - index: StatePartIndex(6), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(7), - kind: BigBool { - index: StatePartIndex(7), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(8), - kind: BigUInt { - index: StatePartIndex(8), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(9), - kind: BigBool { - index: StatePartIndex(9), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(10), - kind: BigClock { - index: StatePartIndex(10), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(11), - kind: BigBool { - index: StatePartIndex(11), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(12), - kind: BigUInt { - index: StatePartIndex(12), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(13), - kind: BigBool { - index: StatePartIndex(13), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(14), - kind: BigClock { - index: StatePartIndex(14), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(15), - kind: BigBool { - index: StatePartIndex(15), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(16), - kind: BigUInt { - index: StatePartIndex(16), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(17), - kind: BigBool { - index: StatePartIndex(17), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(18), - kind: BigClock { - index: StatePartIndex(18), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(19), - kind: BigBool { - index: StatePartIndex(19), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(20), - kind: BigUInt { - index: StatePartIndex(20), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(21), - kind: BigBool { - index: StatePartIndex(21), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(22), - kind: BigClock { - index: StatePartIndex(22), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(23), - kind: BigBool { - index: StatePartIndex(23), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(24), - kind: BigUInt { - index: StatePartIndex(24), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(25), - kind: BigBool { - index: StatePartIndex(25), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(26), - kind: BigClock { - index: StatePartIndex(26), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(27), - kind: BigBool { - index: StatePartIndex(27), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(28), - kind: BigUInt { - index: StatePartIndex(28), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(29), - kind: BigBool { - index: StatePartIndex(29), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(30), - kind: BigClock { - index: StatePartIndex(30), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(31), - kind: BigBool { - index: StatePartIndex(31), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(32), - kind: BigUInt { - index: StatePartIndex(32), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(33), - kind: BigBool { - index: StatePartIndex(33), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(34), - kind: BigClock { - index: StatePartIndex(34), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(35), - kind: BigBool { - index: StatePartIndex(35), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(36), - kind: BigBool { - index: StatePartIndex(36), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(37), - kind: BigUInt { - index: StatePartIndex(37), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(38), - kind: BigBool { - index: StatePartIndex(38), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(39), - kind: BigClock { - index: StatePartIndex(39), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(40), - kind: BigBool { - index: StatePartIndex(40), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(41), - kind: BigBool { - index: StatePartIndex(41), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(42), - kind: BigUInt { - index: StatePartIndex(42), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(43), - kind: BigBool { - index: StatePartIndex(43), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(44), - kind: BigClock { - index: StatePartIndex(44), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(45), - kind: BigBool { - index: StatePartIndex(45), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(46), - kind: BigBool { - index: StatePartIndex(46), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(47), - kind: BigUInt { - index: StatePartIndex(47), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(48), - kind: BigBool { - index: StatePartIndex(48), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(49), - kind: BigClock { - index: StatePartIndex(49), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(50), - kind: BigBool { - index: StatePartIndex(50), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(51), - kind: BigBool { - index: StatePartIndex(51), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(52), - kind: BigUInt { - index: StatePartIndex(52), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(53), - kind: BigBool { - index: StatePartIndex(53), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(54), - kind: BigClock { - index: StatePartIndex(54), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(55), - kind: BigBool { - index: StatePartIndex(55), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(56), - kind: BigBool { - index: StatePartIndex(56), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(57), - kind: BigUInt { - index: StatePartIndex(57), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(58), - kind: BigBool { - index: StatePartIndex(58), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(59), - kind: BigClock { - index: StatePartIndex(59), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(60), - kind: BigBool { - index: StatePartIndex(60), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(61), - kind: BigBool { - index: StatePartIndex(61), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(62), - kind: BigUInt { - index: StatePartIndex(62), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(63), - kind: BigBool { - index: StatePartIndex(63), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(64), - kind: BigClock { - index: StatePartIndex(64), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(65), - kind: BigBool { - index: StatePartIndex(65), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(66), - kind: BigBool { - index: StatePartIndex(66), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(67), - kind: BigUInt { - index: StatePartIndex(67), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(68), - kind: BigBool { - index: StatePartIndex(68), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(69), - kind: BigClock { - index: StatePartIndex(69), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(70), - kind: BigBool { - index: StatePartIndex(70), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(71), - kind: BigBool { - index: StatePartIndex(71), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(72), - kind: BigUInt { - index: StatePartIndex(72), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(73), - kind: BigBool { - index: StatePartIndex(73), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(74), - kind: BigClock { - index: StatePartIndex(74), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(75), - kind: BigBool { - index: StatePartIndex(75), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(76), - kind: BigUInt { - index: StatePartIndex(76), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(77), - kind: BigBool { - index: StatePartIndex(77), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(78), - kind: BigClock { - index: StatePartIndex(78), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(79), - kind: BigBool { - index: StatePartIndex(79), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(80), - kind: BigBool { - index: StatePartIndex(80), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(81), - kind: BigUInt { - index: StatePartIndex(83), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(82), - kind: BigBool { - index: StatePartIndex(84), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(83), - kind: BigClock { - index: StatePartIndex(85), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(84), - kind: BigBool { - index: StatePartIndex(86), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(85), - kind: BigUInt { - index: StatePartIndex(87), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(86), - kind: BigBool { - index: StatePartIndex(88), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(87), - kind: BigClock { - index: StatePartIndex(89), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(88), - kind: BigBool { - index: StatePartIndex(90), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(89), - kind: BigBool { - index: StatePartIndex(91), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(90), - kind: BigUInt { - index: StatePartIndex(94), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(91), - kind: BigBool { - index: StatePartIndex(95), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(92), - kind: BigClock { - index: StatePartIndex(96), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(93), - kind: BigBool { - index: StatePartIndex(97), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(94), - kind: BigUInt { - index: StatePartIndex(98), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(95), - kind: BigBool { - index: StatePartIndex(99), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(96), - kind: BigClock { - index: StatePartIndex(100), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(97), - kind: BigBool { - index: StatePartIndex(101), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(98), - kind: BigBool { - index: StatePartIndex(102), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(99), - kind: BigUInt { - index: StatePartIndex(105), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(100), - kind: BigBool { - index: StatePartIndex(106), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(101), - kind: BigClock { - index: StatePartIndex(107), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(102), - kind: BigBool { - index: StatePartIndex(108), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(103), - kind: BigUInt { - index: StatePartIndex(109), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(104), - kind: BigBool { - index: StatePartIndex(110), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(105), - kind: BigClock { - index: StatePartIndex(111), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(106), - kind: BigBool { - index: StatePartIndex(112), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(107), - kind: BigBool { - index: StatePartIndex(113), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(108), - kind: BigUInt { - index: StatePartIndex(116), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(109), - kind: BigBool { - index: StatePartIndex(117), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(110), - kind: BigClock { - index: StatePartIndex(118), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(111), - kind: BigBool { - index: StatePartIndex(119), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(112), - kind: BigUInt { - index: StatePartIndex(120), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(113), - kind: BigBool { - index: StatePartIndex(121), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(114), - kind: BigClock { - index: StatePartIndex(122), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(115), - kind: BigBool { - index: StatePartIndex(123), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(116), - kind: BigBool { - index: StatePartIndex(124), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(117), - kind: BigUInt { - index: StatePartIndex(127), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(118), - kind: BigBool { - index: StatePartIndex(128), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(119), - kind: BigClock { - index: StatePartIndex(129), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(120), - kind: BigBool { - index: StatePartIndex(130), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(121), - kind: BigUInt { - index: StatePartIndex(131), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(122), - kind: BigBool { - index: StatePartIndex(132), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(123), - kind: BigClock { - index: StatePartIndex(133), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(124), - kind: BigBool { - index: StatePartIndex(134), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(125), - kind: BigBool { - index: StatePartIndex(135), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(126), - kind: BigUInt { - index: StatePartIndex(138), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(127), - kind: BigBool { - index: StatePartIndex(139), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(128), - kind: BigClock { - index: StatePartIndex(140), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(129), - kind: BigBool { - index: StatePartIndex(141), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(130), - kind: BigUInt { - index: StatePartIndex(142), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(131), - kind: BigBool { - index: StatePartIndex(143), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(132), - kind: BigClock { - index: StatePartIndex(144), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(133), - kind: BigBool { - index: StatePartIndex(145), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(134), - kind: BigBool { - index: StatePartIndex(146), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(135), - kind: BigUInt { - index: StatePartIndex(149), - ty: UInt<4>, - }, - state: 0xf, - last_state: 0xf, - }, - SimTrace { - id: TraceScalarId(136), - kind: BigBool { - index: StatePartIndex(150), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(137), - kind: BigClock { - index: StatePartIndex(151), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(138), - kind: BigBool { - index: StatePartIndex(152), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(139), - kind: BigUInt { - index: StatePartIndex(153), - ty: UInt<4>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(140), - kind: BigBool { - index: StatePartIndex(154), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(141), - kind: BigClock { - index: StatePartIndex(155), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(142), - kind: BigBool { - index: StatePartIndex(156), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(143), - kind: BigBool { - index: StatePartIndex(157), - }, - state: 0x1, - last_state: 0x1, - }, - ], - trace_memories: { - StatePartIndex(0): TraceMem { - id: TraceMemoryId(0), - name: "mem_0", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(0), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_0", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(72), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(73), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(74), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(75), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(76), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(77), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(78), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(79), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(80), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - StatePartIndex(1): TraceMem { - id: TraceMemoryId(1), - name: "mem_1", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(1), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_1", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(81), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(82), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(83), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(84), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(85), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(86), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(87), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(88), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(89), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - StatePartIndex(2): TraceMem { - id: TraceMemoryId(2), - name: "mem_2", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(2), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_2", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(90), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(91), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(92), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(93), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(94), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(95), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(96), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(97), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(98), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - StatePartIndex(3): TraceMem { - id: TraceMemoryId(3), - name: "mem_3", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(3), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_3", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(99), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(100), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(101), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(102), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(103), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(104), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(105), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(106), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(107), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - StatePartIndex(4): TraceMem { - id: TraceMemoryId(4), - name: "mem_4", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(4), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_4", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(108), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(109), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(110), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(111), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(112), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(113), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(114), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(115), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(116), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - StatePartIndex(5): TraceMem { - id: TraceMemoryId(5), - name: "mem_5", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(5), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_5", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(117), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(118), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(119), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(120), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(121), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(122), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(123), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(124), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(125), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - StatePartIndex(6): TraceMem { - id: TraceMemoryId(6), - name: "mem_6", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(6), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_6", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(126), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(127), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(128), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(129), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(130), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(131), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(132), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(133), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(134), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - StatePartIndex(7): TraceMem { - id: TraceMemoryId(7), - name: "mem_7", - stride: 1, - element_type: TraceBool { - location: TraceMemoryLocation { - id: TraceMemoryId(7), - depth: 16, - stride: 1, - start: 0, - len: 1, - }, - name: "mem_7", - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(135), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(136), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(137), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(138), - name: "data", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bool, - }, - }, - TraceMemPort { - name: "w1", - bundle: TraceBundle { - name: "w1", - fields: [ - TraceUInt { - location: TraceScalarId(139), - name: "addr", - ty: UInt<4>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(140), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(141), - name: "clk", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(142), - name: "data", - flow: Sink, - }, - TraceBool { - location: TraceScalarId(143), - name: "mask", - flow: Sink, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bool, - /* offset = 7 */ - mask: Bool, - }, - }, - ], - array_type: Array, - }, - }, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [ - StatePartIndex(1), - StatePartIndex(6), - StatePartIndex(13), - StatePartIndex(18), - StatePartIndex(25), - StatePartIndex(30), - StatePartIndex(37), - StatePartIndex(42), - StatePartIndex(49), - StatePartIndex(54), - StatePartIndex(61), - StatePartIndex(66), - StatePartIndex(73), - StatePartIndex(78), - StatePartIndex(85), - StatePartIndex(90), - ], - event_queue: EventQueue(EventQueueData { - instant: 38 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/many_memories.vcd b/crates/fayalite/tests/sim/expected/many_memories.vcd deleted file mode 100644 index 77d1447a..00000000 --- a/crates/fayalite/tests/sim/expected/many_memories.vcd +++ /dev/null @@ -1,2596 +0,0 @@ -$timescale 1 ps $end -$scope module many_memories $end -$scope struct r $end -$scope struct \[0] $end -$var wire 4 ! addr $end -$var wire 1 " en $end -$var wire 1 # clk $end -$var wire 1 $ data $end -$upscope $end -$scope struct \[1] $end -$var wire 4 % addr $end -$var wire 1 & en $end -$var wire 1 ' clk $end -$var wire 1 ( data $end -$upscope $end -$scope struct \[2] $end -$var wire 4 ) addr $end -$var wire 1 * en $end -$var wire 1 + clk $end -$var wire 1 , data $end -$upscope $end -$scope struct \[3] $end -$var wire 4 - addr $end -$var wire 1 . en $end -$var wire 1 / clk $end -$var wire 1 0 data $end -$upscope $end -$scope struct \[4] $end -$var wire 4 1 addr $end -$var wire 1 2 en $end -$var wire 1 3 clk $end -$var wire 1 4 data $end -$upscope $end -$scope struct \[5] $end -$var wire 4 5 addr $end -$var wire 1 6 en $end -$var wire 1 7 clk $end -$var wire 1 8 data $end -$upscope $end -$scope struct \[6] $end -$var wire 4 9 addr $end -$var wire 1 : en $end -$var wire 1 ; clk $end -$var wire 1 < data $end -$upscope $end -$scope struct \[7] $end -$var wire 4 = addr $end -$var wire 1 > en $end -$var wire 1 ? clk $end -$var wire 1 @ data $end -$upscope $end -$upscope $end -$scope struct w $end -$scope struct \[0] $end -$var wire 4 A addr $end -$var wire 1 B en $end -$var wire 1 C clk $end -$var wire 1 D data $end -$var wire 1 E mask $end -$upscope $end -$scope struct \[1] $end -$var wire 4 F addr $end -$var wire 1 G en $end -$var wire 1 H clk $end -$var wire 1 I data $end -$var wire 1 J mask $end -$upscope $end -$scope struct \[2] $end -$var wire 4 K addr $end -$var wire 1 L en $end -$var wire 1 M clk $end -$var wire 1 N data $end -$var wire 1 O mask $end -$upscope $end -$scope struct \[3] $end -$var wire 4 P addr $end -$var wire 1 Q en $end -$var wire 1 R clk $end -$var wire 1 S data $end -$var wire 1 T mask $end -$upscope $end -$scope struct \[4] $end -$var wire 4 U addr $end -$var wire 1 V en $end -$var wire 1 W clk $end -$var wire 1 X data $end -$var wire 1 Y mask $end -$upscope $end -$scope struct \[5] $end -$var wire 4 Z addr $end -$var wire 1 [ en $end -$var wire 1 \ clk $end -$var wire 1 ] data $end -$var wire 1 ^ mask $end -$upscope $end -$scope struct \[6] $end -$var wire 4 _ addr $end -$var wire 1 ` en $end -$var wire 1 a clk $end -$var wire 1 b data $end -$var wire 1 c mask $end -$upscope $end -$scope struct \[7] $end -$var wire 4 d addr $end -$var wire 1 e en $end -$var wire 1 f clk $end -$var wire 1 g data $end -$var wire 1 h mask $end -$upscope $end -$upscope $end -$scope struct mem_0 $end -$scope struct contents $end -$scope struct \[0] $end -$var reg 1 S" mem_0 $end -$upscope $end -$scope struct \[1] $end -$var reg 1 T" mem_0 $end -$upscope $end -$scope struct \[2] $end -$var reg 1 U" mem_0 $end -$upscope $end -$scope struct \[3] $end -$var reg 1 V" mem_0 $end -$upscope $end -$scope struct \[4] $end -$var reg 1 W" mem_0 $end -$upscope $end -$scope struct \[5] $end -$var reg 1 X" mem_0 $end -$upscope $end -$scope struct \[6] $end -$var reg 1 Y" mem_0 $end -$upscope $end -$scope struct \[7] $end -$var reg 1 Z" mem_0 $end -$upscope $end -$scope struct \[8] $end -$var reg 1 [" mem_0 $end -$upscope $end -$scope struct \[9] $end -$var reg 1 \" mem_0 $end -$upscope $end -$scope struct \[10] $end -$var reg 1 ]" mem_0 $end -$upscope $end -$scope struct \[11] $end -$var reg 1 ^" mem_0 $end -$upscope $end -$scope struct \[12] $end -$var reg 1 _" mem_0 $end -$upscope $end -$scope struct \[13] $end -$var reg 1 `" mem_0 $end -$upscope $end -$scope struct \[14] $end -$var reg 1 a" mem_0 $end -$upscope $end -$scope struct \[15] $end -$var reg 1 b" mem_0 $end -$upscope $end -$upscope $end -$scope struct r0 $end -$var wire 4 i addr $end -$var wire 1 j en $end -$var wire 1 k clk $end -$var wire 1 l data $end -$upscope $end -$scope struct w1 $end -$var wire 4 m addr $end -$var wire 1 n en $end -$var wire 1 o clk $end -$var wire 1 p data $end -$var wire 1 q mask $end -$upscope $end -$upscope $end -$scope struct mem_1 $end -$scope struct contents $end -$scope struct \[0] $end -$var reg 1 c" mem_1 $end -$upscope $end -$scope struct \[1] $end -$var reg 1 d" mem_1 $end -$upscope $end -$scope struct \[2] $end -$var reg 1 e" mem_1 $end -$upscope $end -$scope struct \[3] $end -$var reg 1 f" mem_1 $end -$upscope $end -$scope struct \[4] $end -$var reg 1 g" mem_1 $end -$upscope $end -$scope struct \[5] $end -$var reg 1 h" mem_1 $end -$upscope $end -$scope struct \[6] $end -$var reg 1 i" mem_1 $end -$upscope $end -$scope struct \[7] $end -$var reg 1 j" mem_1 $end -$upscope $end -$scope struct \[8] $end -$var reg 1 k" mem_1 $end -$upscope $end -$scope struct \[9] $end -$var reg 1 l" mem_1 $end -$upscope $end -$scope struct \[10] $end -$var reg 1 m" mem_1 $end -$upscope $end -$scope struct \[11] $end -$var reg 1 n" mem_1 $end -$upscope $end -$scope struct \[12] $end -$var reg 1 o" mem_1 $end -$upscope $end -$scope struct \[13] $end -$var reg 1 p" mem_1 $end -$upscope $end -$scope struct \[14] $end -$var reg 1 q" mem_1 $end -$upscope $end -$scope struct \[15] $end -$var reg 1 r" mem_1 $end -$upscope $end -$upscope $end -$scope struct r0 $end -$var wire 4 r addr $end -$var wire 1 s en $end -$var wire 1 t clk $end -$var wire 1 u data $end -$upscope $end -$scope struct w1 $end -$var wire 4 v addr $end -$var wire 1 w en $end -$var wire 1 x clk $end -$var wire 1 y data $end -$var wire 1 z mask $end -$upscope $end -$upscope $end -$scope struct mem_2 $end -$scope struct contents $end -$scope struct \[0] $end -$var reg 1 s" mem_2 $end -$upscope $end -$scope struct \[1] $end -$var reg 1 t" mem_2 $end -$upscope $end -$scope struct \[2] $end -$var reg 1 u" mem_2 $end -$upscope $end -$scope struct \[3] $end -$var reg 1 v" mem_2 $end -$upscope $end -$scope struct \[4] $end -$var reg 1 w" mem_2 $end -$upscope $end -$scope struct \[5] $end -$var reg 1 x" mem_2 $end -$upscope $end -$scope struct \[6] $end -$var reg 1 y" mem_2 $end -$upscope $end -$scope struct \[7] $end -$var reg 1 z" mem_2 $end -$upscope $end -$scope struct \[8] $end -$var reg 1 {" mem_2 $end -$upscope $end -$scope struct \[9] $end -$var reg 1 |" mem_2 $end -$upscope $end -$scope struct \[10] $end -$var reg 1 }" mem_2 $end -$upscope $end -$scope struct \[11] $end -$var reg 1 ~" mem_2 $end -$upscope $end -$scope struct \[12] $end -$var reg 1 !# mem_2 $end -$upscope $end -$scope struct \[13] $end -$var reg 1 "# mem_2 $end -$upscope $end -$scope struct \[14] $end -$var reg 1 ## mem_2 $end -$upscope $end -$scope struct \[15] $end -$var reg 1 $# mem_2 $end -$upscope $end -$upscope $end -$scope struct r0 $end -$var wire 4 { addr $end -$var wire 1 | en $end -$var wire 1 } clk $end -$var wire 1 ~ data $end -$upscope $end -$scope struct w1 $end -$var wire 4 !" addr $end -$var wire 1 "" en $end -$var wire 1 #" clk $end -$var wire 1 $" data $end -$var wire 1 %" mask $end -$upscope $end -$upscope $end -$scope struct mem_3 $end -$scope struct contents $end -$scope struct \[0] $end -$var reg 1 %# mem_3 $end -$upscope $end -$scope struct \[1] $end -$var reg 1 &# mem_3 $end -$upscope $end -$scope struct \[2] $end -$var reg 1 '# mem_3 $end -$upscope $end -$scope struct \[3] $end -$var reg 1 (# mem_3 $end -$upscope $end -$scope struct \[4] $end -$var reg 1 )# mem_3 $end -$upscope $end -$scope struct \[5] $end -$var reg 1 *# mem_3 $end -$upscope $end -$scope struct \[6] $end -$var reg 1 +# mem_3 $end -$upscope $end -$scope struct \[7] $end -$var reg 1 ,# mem_3 $end -$upscope $end -$scope struct \[8] $end -$var reg 1 -# mem_3 $end -$upscope $end -$scope struct \[9] $end -$var reg 1 .# mem_3 $end -$upscope $end -$scope struct \[10] $end -$var reg 1 /# mem_3 $end -$upscope $end -$scope struct \[11] $end -$var reg 1 0# mem_3 $end -$upscope $end -$scope struct \[12] $end -$var reg 1 1# mem_3 $end -$upscope $end -$scope struct \[13] $end -$var reg 1 2# mem_3 $end -$upscope $end -$scope struct \[14] $end -$var reg 1 3# mem_3 $end -$upscope $end -$scope struct \[15] $end -$var reg 1 4# mem_3 $end -$upscope $end -$upscope $end -$scope struct r0 $end -$var wire 4 &" addr $end -$var wire 1 '" en $end -$var wire 1 (" clk $end -$var wire 1 )" data $end -$upscope $end -$scope struct w1 $end -$var wire 4 *" addr $end -$var wire 1 +" en $end -$var wire 1 ," clk $end -$var wire 1 -" data $end -$var wire 1 ." mask $end -$upscope $end -$upscope $end -$scope struct mem_4 $end -$scope struct contents $end -$scope struct \[0] $end -$var reg 1 5# mem_4 $end -$upscope $end -$scope struct \[1] $end -$var reg 1 6# mem_4 $end -$upscope $end -$scope struct \[2] $end -$var reg 1 7# mem_4 $end -$upscope $end -$scope struct \[3] $end -$var reg 1 8# mem_4 $end -$upscope $end -$scope struct \[4] $end -$var reg 1 9# mem_4 $end -$upscope $end -$scope struct \[5] $end -$var reg 1 :# mem_4 $end -$upscope $end -$scope struct \[6] $end -$var reg 1 ;# mem_4 $end -$upscope $end -$scope struct \[7] $end -$var reg 1 <# mem_4 $end -$upscope $end -$scope struct \[8] $end -$var reg 1 =# mem_4 $end -$upscope $end -$scope struct \[9] $end -$var reg 1 ># mem_4 $end -$upscope $end -$scope struct \[10] $end -$var reg 1 ?# mem_4 $end -$upscope $end -$scope struct \[11] $end -$var reg 1 @# mem_4 $end -$upscope $end -$scope struct \[12] $end -$var reg 1 A# mem_4 $end -$upscope $end -$scope struct \[13] $end -$var reg 1 B# mem_4 $end -$upscope $end -$scope struct \[14] $end -$var reg 1 C# mem_4 $end -$upscope $end -$scope struct \[15] $end -$var reg 1 D# mem_4 $end -$upscope $end -$upscope $end -$scope struct r0 $end -$var wire 4 /" addr $end -$var wire 1 0" en $end -$var wire 1 1" clk $end -$var wire 1 2" data $end -$upscope $end -$scope struct w1 $end -$var wire 4 3" addr $end -$var wire 1 4" en $end -$var wire 1 5" clk $end -$var wire 1 6" data $end -$var wire 1 7" mask $end -$upscope $end -$upscope $end -$scope struct mem_5 $end -$scope struct contents $end -$scope struct \[0] $end -$var reg 1 E# mem_5 $end -$upscope $end -$scope struct \[1] $end -$var reg 1 F# mem_5 $end -$upscope $end -$scope struct \[2] $end -$var reg 1 G# mem_5 $end -$upscope $end -$scope struct \[3] $end -$var reg 1 H# mem_5 $end -$upscope $end -$scope struct \[4] $end -$var reg 1 I# mem_5 $end -$upscope $end -$scope struct \[5] $end -$var reg 1 J# mem_5 $end -$upscope $end -$scope struct \[6] $end -$var reg 1 K# mem_5 $end -$upscope $end -$scope struct \[7] $end -$var reg 1 L# mem_5 $end -$upscope $end -$scope struct \[8] $end -$var reg 1 M# mem_5 $end -$upscope $end -$scope struct \[9] $end -$var reg 1 N# mem_5 $end -$upscope $end -$scope struct \[10] $end -$var reg 1 O# mem_5 $end -$upscope $end -$scope struct \[11] $end -$var reg 1 P# mem_5 $end -$upscope $end -$scope struct \[12] $end -$var reg 1 Q# mem_5 $end -$upscope $end -$scope struct \[13] $end -$var reg 1 R# mem_5 $end -$upscope $end -$scope struct \[14] $end -$var reg 1 S# mem_5 $end -$upscope $end -$scope struct \[15] $end -$var reg 1 T# mem_5 $end -$upscope $end -$upscope $end -$scope struct r0 $end -$var wire 4 8" addr $end -$var wire 1 9" en $end -$var wire 1 :" clk $end -$var wire 1 ;" data $end -$upscope $end -$scope struct w1 $end -$var wire 4 <" addr $end -$var wire 1 =" en $end -$var wire 1 >" clk $end -$var wire 1 ?" data $end -$var wire 1 @" mask $end -$upscope $end -$upscope $end -$scope struct mem_6 $end -$scope struct contents $end -$scope struct \[0] $end -$var reg 1 U# mem_6 $end -$upscope $end -$scope struct \[1] $end -$var reg 1 V# mem_6 $end -$upscope $end -$scope struct \[2] $end -$var reg 1 W# mem_6 $end -$upscope $end -$scope struct \[3] $end -$var reg 1 X# mem_6 $end -$upscope $end -$scope struct \[4] $end -$var reg 1 Y# mem_6 $end -$upscope $end -$scope struct \[5] $end -$var reg 1 Z# mem_6 $end -$upscope $end -$scope struct \[6] $end -$var reg 1 [# mem_6 $end -$upscope $end -$scope struct \[7] $end -$var reg 1 \# mem_6 $end -$upscope $end -$scope struct \[8] $end -$var reg 1 ]# mem_6 $end -$upscope $end -$scope struct \[9] $end -$var reg 1 ^# mem_6 $end -$upscope $end -$scope struct \[10] $end -$var reg 1 _# mem_6 $end -$upscope $end -$scope struct \[11] $end -$var reg 1 `# mem_6 $end -$upscope $end -$scope struct \[12] $end -$var reg 1 a# mem_6 $end -$upscope $end -$scope struct \[13] $end -$var reg 1 b# mem_6 $end -$upscope $end -$scope struct \[14] $end -$var reg 1 c# mem_6 $end -$upscope $end -$scope struct \[15] $end -$var reg 1 d# mem_6 $end -$upscope $end -$upscope $end -$scope struct r0 $end -$var wire 4 A" addr $end -$var wire 1 B" en $end -$var wire 1 C" clk $end -$var wire 1 D" data $end -$upscope $end -$scope struct w1 $end -$var wire 4 E" addr $end -$var wire 1 F" en $end -$var wire 1 G" clk $end -$var wire 1 H" data $end -$var wire 1 I" mask $end -$upscope $end -$upscope $end -$scope struct mem_7 $end -$scope struct contents $end -$scope struct \[0] $end -$var reg 1 e# mem_7 $end -$upscope $end -$scope struct \[1] $end -$var reg 1 f# mem_7 $end -$upscope $end -$scope struct \[2] $end -$var reg 1 g# mem_7 $end -$upscope $end -$scope struct \[3] $end -$var reg 1 h# mem_7 $end -$upscope $end -$scope struct \[4] $end -$var reg 1 i# mem_7 $end -$upscope $end -$scope struct \[5] $end -$var reg 1 j# mem_7 $end -$upscope $end -$scope struct \[6] $end -$var reg 1 k# mem_7 $end -$upscope $end -$scope struct \[7] $end -$var reg 1 l# mem_7 $end -$upscope $end -$scope struct \[8] $end -$var reg 1 m# mem_7 $end -$upscope $end -$scope struct \[9] $end -$var reg 1 n# mem_7 $end -$upscope $end -$scope struct \[10] $end -$var reg 1 o# mem_7 $end -$upscope $end -$scope struct \[11] $end -$var reg 1 p# mem_7 $end -$upscope $end -$scope struct \[12] $end -$var reg 1 q# mem_7 $end -$upscope $end -$scope struct \[13] $end -$var reg 1 r# mem_7 $end -$upscope $end -$scope struct \[14] $end -$var reg 1 s# mem_7 $end -$upscope $end -$scope struct \[15] $end -$var reg 1 t# mem_7 $end -$upscope $end -$upscope $end -$scope struct r0 $end -$var wire 4 J" addr $end -$var wire 1 K" en $end -$var wire 1 L" clk $end -$var wire 1 M" data $end -$upscope $end -$scope struct w1 $end -$var wire 4 N" addr $end -$var wire 1 O" en $end -$var wire 1 P" clk $end -$var wire 1 Q" data $end -$var wire 1 R" mask $end -$upscope $end -$upscope $end -$upscope $end -$enddefinitions $end -$dumpvars -0S" -0T" -0U" -0V" -0W" -0X" -0Y" -0Z" -0[" -0\" -0]" -0^" -0_" -0`" -0a" -0b" -1c" -0d" -0e" -0f" -0g" -0h" -0i" -0j" -0k" -0l" -0m" -0n" -0o" -0p" -0q" -0r" -0s" -0t" -0u" -0v" -0w" -1x" -0y" -0z" -0{" -0|" -0}" -0~" -0!# -0"# -0## -0$# -1%# -1&# -0'# -0(# -1)# -1*# -1+# -1,# -0-# -0.# -0/# -00# -01# -02# -03# -04# -05# -06# -07# -08# -09# -0:# -0;# -0<# -0=# -0># -1?# -0@# -0A# -0B# -0C# -0D# -1E# -0F# -1G# -0H# -1I# -1J# -0K# -0L# -0M# -0N# -1O# -1P# -0Q# -0R# -0S# -0T# -0U# -0V# -0W# -0X# -0Y# -1Z# -1[# -0\# -0]# -1^# -1_# -1`# -1a# -0b# -0c# -0d# -1e# -1f# -1g# -0h# -0i# -1j# -0k# -1l# -1m# -0n# -0o# -0p# -0q# -0r# -1s# -0t# -b0 ! -0" -0# -0$ -b0 % -0& -0' -0( -b0 ) -0* -0+ -0, -b0 - -0. -0/ -00 -b0 1 -02 -03 -04 -b0 5 -06 -07 -08 -b0 9 -0: -0; -0< -b0 = -0> -0? -0@ -b0 A -0B -0C -0D -0E -b0 F -0G -0H -0I -0J -b0 K -0L -0M -0N -0O -b0 P -0Q -0R -0S -0T -b0 U -0V -0W -0X -0Y -b0 Z -0[ -0\ -0] -0^ -b0 _ -0` -0a -0b -0c -b0 d -0e -0f -0g -0h -b0 i -0j -0k -0l -b0 m -0n -0o -0p -0q -b0 r -0s -0t -0u -b0 v -0w -0x -0y -0z -b0 { -0| -0} -0~ -b0 !" -0"" -0#" -0$" -0%" -b0 &" -0'" -0(" -0)" -b0 *" -0+" -0," -0-" -0." -b0 /" -00" -01" -02" -b0 3" -04" -05" -06" -07" -b0 8" -09" -0:" -0;" -b0 <" -0=" -0>" -0?" -0@" -b0 A" -0B" -0C" -0D" -b0 E" -0F" -0G" -0H" -0I" -b0 J" -0K" -0L" -0M" -b0 N" -0O" -0P" -0Q" -0R" -$end -#1000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#2000000 -1" -0# -1& -0' -1( -1* -0+ -1. -0/ -10 -12 -03 -16 -07 -18 -1: -0; -1> -0? -1@ -1B -0C -1D -1E -1G -0H -1I -1J -1L -0M -1N -1O -1Q -0R -1S -1T -1V -0W -1X -1Y -1[ -0\ -1] -1^ -1` -0a -1b -1c -1e -0f -1g -1h -1j -0k -1n -0o -1p -1q -1s -0t -1u -1w -0x -1y -1z -1| -0} -1"" -0#" -1$" -1%" -1'" -0(" -1)" -1+" -0," -1-" -1." -10" -01" -14" -05" -16" -17" -19" -0:" -1;" -1=" -0>" -1?" -1@" -1B" -0C" -1F" -0G" -1H" -1I" -1K" -0L" -1M" -1O" -0P" -1Q" -1R" -#3000000 -1S" -1c" -1s" -1%# -15# -1E# -1U# -1e# -1# -1$ -1' -1+ -1, -1/ -13 -14 -17 -1; -1< -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1l -1o -1t -1x -1} -1~ -1#" -1(" -1," -11" -12" -15" -1:" -1>" -1C" -1D" -1G" -1L" -1P" -#4000000 -0# -0' -0+ -0/ -03 -07 -0; -0? -0C -0D -0H -0I -0M -0N -0R -0S -0W -0X -0\ -0] -0a -0b -0f -0g -0k -0o -0p -0t -0x -0y -0} -0#" -0$" -0(" -0," -0-" -01" -05" -06" -0:" -0>" -0?" -0C" -0G" -0H" -0L" -0P" -0Q" -#5000000 -0S" -0c" -0s" -0%# -05# -0E# -0U# -0e# -1# -0$ -1' -0( -1+ -0, -1/ -00 -13 -04 -17 -08 -1; -0< -1? -0@ -1C -1H -1M -1R -1W -1\ -1a -1f -1k -0l -1o -1t -0u -1x -1} -0~ -1#" -1(" -0)" -1," -11" -02" -15" -1:" -0;" -1>" -1C" -0D" -1G" -1L" -0M" -1P" -#6000000 -0# -0' -0+ -0/ -03 -07 -0; -0? -0B -0C -0G -0H -0L -0M -0Q -0R -0V -0W -0[ -0\ -0` -0a -0e -0f -0k -0n -0o -0t -0w -0x -0} -0"" -0#" -0(" -0+" -0," -01" -04" -05" -0:" -0=" -0>" -0C" -0F" -0G" -0L" -0O" -0P" -#7000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#8000000 -b1 ! -0# -b1 % -0' -b1 ) -0+ -b1 - -0/ -10 -b1 1 -03 -b1 5 -07 -b1 9 -0; -b1 = -0? -1@ -0C -0H -0M -0R -0W -0\ -0a -0f -b1 i -0k -0o -b1 r -0t -0x -b1 { -0} -0#" -b1 &" -0(" -1)" -0," -b1 /" -01" -05" -b1 8" -0:" -0>" -b1 A" -0C" -0G" -b1 J" -0L" -1M" -0P" -#9000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#10000000 -b10 ! -0# -b10 % -0' -b10 ) -0+ -b10 - -0/ -00 -b10 1 -03 -b10 5 -07 -18 -b10 9 -0; -b10 = -0? -0C -0H -0M -0R -0W -0\ -0a -0f -b10 i -0k -0o -b10 r -0t -0x -b10 { -0} -0#" -b10 &" -0(" -0)" -0," -b10 /" -01" -05" -b10 8" -0:" -1;" -0>" -b10 A" -0C" -0G" -b10 J" -0L" -0P" -#11000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#12000000 -b11 ! -0# -b11 % -0' -b11 ) -0+ -b11 - -0/ -b11 1 -03 -b11 5 -07 -08 -b11 9 -0; -b11 = -0? -0@ -0C -0H -0M -0R -0W -0\ -0a -0f -b11 i -0k -0o -b11 r -0t -0x -b11 { -0} -0#" -b11 &" -0(" -0," -b11 /" -01" -05" -b11 8" -0:" -0;" -0>" -b11 A" -0C" -0G" -b11 J" -0L" -0M" -0P" -#13000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#14000000 -b100 ! -0# -b100 % -0' -b100 ) -0+ -b100 - -0/ -10 -b100 1 -03 -b100 5 -07 -18 -b100 9 -0; -b100 = -0? -0C -0H -0M -0R -0W -0\ -0a -0f -b100 i -0k -0o -b100 r -0t -0x -b100 { -0} -0#" -b100 &" -0(" -1)" -0," -b100 /" -01" -05" -b100 8" -0:" -1;" -0>" -b100 A" -0C" -0G" -b100 J" -0L" -0P" -#15000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#16000000 -b101 ! -0# -b101 % -0' -b101 ) -0+ -1, -b101 - -0/ -b101 1 -03 -b101 5 -07 -b101 9 -0; -1< -b101 = -0? -1@ -0C -0H -0M -0R -0W -0\ -0a -0f -b101 i -0k -0o -b101 r -0t -0x -b101 { -0} -1~ -0#" -b101 &" -0(" -0," -b101 /" -01" -05" -b101 8" -0:" -0>" -b101 A" -0C" -1D" -0G" -b101 J" -0L" -1M" -0P" -#17000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#18000000 -b110 ! -0# -b110 % -0' -b110 ) -0+ -0, -b110 - -0/ -b110 1 -03 -b110 5 -07 -08 -b110 9 -0; -b110 = -0? -0@ -0C -0H -0M -0R -0W -0\ -0a -0f -b110 i -0k -0o -b110 r -0t -0x -b110 { -0} -0~ -0#" -b110 &" -0(" -0," -b110 /" -01" -05" -b110 8" -0:" -0;" -0>" -b110 A" -0C" -0G" -b110 J" -0L" -0M" -0P" -#19000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#20000000 -b111 ! -0# -b111 % -0' -b111 ) -0+ -b111 - -0/ -b111 1 -03 -b111 5 -07 -b111 9 -0; -0< -b111 = -0? -1@ -0C -0H -0M -0R -0W -0\ -0a -0f -b111 i -0k -0o -b111 r -0t -0x -b111 { -0} -0#" -b111 &" -0(" -0," -b111 /" -01" -05" -b111 8" -0:" -0>" -b111 A" -0C" -0D" -0G" -b111 J" -0L" -1M" -0P" -#21000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#22000000 -b1000 ! -0# -b1000 % -0' -b1000 ) -0+ -b1000 - -0/ -00 -b1000 1 -03 -b1000 5 -07 -b1000 9 -0; -b1000 = -0? -0C -0H -0M -0R -0W -0\ -0a -0f -b1000 i -0k -0o -b1000 r -0t -0x -b1000 { -0} -0#" -b1000 &" -0(" -0)" -0," -b1000 /" -01" -05" -b1000 8" -0:" -0>" -b1000 A" -0C" -0G" -b1000 J" -0L" -0P" -#23000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#24000000 -b1001 ! -0# -b1001 % -0' -b1001 ) -0+ -b1001 - -0/ -b1001 1 -03 -b1001 5 -07 -b1001 9 -0; -1< -b1001 = -0? -0@ -0C -0H -0M -0R -0W -0\ -0a -0f -b1001 i -0k -0o -b1001 r -0t -0x -b1001 { -0} -0#" -b1001 &" -0(" -0," -b1001 /" -01" -05" -b1001 8" -0:" -0>" -b1001 A" -0C" -1D" -0G" -b1001 J" -0L" -0M" -0P" -#25000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#26000000 -b1010 ! -0# -b1010 % -0' -b1010 ) -0+ -b1010 - -0/ -b1010 1 -03 -14 -b1010 5 -07 -18 -b1010 9 -0; -b1010 = -0? -0C -0H -0M -0R -0W -0\ -0a -0f -b1010 i -0k -0o -b1010 r -0t -0x -b1010 { -0} -0#" -b1010 &" -0(" -0," -b1010 /" -01" -12" -05" -b1010 8" -0:" -1;" -0>" -b1010 A" -0C" -0G" -b1010 J" -0L" -0P" -#27000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#28000000 -b1011 ! -0# -b1011 % -0' -b1011 ) -0+ -b1011 - -0/ -b1011 1 -03 -04 -b1011 5 -07 -b1011 9 -0; -b1011 = -0? -0C -0H -0M -0R -0W -0\ -0a -0f -b1011 i -0k -0o -b1011 r -0t -0x -b1011 { -0} -0#" -b1011 &" -0(" -0," -b1011 /" -01" -02" -05" -b1011 8" -0:" -0>" -b1011 A" -0C" -0G" -b1011 J" -0L" -0P" -#29000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#30000000 -b1100 ! -0# -b1100 % -0' -b1100 ) -0+ -b1100 - -0/ -b1100 1 -03 -b1100 5 -07 -08 -b1100 9 -0; -b1100 = -0? -0C -0H -0M -0R -0W -0\ -0a -0f -b1100 i -0k -0o -b1100 r -0t -0x -b1100 { -0} -0#" -b1100 &" -0(" -0," -b1100 /" -01" -05" -b1100 8" -0:" -0;" -0>" -b1100 A" -0C" -0G" -b1100 J" -0L" -0P" -#31000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#32000000 -b1101 ! -0# -b1101 % -0' -b1101 ) -0+ -b1101 - -0/ -b1101 1 -03 -b1101 5 -07 -b1101 9 -0; -0< -b1101 = -0? -0C -0H -0M -0R -0W -0\ -0a -0f -b1101 i -0k -0o -b1101 r -0t -0x -b1101 { -0} -0#" -b1101 &" -0(" -0," -b1101 /" -01" -05" -b1101 8" -0:" -0>" -b1101 A" -0C" -0D" -0G" -b1101 J" -0L" -0P" -#33000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#34000000 -b1110 ! -0# -b1110 % -0' -b1110 ) -0+ -b1110 - -0/ -b1110 1 -03 -b1110 5 -07 -b1110 9 -0; -b1110 = -0? -1@ -0C -0H -0M -0R -0W -0\ -0a -0f -b1110 i -0k -0o -b1110 r -0t -0x -b1110 { -0} -0#" -b1110 &" -0(" -0," -b1110 /" -01" -05" -b1110 8" -0:" -0>" -b1110 A" -0C" -0G" -b1110 J" -0L" -1M" -0P" -#35000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#36000000 -b1111 ! -0# -b1111 % -0' -b1111 ) -0+ -b1111 - -0/ -b1111 1 -03 -b1111 5 -07 -b1111 9 -0; -b1111 = -0? -0@ -0C -0H -0M -0R -0W -0\ -0a -0f -b1111 i -0k -0o -b1111 r -0t -0x -b1111 { -0} -0#" -b1111 &" -0(" -0," -b1111 /" -01" -05" -b1111 8" -0:" -0>" -b1111 A" -0C" -0G" -b1111 J" -0L" -0M" -0P" -#37000000 -1# -1' -1+ -1/ -13 -17 -1; -1? -1C -1H -1M -1R -1W -1\ -1a -1f -1k -1o -1t -1x -1} -1#" -1(" -1," -11" -15" -1:" -1>" -1C" -1G" -1L" -1P" -#38000000 -0# -0' -0+ -0/ -03 -07 -0; -0? -0C -0H -0M -0R -0W -0\ -0a -0f -0k -0o -0t -0x -0} -0#" -0(" -0," -01" -05" -0:" -0>" -0C" -0G" -0L" -0P" diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt index 03c5ee37..f7f88e3b 100644 --- a/crates/fayalite/tests/sim/expected/memories.txt +++ b/crates/fayalite/tests/sim/expected/memories.txt @@ -721,6 +721,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "memories", children: [ @@ -1615,15 +1616,10 @@ Simulation { }, ), ], + instant: 22 μs, clocks_triggered: [ StatePartIndex(1), StatePartIndex(6), ], - event_queue: EventQueue(EventQueueData { - instant: 22 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories.vcd b/crates/fayalite/tests/sim/expected/memories.vcd index d8f58172..bedc354b 100644 --- a/crates/fayalite/tests/sim/expected/memories.vcd +++ b/crates/fayalite/tests/sim/expected/memories.vcd @@ -234,13 +234,13 @@ b100000 6 b10000 9 b100000 I 1# -b10000 $ -b100000 % 1( 1/ +14 +b10000 $ +b100000 % b10000 0 b100000 1 -14 #4000000 0# 0( @@ -256,11 +256,11 @@ b1000000 6 b10000 9 b1000000 I 1# -b1000000 % 1( 1/ -b1000000 1 14 +b1000000 % +b1000000 1 #6000000 0# 0( @@ -278,11 +278,11 @@ b1100000 6 b1010000 9 b1000000 I 1# -b1010000 $ 1( 1/ -b1010000 0 14 +b1010000 $ +b1010000 0 #8000000 0# 0( diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt index f1cb72b6..c216104c 100644 --- a/crates/fayalite/tests/sim/expected/memories2.txt +++ b/crates/fayalite/tests/sim/expected/memories2.txt @@ -679,6 +679,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "memories2", children: [ @@ -1259,14 +1260,9 @@ Simulation { }, ), ], + instant: 22 μs, clocks_triggered: [ StatePartIndex(3), ], - event_queue: EventQueue(EventQueueData { - instant: 22 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories2.vcd b/crates/fayalite/tests/sim/expected/memories2.vcd index 0ac20f19..4039754f 100644 --- a/crates/fayalite/tests/sim/expected/memories2.vcd +++ b/crates/fayalite/tests/sim/expected/memories2.vcd @@ -100,8 +100,8 @@ $end 1) #1250000 1# -b11 $ 1* +b11 $ sHdlSome\x20(1) + 1, #1500000 @@ -113,8 +113,8 @@ sHdlSome\x20(1) + 0) #2250000 1# -b0 $ 1* +b0 $ sHdlNone\x20(0) + 0, #2500000 @@ -303,8 +303,8 @@ b11 ! b11 ( #17250000 1# -b11 $ 1* +b11 $ sHdlSome\x20(1) + 1, #17500000 @@ -316,8 +316,8 @@ b10 ! b10 ( #18250000 1# -b0 $ 1* +b0 $ sHdlNone\x20(0) + 0, #18500000 @@ -339,8 +339,8 @@ b1 ! b1 ( #20250000 1# -b1 $ 1* +b1 $ sHdlSome\x20(1) + #20500000 #20750000 @@ -353,8 +353,8 @@ b0 ( 0) #21250000 1# -b0 $ 1* +b0 $ sHdlNone\x20(0) + #21500000 #21750000 diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt index 3166e17b..8114c7e4 100644 --- a/crates/fayalite/tests/sim/expected/memories3.txt +++ b/crates/fayalite/tests/sim/expected/memories3.txt @@ -1763,6 +1763,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "memories3", children: [ @@ -3274,15 +3275,10 @@ Simulation { }, ), ], + instant: 15 μs, clocks_triggered: [ StatePartIndex(1), StatePartIndex(6), ], - event_queue: EventQueue(EventQueueData { - instant: 15 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories3.vcd b/crates/fayalite/tests/sim/expected/memories3.vcd index 32ee75e6..5768560e 100644 --- a/crates/fayalite/tests/sim/expected/memories3.vcd +++ b/crates/fayalite/tests/sim/expected/memories3.vcd @@ -420,10 +420,6 @@ b10000 T 1\ #3250000 1# -b110100 % -b1111000 ' -b10011010 ( -b11110000 + 1. 1A b110100 C @@ -431,6 +427,10 @@ b1111000 E b10011010 F b11110000 I 1L +b110100 % +b1111000 ' +b10011010 ( +b11110000 + #3500000 #3750000 0# @@ -508,14 +508,6 @@ b1010100 '" b110010 /" b10000 7" 1# -b11111110 $ -b11011100 % -b10111010 & -b10011000 ' -b1110110 ( -b1010100 ) -b110010 * -b10000 + 1. 1A b11111110 B @@ -527,6 +519,14 @@ b1010100 G b110010 H b10000 I 1L +b11111110 $ +b11011100 % +b10111010 & +b10011000 ' +b1110110 ( +b1010100 ) +b110010 * +b10000 + #6500000 #6750000 0# @@ -562,14 +562,6 @@ b1000110 (" b10001010 0" b11001110 8" 1# -b0 $ -b0 % -b0 & -b0 ' -b0 ( -b0 ) -b0 * -b0 + 1. 1A b0 B @@ -581,6 +573,14 @@ b0 G b0 H b0 I 1L +b0 $ +b0 % +b0 & +b0 ' +b0 ( +b0 ) +b0 * +b0 + #7500000 #7750000 0# @@ -688,14 +688,6 @@ b1 ! b1 ? #10250000 1# -b11111110 $ -b11011100 % -b10111010 & -b10011000 ' -b1110110 ( -b1010100 ) -b110010 * -b10000 + 1. 1A b11111110 B @@ -707,6 +699,14 @@ b1010100 G b110010 H b10000 I 1L +b11111110 $ +b11011100 % +b10111010 & +b10011000 ' +b1110110 ( +b1010100 ) +b110010 * +b10000 + #10500000 #10750000 0# @@ -718,14 +718,6 @@ b10 ! b10 ? #11250000 1# -b10011 $ -b1010111 % -b10011011 & -b11011111 ' -b10 ( -b1000110 ) -b10001010 * -b11001110 + 1. 1A b10011 B @@ -737,6 +729,14 @@ b1000110 G b10001010 H b11001110 I 1L +b10011 $ +b1010111 % +b10011011 & +b11011111 ' +b10 ( +b1000110 ) +b10001010 * +b11001110 + #11500000 #11750000 0# @@ -748,14 +748,6 @@ b11 ! b11 ? #12250000 1# -b1110100 $ -b1100101 % -b1110011 & -b1110100 ' -b1101001 ( -b1101110 ) -b1100111 * -b100001 + 1. 1A b1110100 B @@ -767,6 +759,14 @@ b1101110 G b1100111 H b100001 I 1L +b1110100 $ +b1100101 % +b1110011 & +b1110100 ' +b1101001 ( +b1101110 ) +b1100111 * +b100001 + #12500000 #12750000 0# @@ -780,14 +780,6 @@ b0 ? 0@ #13250000 1# -b1101101 $ -b1101111 % -b1110010 & -b1100101 ' -b100000 ( -b1110100 ) -b1110011 * -b1110100 + 1. 1A b1101101 B @@ -799,6 +791,14 @@ b1110100 G b1110011 H b1110100 I 1L +b1101101 $ +b1101111 % +b1110010 & +b1100101 ' +b100000 ( +b1110100 ) +b1110011 * +b1110100 + #13500000 #13750000 0# @@ -808,14 +808,6 @@ b1110100 I #14000000 #14250000 1# -b0 $ -b0 % -b0 & -b0 ' -b0 ( -b0 ) -b0 * -b0 + 1. 1A b0 B @@ -827,6 +819,14 @@ b0 G b0 H b0 I 1L +b0 $ +b0 % +b0 & +b0 ' +b0 ( +b0 ) +b0 * +b0 + #14500000 #14750000 0# diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt index 355b6ee0..4ef02b2e 100644 --- a/crates/fayalite/tests/sim/expected/mod1.txt +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -276,6 +276,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "mod1", children: [ @@ -557,12 +558,7 @@ Simulation { }, ), ], + instant: 2 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 2 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt index 58189754..9e4e0d1b 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.txt +++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt @@ -827,6 +827,52 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 3, len: 0 }, + big_slots: StatePartIndexRange { start: 33, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + }, }, SimulationExternModuleState { module_state: SimulationModuleState { @@ -910,6 +956,52 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 6, len: 0 }, + big_slots: StatePartIndexRange { start: 44, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + }, }, SimulationExternModuleState { module_state: SimulationModuleState { @@ -993,8 +1085,55 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 55, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + }, }, ], + state_ready_to_run: false, trace_decls: TraceModule { name: "ripple_counter", children: [ @@ -1454,315 +1593,11 @@ Simulation { }, ), ], + instant: 256 μs, clocks_triggered: [ StatePartIndex(1), StatePartIndex(4), StatePartIndex(7), ], - event_queue: EventQueue(EventQueueData { - instant: 256 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 152, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 55, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - SensitivitySet { - id: 167, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 6, len: 0 }, - big_slots: StatePartIndexRange { start: 44, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - SensitivitySet { - id: 170, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 3, len: 0 }, - big_slots: StatePartIndexRange { start: 33, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 3, len: 0 }, - big_slots: StatePartIndexRange { start: 33, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 170, - .. - }, - }, - ), - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 6, len: 0 }, - big_slots: StatePartIndexRange { start: 44, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 167, - .. - }, - }, - ), - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 55, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 152, - .. - }, - }, - ), - }, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.vcd b/crates/fayalite/tests/sim/expected/ripple_counter.vcd index 550205f8..6f14a8e8 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.vcd +++ b/crates/fayalite/tests/sim/expected/ripple_counter.vcd @@ -66,1648 +66,1688 @@ b0 " $end #1000000 1! +1) b1 " 1# -1) 1* 1, -b111 " -1$ -1% 1+ +b11 " +1$ 1- 1. +b111 " +1% 1/ 11 -b11111 " -1& -1' 10 +b1111 " +1& 12 13 +b11111 " +1' 14 16 +15 b111111 " 1( -15 17 #2000000 0! #3000000 1! +0) b111110 " 0# -0) 0* 0, #4000000 0! #5000000 1! +1) b111111 " 1# -1) 1* 1, +0+ b111101 " 0$ -0+ 0- #6000000 0! #7000000 1! +0) b111100 " 0# -0) 0* 0, #8000000 0! #9000000 1! +1) b111101 " 1# -1) 1* 1, -b111011 " -1$ -0% 1+ +b111111 " +1$ 1- 0. +b111011 " +0% 0/ 01 #10000000 0! #11000000 1! +0) b111010 " 0# -0) 0* 0, #12000000 0! #13000000 1! +1) b111011 " 1# -1) 1* 1, +0+ b111001 " 0$ -0+ 0- #14000000 0! #15000000 1! +0) b111000 " 0# -0) 0* 0, #16000000 0! #17000000 1! +1) b111001 " 1# -1) 1* 1, -b111111 " -1$ -1% 1+ +b111011 " +1$ 1- 1. +b111111 " +1% 1/ 11 +00 b110111 " 0& -00 02 #18000000 0! #19000000 1! +0) b110110 " 0# -0) 0* 0, #20000000 0! #21000000 1! +1) b110111 " 1# -1) 1* 1, +0+ b110101 " 0$ -0+ 0- #22000000 0! #23000000 1! +0) b110100 " 0# -0) 0* 0, #24000000 0! #25000000 1! +1) b110101 " 1# -1) 1* 1, -b110011 " -1$ -0% 1+ +b110111 " +1$ 1- 0. +b110011 " +0% 0/ 01 #26000000 0! #27000000 1! +0) b110010 " 0# -0) 0* 0, #28000000 0! #29000000 1! +1) b110011 " 1# -1) 1* 1, +0+ b110001 " 0$ -0+ 0- #30000000 0! #31000000 1! +0) b110000 " 0# -0) 0* 0, #32000000 0! #33000000 1! +1) b110001 " 1# -1) 1* 1, -b110111 " -1$ -1% 1+ +b110011 " +1$ 1- 1. +b110111 " +1% 1/ 11 -b101111 " -1& -0' 10 +b111111 " +1& 12 03 +b101111 " +0' 04 06 #34000000 0! #35000000 1! +0) b101110 " 0# -0) 0* 0, #36000000 0! #37000000 1! +1) b101111 " 1# -1) 1* 1, +0+ b101101 " 0$ -0+ 0- #38000000 0! #39000000 1! +0) b101100 " 0# -0) 0* 0, #40000000 0! #41000000 1! +1) b101101 " 1# -1) 1* 1, -b101011 " -1$ -0% 1+ +b101111 " +1$ 1- 0. +b101011 " +0% 0/ 01 #42000000 0! #43000000 1! +0) b101010 " 0# -0) 0* 0, #44000000 0! #45000000 1! +1) b101011 " 1# -1) 1* 1, +0+ b101001 " 0$ -0+ 0- #46000000 0! #47000000 1! +0) b101000 " 0# -0) 0* 0, #48000000 0! #49000000 1! +1) b101001 " 1# -1) 1* 1, -b101111 " -1$ -1% 1+ +b101011 " +1$ 1- 1. +b101111 " +1% 1/ 11 +00 b100111 " 0& -00 02 #50000000 0! #51000000 1! +0) b100110 " 0# -0) 0* 0, #52000000 0! #53000000 1! +1) b100111 " 1# -1) 1* 1, +0+ b100101 " 0$ -0+ 0- #54000000 0! #55000000 1! +0) b100100 " 0# -0) 0* 0, #56000000 0! #57000000 1! +1) b100101 " 1# -1) 1* 1, -b100011 " -1$ -0% 1+ +b100111 " +1$ 1- 0. +b100011 " +0% 0/ 01 #58000000 0! #59000000 1! +0) b100010 " 0# -0) 0* 0, #60000000 0! #61000000 1! +1) b100011 " 1# -1) 1* 1, +0+ b100001 " 0$ -0+ 0- #62000000 0! #63000000 1! +0) b100000 " 0# -0) 0* 0, #64000000 0! #65000000 1! +1) b100001 " 1# -1) 1* 1, -b100111 " -1$ -1% 1+ +b100011 " +1$ 1- 1. +b100111 " +1% 1/ 11 -b111111 " -1& -1' 10 +b101111 " +1& 12 13 +b111111 " +1' 14 16 +05 b11111 " 0( -05 07 #66000000 0! #67000000 1! +0) b11110 " 0# -0) 0* 0, #68000000 0! #69000000 1! +1) b11111 " 1# -1) 1* 1, +0+ b11101 " 0$ -0+ 0- #70000000 0! #71000000 1! +0) b11100 " 0# -0) 0* 0, #72000000 0! #73000000 1! +1) b11101 " 1# -1) 1* 1, -b11011 " -1$ -0% 1+ +b11111 " +1$ 1- 0. +b11011 " +0% 0/ 01 #74000000 0! #75000000 1! +0) b11010 " 0# -0) 0* 0, #76000000 0! #77000000 1! +1) b11011 " 1# -1) 1* 1, +0+ b11001 " 0$ -0+ 0- #78000000 0! #79000000 1! +0) b11000 " 0# -0) 0* 0, #80000000 0! #81000000 1! +1) b11001 " 1# -1) 1* 1, -b11111 " -1$ -1% 1+ +b11011 " +1$ 1- 1. +b11111 " +1% 1/ 11 +00 b10111 " 0& -00 02 #82000000 0! #83000000 1! +0) b10110 " 0# -0) 0* 0, #84000000 0! #85000000 1! +1) b10111 " 1# -1) 1* 1, +0+ b10101 " 0$ -0+ 0- #86000000 0! #87000000 1! +0) b10100 " 0# -0) 0* 0, #88000000 0! #89000000 1! +1) b10101 " 1# -1) 1* 1, -b10011 " -1$ -0% 1+ +b10111 " +1$ 1- 0. +b10011 " +0% 0/ 01 #90000000 0! #91000000 1! +0) b10010 " 0# -0) 0* 0, #92000000 0! #93000000 1! +1) b10011 " 1# -1) 1* 1, +0+ b10001 " 0$ -0+ 0- #94000000 0! #95000000 1! +0) b10000 " 0# -0) 0* 0, #96000000 0! #97000000 1! +1) b10001 " 1# -1) 1* 1, -b10111 " -1$ -1% 1+ +b10011 " +1$ 1- 1. +b10111 " +1% 1/ 11 -b1111 " -1& -0' 10 +b11111 " +1& 12 03 +b1111 " +0' 04 06 #98000000 0! #99000000 1! +0) b1110 " 0# -0) 0* 0, #100000000 0! #101000000 1! +1) b1111 " 1# -1) 1* 1, +0+ b1101 " 0$ -0+ 0- #102000000 0! #103000000 1! +0) b1100 " 0# -0) 0* 0, #104000000 0! #105000000 1! +1) b1101 " 1# -1) 1* 1, -b1011 " -1$ -0% 1+ +b1111 " +1$ 1- 0. +b1011 " +0% 0/ 01 #106000000 0! #107000000 1! +0) b1010 " 0# -0) 0* 0, #108000000 0! #109000000 1! +1) b1011 " 1# -1) 1* 1, +0+ b1001 " 0$ -0+ 0- #110000000 0! #111000000 1! +0) b1000 " 0# -0) 0* 0, #112000000 0! #113000000 1! +1) b1001 " 1# -1) 1* 1, -b1111 " -1$ -1% 1+ +b1011 " +1$ 1- 1. +b1111 " +1% 1/ 11 +00 b111 " 0& -00 02 #114000000 0! #115000000 1! +0) b110 " 0# -0) 0* 0, #116000000 0! #117000000 1! +1) b111 " 1# -1) 1* 1, +0+ b101 " 0$ -0+ 0- #118000000 0! #119000000 1! +0) b100 " 0# -0) 0* 0, #120000000 0! #121000000 1! +1) b101 " 1# -1) 1* 1, -b11 " -1$ -0% 1+ +b111 " +1$ 1- 0. +b11 " +0% 0/ 01 #122000000 0! #123000000 1! +0) b10 " 0# -0) 0* 0, #124000000 0! #125000000 1! +1) b11 " 1# -1) 1* 1, +0+ b1 " 0$ -0+ 0- #126000000 0! #127000000 1! +0) b0 " 0# -0) 0* 0, #128000000 0! #129000000 1! +1) b1 " 1# -1) 1* 1, -b111 " -1$ -1% 1+ +b11 " +1$ 1- 1. +b111 " +1% 1/ 11 -b11111 " -1& -1' 10 +b1111 " +1& 12 13 +b11111 " +1' 14 16 +15 b111111 " 1( -15 17 #130000000 0! #131000000 1! +0) b111110 " 0# -0) 0* 0, #132000000 0! #133000000 1! +1) b111111 " 1# -1) 1* 1, +0+ b111101 " 0$ -0+ 0- #134000000 0! #135000000 1! +0) b111100 " 0# -0) 0* 0, #136000000 0! #137000000 1! +1) b111101 " 1# -1) 1* 1, -b111011 " -1$ -0% 1+ +b111111 " +1$ 1- 0. +b111011 " +0% 0/ 01 #138000000 0! #139000000 1! +0) b111010 " 0# -0) 0* 0, #140000000 0! #141000000 1! +1) b111011 " 1# -1) 1* 1, +0+ b111001 " 0$ -0+ 0- #142000000 0! #143000000 1! +0) b111000 " 0# -0) 0* 0, #144000000 0! #145000000 1! +1) b111001 " 1# -1) 1* 1, -b111111 " -1$ -1% 1+ +b111011 " +1$ 1- 1. +b111111 " +1% 1/ 11 +00 b110111 " 0& -00 02 #146000000 0! #147000000 1! +0) b110110 " 0# -0) 0* 0, #148000000 0! #149000000 1! +1) b110111 " 1# -1) 1* 1, +0+ b110101 " 0$ -0+ 0- #150000000 0! #151000000 1! +0) b110100 " 0# -0) 0* 0, #152000000 0! #153000000 1! +1) b110101 " 1# -1) 1* 1, -b110011 " -1$ -0% 1+ +b110111 " +1$ 1- 0. +b110011 " +0% 0/ 01 #154000000 0! #155000000 1! +0) b110010 " 0# -0) 0* 0, #156000000 0! #157000000 1! +1) b110011 " 1# -1) 1* 1, +0+ b110001 " 0$ -0+ 0- #158000000 0! #159000000 1! +0) b110000 " 0# -0) 0* 0, #160000000 0! #161000000 1! +1) b110001 " 1# -1) 1* 1, -b110111 " -1$ -1% 1+ +b110011 " +1$ 1- 1. +b110111 " +1% 1/ 11 -b101111 " -1& -0' 10 +b111111 " +1& 12 03 +b101111 " +0' 04 06 #162000000 0! #163000000 1! +0) b101110 " 0# -0) 0* 0, #164000000 0! #165000000 1! +1) b101111 " 1# -1) 1* 1, +0+ b101101 " 0$ -0+ 0- #166000000 0! #167000000 1! +0) b101100 " 0# -0) 0* 0, #168000000 0! #169000000 1! +1) b101101 " 1# -1) 1* 1, -b101011 " -1$ -0% 1+ +b101111 " +1$ 1- 0. +b101011 " +0% 0/ 01 #170000000 0! #171000000 1! +0) b101010 " 0# -0) 0* 0, #172000000 0! #173000000 1! +1) b101011 " 1# -1) 1* 1, +0+ b101001 " 0$ -0+ 0- #174000000 0! #175000000 1! +0) b101000 " 0# -0) 0* 0, #176000000 0! #177000000 1! +1) b101001 " 1# -1) 1* 1, -b101111 " -1$ -1% 1+ +b101011 " +1$ 1- 1. +b101111 " +1% 1/ 11 +00 b100111 " 0& -00 02 #178000000 0! #179000000 1! +0) b100110 " 0# -0) 0* 0, #180000000 0! #181000000 1! +1) b100111 " 1# -1) 1* 1, +0+ b100101 " 0$ -0+ 0- #182000000 0! #183000000 1! +0) b100100 " 0# -0) 0* 0, #184000000 0! #185000000 1! +1) b100101 " 1# -1) 1* 1, -b100011 " -1$ -0% 1+ +b100111 " +1$ 1- 0. +b100011 " +0% 0/ 01 #186000000 0! #187000000 1! +0) b100010 " 0# -0) 0* 0, #188000000 0! #189000000 1! +1) b100011 " 1# -1) 1* 1, +0+ b100001 " 0$ -0+ 0- #190000000 0! #191000000 1! +0) b100000 " 0# -0) 0* 0, #192000000 0! #193000000 1! +1) b100001 " 1# -1) 1* 1, -b100111 " -1$ -1% 1+ +b100011 " +1$ 1- 1. +b100111 " +1% 1/ 11 -b111111 " -1& -1' 10 +b101111 " +1& 12 13 +b111111 " +1' 14 16 +05 b11111 " 0( -05 07 #194000000 0! #195000000 1! +0) b11110 " 0# -0) 0* 0, #196000000 0! #197000000 1! +1) b11111 " 1# -1) 1* 1, +0+ b11101 " 0$ -0+ 0- #198000000 0! #199000000 1! +0) b11100 " 0# -0) 0* 0, #200000000 0! #201000000 1! +1) b11101 " 1# -1) 1* 1, -b11011 " -1$ -0% 1+ +b11111 " +1$ 1- 0. +b11011 " +0% 0/ 01 #202000000 0! #203000000 1! +0) b11010 " 0# -0) 0* 0, #204000000 0! #205000000 1! +1) b11011 " 1# -1) 1* 1, +0+ b11001 " 0$ -0+ 0- #206000000 0! #207000000 1! +0) b11000 " 0# -0) 0* 0, #208000000 0! #209000000 1! +1) b11001 " 1# -1) 1* 1, -b11111 " -1$ -1% 1+ +b11011 " +1$ 1- 1. +b11111 " +1% 1/ 11 +00 b10111 " 0& -00 02 #210000000 0! #211000000 1! +0) b10110 " 0# -0) 0* 0, #212000000 0! #213000000 1! +1) b10111 " 1# -1) 1* 1, +0+ b10101 " 0$ -0+ 0- #214000000 0! #215000000 1! +0) b10100 " 0# -0) 0* 0, #216000000 0! #217000000 1! +1) b10101 " 1# -1) 1* 1, -b10011 " -1$ -0% 1+ +b10111 " +1$ 1- 0. +b10011 " +0% 0/ 01 #218000000 0! #219000000 1! +0) b10010 " 0# -0) 0* 0, #220000000 0! #221000000 1! +1) b10011 " 1# -1) 1* 1, +0+ b10001 " 0$ -0+ 0- #222000000 0! #223000000 1! +0) b10000 " 0# -0) 0* 0, #224000000 0! #225000000 1! +1) b10001 " 1# -1) 1* 1, -b10111 " -1$ -1% 1+ +b10011 " +1$ 1- 1. +b10111 " +1% 1/ 11 -b1111 " -1& -0' 10 +b11111 " +1& 12 03 +b1111 " +0' 04 06 #226000000 0! #227000000 1! +0) b1110 " 0# -0) 0* 0, #228000000 0! #229000000 1! +1) b1111 " 1# -1) 1* 1, +0+ b1101 " 0$ -0+ 0- #230000000 0! #231000000 1! +0) b1100 " 0# -0) 0* 0, #232000000 0! #233000000 1! +1) b1101 " 1# -1) 1* 1, -b1011 " -1$ -0% 1+ +b1111 " +1$ 1- 0. +b1011 " +0% 0/ 01 #234000000 0! #235000000 1! +0) b1010 " 0# -0) 0* 0, #236000000 0! #237000000 1! +1) b1011 " 1# -1) 1* 1, +0+ b1001 " 0$ -0+ 0- #238000000 0! #239000000 1! +0) b1000 " 0# -0) 0* 0, #240000000 0! #241000000 1! +1) b1001 " 1# -1) 1* 1, -b1111 " -1$ -1% 1+ +b1011 " +1$ 1- 1. +b1111 " +1% 1/ 11 +00 b111 " 0& -00 02 #242000000 0! #243000000 1! +0) b110 " 0# -0) 0* 0, #244000000 0! #245000000 1! +1) b111 " 1# -1) 1* 1, +0+ b101 " 0$ -0+ 0- #246000000 0! #247000000 1! +0) b100 " 0# -0) 0* 0, #248000000 0! #249000000 1! +1) b101 " 1# -1) 1* 1, -b11 " -1$ -0% 1+ +b111 " +1$ 1- 0. +b11 " +0% 0/ 01 #250000000 0! #251000000 1! +0) b10 " 0# -0) 0* 0, #252000000 0! #253000000 1! +1) b11 " 1# -1) 1* 1, +0+ b1 " 0$ -0+ 0- #254000000 0! #255000000 1! +0) b0 " 0# -0) 0* 0, #256000000 diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt index 2ca06d2d..9bab4248 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -339,6 +339,7 @@ Simulation { did_initial_settle: true, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "shift_register", children: [ @@ -439,7 +440,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x0, + last_state: 0x1, }, SimTrace { id: TraceScalarId(1), @@ -508,14 +509,9 @@ Simulation { }, ), ], + instant: 66 μs, clocks_triggered: [ StatePartIndex(1), ], - event_queue: EventQueue(EventQueueData { - instant: 66 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/shift_register.vcd b/crates/fayalite/tests/sim/expected/shift_register.vcd index 26726eb0..0b5f4290 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.vcd +++ b/crates/fayalite/tests/sim/expected/shift_register.vcd @@ -52,9 +52,9 @@ $end 0! #11000000 1! -1$ 0& 1( +1$ #12000000 0! 1# @@ -67,10 +67,10 @@ $end 0# #15000000 1! -0$ 0% 1& 0( +0$ #16000000 0! 1# @@ -83,23 +83,23 @@ $end 0! #19000000 1! -1$ 1& 0' 1( +1$ #20000000 0! #21000000 1! -0$ 1' 0( +0$ #22000000 0! #23000000 1! -1$ 1( +1$ #24000000 0! 0# @@ -120,8 +120,8 @@ $end 0! #31000000 1! -0$ 0( +0$ #32000000 0! #33000000 diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.txt b/crates/fayalite/tests/sim/expected/sim_fork_join.txt deleted file mode 100644 index 4ad3e620..00000000 --- a/crates/fayalite/tests/sim/expected/sim_fork_join.txt +++ /dev/null @@ -1,523 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 6, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[2]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[2]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - 0: Return, - ], - .. - }, - pc: 0, - memory_write_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 0, - 0, - 0, - 49, - 50, - 50, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.clocks, - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.outputs, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.clocks, - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.clocks[0], - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.clocks[1], - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.clocks[2], - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.outputs, - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.outputs[0], - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.outputs[1], - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.outputs[2], - }, - did_initial_settle: true, - }, - extern_modules: [ - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }[0], - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }[1], - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }[2], - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }[0], - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }[1], - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }[2], - }, - did_initial_settle: true, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ), - f: ..., - }, - sim_io_to_generator_map: { - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }: ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }: ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - }, - source_location: SourceLocation( - module-XXXXXXXXXX.rs:4:1, - ), - }, - running_generator: Some( - ..., - ), - }, - ], - trace_decls: TraceModule { - name: "sim_fork_join", - children: [ - TraceModuleIO { - name: "clocks", - child: TraceArray { - name: "clocks", - elements: [ - TraceClock { - location: TraceScalarId(0), - name: "[0]", - flow: Source, - }, - TraceClock { - location: TraceScalarId(1), - name: "[1]", - flow: Source, - }, - TraceClock { - location: TraceScalarId(2), - name: "[2]", - flow: Source, - }, - ], - ty: Array, - flow: Source, - }, - ty: Array, - flow: Source, - }, - TraceModuleIO { - name: "outputs", - child: TraceArray { - name: "outputs", - elements: [ - TraceUInt { - location: TraceScalarId(3), - name: "[0]", - ty: UInt<8>, - flow: Sink, - }, - TraceUInt { - location: TraceScalarId(4), - name: "[1]", - ty: UInt<8>, - flow: Sink, - }, - TraceUInt { - location: TraceScalarId(5), - name: "[2]", - ty: UInt<8>, - flow: Sink, - }, - ], - ty: Array, 3>, - flow: Sink, - }, - ty: Array, 3>, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigClock { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigClock { - index: StatePartIndex(2), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigUInt { - index: StatePartIndex(3), - ty: UInt<8>, - }, - state: 0x31, - last_state: 0x31, - }, - SimTrace { - id: TraceScalarId(4), - kind: BigUInt { - index: StatePartIndex(4), - ty: UInt<8>, - }, - state: 0x32, - last_state: 0x32, - }, - SimTrace { - id: TraceScalarId(5), - kind: BigUInt { - index: StatePartIndex(5), - ty: UInt<8>, - }, - state: 0x32, - last_state: 0x32, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 648 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 198, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 198, - .. - }, - }, - ), - }, - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.vcd b/crates/fayalite/tests/sim/expected/sim_fork_join.vcd deleted file mode 100644 index a420c2b7..00000000 --- a/crates/fayalite/tests/sim/expected/sim_fork_join.vcd +++ /dev/null @@ -1,1467 +0,0 @@ -$timescale 1 ps $end -$scope module sim_fork_join $end -$scope struct clocks $end -$var wire 1 ! \[0] $end -$var wire 1 " \[1] $end -$var wire 1 # \[2] $end -$upscope $end -$scope struct outputs $end -$var wire 8 $ \[0] $end -$var wire 8 % \[1] $end -$var wire 8 & \[2] $end -$upscope $end -$upscope $end -$enddefinitions $end -$dumpvars -0! -0" -0# -b0 $ -b0 % -b0 & -$end -#1000000 -1! -b1 $ -#2000000 -0! -#3000000 -1! -#4000000 -0! -#5000000 -1! -#6000000 -0! -#7000000 -1! -#8000000 -0! -#9000000 -1! -#10000000 -0! -#11000000 -1! -#12000000 -0! -#13000000 -1! -#14000000 -0! -#15000000 -1" -b1 % -#16000000 -0" -#17000000 -1! -#18000000 -0! -#19000000 -1! -#20000000 -0! -#21000000 -1! -#22000000 -0! -#23000000 -1# -b1 & -#24000000 -0# -#25000000 -1! -b10 $ -#26000000 -0! -#27000000 -1! -#28000000 -0! -#29000000 -1" -b10 % -#30000000 -0" -#31000000 -1! -#32000000 -0! -#33000000 -1! -#34000000 -0! -#35000000 -1! -#36000000 -0! -#37000000 -1" -#38000000 -0" -#39000000 -1" -#40000000 -0" -#41000000 -1! -#42000000 -0! -#43000000 -1! -#44000000 -0! -#45000000 -1" -#46000000 -0" -#47000000 -1# -b10 & -#48000000 -0# -#49000000 -1! -b11 $ -#50000000 -0! -#51000000 -1! -#52000000 -0! -#53000000 -1# -b11 & -#54000000 -0# -#55000000 -1! -#56000000 -0! -#57000000 -1! -#58000000 -0! -#59000000 -1! -#60000000 -0! -#61000000 -1# -#62000000 -0# -#63000000 -1" -b11 % -#64000000 -0" -#65000000 -1! -b100 $ -#66000000 -0! -#67000000 -1! -#68000000 -0! -#69000000 -1# -b100 & -#70000000 -0# -#71000000 -1# -#72000000 -0# -#73000000 -1! -#74000000 -0! -#75000000 -1" -b100 % -#76000000 -0" -#77000000 -1! -b101 $ -#78000000 -0! -#79000000 -1! -#80000000 -0! -#81000000 -1! -#82000000 -0! -#83000000 -1" -b101 % -#84000000 -0" -#85000000 -1! -#86000000 -0! -#87000000 -1" -#88000000 -0" -#89000000 -1! -#90000000 -0! -#91000000 -1" -#92000000 -0" -#93000000 -1! -#94000000 -0! -#95000000 -1# -b101 & -#96000000 -0# -#97000000 -1! -b110 $ -#98000000 -0! -#99000000 -1" -b110 % -#100000000 -0" -#101000000 -1" -#102000000 -0" -#103000000 -1! -#104000000 -0! -#105000000 -1! -#106000000 -0! -#107000000 -1" -#108000000 -0" -#109000000 -1" -#110000000 -0" -#111000000 -1" -#112000000 -0" -#113000000 -1! -#114000000 -0! -#115000000 -1" -#116000000 -0" -#117000000 -1" -#118000000 -0" -#119000000 -1# -b110 & -#120000000 -0# -#121000000 -1! -b111 $ -#122000000 -0! -#123000000 -1" -b111 % -#124000000 -0" -#125000000 -1# -b111 & -#126000000 -0# -#127000000 -1! -b1000 $ -#128000000 -0! -#129000000 -1! -#130000000 -0! -#131000000 -1" -b1000 % -#132000000 -0" -#133000000 -1# -b1000 & -#134000000 -0# -#135000000 -1" -b1001 % -#136000000 -0" -#137000000 -1! -b1001 $ -#138000000 -0! -#139000000 -1" -#140000000 -0" -#141000000 -1# -b1001 & -#142000000 -0# -#143000000 -1# -b1010 & -#144000000 -0# -#145000000 -1! -b1010 $ -#146000000 -0! -#147000000 -1# -#148000000 -0# -#149000000 -1! -#150000000 -0! -#151000000 -1! -#152000000 -0! -#153000000 -1! -#154000000 -0! -#155000000 -1# -#156000000 -0# -#157000000 -1! -#158000000 -0! -#159000000 -1" -b1010 % -#160000000 -0" -#161000000 -1! -b1011 $ -#162000000 -0! -#163000000 -1# -b1011 & -#164000000 -0# -#165000000 -1! -#166000000 -0! -#167000000 -1# -#168000000 -0# -#169000000 -1! -#170000000 -0! -#171000000 -1# -#172000000 -0# -#173000000 -1" -b1011 % -#174000000 -0" -#175000000 -1! -b1100 $ -#176000000 -0! -#177000000 -1! -#178000000 -0! -#179000000 -1# -b1100 & -#180000000 -0# -#181000000 -1" -b1100 % -#182000000 -0" -#183000000 -1" -b1101 % -#184000000 -0" -#185000000 -1! -b1101 $ -#186000000 -0! -#187000000 -1# -b1101 & -#188000000 -0# -#189000000 -1" -b1110 % -#190000000 -0" -#191000000 -1# -b1110 & -#192000000 -0# -#193000000 -1! -b1110 $ -#194000000 -0! -#195000000 -1# -b1111 & -#196000000 -0# -#197000000 -1# -#198000000 -0# -#199000000 -1! -b1111 $ -#200000000 -0! -#201000000 -1! -#202000000 -0! -#203000000 -1# -#204000000 -0# -#205000000 -1# -#206000000 -0# -#207000000 -1" -b1111 % -#208000000 -0" -#209000000 -1! -b10000 $ -#210000000 -0! -#211000000 -1# -b10000 & -#212000000 -0# -#213000000 -1# -#214000000 -0# -#215000000 -1# -#216000000 -0# -#217000000 -1" -b10000 % -#218000000 -0" -#219000000 -1! -b10001 $ -#220000000 -0! -#221000000 -1! -#222000000 -0! -#223000000 -1! -#224000000 -0! -#225000000 -1" -b10001 % -#226000000 -0" -#227000000 -1! -#228000000 -0! -#229000000 -1! -#230000000 -0! -#231000000 -1" -#232000000 -0" -#233000000 -1" -#234000000 -0" -#235000000 -1! -#236000000 -0! -#237000000 -1! -#238000000 -0! -#239000000 -1# -b10001 & -#240000000 -0# -#241000000 -1" -b10010 % -#242000000 -0" -#243000000 -1! -b10010 $ -#244000000 -0! -#245000000 -1" -#246000000 -0" -#247000000 -1! -#248000000 -0! -#249000000 -1" -#250000000 -0" -#251000000 -1! -#252000000 -0! -#253000000 -1" -#254000000 -0" -#255000000 -1" -#256000000 -0" -#257000000 -1" -#258000000 -0" -#259000000 -1! -#260000000 -0! -#261000000 -1" -#262000000 -0" -#263000000 -1# -b10010 & -#264000000 -0# -#265000000 -1" -b10011 % -#266000000 -0" -#267000000 -1! -b10011 $ -#268000000 -0! -#269000000 -1# -b10011 & -#270000000 -0# -#271000000 -1! -b10100 $ -#272000000 -0! -#273000000 -1" -b10100 % -#274000000 -0" -#275000000 -1! -#276000000 -0! -#277000000 -1# -b10100 & -#278000000 -0# -#279000000 -1" -b10101 % -#280000000 -0" -#281000000 -1" -#282000000 -0" -#283000000 -1! -b10101 $ -#284000000 -0! -#285000000 -1# -b10101 & -#286000000 -0# -#287000000 -1# -b10110 & -#288000000 -0# -#289000000 -1" -b10110 % -#290000000 -0" -#291000000 -1" -#292000000 -0" -#293000000 -1! -b10110 $ -#294000000 -0! -#295000000 -1! -b10111 $ -#296000000 -0! -#297000000 -1" -b10111 % -#298000000 -0" -#299000000 -1" -#300000000 -0" -#301000000 -1! -#302000000 -0! -#303000000 -1" -#304000000 -0" -#305000000 -1" -#306000000 -0" -#307000000 -1" -#308000000 -0" -#309000000 -1! -#310000000 -0! -#311000000 -1# -b10111 & -#312000000 -0# -#313000000 -1" -b11000 % -#314000000 -0" -#315000000 -1" -#316000000 -0" -#317000000 -1" -#318000000 -0" -#319000000 -1! -b11000 $ -#320000000 -0! -#321000000 -1" -#322000000 -0" -#323000000 -1" -#324000000 -0" -#325000000 -1" -#326000000 -0" -#327000000 -1" -#328000000 -0" -#329000000 -1" -#330000000 -0" -#331000000 -1" -#332000000 -0" -#333000000 -1" -#334000000 -0" -#335000000 -1# -b11000 & -#336000000 -0# -#337000000 -1" -b11001 % -#338000000 -0" -#339000000 -1" -#340000000 -0" -#341000000 -1# -b11001 & -#342000000 -0# -#343000000 -1! -b11001 $ -#344000000 -0! -#345000000 -1" -b11010 % -#346000000 -0" -#347000000 -1" -#348000000 -0" -#349000000 -1# -b11010 & -#350000000 -0# -#351000000 -1" -#352000000 -0" -#353000000 -1" -#354000000 -0" -#355000000 -1" -#356000000 -0" -#357000000 -1# -#358000000 -0# -#359000000 -1# -#360000000 -0# -#361000000 -1" -#362000000 -0" -#363000000 -1# -#364000000 -0# -#365000000 -1! -b11010 $ -#366000000 -0! -#367000000 -1! -b11011 $ -#368000000 -0! -#369000000 -1" -b11011 % -#370000000 -0" -#371000000 -1# -b11011 & -#372000000 -0# -#373000000 -1! -b11100 $ -#374000000 -0! -#375000000 -1" -b11100 % -#376000000 -0" -#377000000 -1" -#378000000 -0" -#379000000 -1# -b11100 & -#380000000 -0# -#381000000 -1! -b11101 $ -#382000000 -0! -#383000000 -1# -b11101 & -#384000000 -0# -#385000000 -1" -b11101 % -#386000000 -0" -#387000000 -1# -b11110 & -#388000000 -0# -#389000000 -1" -b11110 % -#390000000 -0" -#391000000 -1! -b11110 $ -#392000000 -0! -#393000000 -1" -b11111 % -#394000000 -0" -#395000000 -1# -b11111 & -#396000000 -0# -#397000000 -1" -#398000000 -0" -#399000000 -1" -#400000000 -0" -#401000000 -1" -#402000000 -0" -#403000000 -1# -#404000000 -0# -#405000000 -1" -#406000000 -0" -#407000000 -1# -#408000000 -0# -#409000000 -1" -#410000000 -0" -#411000000 -1# -#412000000 -0# -#413000000 -1# -#414000000 -0# -#415000000 -1! -b11111 $ -#416000000 -0! -#417000000 -1" -b100000 % -#418000000 -0" -#419000000 -1# -b100000 & -#420000000 -0# -#421000000 -1# -#422000000 -0# -#423000000 -1" -#424000000 -0" -#425000000 -1" -#426000000 -0" -#427000000 -1# -#428000000 -0# -#429000000 -1# -#430000000 -0# -#431000000 -1# -#432000000 -0# -#433000000 -1# -#434000000 -0# -#435000000 -1! -b100000 $ -#436000000 -0! -#437000000 -1! -b100001 $ -#438000000 -0! -#439000000 -1! -#440000000 -0! -#441000000 -1# -b100001 & -#442000000 -0# -#443000000 -1! -#444000000 -0! -#445000000 -1! -#446000000 -0! -#447000000 -1" -b100001 % -#448000000 -0" -#449000000 -1# -b100010 & -#450000000 -0# -#451000000 -1! -b100010 $ -#452000000 -0! -#453000000 -1! -#454000000 -0! -#455000000 -1# -#456000000 -0# -#457000000 -1# -#458000000 -0# -#459000000 -1! -#460000000 -0! -#461000000 -1" -b100010 % -#462000000 -0" -#463000000 -1! -b100011 $ -#464000000 -0! -#465000000 -1# -b100011 & -#466000000 -0# -#467000000 -1! -#468000000 -0! -#469000000 -1" -b100011 % -#470000000 -0" -#471000000 -1" -b100100 % -#472000000 -0" -#473000000 -1# -b100100 & -#474000000 -0# -#475000000 -1! -b100100 $ -#476000000 -0! -#477000000 -1" -b100101 % -#478000000 -0" -#479000000 -1# -b100101 & -#480000000 -0# -#481000000 -1# -#482000000 -0# -#483000000 -1! -b100101 $ -#484000000 -0! -#485000000 -1# -b100110 & -#486000000 -0# -#487000000 -1! -b100110 $ -#488000000 -0! -#489000000 -1# -#490000000 -0# -#491000000 -1! -#492000000 -0! -#493000000 -1# -#494000000 -0# -#495000000 -1" -b100110 % -#496000000 -0" -#497000000 -1# -b100111 & -#498000000 -0# -#499000000 -1! -b100111 $ -#500000000 -0! -#501000000 -1# -#502000000 -0# -#503000000 -1# -#504000000 -0# -#505000000 -1# -#506000000 -0# -#507000000 -1" -b100111 % -#508000000 -0" -#509000000 -1! -b101000 $ -#510000000 -0! -#511000000 -1! -#512000000 -0! -#513000000 -1# -b101000 & -#514000000 -0# -#515000000 -1" -b101000 % -#516000000 -0" -#517000000 -1! -b101001 $ -#518000000 -0! -#519000000 -1" -b101001 % -#520000000 -0" -#521000000 -1# -b101001 & -#522000000 -0# -#523000000 -1" -b101010 % -#524000000 -0" -#525000000 -1! -b101010 $ -#526000000 -0! -#527000000 -1# -b101010 & -#528000000 -0# -#529000000 -1# -b101011 & -#530000000 -0# -#531000000 -1" -b101011 % -#532000000 -0" -#533000000 -1" -#534000000 -0" -#535000000 -1! -b101011 $ -#536000000 -0! -#537000000 -1# -b101100 & -#538000000 -0# -#539000000 -1" -b101100 % -#540000000 -0" -#541000000 -1" -#542000000 -0" -#543000000 -1" -#544000000 -0" -#545000000 -1# -#546000000 -0# -#547000000 -1" -#548000000 -0" -#549000000 -1" -#550000000 -0" -#551000000 -1# -#552000000 -0# -#553000000 -1# -#554000000 -0# -#555000000 -1" -#556000000 -0" -#557000000 -1# -#558000000 -0# -#559000000 -1! -b101100 $ -#560000000 -0! -#561000000 -1# -b101101 & -#562000000 -0# -#563000000 -1" -b101101 % -#564000000 -0" -#565000000 -1# -#566000000 -0# -#567000000 -1" -#568000000 -0" -#569000000 -1# -#570000000 -0# -#571000000 -1" -#572000000 -0" -#573000000 -1# -#574000000 -0# -#575000000 -1# -#576000000 -0# -#577000000 -1# -#578000000 -0# -#579000000 -1# -#580000000 -0# -#581000000 -1! -b101101 $ -#582000000 -0! -#583000000 -1! -b101110 $ -#584000000 -0! -#585000000 -1# -b101110 & -#586000000 -0# -#587000000 -1# -#588000000 -0# -#589000000 -1! -#590000000 -0! -#591000000 -1" -b101110 % -#592000000 -0" -#593000000 -1# -b101111 & -#594000000 -0# -#595000000 -1# -#596000000 -0# -#597000000 -1! -b101111 $ -#598000000 -0! -#599000000 -1# -#600000000 -0# -#601000000 -1# -#602000000 -0# -#603000000 -1# -#604000000 -0# -#605000000 -1" -b101111 % -#606000000 -0" -#607000000 -1! -b110000 $ -#608000000 -0! -#609000000 -1# -b110000 & -#610000000 -0# -#611000000 -1# -#612000000 -0# -#613000000 -1" -b110000 % -#614000000 -0" -#615000000 -1" -b110001 % -#616000000 -0" -#617000000 -1# -b110001 & -#618000000 -0# -#619000000 -1# -#620000000 -0# -#621000000 -1" -#622000000 -0" -#623000000 -1# -#624000000 -0# -#625000000 -1# -#626000000 -0# -#627000000 -1# -#628000000 -0# -#629000000 -1# -#630000000 -0# -#631000000 -1! -b110001 $ -#632000000 -0! -#633000000 -1# -b110010 & -#634000000 -0# -#635000000 -1# -#636000000 -0# -#637000000 -1# -#638000000 -0# -#639000000 -1" -b110010 % -#640000000 -0" -#641000000 -1# -#642000000 -0# -#643000000 -1# -#644000000 -0# -#645000000 -1# -#646000000 -0# -#647000000 -1# -#648000000 -0# diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.txt b/crates/fayalite/tests/sim/expected/sim_only_connects.txt index 3c1605d1..114b3138 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.txt +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.txt @@ -717,6 +717,52 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 6, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + }, + }, }, SimulationExternModuleState { module_state: SimulationModuleState { @@ -876,8 +922,55 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 4, len: 0 }, + big_slots: StatePartIndexRange { start: 12, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 13, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + }, + }, }, ], + state_ready_to_run: false, trace_decls: TraceModule { name: "sim_only_connects", children: [ @@ -1535,214 +1628,9 @@ Simulation { }, ), ], + instant: 16 μs, clocks_triggered: [ StatePartIndex(1), ], - event_queue: EventQueue(EventQueueData { - instant: 16 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 30, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 6, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - SensitivitySet { - id: 31, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 4, len: 0 }, - big_slots: StatePartIndexRange { start: 12, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 13, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 6, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 30, - .. - }, - }, - ), - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 4, len: 0 }, - big_slots: StatePartIndexRange { start: 12, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 13, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 31, - .. - }, - }, - ), - }, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.vcd b/crates/fayalite/tests/sim/expected/sim_only_connects.vcd index 1e4c2497..2f464c0e 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.vcd +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.vcd @@ -72,22 +72,22 @@ s{} 8 $end #1000000 1! -s{\"extra\":\x20\"value\"} $ 1' -s{\"extra\":\x20\"value\"} ) 1+ -s{\"extra\":\x20\"value\"} - 10 11 15 -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} % +s{\"extra\":\x20\"value\"} $ +s{\"extra\":\x20\"value\"} ) +s{\"extra\":\x20\"value\"} - s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} * +s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 4 +s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} % +s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} & s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} . s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 3 s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 7 -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} & -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4 -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8 +s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 8 #2000000 0! 0" @@ -107,6 +107,9 @@ s{\"extra\":\x20\"value\"} / 00 11 15 +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4 +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} & +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8 #4000000 0! 0'