diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs
index 995510e..843eb6c 100644
--- a/crates/fayalite/src/bundle.rs
+++ b/crates/fayalite/src/bundle.rs
@@ -4,14 +4,12 @@
 use crate::{
     expr::{ops::BundleLiteral, Expr, ToExpr},
     intern::{Intern, Interned},
-    sim::{SimValue, ToSimValue},
     source_location::SourceLocation,
     ty::{
         impl_match_variant_as_self, CanonicalType, MatchVariantWithoutScope, StaticType, Type,
         TypeProperties, TypeWithDeref,
     },
 };
-use bitvec::vec::BitVec;
 use hashbrown::HashMap;
 use std::{fmt, marker::PhantomData};
 
@@ -325,7 +323,7 @@ macro_rules! impl_tuple_builder_fields {
 }
 
 macro_rules! impl_tuples {
-    ([$({#[num = $num:literal, field = $field:ident, ty = $ty_var:ident: $Ty:ident] $var:ident: $T:ident})*] []) => {
+    ([$({#[num = $num:literal, field = $field:ident] $var:ident: $T:ident})*] []) => {
         impl_tuple_builder_fields! {
             {}
             [$({
@@ -425,79 +423,6 @@ macro_rules! impl_tuples {
                 BundleLiteral::new(ty, field_values[..].intern()).to_expr()
             }
         }
-        impl<$($T: ToSimValue<CanonicalType>,)*> ToSimValue<CanonicalType> for ($($T,)*) {
-            #[track_caller]
-            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                ToSimValue::<Bundle>::to_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
-            }
-            #[track_caller]
-            fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType>
-            {
-                ToSimValue::<Bundle>::into_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
-            }
-            #[track_caller]
-            fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
-                ToSimValue::<Bundle>::box_into_sim_value(self, Bundle::from_canonical(ty)).into_canonical()
-            }
-        }
-        impl<$($T: ToSimValue<CanonicalType>,)*> ToSimValue<Bundle> for ($($T,)*) {
-            #[track_caller]
-            fn to_sim_value(&self, ty: Bundle) -> SimValue<Bundle> {
-                let ($($var,)*) = self;
-                let [$($ty_var,)*] = *ty.fields() else {
-                    panic!("bundle has wrong number of fields");
-                };
-                $(let $var = $var.to_sim_value($ty_var.ty);)*
-                ToSimValue::into_sim_value(($($var,)*), ty)
-            }
-            #[track_caller]
-            fn into_sim_value(self, ty: Bundle) -> SimValue<Bundle> {
-                #![allow(unused_mut)]
-                #![allow(clippy::unused_unit)]
-                let ($($var,)*) = self;
-                let [$($ty_var,)*] = *ty.fields() else {
-                    panic!("bundle has wrong number of fields");
-                };
-                let mut bits: Option<BitVec> = None;
-                $(let $var = $var.into_sim_value($ty_var.ty);
-                assert_eq!($var.ty(), $ty_var.ty);
-                if !$var.bits().is_empty() {
-                    if let Some(bits) = &mut bits {
-                        bits.extend_from_bitslice($var.bits());
-                    } else {
-                        let mut $var = $var.into_bits();
-                        $var.reserve(ty.type_properties().bit_width - $var.len());
-                        bits = Some($var);
-                    }
-                }
-                )*
-                bits.unwrap_or_else(BitVec::new).into_sim_value(ty)
-            }
-            #[track_caller]
-            fn box_into_sim_value(self: Box<Self>, ty: Bundle) -> SimValue<Bundle> {
-                Self::into_sim_value(*self, ty)
-            }
-        }
-        impl<$($T: ToSimValue<$Ty>, $Ty: Type,)*> ToSimValue<($($Ty,)*)> for ($($T,)*) {
-            #[track_caller]
-            fn to_sim_value(&self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
-                let ($($var,)*) = self;
-                let ($($ty_var,)*) = ty;
-                $(let $var = $var.to_sim_value($ty_var).into_canonical();)*
-                SimValue::from_canonical(ToSimValue::into_sim_value(($($var,)*), ty.canonical()))
-            }
-            #[track_caller]
-            fn into_sim_value(self, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
-                let ($($var,)*) = self;
-                let ($($ty_var,)*) = ty;
-                $(let $var = $var.into_sim_value($ty_var).into_canonical();)*
-                SimValue::from_canonical(ToSimValue::into_sim_value(($($var,)*), ty.canonical()))
-            }
-            #[track_caller]
-            fn box_into_sim_value(self: Box<Self>, ty: ($($Ty,)*)) -> SimValue<($($Ty,)*)> {
-                Self::into_sim_value(*self, ty)
-            }
-        }
     };
     ([$($lhs:tt)*] [$rhs_first:tt $($rhs:tt)*]) => {
         impl_tuples!([$($lhs)*] []);
@@ -507,18 +432,18 @@ macro_rules! impl_tuples {
 
 impl_tuples! {
     [] [
-        {#[num = 0, field = field_0, ty = ty0: Ty0] v0: T0}
-        {#[num = 1, field = field_1, ty = ty1: Ty1] v1: T1}
-        {#[num = 2, field = field_2, ty = ty2: Ty2] v2: T2}
-        {#[num = 3, field = field_3, ty = ty3: Ty3] v3: T3}
-        {#[num = 4, field = field_4, ty = ty4: Ty4] v4: T4}
-        {#[num = 5, field = field_5, ty = ty5: Ty5] v5: T5}
-        {#[num = 6, field = field_6, ty = ty6: Ty6] v6: T6}
-        {#[num = 7, field = field_7, ty = ty7: Ty7] v7: T7}
-        {#[num = 8, field = field_8, ty = ty8: Ty8] v8: T8}
-        {#[num = 9, field = field_9, ty = ty9: Ty9] v9: T9}
-        {#[num = 10, field = field_10, ty = ty10: Ty10] v10: T10}
-        {#[num = 11, field = field_11, ty = ty11: Ty11] v11: T11}
+        {#[num = 0, field = field_0] v0: T0}
+        {#[num = 1, field = field_1] v1: T1}
+        {#[num = 2, field = field_2] v2: T2}
+        {#[num = 3, field = field_3] v3: T3}
+        {#[num = 4, field = field_4] v4: T4}
+        {#[num = 5, field = field_5] v5: T5}
+        {#[num = 6, field = field_6] v6: T6}
+        {#[num = 7, field = field_7] v7: T7}
+        {#[num = 8, field = field_8] v8: T8}
+        {#[num = 9, field = field_9] v9: T9}
+        {#[num = 10, field = field_10] v10: T10}
+        {#[num = 11, field = field_11] v11: T11}
     ]
 }
 
@@ -603,27 +528,3 @@ impl<T: ?Sized + Send + Sync + 'static> ToExpr for PhantomData<T> {
         BundleLiteral::new(PhantomData, Interned::default()).to_expr()
     }
 }
-
-impl<T: ?Sized + Send + Sync + 'static> ToSimValue<Self> for PhantomData<T> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: Self) -> SimValue<Self> {
-        ToSimValue::into_sim_value(BitVec::new(), ty)
-    }
-}
-
-impl<T: ?Sized> ToSimValue<Bundle> for PhantomData<T> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: Bundle) -> SimValue<Bundle> {
-        assert!(ty.fields().is_empty());
-        ToSimValue::into_sim_value(BitVec::new(), ty)
-    }
-}
-
-impl<T: ?Sized> ToSimValue<CanonicalType> for PhantomData<T> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        let ty = Bundle::from_canonical(ty);
-        assert!(ty.fields().is_empty());
-        ToSimValue::into_sim_value(BitVec::new(), ty).into_canonical()
-    }
-}
diff --git a/crates/fayalite/src/memory.rs b/crates/fayalite/src/memory.rs
index 2f0ec47..4992cd6 100644
--- a/crates/fayalite/src/memory.rs
+++ b/crates/fayalite/src/memory.rs
@@ -519,12 +519,7 @@ impl<Element: Type, Len: Size> fmt::Debug for Mem<Element, Len> {
         f.debug_struct("Mem")
             .field("name", scoped_name)
             .field("array_type", array_type)
-            .field(
-                "initial_value",
-                &initial_value.as_ref().map(|initial_value| {
-                    DebugMemoryData::from_bit_slice(*array_type, initial_value)
-                }),
-            )
+            .field("initial_value", initial_value)
             .field("read_latency", read_latency)
             .field("write_latency", write_latency)
             .field("read_under_write", read_under_write)
@@ -1084,61 +1079,3 @@ pub fn splat_mask<T: Type>(ty: T, value: Expr<Bool>) -> Expr<AsMask<T>> {
         )),
     }
 }
-
-pub trait DebugMemoryDataGetElement {
-    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice;
-}
-
-impl<'a, F: ?Sized + Fn(usize, Array) -> &'a BitSlice> DebugMemoryDataGetElement for &'a F {
-    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice {
-        self(element_index, array_type)
-    }
-}
-
-#[derive(Clone)]
-pub struct DebugMemoryData<GetElement: DebugMemoryDataGetElement> {
-    pub array_type: Array,
-    pub get_element: GetElement,
-}
-
-impl DebugMemoryDataGetElement for &'_ BitSlice {
-    fn get_element(&self, element_index: usize, array_type: Array) -> &BitSlice {
-        assert!(element_index < array_type.len());
-        let stride = array_type.element().bit_width();
-        let start = element_index
-            .checked_mul(stride)
-            .expect("memory is too big");
-        let end = start.checked_add(stride).expect("memory is too big");
-        &self[start..end]
-    }
-}
-
-impl<'a> DebugMemoryData<&'a BitSlice> {
-    pub fn from_bit_slice<T: Type, Depth: Size>(
-        array_type: ArrayType<T, Depth>,
-        bit_slice: &'a BitSlice,
-    ) -> Self {
-        let array_type = array_type.as_dyn_array();
-        assert_eq!(bit_slice.len(), array_type.type_properties().bit_width);
-        Self {
-            array_type,
-            get_element: bit_slice,
-        }
-    }
-}
-
-impl<GetElement: DebugMemoryDataGetElement> fmt::Debug for DebugMemoryData<GetElement> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        if self.array_type.len() == 0 {
-            return f.write_str("[]");
-        }
-        writeln!(f, "[\n    // len = {:#x}", self.array_type.len())?;
-        for element_index in 0..self.array_type.len() {
-            let element = crate::util::BitSliceWriteWithBase(
-                self.get_element.get_element(element_index, self.array_type),
-            );
-            writeln!(f, "    [{element_index:#x}]: {element:#x},")?;
-        }
-        f.write_str("]")
-    }
-}
diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs
index cb6228d..ab5b7b7 100644
--- a/crates/fayalite/src/sim.rs
+++ b/crates/fayalite/src/sim.rs
@@ -14,7 +14,7 @@ use crate::{
         },
         ExprEnum, Flow, ToLiteralBits,
     },
-    int::{BoolOrIntType, IntType, SIntValue, UIntValue},
+    int::BoolOrIntType,
     intern::{Intern, Interned, Memoize},
     memory::PortKind,
     module::{
@@ -26,13 +26,12 @@ use crate::{
     reset::{ResetType, ResetTypeDispatch},
     sim::{
         interpreter::{
-            BreakAction, BreakpointsSet, Insn, InsnField, InsnFieldKind, InsnFieldType,
-            InsnOrLabel, Insns, InsnsBuilding, InsnsBuildingDone, InsnsBuildingKind, Label,
-            MemoryData, RunResult, SlotDebugData, SmallUInt, State, StatePartArrayIndex,
-            StatePartArrayIndexed, StatePartIndex, StatePartIndexRange, StatePartKind,
-            StatePartKindBigSlots, StatePartKindMemories, StatePartKindSmallSlots, StatePartLayout,
-            StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes, TypeIndex,
-            TypeIndexRange, TypeLayout, TypeLen, TypeParts,
+            Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding,
+            InsnsBuildingDone, InsnsBuildingKind, Label, SlotDebugData, SmallUInt, State,
+            StatePartArrayIndex, StatePartArrayIndexed, StatePartIndex, StatePartIndexRange,
+            StatePartKind, StatePartKindBigSlots, StatePartKindMemories, StatePartKindSmallSlots,
+            StatePartLayout, StatePartLen, StatePartsValue, TypeArrayIndex, TypeArrayIndexes,
+            TypeIndex, TypeIndexRange, TypeLayout, TypeLen, TypeParts,
         },
         time::{SimDuration, SimInstant},
     },
@@ -42,7 +41,7 @@ use crate::{
 use bitvec::{bits, order::Lsb0, slice::BitSlice, vec::BitVec, view::BitView};
 use hashbrown::{HashMap, HashSet};
 use num_bigint::BigInt;
-use num_traits::{Signed, Zero};
+use num_traits::{Signed, ToPrimitive, Zero};
 use petgraph::{
     data::FromElements,
     visit::{
@@ -50,9 +49,7 @@ use petgraph::{
         IntoNodeIdentifiers, IntoNodeReferences, NodeRef, VisitMap, Visitable,
     },
 };
-use std::{
-    borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut, sync::Arc,
-};
+use std::{borrow::Cow, collections::BTreeSet, fmt, marker::PhantomData, mem, ops::IndexMut};
 
 mod interpreter;
 pub mod time;
@@ -1570,45 +1567,9 @@ struct MemoryPortWriteInsns<'a> {
 struct Memory {
     mem: Mem,
     memory: StatePartIndex<StatePartKindMemories>,
-    trace: TraceMem,
     ports: Vec<MemoryPort>,
 }
 
-#[derive(Copy, Clone)]
-enum MakeTraceDeclTarget {
-    Expr(Expr<CanonicalType>),
-    Memory {
-        id: TraceMemoryId,
-        depth: usize,
-        stride: usize,
-        start: usize,
-        ty: CanonicalType,
-    },
-}
-
-impl MakeTraceDeclTarget {
-    fn flow(self) -> Flow {
-        match self {
-            MakeTraceDeclTarget::Expr(expr) => Expr::flow(expr),
-            MakeTraceDeclTarget::Memory { .. } => Flow::Duplex,
-        }
-    }
-    fn ty(self) -> CanonicalType {
-        match self {
-            MakeTraceDeclTarget::Expr(expr) => Expr::ty(expr),
-            MakeTraceDeclTarget::Memory { ty, .. } => ty,
-        }
-    }
-}
-
-struct DebugOpaque<T>(T);
-
-impl<T> fmt::Debug for DebugOpaque<T> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        f.write_str("<...>")
-    }
-}
-
 #[derive(Debug)]
 pub struct Compiler {
     insns: Insns<InsnsBuilding>,
@@ -1628,9 +1589,8 @@ pub struct Compiler {
     compiled_value_to_clock_trigger_map: HashMap<CompiledValue<Clock>, ClockTrigger>,
     enum_discriminants: HashMap<CompiledValue<Enum>, StatePartIndex<StatePartKindSmallSlots>>,
     registers: Vec<Register>,
-    traces: SimTraces<Vec<SimTrace<SimTraceKind, ()>>>,
+    traces: Vec<SimTrace<()>>,
     memories: Vec<Memory>,
-    dump_assignments_dot: Option<DebugOpaque<Box<dyn Fn(&dyn fmt::Debug)>>>,
 }
 
 impl Compiler {
@@ -1654,19 +1614,14 @@ impl Compiler {
             compiled_value_to_clock_trigger_map: HashMap::new(),
             enum_discriminants: HashMap::new(),
             registers: Vec::new(),
-            traces: SimTraces(Vec::new()),
+            traces: Vec::new(),
             memories: Vec::new(),
-            dump_assignments_dot: None,
         }
     }
-    #[doc(hidden)]
-    /// This is explicitly unstable and may be changed/removed at any time
-    pub fn dump_assignments_dot(&mut self, callback: Box<dyn Fn(&dyn fmt::Debug)>) {
-        self.dump_assignments_dot = Some(DebugOpaque(callback));
-    }
     fn new_sim_trace(&mut self, kind: SimTraceKind) -> TraceScalarId {
-        let id = TraceScalarId(self.traces.0.len());
-        self.traces.0.push(SimTrace {
+        let id = TraceScalarId(self.traces.len());
+        self.traces.push(SimTrace {
+            id,
             kind,
             state: (),
             last_state: (),
@@ -1676,47 +1631,30 @@ impl Compiler {
     fn make_trace_scalar_helper(
         &mut self,
         instantiated_module: InstantiatedModule,
-        target: MakeTraceDeclTarget,
+        target: Expr<CanonicalType>,
         source_location: SourceLocation,
         small_kind: impl FnOnce(StatePartIndex<StatePartKindSmallSlots>) -> SimTraceKind,
         big_kind: impl FnOnce(StatePartIndex<StatePartKindBigSlots>) -> SimTraceKind,
-    ) -> TraceLocation {
-        match target {
-            MakeTraceDeclTarget::Expr(target) => {
-                let compiled_value = self.compile_expr(instantiated_module, target);
-                let compiled_value = self.compiled_expr_to_value(compiled_value, source_location);
-                TraceLocation::Scalar(self.new_sim_trace(match compiled_value.range.len() {
-                    TypeLen::A_SMALL_SLOT => small_kind(compiled_value.range.small_slots.start),
-                    TypeLen::A_BIG_SLOT => big_kind(compiled_value.range.big_slots.start),
-                    _ => unreachable!(),
-                }))
-            }
-            MakeTraceDeclTarget::Memory {
-                id,
-                depth,
-                stride,
-                start,
-                ty,
-            } => TraceLocation::Memory(TraceMemoryLocation {
-                id,
-                depth,
-                stride,
-                start,
-                len: ty.bit_width(),
-            }),
-        }
+    ) -> TraceScalarId {
+        let compiled_value = self.compile_expr(instantiated_module, target);
+        let compiled_value = self.compiled_expr_to_value(compiled_value, source_location);
+        self.new_sim_trace(match compiled_value.range.len() {
+            TypeLen::A_SMALL_SLOT => small_kind(compiled_value.range.small_slots.start),
+            TypeLen::A_BIG_SLOT => big_kind(compiled_value.range.big_slots.start),
+            _ => unreachable!(),
+        })
     }
     fn make_trace_scalar(
         &mut self,
         instantiated_module: InstantiatedModule,
-        target: MakeTraceDeclTarget,
+        target: Expr<CanonicalType>,
         name: Interned<str>,
         source_location: SourceLocation,
     ) -> TraceDecl {
-        let flow = target.flow();
-        match target.ty() {
+        let flow = Expr::flow(target);
+        match Expr::ty(target) {
             CanonicalType::UInt(ty) => TraceUInt {
-                location: self.make_trace_scalar_helper(
+                id: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1729,7 +1667,7 @@ impl Compiler {
             }
             .into(),
             CanonicalType::SInt(ty) => TraceSInt {
-                location: self.make_trace_scalar_helper(
+                id: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1742,7 +1680,7 @@ impl Compiler {
             }
             .into(),
             CanonicalType::Bool(_) => TraceBool {
-                location: self.make_trace_scalar_helper(
+                id: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1756,36 +1694,17 @@ impl Compiler {
             CanonicalType::Array(_) => unreachable!(),
             CanonicalType::Enum(ty) => {
                 assert_eq!(ty.discriminant_bit_width(), ty.type_properties().bit_width);
-                let location = match target {
-                    MakeTraceDeclTarget::Expr(target) => {
-                        let compiled_value = self.compile_expr(instantiated_module, target);
-                        let compiled_value =
-                            self.compiled_expr_to_value(compiled_value, source_location);
-                        let discriminant = self.compile_enum_discriminant(
-                            compiled_value.map_ty(Enum::from_canonical),
-                            source_location,
-                        );
-                        TraceLocation::Scalar(self.new_sim_trace(SimTraceKind::EnumDiscriminant {
-                            index: discriminant,
-                            ty,
-                        }))
-                    }
-                    MakeTraceDeclTarget::Memory {
-                        id,
-                        depth,
-                        stride,
-                        start,
-                        ty: _,
-                    } => TraceLocation::Memory(TraceMemoryLocation {
-                        id,
-                        depth,
-                        stride,
-                        start,
-                        len: ty.type_properties().bit_width,
-                    }),
-                };
+                let compiled_value = self.compile_expr(instantiated_module, target);
+                let compiled_value = self.compiled_expr_to_value(compiled_value, source_location);
+                let discriminant = self.compile_enum_discriminant(
+                    compiled_value.map_ty(Enum::from_canonical),
+                    source_location,
+                );
                 TraceFieldlessEnum {
-                    location,
+                    id: self.new_sim_trace(SimTraceKind::EnumDiscriminant {
+                        index: discriminant,
+                        ty,
+                    }),
                     name,
                     ty,
                     flow,
@@ -1794,7 +1713,7 @@ impl Compiler {
             }
             CanonicalType::Bundle(_) => unreachable!(),
             CanonicalType::AsyncReset(_) => TraceAsyncReset {
-                location: self.make_trace_scalar_helper(
+                id: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1806,7 +1725,7 @@ impl Compiler {
             }
             .into(),
             CanonicalType::SyncReset(_) => TraceSyncReset {
-                location: self.make_trace_scalar_helper(
+                id: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1819,7 +1738,7 @@ impl Compiler {
             .into(),
             CanonicalType::Reset(_) => unreachable!(),
             CanonicalType::Clock(_) => TraceClock {
-                location: self.make_trace_scalar_helper(
+                id: self.make_trace_scalar_helper(
                     instantiated_module,
                     target,
                     source_location,
@@ -1835,33 +1754,16 @@ impl Compiler {
     fn make_trace_decl_child(
         &mut self,
         instantiated_module: InstantiatedModule,
-        target: MakeTraceDeclTarget,
+        target: Expr<CanonicalType>,
         name: Interned<str>,
         source_location: SourceLocation,
     ) -> TraceDecl {
-        match target.ty() {
+        match Expr::ty(target) {
             CanonicalType::Array(ty) => {
                 let elements = Interned::from_iter((0..ty.len()).map(|index| {
                     self.make_trace_decl_child(
                         instantiated_module,
-                        match target {
-                            MakeTraceDeclTarget::Expr(target) => MakeTraceDeclTarget::Expr(
-                                Expr::<Array>::from_canonical(target)[index],
-                            ),
-                            MakeTraceDeclTarget::Memory {
-                                id,
-                                depth,
-                                stride,
-                                start,
-                                ty: _,
-                            } => MakeTraceDeclTarget::Memory {
-                                id,
-                                depth,
-                                stride,
-                                start: start + ty.element().bit_width() * index,
-                                ty: ty.element(),
-                            },
-                        },
+                        Expr::<Array>::from_canonical(target)[index],
                         Intern::intern_owned(format!("[{index}]")),
                         source_location,
                     )
@@ -1870,7 +1772,7 @@ impl Compiler {
                     name,
                     elements,
                     ty,
-                    flow: target.flow(),
+                    flow: Expr::flow(target),
                 }
                 .into()
             }
@@ -1878,73 +1780,32 @@ impl Compiler {
                 if ty.variants().iter().all(|v| v.ty.is_none()) {
                     self.make_trace_scalar(instantiated_module, target, name, source_location)
                 } else {
-                    let flow = target.flow();
-                    let location = match target {
-                        MakeTraceDeclTarget::Expr(target) => {
-                            let compiled_value = self.compile_expr(instantiated_module, target);
-                            let compiled_value =
-                                self.compiled_expr_to_value(compiled_value, source_location);
-                            let discriminant = self.compile_enum_discriminant(
-                                compiled_value.map_ty(Enum::from_canonical),
-                                source_location,
-                            );
-                            TraceLocation::Scalar(self.new_sim_trace(
-                                SimTraceKind::EnumDiscriminant {
-                                    index: discriminant,
-                                    ty,
-                                },
-                            ))
-                        }
-                        MakeTraceDeclTarget::Memory {
-                            id,
-                            depth,
-                            stride,
-                            start,
-                            ty: _,
-                        } => TraceLocation::Memory(TraceMemoryLocation {
-                            id,
-                            depth,
-                            stride,
-                            start,
-                            len: ty.discriminant_bit_width(),
-                        }),
-                    };
+                    let flow = Expr::flow(target);
+                    let compiled_value = self.compile_expr(instantiated_module, target);
+                    let compiled_value =
+                        self.compiled_expr_to_value(compiled_value, source_location);
+                    let discriminant = self.compile_enum_discriminant(
+                        compiled_value.map_ty(Enum::from_canonical),
+                        source_location,
+                    );
                     let discriminant = TraceEnumDiscriminant {
-                        location,
+                        id: self.new_sim_trace(SimTraceKind::EnumDiscriminant {
+                            index: discriminant,
+                            ty,
+                        }),
                         name: "$tag".intern(),
                         ty,
                         flow,
                     };
+                    let base = Expr::<Enum>::from_canonical(target);
                     let non_empty_fields =
                         Interned::from_iter(ty.variants().into_iter().enumerate().flat_map(
                             |(variant_index, variant)| {
-                                variant.ty.map(|variant_ty| {
+                                variant.ty.map(|_| {
                                     self.make_trace_decl_child(
                                         instantiated_module,
-                                        match target {
-                                            MakeTraceDeclTarget::Expr(target) => {
-                                                MakeTraceDeclTarget::Expr(
-                                                    ops::VariantAccess::new_by_index(
-                                                        Expr::<Enum>::from_canonical(target),
-                                                        variant_index,
-                                                    )
-                                                    .to_expr(),
-                                                )
-                                            }
-                                            MakeTraceDeclTarget::Memory {
-                                                id,
-                                                depth,
-                                                stride,
-                                                start,
-                                                ty: _,
-                                            } => MakeTraceDeclTarget::Memory {
-                                                id,
-                                                depth,
-                                                stride,
-                                                start: start + ty.discriminant_bit_width(),
-                                                ty: variant_ty,
-                                            },
-                                        },
+                                        ops::VariantAccess::new_by_index(base, variant_index)
+                                            .to_expr(),
                                         variant.name,
                                         source_location,
                                     )
@@ -1962,41 +1823,19 @@ impl Compiler {
                 }
             }
             CanonicalType::Bundle(ty) => {
-                let fields = Interned::from_iter(ty.fields().iter().zip(ty.field_offsets()).map(
-                    |(field, field_offset)| {
-                        self.make_trace_decl_child(
-                            instantiated_module,
-                            match target {
-                                MakeTraceDeclTarget::Expr(target) => {
-                                    MakeTraceDeclTarget::Expr(Expr::field(
-                                        Expr::<Bundle>::from_canonical(target),
-                                        &field.name,
-                                    ))
-                                }
-                                MakeTraceDeclTarget::Memory {
-                                    id,
-                                    depth,
-                                    stride,
-                                    start,
-                                    ty: _,
-                                } => MakeTraceDeclTarget::Memory {
-                                    id,
-                                    depth,
-                                    stride,
-                                    start: start + field_offset,
-                                    ty: field.ty,
-                                },
-                            },
-                            field.name,
-                            source_location,
-                        )
-                    },
-                ));
+                let fields = Interned::from_iter(ty.fields().iter().map(|field| {
+                    self.make_trace_decl_child(
+                        instantiated_module,
+                        Expr::field(Expr::<Bundle>::from_canonical(target), &field.name),
+                        field.name,
+                        source_location,
+                    )
+                }));
                 TraceBundle {
                     name,
                     fields,
                     ty,
-                    flow: target.flow(),
+                    flow: Expr::flow(target),
                 }
                 .into()
             }
@@ -2016,7 +1855,7 @@ impl Compiler {
         instantiated_module: InstantiatedModule,
         target_base: TargetBase,
     ) -> TraceDecl {
-        let target = MakeTraceDeclTarget::Expr(target_base.to_expr());
+        let target = target_base.to_expr();
         match target_base {
             TargetBase::ModuleIO(module_io) => TraceModuleIO {
                 name: module_io.name(),
@@ -3971,10 +3810,10 @@ impl Compiler {
                     insns.push(
                         match data.len() {
                             TypeLen::A_BIG_SLOT => {
-                                let value = data.big_slots.start;
+                                let dest = data.big_slots.start;
                                 if signed {
-                                    Insn::MemoryWriteSInt {
-                                        value,
+                                    Insn::MemoryReadSInt {
+                                        dest,
                                         memory,
                                         addr,
                                         stride,
@@ -3982,8 +3821,8 @@ impl Compiler {
                                         width,
                                     }
                                 } else {
-                                    Insn::MemoryWriteUInt {
-                                        value,
+                                    Insn::MemoryReadUInt {
+                                        dest,
                                         memory,
                                         addr,
                                         stride,
@@ -3993,7 +3832,7 @@ impl Compiler {
                                 }
                             }
                             TypeLen::A_SMALL_SLOT => {
-                                let _value = data.small_slots.start;
+                                let _dest = data.small_slots.start;
                                 todo!("memory ports' data are always big for now");
                             }
                             _ => unreachable!(),
@@ -4292,18 +4131,15 @@ impl Compiler {
             .memories
             .allocate(&StatePartLayout::scalar(
                 (),
-                MemoryData {
-                    array_type: mem.array_type(),
-                    data: mem.initial_value().unwrap_or_else(|| {
-                        Intern::intern_owned(BitVec::repeat(
-                            false,
-                            mem.array_type().type_properties().bit_width,
-                        ))
-                    }),
-                },
+                mem.initial_value().unwrap_or_else(|| {
+                    Intern::intern_owned(BitVec::repeat(
+                        false,
+                        mem.array_type().type_properties().bit_width,
+                    ))
+                }),
             ))
             .start;
-        let (ports, trace_ports) = mem
+        let ports = mem
             .ports()
             .iter()
             .map(|&port| {
@@ -4313,11 +4149,7 @@ impl Compiler {
                     target: target_base.into(),
                 };
                 self.decl_conditions.insert(target, conditions);
-                let TraceDecl::Scope(TraceScope::MemPort(trace_port)) =
-                    self.make_trace_decl(instantiated_module, target_base)
-                else {
-                    unreachable!();
-                };
+                trace_decls.push(self.make_trace_decl(instantiated_module, target_base));
                 let clk = Expr::field(port.to_expr(), "clk");
                 let clk = self.compile_expr(instantiated_module, clk);
                 let clk = self.compiled_expr_to_value(clk, mem.source_location());
@@ -4486,53 +4318,20 @@ impl Compiler {
                     }),
                 );
                 self.add_assignment(Interned::default(), read_insns, mem.source_location());
-                (
-                    MemoryPort {
-                        clk_triggered,
-                        addr_delayed,
-                        en_delayed,
-                        data_layout,
-                        read_data_delayed,
-                        write_data_delayed,
-                        write_mask_delayed,
-                        write_mode_delayed,
-                        write_insns,
-                    },
-                    trace_port,
-                )
+                MemoryPort {
+                    clk_triggered,
+                    addr_delayed,
+                    en_delayed,
+                    data_layout,
+                    read_data_delayed,
+                    write_data_delayed,
+                    write_mask_delayed,
+                    write_mode_delayed,
+                    write_insns,
+                }
             })
-            .unzip();
-        let name = mem.scoped_name().1 .0;
-        let id = TraceMemoryId(self.memories.len());
-        let stride = mem.array_type().element().bit_width();
-        let trace = TraceMem {
-            id,
-            name,
-            stride,
-            element_type: self
-                .make_trace_decl_child(
-                    instantiated_module,
-                    MakeTraceDeclTarget::Memory {
-                        id,
-                        depth: mem.array_type().len(),
-                        stride,
-                        start: 0,
-                        ty: mem.array_type().element(),
-                    },
-                    name,
-                    mem.source_location(),
-                )
-                .intern_sized(),
-            ports: Intern::intern_owned(trace_ports),
-            array_type: mem.array_type(),
-        };
-        trace_decls.push(trace.into());
-        self.memories.push(Memory {
-            mem,
-            memory,
-            trace,
-            ports,
-        });
+            .collect();
+        self.memories.push(Memory { mem, memory, ports });
     }
     fn compile_block(
         &mut self,
@@ -4665,11 +4464,12 @@ impl Compiler {
     fn process_assignments(&mut self) {
         self.assignments
             .finalize(self.insns.state_layout().ty.clone().into());
-        if let Some(DebugOpaque(dump_assignments_dot)) = &self.dump_assignments_dot {
-            let graph =
-                petgraph::graph::DiGraph::<_, _, usize>::from_elements(self.assignments.elements());
-            dump_assignments_dot(&petgraph::dot::Dot::new(&graph));
-        }
+        println!(
+            "{:#?}",
+            petgraph::dot::Dot::new(&petgraph::graph::DiGraph::<_, _, usize>::from_elements(
+                self.assignments.elements()
+            ))
+        );
         let assignments_order: Vec<_> = match petgraph::algo::toposort(&self.assignments, None) {
             Ok(nodes) => nodes
                 .into_iter()
@@ -4785,10 +4585,9 @@ impl Compiler {
                      source_location,
                  }| {
                     self.insns.push(
-                        Insn::XorSmallImmediate {
+                        Insn::NotSmall {
                             dest: last_clk_was_low,
-                            lhs: clk,
-                            rhs: 1,
+                            src: clk,
                         },
                         source_location,
                     );
@@ -4858,13 +4657,12 @@ impl Compiler {
         }
     }
     fn process_memories(&mut self) {
-        for memory_index in 0..self.memories.len() {
-            let Memory {
-                mem,
-                memory: _,
-                trace: _,
-                ref mut ports,
-            } = self.memories[memory_index];
+        for Memory {
+            mem,
+            memory: _,
+            ports,
+        } in mem::take(&mut self.memories)
+        {
             for MemoryPort {
                 clk_triggered,
                 addr_delayed,
@@ -4875,9 +4673,17 @@ impl Compiler {
                 write_mask_delayed,
                 write_mode_delayed,
                 write_insns,
-            } in mem::take(ports)
+            } in ports
             {
                 let port_end = self.insns.new_label();
+                self.insns.push(
+                    Insn::BranchIfSmallZero {
+                        target: port_end.0,
+                        value: clk_triggered,
+                    },
+                    mem.source_location(),
+                );
+                self.insns.extend(write_insns, mem.source_location());
                 let small_shift_reg =
                     |this: &mut Self, values: &[StatePartIndex<StatePartKindSmallSlots>]| {
                         for pair in values.windows(2).rev() {
@@ -4896,20 +4702,12 @@ impl Compiler {
                             .extend(pair[0].insns_for_copy_to(pair[1]), mem.source_location());
                     }
                 };
-                self.insns.push(
-                    Insn::BranchIfSmallZero {
-                        target: port_end.0,
-                        value: clk_triggered,
-                    },
-                    mem.source_location(),
-                );
                 small_shift_reg(self, &addr_delayed);
                 small_shift_reg(self, &en_delayed);
+                shift_reg(self, &read_data_delayed);
                 shift_reg(self, &write_data_delayed);
                 shift_reg(self, &write_mask_delayed);
                 small_shift_reg(self, &write_mode_delayed);
-                shift_reg(self, &read_data_delayed);
-                self.insns.extend(write_insns, mem.source_location());
                 self.insns.define_label_at_next_insn(port_end);
             }
         }
@@ -4934,15 +4732,7 @@ impl Compiler {
                 self.original_base_module,
                 self.original_base_module.source_location(),
             ),
-            traces: SimTraces(Intern::intern_owned(self.traces.0)),
-            trace_memories: Interned::from_iter(self.memories.iter().map(
-                |&Memory {
-                     mem: _,
-                     memory,
-                     trace,
-                     ports: _,
-                 }| (memory, trace),
-            )),
+            traces: Intern::intern_owned(self.traces),
             clocks_triggered,
         }
     }
@@ -4959,8 +4749,7 @@ pub struct Compiled<T: BundleType> {
     insns: Interned<Insns<InsnsBuildingDone>>,
     base_module: CompiledModule,
     io: Instance<T>,
-    traces: SimTraces<Interned<[SimTrace<SimTraceKind, ()>]>>,
-    trace_memories: Interned<[(StatePartIndex<StatePartKindMemories>, TraceMem)]>,
+    traces: Interned<[SimTrace<()>]>,
     clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
 }
 
@@ -4974,7 +4763,6 @@ impl<T: BundleType> Compiled<T> {
             base_module,
             io,
             traces,
-            trace_memories,
             clocks_triggered,
         } = self;
         Compiled {
@@ -4982,7 +4770,6 @@ impl<T: BundleType> Compiled<T> {
             base_module,
             io: Instance::from_canonical(io.canonical()),
             traces,
-            trace_memories,
             clocks_triggered,
         }
     }
@@ -4992,7 +4779,6 @@ impl<T: BundleType> Compiled<T> {
             base_module,
             io,
             traces,
-            trace_memories,
             clocks_triggered,
         } = canonical;
         Self {
@@ -5000,7 +4786,6 @@ impl<T: BundleType> Compiled<T> {
             base_module,
             io: Instance::from_canonical(io.canonical()),
             traces,
-            trace_memories,
             clocks_triggered,
         }
     }
@@ -5021,45 +4806,6 @@ impl TraceScalarId {
     }
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
-pub struct TraceMemoryId(usize);
-
-impl fmt::Debug for TraceMemoryId {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        write!(f, "TraceMemoryId({})", self.0)
-    }
-}
-
-impl TraceMemoryId {
-    pub fn as_usize(self) -> usize {
-        self.0
-    }
-}
-
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
-pub struct TraceMemoryLocation {
-    pub id: TraceMemoryId,
-    pub depth: usize,
-    pub stride: usize,
-    pub start: usize,
-    pub len: usize,
-}
-
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
-pub enum TraceLocation {
-    Scalar(TraceScalarId),
-    Memory(TraceMemoryLocation),
-}
-
-impl fmt::Debug for TraceLocation {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        match self {
-            Self::Scalar(v) => v.fmt(f),
-            Self::Memory(v) => v.fmt(f),
-        }
-    }
-}
-
 macro_rules! impl_trace_decl {
     (
         $(
@@ -5210,17 +4956,6 @@ impl_trace_decl! {
             module: TraceModule,
             ty: Bundle,
         }),
-        Mem(TraceMem {
-            fn children(self) -> _ {
-                Interned::from_iter([*self.element_type].into_iter().chain(self.ports.iter().map(|&v| v.into())))
-            }
-            id: TraceMemoryId,
-            name: Interned<str>,
-            stride: usize,
-            element_type: Interned<TraceDecl>,
-            ports: Interned<[TraceMemPort]>,
-            array_type: Array,
-        }),
         MemPort(TraceMemPort {
             fn children(self) -> _ {
                 [self.bundle.into()][..].intern()
@@ -5285,72 +5020,72 @@ impl_trace_decl! {
     }),
     #[kind = TraceScalarKind]
     Scalar(TraceScalar {
-        fn location(self) -> TraceLocation;
+        fn id(self) -> TraceScalarId;
         UInt(TraceUInt {
-            fn location(self) -> _ {
-                self.location
+            fn id(self) -> _ {
+                self.id
             }
-            location: TraceLocation,
+            id: TraceScalarId,
             name: Interned<str>,
             ty: UInt,
             flow: Flow,
         }),
         SInt(TraceSInt {
-            fn location(self) -> _ {
-                self.location
+            fn id(self) -> _ {
+                self.id
             }
-            location: TraceLocation,
+            id: TraceScalarId,
             name: Interned<str>,
             ty: SInt,
             flow: Flow,
         }),
         Bool(TraceBool {
-            fn location(self) -> _ {
-                self.location
+            fn id(self) -> _ {
+                self.id
             }
-            location: TraceLocation,
+            id: TraceScalarId,
             name: Interned<str>,
             flow: Flow,
         }),
         FieldlessEnum(TraceFieldlessEnum {
-            fn location(self) -> _ {
-                self.location
+            fn id(self) -> _ {
+                self.id
             }
-            location: TraceLocation,
+            id: TraceScalarId,
             name: Interned<str>,
             ty: Enum,
             flow: Flow,
         }),
         EnumDiscriminant(TraceEnumDiscriminant {
-            fn location(self) -> _ {
-                self.location
+            fn id(self) -> _ {
+                self.id
             }
-            location: TraceLocation,
+            id: TraceScalarId,
             name: Interned<str>,
             ty: Enum,
             flow: Flow,
         }),
         Clock(TraceClock {
-            fn location(self) -> _ {
-                self.location
+            fn id(self) -> _ {
+                self.id
             }
-            location: TraceLocation,
+            id: TraceScalarId,
             name: Interned<str>,
             flow: Flow,
         }),
         SyncReset(TraceSyncReset {
-            fn location(self) -> _ {
-                self.location
+            fn id(self) -> _ {
+                self.id
             }
-            location: TraceLocation,
+            id: TraceScalarId,
             name: Interned<str>,
             flow: Flow,
         }),
         AsyncReset(TraceAsyncReset {
-            fn location(self) -> _ {
-                self.location
+            fn id(self) -> _ {
+                self.id
             }
-            location: TraceLocation,
+            id: TraceScalarId,
             name: Interned<str>,
             flow: Flow,
         }),
@@ -5360,21 +5095,11 @@ impl_trace_decl! {
 pub trait TraceWriterDecls: fmt::Debug + 'static + Sized {
     type Error: std::error::Error + Send + Sync + 'static;
     type TraceWriter: TraceWriter<Error = Self::Error>;
-    fn write_decls(
-        self,
-        module: TraceModule,
-        trace_scalar_id_count: usize,
-        trace_memory_id_count: usize,
-    ) -> Result<Self::TraceWriter, Self::Error>;
+    fn write_decls(self, module: TraceModule) -> Result<Self::TraceWriter, Self::Error>;
 }
 
 trait TraceWriterDeclsDynTrait: fmt::Debug {
-    fn write_decls_dyn(
-        self: Box<Self>,
-        module: TraceModule,
-        trace_scalar_id_count: usize,
-        trace_memory_id_count: usize,
-    ) -> std::io::Result<DynTraceWriter>;
+    fn write_decls_dyn(self: Box<Self>, module: TraceModule) -> std::io::Result<DynTraceWriter>;
 }
 
 fn err_into_io<E: std::error::Error + Send + Sync + 'static>(e: E) -> std::io::Error {
@@ -5385,20 +5110,9 @@ fn err_into_io<E: std::error::Error + Send + Sync + 'static>(e: E) -> std::io::E
 }
 
 impl<T: TraceWriterDecls> TraceWriterDeclsDynTrait for T {
-    fn write_decls_dyn(
-        self: Box<Self>,
-        module: TraceModule,
-        trace_scalar_id_count: usize,
-        trace_memory_id_count: usize,
-    ) -> std::io::Result<DynTraceWriter> {
+    fn write_decls_dyn(self: Box<Self>, module: TraceModule) -> std::io::Result<DynTraceWriter> {
         Ok(DynTraceWriter(Box::new(
-            TraceWriterDecls::write_decls(
-                *self,
-                module,
-                trace_scalar_id_count,
-                trace_memory_id_count,
-            )
-            .map_err(err_into_io)?,
+            TraceWriterDecls::write_decls(*self, module).map_err(err_into_io)?,
         )))
     }
 }
@@ -5421,12 +5135,6 @@ pub trait TraceWriter: fmt::Debug + 'static {
     {
         Ok(())
     }
-    fn set_memory_element(
-        &mut self,
-        memory: TraceMemoryId,
-        element_index: usize,
-        element_data: &BitSlice,
-    ) -> Result<(), Self::Error>;
     fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error>;
     fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error>;
     fn set_signal_bool(&mut self, id: TraceScalarId, value: bool) -> Result<(), Self::Error> {
@@ -5474,14 +5182,8 @@ impl fmt::Debug for DynTraceWriterDecls {
 impl TraceWriterDecls for DynTraceWriterDecls {
     type Error = std::io::Error;
     type TraceWriter = DynTraceWriter;
-    fn write_decls(
-        self,
-        module: TraceModule,
-        trace_scalar_id_count: usize,
-        trace_memory_id_count: usize,
-    ) -> Result<Self::TraceWriter, Self::Error> {
-        self.0
-            .write_decls_dyn(module, trace_scalar_id_count, trace_memory_id_count)
+    fn write_decls(self, module: TraceModule) -> Result<Self::TraceWriter, Self::Error> {
+        self.0.write_decls_dyn(module)
     }
 }
 
@@ -5490,12 +5192,6 @@ trait TraceWriterDynTrait: fmt::Debug + 'static {
     fn change_time_to_dyn(&mut self, instant: SimInstant) -> std::io::Result<()>;
     fn flush_dyn(&mut self) -> std::io::Result<()>;
     fn close_dyn(self: Box<Self>) -> std::io::Result<()>;
-    fn set_memory_element_dyn(
-        &mut self,
-        memory: TraceMemoryId,
-        element_index: usize,
-        element_data: &BitSlice,
-    ) -> std::io::Result<()>;
     fn set_signal_uint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()>;
     fn set_signal_sint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()>;
     fn set_signal_bool_dyn(&mut self, id: TraceScalarId, value: bool) -> std::io::Result<()>;
@@ -5524,17 +5220,6 @@ impl<T: TraceWriter> TraceWriterDynTrait for T {
     fn close_dyn(self: Box<Self>) -> std::io::Result<()> {
         Ok(TraceWriter::close(*self).map_err(err_into_io)?)
     }
-    fn set_memory_element_dyn(
-        &mut self,
-        memory: TraceMemoryId,
-        element_index: usize,
-        element_data: &BitSlice,
-    ) -> std::io::Result<()> {
-        Ok(
-            TraceWriter::set_memory_element(self, memory, element_index, element_data)
-                .map_err(err_into_io)?,
-        )
-    }
     fn set_signal_uint_dyn(&mut self, id: TraceScalarId, value: &BitSlice) -> std::io::Result<()> {
         Ok(TraceWriter::set_signal_uint(self, id, value).map_err(err_into_io)?)
     }
@@ -5589,15 +5274,6 @@ impl TraceWriter for DynTraceWriter {
     fn close(self) -> Result<(), Self::Error> {
         self.0.close_dyn()
     }
-    fn set_memory_element(
-        &mut self,
-        memory: TraceMemoryId,
-        element_index: usize,
-        element_data: &BitSlice,
-    ) -> Result<(), Self::Error> {
-        self.0
-            .set_memory_element_dyn(memory, element_index, element_data)
-    }
     fn change_time_to(&mut self, instant: SimInstant) -> Result<(), Self::Error> {
         self.0.change_time_to_dyn(instant)
     }
@@ -5642,91 +5318,24 @@ enum TraceWriterState<T: TraceWriterDecls> {
     Errored(Option<T::Error>),
 }
 
-trait SimTraceDebug<I> {
-    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result;
-}
-
-struct SimTraceDebugAsDebug<T, I>(T, I);
-
-impl<T: ?Sized, I: Copy> fmt::Debug for SimTraceDebugAsDebug<&'_ T, I>
-where
-    T: SimTraceDebug<I>,
-{
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.0.fmt(self.1, f)
-    }
-}
-
-impl<T, I> SimTraceDebug<I> for Vec<T>
-where
-    [T]: SimTraceDebug<I>,
-{
-    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        <[T]>::fmt(&**self, id, f)
-    }
-}
-
-impl<T: ?Sized + 'static + Send + Sync, I> SimTraceDebug<I> for Interned<T>
-where
-    T: SimTraceDebug<I>,
-{
-    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        T::fmt(&**self, id, f)
-    }
-}
-
-impl<T: ?Sized + 'static + Send + Sync, I> SimTraceDebug<I> for Box<T>
-where
-    T: SimTraceDebug<I>,
-{
-    fn fmt(&self, id: I, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        T::fmt(&**self, id, f)
-    }
-}
-
-impl<T> SimTraceDebug<()> for [T]
-where
-    T: SimTraceDebug<TraceScalarId>,
-{
-    fn fmt(&self, _id: (), f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        f.debug_list()
-            .entries(
-                self.iter()
-                    .enumerate()
-                    .map(|(id, v)| SimTraceDebugAsDebug(v, TraceScalarId(id))),
-            )
-            .finish()
-    }
-}
-
 #[derive(Clone, PartialEq, Eq, Hash)]
-struct SimTrace<K, S> {
-    kind: K,
+struct SimTrace<S> {
+    id: TraceScalarId,
+    kind: SimTraceKind,
     state: S,
     last_state: S,
 }
 
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
-struct SimTraces<T>(T);
-
-impl<T> fmt::Debug for SimTraces<T>
-where
-    T: SimTraceDebug<()>,
-{
+impl fmt::Debug for SimTrace<()> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.0.fmt((), f)
-    }
-}
-
-impl<K: fmt::Debug> SimTraceDebug<TraceScalarId> for SimTrace<K, ()> {
-    fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
+            id,
             kind,
             state,
             last_state,
         } = self;
         f.debug_struct("SimTrace")
-            .field("id", &id)
+            .field("id", id)
             .field("kind", kind)
             .field("state", state)
             .field("last_state", last_state)
@@ -5734,15 +5343,16 @@ impl<K: fmt::Debug> SimTraceDebug<TraceScalarId> for SimTrace<K, ()> {
     }
 }
 
-impl<K: fmt::Debug> SimTraceDebug<TraceScalarId> for SimTrace<K, BitVec> {
-    fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+impl fmt::Debug for SimTrace<BitVec> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
+            id,
             kind,
             state,
             last_state,
         } = self;
         f.debug_struct("SimTrace")
-            .field("id", &id)
+            .field("id", id)
             .field("kind", kind)
             .field("state", &BitSliceWriteWithBase(state))
             .field("last_state", &BitSliceWriteWithBase(last_state))
@@ -5822,727 +5432,52 @@ impl SimTraceKind {
     }
 }
 
-#[derive(Clone, PartialEq, Eq, Hash, Debug)]
-pub struct SimValue<T: Type> {
-    ty: T,
-    bits: BitVec,
-}
-
-impl SimValue<CanonicalType> {
-    #[track_caller]
-    fn to_expr_impl(ty: CanonicalType, bits: &BitSlice) -> Expr<CanonicalType> {
-        match ty {
-            CanonicalType::UInt(_) => Expr::canonical(<UInt>::bits_to_expr(Cow::Borrowed(bits))),
-            CanonicalType::SInt(_) => Expr::canonical(<SInt>::bits_to_expr(Cow::Borrowed(bits))),
-            CanonicalType::Bool(_) => Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits))),
-            CanonicalType::Array(ty) => {
-                let element_bit_width = ty.element().bit_width();
-                Expr::<Array>::canonical(
-                    crate::expr::ops::ArrayLiteral::new(
-                        ty.element(),
-                        (0..ty.len())
-                            .map(|array_index| {
-                                let start = element_bit_width * array_index;
-                                let end = start + element_bit_width;
-                                Self::to_expr_impl(ty.element(), &bits[start..end])
-                            })
-                            .collect(),
-                    )
-                    .to_expr(),
-                )
-            }
-            CanonicalType::Enum(ty) => {
-                let discriminant_bit_width = ty.discriminant_bit_width();
-                let mut variant_index = [0; mem::size_of::<usize>()];
-                variant_index.view_bits_mut::<Lsb0>()[0..discriminant_bit_width]
-                    .clone_from_bitslice(&bits[..discriminant_bit_width]);
-                let variant_index = usize::from_le_bytes(variant_index);
-                if let Some(variant) = ty.variants().get(variant_index) {
-                    let data_bit_width = variant.ty.map_or(0, CanonicalType::bit_width);
-                    Expr::canonical(
-                        crate::expr::ops::EnumLiteral::new_by_index(
-                            ty,
-                            variant_index,
-                            variant.ty.map(|ty| {
-                                Self::to_expr_impl(
-                                    ty,
-                                    &bits[discriminant_bit_width
-                                        ..discriminant_bit_width + data_bit_width],
-                                )
-                            }),
-                        )
-                        .to_expr(),
-                    )
-                } else {
-                    Expr::canonical(<UInt>::bits_to_expr(Cow::Borrowed(bits)).cast_bits_to(ty))
-                }
-            }
-            CanonicalType::Bundle(ty) => Expr::canonical(
-                crate::expr::ops::BundleLiteral::new(
-                    ty,
-                    ty.fields()
-                        .iter()
-                        .zip(ty.field_offsets().iter())
-                        .map(|(field, &field_offset)| {
-                            Self::to_expr_impl(
-                                field.ty,
-                                &bits[field_offset..field_offset + field.ty.bit_width()],
-                            )
-                        })
-                        .collect(),
-                )
-                .to_expr(),
-            ),
-            CanonicalType::AsyncReset(ty) => {
-                Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits)).cast_to(ty))
-            }
-            CanonicalType::SyncReset(ty) => {
-                Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits)).cast_to(ty))
-            }
-            CanonicalType::Reset(_) => panic!(
-                "can't convert SimValue<Reset> to Expr<Reset> -- \
-                can't deduce whether reset value should be sync or async"
-            ),
-            CanonicalType::Clock(ty) => {
-                Expr::canonical(Bool::bits_to_expr(Cow::Borrowed(bits)).cast_to(ty))
-            }
-        }
-    }
-}
-
-impl<T: Type> ToExpr for SimValue<T> {
-    type Type = T;
-
-    #[track_caller]
-    fn to_expr(&self) -> Expr<Self::Type> {
-        Expr::from_canonical(SimValue::to_expr_impl(self.ty.canonical(), &self.bits))
-    }
-}
-
-impl<T: Type> ToSimValue<T> for SimValue<T> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        assert_eq!(self.ty, ty);
-        self.clone()
-    }
-
-    #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        assert_eq!(self.ty, ty);
-        self
-    }
-
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
-        assert_eq!(self.ty, ty);
-        *self
-    }
-}
-
-impl<T: Type> ToSimValue<T> for BitVec {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        self.clone().into_sim_value(ty)
-    }
-
-    #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        assert_eq!(ty.canonical().bit_width(), self.len());
-        SimValue { ty, bits: self }
-    }
-
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
-        Self::into_sim_value(*self, ty)
-    }
-}
-
-impl<T: Type> ToSimValue<T> for bitvec::boxed::BitBox {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        self.clone().into_sim_value(ty)
-    }
-
-    #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        assert_eq!(ty.canonical().bit_width(), self.len());
-        SimValue {
-            ty,
-            bits: self.into_bitvec(),
-        }
-    }
-
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
-        Self::into_sim_value(*self, ty)
-    }
-}
-
-impl<T: Type> ToSimValue<T> for BitSlice {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        assert_eq!(ty.canonical().bit_width(), self.len());
-        SimValue {
-            ty,
-            bits: self.to_bitvec(),
-        }
-    }
-}
-
-impl<T: Type> SimValue<T> {
-    pub fn ty(&self) -> T {
-        self.ty
-    }
-    pub fn bits(&self) -> &BitSlice {
-        &self.bits
-    }
-    pub fn into_bits(self) -> BitVec {
-        self.bits
-    }
-    #[track_caller]
-    pub fn from_canonical(v: SimValue<CanonicalType>) -> Self {
-        Self {
-            ty: T::from_canonical(v.ty),
-            bits: v.bits,
-        }
-    }
-    pub fn into_canonical(self) -> SimValue<CanonicalType> {
-        SimValue {
-            ty: self.ty.canonical(),
-            bits: self.bits,
-        }
-    }
-    #[track_caller]
-    pub fn from_dyn_int(v: SimValue<T::Dyn>) -> Self
-    where
-        T: IntType,
-    {
-        Self {
-            ty: T::from_dyn_int(v.ty),
-            bits: v.bits,
-        }
-    }
-    pub fn into_dyn_int(self) -> SimValue<T::Dyn>
-    where
-        T: IntType,
-    {
-        SimValue {
-            ty: self.ty.as_dyn_int(),
-            bits: self.bits,
-        }
-    }
-    #[track_caller]
-    pub fn from_bundle(v: SimValue<Bundle>) -> Self
-    where
-        T: BundleType,
-    {
-        Self {
-            ty: T::from_canonical(CanonicalType::Bundle(v.ty)),
-            bits: v.bits,
-        }
-    }
-    pub fn into_bundle(self) -> SimValue<Bundle>
-    where
-        T: BundleType,
-    {
-        SimValue {
-            ty: Bundle::from_canonical(self.ty.canonical()),
-            bits: self.bits,
-        }
-    }
-    #[track_caller]
-    pub fn from_enum(v: SimValue<Enum>) -> Self
-    where
-        T: EnumType,
-    {
-        Self {
-            ty: T::from_canonical(CanonicalType::Enum(v.ty)),
-            bits: v.bits,
-        }
-    }
-    pub fn into_enum(self) -> SimValue<Enum>
-    where
-        T: EnumType,
-    {
-        SimValue {
-            ty: Enum::from_canonical(self.ty.canonical()),
-            bits: self.bits,
-        }
-    }
-}
-
-pub trait ToSimValue<T: Type> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T>;
-    #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T>
-    where
-        Self: Sized,
-    {
-        self.to_sim_value(ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
-        self.to_sim_value(ty)
-    }
-}
-
-impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for &'_ This {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
-    }
-}
-
-impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for &'_ mut This {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
-    }
-}
-
-impl<This: ?Sized + ToSimValue<T>, T: Type> ToSimValue<T> for Box<This> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: T) -> SimValue<T> {
-        This::box_into_sim_value(self, ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: T) -> SimValue<T> {
-        This::box_into_sim_value(*self, ty)
-    }
-}
-
-impl<This: ?Sized + ToSimValue<T> + Send + Sync + 'static, T: Type> ToSimValue<T>
-    for Interned<This>
-{
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        This::to_sim_value(self, ty)
-    }
-}
-
-impl<T: Type, Len: Size> SimValue<ArrayType<T, Len>> {
-    #[track_caller]
-    pub fn from_array_elements<
-        I: IntoIterator<Item: ToSimValue<T>, IntoIter: ExactSizeIterator>,
-    >(
-        elements: I,
-        ty: ArrayType<T, Len>,
-    ) -> Self {
-        let mut iter = elements.into_iter();
-        assert_eq!(iter.len(), ty.len());
-        let Some(first) = iter.next() else {
-            return SimValue {
-                ty,
-                bits: BitVec::new(),
-            };
-        };
-        let SimValue {
-            ty: element_ty,
-            mut bits,
-        } = first.into_sim_value(ty.element());
-        assert_eq!(element_ty, ty.element());
-        bits.reserve(ty.type_properties().bit_width - bits.len());
-        for element in iter {
-            let SimValue {
-                ty: element_ty,
-                bits: element_bits,
-            } = element.into_sim_value(ty.element());
-            assert_eq!(element_ty, ty.element());
-            bits.extend_from_bitslice(&element_bits);
-        }
-        SimValue { ty, bits }
-    }
-}
-
-impl<Element: ToSimValue<T>, T: Type> ToSimValue<Array<T>> for [Element] {
-    #[track_caller]
-    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-}
-
-impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for [Element] {
-    #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-}
-
-impl<Element: ToSimValue<T>, T: Type, const N: usize> ToSimValue<Array<T, N>> for [Element; N]
-where
-    ConstUsize<N>: KnownSize,
-{
-    #[track_caller]
-    fn to_sim_value(&self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: Array<T, N>) -> SimValue<Array<T, N>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: Array<T, N>) -> SimValue<Array<T, N>> {
-        SimValue::from_array_elements(<Vec<Element> as From<Box<[Element]>>>::from(self), ty)
-    }
-}
-
-impl<Element: ToSimValue<T>, T: Type, const N: usize> ToSimValue<Array<T>> for [Element; N]
-where
-    ConstUsize<N>: KnownSize,
-{
-    #[track_caller]
-    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(<Vec<Element> as From<Box<[Element]>>>::from(self), ty)
-    }
-}
-
-impl<Element: ToSimValue<CanonicalType>, const N: usize> ToSimValue<CanonicalType>
-    for [Element; N]
-{
-    #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(
-            <Vec<Element> as From<Box<[Element]>>>::from(self),
-            <Array>::from_canonical(ty),
-        )
-        .into_canonical()
-    }
-}
-
-impl<Element: ToSimValue<T>, T: Type> ToSimValue<Array<T>> for Vec<Element> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(self, ty)
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: Array<T>) -> SimValue<Array<T>> {
-        SimValue::from_array_elements(*self, ty)
-    }
-}
-
-impl<Element: ToSimValue<CanonicalType>> ToSimValue<CanonicalType> for Vec<Element> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-    #[track_caller]
-    fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(self, <Array>::from_canonical(ty)).into_canonical()
-    }
-    #[track_caller]
-    fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
-        SimValue::from_array_elements(*self, <Array>::from_canonical(ty)).into_canonical()
-    }
-}
-
-impl<T: Type> ToSimValue<T> for Expr<T> {
-    #[track_caller]
-    fn to_sim_value(&self, ty: T) -> SimValue<T> {
-        assert_eq!(Expr::ty(*self), ty);
-        SimValue {
-            ty,
-            bits: self
-                .to_literal_bits()
-                .expect("must be a literal expression")
-                .to_bitvec(),
-        }
-    }
-}
-
-macro_rules! impl_to_sim_value_for_bool_like {
-    ($ty:ident) => {
-        impl ToSimValue<$ty> for bool {
-            fn to_sim_value(&self, ty: $ty) -> SimValue<$ty> {
-                SimValue {
-                    ty,
-                    bits: BitVec::repeat(*self, 1),
-                }
-            }
-        }
-    };
-}
-
-impl_to_sim_value_for_bool_like!(Bool);
-impl_to_sim_value_for_bool_like!(AsyncReset);
-impl_to_sim_value_for_bool_like!(SyncReset);
-impl_to_sim_value_for_bool_like!(Reset);
-impl_to_sim_value_for_bool_like!(Clock);
-
-impl ToSimValue<CanonicalType> for bool {
-    #[track_caller]
-    fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-        match ty {
-            CanonicalType::UInt(_)
-            | CanonicalType::SInt(_)
-            | CanonicalType::Array(_)
-            | CanonicalType::Enum(_)
-            | CanonicalType::Bundle(_) => {
-                panic!("can't create SimValue from bool: expected value of type: {ty:?}");
-            }
-            CanonicalType::Bool(_)
-            | CanonicalType::AsyncReset(_)
-            | CanonicalType::SyncReset(_)
-            | CanonicalType::Reset(_)
-            | CanonicalType::Clock(_) => SimValue {
-                ty,
-                bits: BitVec::repeat(*self, 1),
-            },
-        }
-    }
-}
-
-macro_rules! impl_to_sim_value_for_primitive_int {
-    ($prim:ident) => {
-        impl ToSimValue<<$prim as ToExpr>::Type> for $prim {
-            #[track_caller]
-            fn to_sim_value(
-                &self,
-                ty: <$prim as ToExpr>::Type,
-            ) -> SimValue<<$prim as ToExpr>::Type> {
-                SimValue {
-                    ty,
-                    bits: <<$prim as ToExpr>::Type as BoolOrIntType>::le_bytes_to_bits_wrapping(
-                        &self.to_le_bytes(),
-                        ty.width(),
-                    ),
-                }
-            }
-        }
-
-        impl ToSimValue<<<$prim as ToExpr>::Type as IntType>::Dyn> for $prim {
-            #[track_caller]
-            fn to_sim_value(
-                &self,
-                ty: <<$prim as ToExpr>::Type as IntType>::Dyn,
-            ) -> SimValue<<<$prim as ToExpr>::Type as IntType>::Dyn> {
-                SimValue {
-                    ty,
-                    bits: <<$prim as ToExpr>::Type as BoolOrIntType>::le_bytes_to_bits_wrapping(
-                        &self.to_le_bytes(),
-                        ty.width(),
-                    ),
-                }
-            }
-        }
-
-        impl ToSimValue<CanonicalType> for $prim {
-            #[track_caller]
-            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                let ty: <<$prim as ToExpr>::Type as IntType>::Dyn = Type::from_canonical(ty);
-                self.to_sim_value(ty).into_canonical()
-            }
-        }
-    };
-}
-
-impl_to_sim_value_for_primitive_int!(u8);
-impl_to_sim_value_for_primitive_int!(u16);
-impl_to_sim_value_for_primitive_int!(u32);
-impl_to_sim_value_for_primitive_int!(u64);
-impl_to_sim_value_for_primitive_int!(u128);
-impl_to_sim_value_for_primitive_int!(usize);
-impl_to_sim_value_for_primitive_int!(i8);
-impl_to_sim_value_for_primitive_int!(i16);
-impl_to_sim_value_for_primitive_int!(i32);
-impl_to_sim_value_for_primitive_int!(i64);
-impl_to_sim_value_for_primitive_int!(i128);
-impl_to_sim_value_for_primitive_int!(isize);
-
-macro_rules! impl_to_sim_value_for_int_value {
-    ($IntValue:ident, $Int:ident, $IntType:ident) => {
-        impl<Width: KnownSize> ToSimValue<$IntType<Width>> for $IntValue<Width> {
-            fn to_sim_value(&self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
-                self.bits().to_bitvec().into_sim_value(ty)
-            }
-
-            fn into_sim_value(self, ty: $IntType<Width>) -> SimValue<$IntType<Width>> {
-                Arc::try_unwrap(self.into_bits())
-                    .unwrap_or_else(|v: Arc<BitVec>| v.to_bitvec())
-                    .into_sim_value(ty)
-            }
-
-            fn box_into_sim_value(
-                self: Box<Self>,
-                ty: $IntType<Width>,
-            ) -> SimValue<$IntType<Width>> {
-                Self::into_sim_value(*self, ty)
-            }
-        }
-
-        impl<Width: Size> ToSimValue<$Int> for $IntValue<Width> {
-            fn to_sim_value(&self, ty: $Int) -> SimValue<$Int> {
-                self.bits().to_bitvec().into_sim_value(ty)
-            }
-
-            fn into_sim_value(self, ty: $Int) -> SimValue<$Int> {
-                Arc::try_unwrap(self.into_bits())
-                    .unwrap_or_else(|v: Arc<BitVec>| v.to_bitvec())
-                    .into_sim_value(ty)
-            }
-
-            fn box_into_sim_value(self: Box<Self>, ty: $Int) -> SimValue<$Int> {
-                Self::into_sim_value(*self, ty)
-            }
-        }
-
-        impl<Width: Size> ToSimValue<CanonicalType> for $IntValue<Width> {
-            #[track_caller]
-            fn to_sim_value(&self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                ToSimValue::<$Int>::to_sim_value(self, $Int::from_canonical(ty)).into_canonical()
-            }
-
-            #[track_caller]
-            fn into_sim_value(self, ty: CanonicalType) -> SimValue<CanonicalType> {
-                ToSimValue::<$Int>::into_sim_value(self, $Int::from_canonical(ty)).into_canonical()
-            }
-
-            #[track_caller]
-            fn box_into_sim_value(self: Box<Self>, ty: CanonicalType) -> SimValue<CanonicalType> {
-                Self::into_sim_value(*self, ty)
-            }
-        }
-    };
-}
-
-impl_to_sim_value_for_int_value!(UIntValue, UInt, UIntType);
-impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType);
-
 struct SimulationImpl {
     state: interpreter::State,
     io: Expr<Bundle>,
-    uninitialized_inputs: HashMap<Target, Vec<Target>>,
+    uninitialized_inputs: HashSet<Target>,
     io_targets: HashMap<Target, CompiledValue<CanonicalType>>,
     made_initial_step: bool,
     needs_settle: bool,
     trace_decls: TraceModule,
-    traces: SimTraces<Box<[SimTrace<SimTraceKind, BitVec>]>>,
-    trace_memories: HashMap<StatePartIndex<StatePartKindMemories>, TraceMem>,
+    traces: Box<[SimTrace<BitVec>]>,
     trace_writers: Vec<TraceWriterState<DynTraceWriterDecls>>,
     instant: SimInstant,
     clocks_triggered: Interned<[StatePartIndex<StatePartKindSmallSlots>]>,
-    breakpoints: Option<BreakpointsSet>,
-}
-
-impl fmt::Debug for SimulationImpl {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.debug_fmt(None, f)
-    }
 }
 
 impl SimulationImpl {
-    fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let Self {
-            state,
-            io: self_io,
-            uninitialized_inputs,
-            io_targets,
-            made_initial_step,
-            needs_settle,
-            trace_decls,
-            traces,
-            trace_memories,
-            trace_writers,
-            instant,
-            clocks_triggered,
-            breakpoints: _,
-        } = self;
-        f.debug_struct("Simulation")
-            .field("state", state)
-            .field("io", io.unwrap_or(self_io))
-            .field(
-                "uninitialized_inputs",
-                &SortedSetDebug(uninitialized_inputs),
-            )
-            .field("io_targets", &SortedMapDebug(io_targets))
-            .field("made_initial_step", made_initial_step)
-            .field("needs_settle", needs_settle)
-            .field("trace_decls", trace_decls)
-            .field("traces", traces)
-            .field("trace_memories", trace_memories)
-            .field("trace_writers", trace_writers)
-            .field("instant", instant)
-            .field("clocks_triggered", clocks_triggered)
-            .finish_non_exhaustive()
-    }
-    /// returns `true` if `target` or any sub-targets are uninitialized inputs
-    fn parse_io(&mut self, target: Target, value: CompiledValue<CanonicalType>) -> bool {
+    fn parse_io(&mut self, target: Target, value: CompiledValue<CanonicalType>) {
         self.io_targets.insert(target, value);
         match value.layout.body {
             CompiledTypeLayoutBody::Scalar => match target.flow() {
-                Flow::Source => false,
+                Flow::Source => {}
                 Flow::Sink => {
-                    self.uninitialized_inputs.insert(target, vec![]);
-                    true
+                    self.uninitialized_inputs.insert(target);
                 }
                 Flow::Duplex => unreachable!(),
             },
             CompiledTypeLayoutBody::Array { .. } => {
                 let value = value.map_ty(Array::from_canonical);
-                let mut sub_targets = Vec::new();
                 for index in 0..value.layout.ty.len() {
-                    let sub_target = target.join(
-                        TargetPathElement::from(TargetPathArrayElement { index }).intern_sized(),
+                    self.parse_io(
+                        target.join(
+                            TargetPathElement::from(TargetPathArrayElement { index })
+                                .intern_sized(),
+                        ),
+                        value.element(index),
                     );
-                    if self.parse_io(sub_target, value.element(index)) {
-                        sub_targets.push(sub_target);
-                    }
-                }
-                if sub_targets.is_empty() {
-                    false
-                } else {
-                    self.uninitialized_inputs.insert(target, sub_targets);
-                    true
                 }
             }
             CompiledTypeLayoutBody::Bundle { .. } => {
                 let value = value.map_ty(Bundle::from_canonical);
-                let mut sub_targets = Vec::new();
                 for BundleField { name, .. } in value.layout.ty.fields() {
-                    let sub_target = target.join(
-                        TargetPathElement::from(TargetPathBundleField { name }).intern_sized(),
+                    self.parse_io(
+                        target.join(
+                            TargetPathElement::from(TargetPathBundleField { name }).intern_sized(),
+                        ),
+                        value.field_by_name(name),
                     );
-                    if self.parse_io(sub_target, value.field_by_name(name)) {
-                        sub_targets.push(sub_target);
-                    }
-                }
-                if sub_targets.is_empty() {
-                    false
-                } else {
-                    self.uninitialized_inputs.insert(target, sub_targets);
-                    true
                 }
             }
         }
@@ -6551,27 +5486,27 @@ impl SimulationImpl {
         let mut retval = Self {
             state: State::new(compiled.insns),
             io: compiled.io.to_expr(),
-            uninitialized_inputs: HashMap::new(),
+            uninitialized_inputs: HashSet::new(),
             io_targets: HashMap::new(),
             made_initial_step: false,
             needs_settle: true,
             trace_decls: compiled.base_module.trace_decls,
-            traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map(
+            traces: Box::from_iter(compiled.traces.iter().map(
                 |&SimTrace {
+                     id,
                      kind,
                      state: _,
                      last_state: _,
                  }| SimTrace {
+                    id,
                     kind,
                     state: kind.make_state(),
                     last_state: kind.make_state(),
                 },
-            ))),
-            trace_memories: HashMap::from_iter(compiled.trace_memories.iter().copied()),
+            )),
             trace_writers: vec![],
             instant: SimInstant::START,
             clocks_triggered: compiled.clocks_triggered,
-            breakpoints: None,
         };
         let io_target = Target::from(compiled.io);
         for (BundleField { name, .. }, value) in compiled
@@ -6593,41 +5528,16 @@ impl SimulationImpl {
         &mut self,
         mut trace_writer: DynTraceWriter,
     ) -> std::io::Result<DynTraceWriter> {
-        let mut set_memory_element = |memory: StatePartIndex<StatePartKindMemories>,
-                                      trace_mem: &TraceMem,
-                                      element_index: usize| {
-            let start = trace_mem.stride * element_index;
-            let end = start + trace_mem.stride;
-            trace_writer.set_memory_element(
-                self.trace_memories[&memory].id,
-                element_index,
-                &self.state.memories[memory].data[start..end],
-            )
-        };
-        if ONLY_IF_CHANGED {
-            for &(memory, element_index) in &self.state.memory_write_log {
-                set_memory_element(memory, &self.trace_memories[&memory], element_index)?;
-            }
-        } else {
-            for (&memory, trace_mem) in &self.trace_memories {
-                for element_index in 0..trace_mem.array_type.len() {
-                    set_memory_element(memory, trace_mem, element_index)?;
-                }
-            }
-        }
-        for (
+        for &SimTrace {
             id,
-            &SimTrace {
-                kind,
-                ref state,
-                ref last_state,
-            },
-        ) in self.traces.0.iter().enumerate()
+            kind,
+            ref state,
+            ref last_state,
+        } in &self.traces
         {
             if ONLY_IF_CHANGED && state == last_state {
                 continue;
             }
-            let id = TraceScalarId(id);
             match kind {
                 SimTraceKind::BigUInt { .. } | SimTraceKind::SmallUInt { .. } => {
                     trace_writer.set_signal_uint(id, state)?;
@@ -6678,10 +5588,11 @@ impl SimulationImpl {
     #[inline(never)]
     fn read_traces<const IS_INITIAL_STEP: bool>(&mut self) {
         for &mut SimTrace {
+            id: _,
             kind,
             ref mut state,
             ref mut last_state,
-        } in &mut self.traces.0
+        } in &mut self.traces
         {
             if !IS_INITIAL_STEP {
                 mem::swap(state, last_state);
@@ -6750,37 +5661,12 @@ impl SimulationImpl {
                 return;
             }
             self.state.setup_call(0);
-            if self.breakpoints.is_some() {
-                loop {
-                    match self
-                        .state
-                        .run(self.breakpoints.as_mut().expect("just checked"))
-                    {
-                        RunResult::Break(break_action) => {
-                            println!(
-                                "hit breakpoint at:\n{:?}",
-                                self.state.debug_insn_at(self.state.pc),
-                            );
-                            match break_action {
-                                BreakAction::DumpStateAndContinue => {
-                                    println!("{self:#?}");
-                                }
-                                BreakAction::Continue => {}
-                            }
-                        }
-                        RunResult::Return(()) => break,
-                    }
-                }
-            } else {
-                let RunResult::Return(()) = self.state.run(());
-            }
+            self.state.run();
             if self.made_initial_step {
                 self.read_traces::<false>();
             } else {
                 self.read_traces::<true>();
             }
-            self.state.memory_write_log.sort_unstable();
-            self.state.memory_write_log.dedup();
             self.made_initial_step = true;
             self.needs_settle = self
                 .clocks_triggered
@@ -6789,11 +5675,7 @@ impl SimulationImpl {
             self.for_each_trace_writer_storing_error(|this, trace_writer_state| {
                 Ok(match trace_writer_state {
                     TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running(
-                        this.init_trace_writer(trace_writer_decls.write_decls(
-                            this.trace_decls,
-                            this.traces.0.len(),
-                            this.trace_memories.len(),
-                        )?)?,
+                        this.init_trace_writer(trace_writer_decls.write_decls(this.trace_decls)?)?,
                     ),
                     TraceWriterState::Init(trace_writer) => {
                         TraceWriterState::Running(this.init_trace_writer(trace_writer)?)
@@ -6804,7 +5686,6 @@ impl SimulationImpl {
                     TraceWriterState::Errored(e) => TraceWriterState::Errored(e),
                 })
             });
-            self.state.memory_write_log.clear();
         }
         panic!("settle(): took too many steps");
     }
@@ -6816,39 +5697,10 @@ impl SimulationImpl {
         if Some(&target) == self.io.target().as_deref()
             || Some(target.base()) != self.io.target().map(|v| v.base())
         {
-            panic!("simulator read/write expression must be an array element/field of `Simulation::io()`");
+            panic!("simulator read/write expression must be an array element/field of `Simulator::io()`");
         };
         panic!("simulator read/write expression must not have dynamic array indexes");
     }
-    fn mark_target_as_initialized(&mut self, mut target: Target) {
-        fn remove_target_and_children(
-            uninitialized_inputs: &mut HashMap<Target, Vec<Target>>,
-            target: Target,
-        ) {
-            let Some(children) = uninitialized_inputs.remove(&target) else {
-                return;
-            };
-            for child in children {
-                remove_target_and_children(uninitialized_inputs, child);
-            }
-        }
-        remove_target_and_children(&mut self.uninitialized_inputs, target);
-        while let Some(target_child) = target.child() {
-            let parent = target_child.parent();
-            for child in self
-                .uninitialized_inputs
-                .get(&*parent)
-                .map(|v| &**v)
-                .unwrap_or(&[])
-            {
-                if self.uninitialized_inputs.contains_key(child) {
-                    return;
-                }
-            }
-            target = *parent;
-            self.uninitialized_inputs.remove(&target);
-        }
-    }
     #[track_caller]
     fn read_helper(&mut self, io: Expr<CanonicalType>) -> CompiledValue<CanonicalType> {
         let Some(target) = io.target() else {
@@ -6860,15 +5712,10 @@ impl SimulationImpl {
         } else {
             match target.flow() {
                 Flow::Source => {
-                    if !self.uninitialized_inputs.is_empty() {
-                        panic!(
-                            "can't read from an output before the simulation has made any steps"
-                        );
-                    }
-                    self.settle();
+                    panic!("can't read from an output before the simulation has made any steps");
                 }
                 Flow::Sink => {
-                    if self.uninitialized_inputs.contains_key(&*target) {
+                    if self.uninitialized_inputs.contains(&*target) {
                         panic!("can't read from an uninitialized input");
                     }
                 }
@@ -6891,7 +5738,7 @@ impl SimulationImpl {
             Flow::Duplex => unreachable!(),
         }
         if !self.made_initial_step {
-            self.mark_target_as_initialized(*target);
+            self.uninitialized_inputs.remove(&*target);
         }
         self.needs_settle = true;
         compiled_value
@@ -6941,11 +5788,8 @@ impl SimulationImpl {
         let value: BigInt = value.into();
         match compiled_value.range.len() {
             TypeLen::A_SMALL_SLOT => {
-                let mut small_value = value.iter_u64_digits().next().unwrap_or(0);
-                if value.is_negative() {
-                    small_value = small_value.wrapping_neg();
-                }
-                self.state.small_slots[compiled_value.range.small_slots.start] = small_value;
+                self.state.small_slots[compiled_value.range.small_slots.start] =
+                    value.to_u64().expect("value out of range");
             }
             TypeLen::A_BIG_SLOT => {
                 self.state.big_slots[compiled_value.range.big_slots.start] = value
@@ -6953,142 +5797,12 @@ impl SimulationImpl {
             _ => unreachable!(),
         }
     }
-    #[track_caller]
-    fn read_write_sim_value_helper(
-        &mut self,
-        compiled_value: CompiledValue<CanonicalType>,
-        bits: &mut BitSlice,
-        read_write_big_scalar: impl Fn(bool, &mut BitSlice, &mut BigInt) + Copy,
-        read_write_small_scalar: impl Fn(bool, &mut BitSlice, &mut SmallUInt) + Copy,
-    ) {
-        match compiled_value.layout.body {
-            CompiledTypeLayoutBody::Scalar => {
-                let signed = match compiled_value.layout.ty {
-                    CanonicalType::UInt(_) => false,
-                    CanonicalType::SInt(_) => true,
-                    CanonicalType::Bool(_) => false,
-                    CanonicalType::Array(_) => unreachable!(),
-                    CanonicalType::Enum(_) => false,
-                    CanonicalType::Bundle(_) => unreachable!(),
-                    CanonicalType::AsyncReset(_) => false,
-                    CanonicalType::SyncReset(_) => false,
-                    CanonicalType::Reset(_) => false,
-                    CanonicalType::Clock(_) => false,
-                };
-                match compiled_value.range.len() {
-                    TypeLen::A_SMALL_SLOT => read_write_small_scalar(
-                        signed,
-                        bits,
-                        &mut self.state.small_slots[compiled_value.range.small_slots.start],
-                    ),
-                    TypeLen::A_BIG_SLOT => read_write_big_scalar(
-                        signed,
-                        bits,
-                        &mut self.state.big_slots[compiled_value.range.big_slots.start],
-                    ),
-                    _ => unreachable!(),
-                }
-            }
-            CompiledTypeLayoutBody::Array { element } => {
-                let ty = <Array>::from_canonical(compiled_value.layout.ty);
-                let element_bit_width = ty.element().bit_width();
-                for element_index in 0..ty.len() {
-                    self.read_write_sim_value_helper(
-                        CompiledValue {
-                            layout: *element,
-                            range: compiled_value
-                                .range
-                                .index_array(element.layout.len(), element_index),
-                            write: None,
-                        },
-                        &mut bits[element_index * element_bit_width..][..element_bit_width],
-                        read_write_big_scalar,
-                        read_write_small_scalar,
-                    );
-                }
-            }
-            CompiledTypeLayoutBody::Bundle { fields } => {
-                let ty = Bundle::from_canonical(compiled_value.layout.ty);
-                for (
-                    (field, offset),
-                    CompiledBundleField {
-                        offset: layout_offset,
-                        ty: field_layout,
-                    },
-                ) in ty.fields().iter().zip(ty.field_offsets()).zip(fields)
-                {
-                    self.read_write_sim_value_helper(
-                        CompiledValue {
-                            layout: field_layout,
-                            range: compiled_value.range.slice(TypeIndexRange::new(
-                                layout_offset,
-                                field_layout.layout.len(),
-                            )),
-                            write: None,
-                        },
-                        &mut bits[offset..][..field.ty.bit_width()],
-                        read_write_big_scalar,
-                        read_write_small_scalar,
-                    );
-                }
-            }
-        }
-    }
-    #[track_caller]
-    fn read(&mut self, io: Expr<CanonicalType>) -> SimValue<CanonicalType> {
-        let compiled_value = self.read_helper(io);
-        let mut bits = BitVec::repeat(false, compiled_value.layout.ty.bit_width());
-        self.read_write_sim_value_helper(
-            compiled_value,
-            &mut bits,
-            |_signed, bits, value| <UInt>::copy_bits_from_bigint_wrapping(value, bits),
-            |_signed, bits, value| {
-                let bytes = value.to_le_bytes();
-                let bitslice = BitSlice::<u8, Lsb0>::from_slice(&bytes);
-                bits.clone_from_bitslice(&bitslice[..bits.len()]);
-            },
-        );
-        SimValue {
-            ty: Expr::ty(io),
-            bits,
-        }
-    }
-    #[track_caller]
-    fn write(&mut self, io: Expr<CanonicalType>, value: SimValue<CanonicalType>) {
-        let compiled_value = self.write_helper(io);
-        assert_eq!(Expr::ty(io), value.ty());
-        self.read_write_sim_value_helper(
-            compiled_value,
-            &mut value.into_bits(),
-            |signed, bits, value| {
-                if signed {
-                    *value = SInt::bits_to_bigint(bits);
-                } else {
-                    *value = UInt::bits_to_bigint(bits);
-                }
-            },
-            |signed, bits, value| {
-                let mut small_value = [0; mem::size_of::<SmallUInt>()];
-                if signed && bits.last().as_deref().copied() == Some(true) {
-                    small_value.fill(u8::MAX);
-                }
-                small_value.view_bits_mut::<Lsb0>()[0..bits.len()].clone_from_bitslice(bits);
-                *value = SmallUInt::from_le_bytes(small_value);
-            },
-        );
-    }
     fn close_all_trace_writers(&mut self) -> std::io::Result<()> {
         let trace_writers = mem::take(&mut self.trace_writers);
         let mut retval = Ok(());
         let close_trace_writer =
             |trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
-                TraceWriterState::Decls(v) => v
-                    .write_decls(
-                        self.trace_decls,
-                        self.traces.0.len(),
-                        self.trace_memories.len(),
-                    )?
-                    .close(),
+                TraceWriterState::Decls(v) => v.write_decls(self.trace_decls)?.close(),
                 TraceWriterState::Init(v) => v.close(),
                 TraceWriterState::Running(v) => v.close(),
                 TraceWriterState::Errored(Some(e)) => Err(e),
@@ -7159,11 +5873,7 @@ impl SimulationImpl {
         self.for_each_trace_writer_getting_error(
             |this, trace_writer: TraceWriterState<DynTraceWriterDecls>| match trace_writer {
                 TraceWriterState::Decls(v) => {
-                    let mut v = v.write_decls(
-                        this.trace_decls,
-                        this.traces.0.len(),
-                        this.trace_memories.len(),
-                    )?;
+                    let mut v = v.write_decls(this.trace_decls)?;
                     v.flush()?;
                     Ok(TraceWriterState::Init(v))
                 }
@@ -7194,11 +5904,11 @@ pub struct Simulation<T: BundleType> {
     io: Expr<T>,
 }
 
-struct SortedSetDebug<'a, T, V>(&'a HashMap<T, V>);
+struct SortedSetDebug<'a, T>(&'a HashSet<T>);
 
-impl<T: fmt::Debug, V> fmt::Debug for SortedSetDebug<'_, T, V> {
+impl<T: fmt::Debug> fmt::Debug for SortedSetDebug<'_, T> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let mut entries = Vec::from_iter(self.0.iter().map(|(v, _)| {
+        let mut entries = Vec::from_iter(self.0.iter().map(|v| {
             if f.alternate() {
                 format!("{v:#?}")
             } else {
@@ -7236,8 +5946,39 @@ impl<K: fmt::Debug, V: fmt::Debug> fmt::Debug for SortedMapDebug<'_, K, V> {
 
 impl<T: BundleType> fmt::Debug for Simulation<T> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let Self { sim_impl, io } = self;
-        sim_impl.debug_fmt(Some(io), f)
+        let Self {
+            sim_impl:
+                SimulationImpl {
+                    state,
+                    io: _,
+                    uninitialized_inputs,
+                    io_targets,
+                    made_initial_step,
+                    needs_settle,
+                    trace_decls,
+                    traces,
+                    trace_writers,
+                    instant,
+                    clocks_triggered,
+                },
+            io,
+        } = self;
+        f.debug_struct("Simulation")
+            .field("state", state)
+            .field("io", io)
+            .field(
+                "uninitialized_inputs",
+                &SortedSetDebug(uninitialized_inputs),
+            )
+            .field("io_targets", &SortedMapDebug(io_targets))
+            .field("made_initial_step", made_initial_step)
+            .field("needs_settle", needs_settle)
+            .field("trace_decls", trace_decls)
+            .field("traces", traces)
+            .field("trace_writers", trace_writers)
+            .field("instant", instant)
+            .field("clocks_triggered", clocks_triggered)
+            .finish()
     }
 }
 
@@ -7330,24 +6071,4 @@ impl<T: BundleType> Simulation<T> {
     pub fn read_reset<R: ResetType>(&mut self, io: Expr<R>) -> bool {
         self.sim_impl.read_bit(Expr::canonical(io))
     }
-    #[track_caller]
-    pub fn read<IO: Type>(&mut self, io: Expr<IO>) -> SimValue<IO> {
-        SimValue::from_canonical(self.sim_impl.read(Expr::canonical(io)))
-    }
-    #[track_caller]
-    pub fn write<IO: Type, V: ToSimValue<IO>>(&mut self, io: Expr<IO>, value: V) {
-        self.sim_impl.write(
-            Expr::canonical(io),
-            value.into_sim_value(Expr::ty(io)).into_canonical(),
-        );
-    }
-    #[doc(hidden)]
-    /// This is explicitly unstable and may be changed/removed at any time
-    pub fn set_breakpoints_unstable(&mut self, pcs: HashSet<usize>, trace: bool) {
-        self.sim_impl.breakpoints = Some(BreakpointsSet {
-            last_was_break: false,
-            set: pcs,
-            trace,
-        });
-    }
 }
diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs
index 22f6f5f..aabf6e2 100644
--- a/crates/fayalite/src/sim/interpreter.rs
+++ b/crates/fayalite/src/sim/interpreter.rs
@@ -2,7 +2,6 @@
 // See Notices.txt for copyright information
 
 use crate::{
-    array::Array,
     int::{BoolOrIntType, SInt, UInt},
     intern::{Intern, Interned, Memoize},
     source_location::SourceLocation,
@@ -10,17 +9,17 @@ use crate::{
     util::get_many_mut,
 };
 use bitvec::{boxed::BitBox, slice::BitSlice};
-use hashbrown::{HashMap, HashSet};
+use hashbrown::HashMap;
 use num_bigint::BigInt;
 use num_traits::{One, Signed, ToPrimitive, Zero};
 use std::{
     any::TypeId,
     borrow::BorrowMut,
     convert::Infallible,
-    fmt::{self, Write},
+    fmt,
     hash::{Hash, Hasher},
     marker::PhantomData,
-    ops::{ControlFlow, Deref, DerefMut, Index, IndexMut},
+    ops::{Deref, DerefMut, Index, IndexMut},
 };
 use vec_map::VecMap;
 
@@ -175,37 +174,7 @@ fn make_array_into_iter<T, const I: usize, const N: usize>(
 
 impl fmt::Debug for Insn {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.debug_fmt::<InsnsBuildingDone>(f, None, None, None)
-    }
-}
-
-struct PrefixLinesWrapper<'a, W> {
-    writer: W,
-    at_beginning_of_line: bool,
-    blank_line_prefix: &'a str,
-    line_prefix: &'a str,
-}
-
-impl<T: fmt::Write> fmt::Write for PrefixLinesWrapper<'_, T> {
-    fn write_str(&mut self, input: &str) -> fmt::Result {
-        for part in input.split_inclusive('\n') {
-            if part.is_empty() {
-                continue;
-            }
-            if self.at_beginning_of_line {
-                let prefix = match part {
-                    "\n" => self.blank_line_prefix,
-                    _ => self.line_prefix,
-                };
-                if !prefix.is_empty() {
-                    self.writer.write_str(prefix)?;
-                }
-                self.at_beginning_of_line = false;
-            }
-            self.writer.write_str(part)?;
-            self.at_beginning_of_line = part.ends_with('\n');
-        }
-        Ok(())
+        self.debug_fmt::<InsnsBuildingDone>(f, None, None)
     }
 }
 
@@ -215,22 +184,15 @@ impl Insn {
         f: &mut fmt::Formatter<'_>,
         labels: Option<&Labels>,
         state_layout: Option<&StateLayout<BK>>,
-        state: Option<&State>,
     ) -> fmt::Result {
         let (insn_name, fields) = self.fields_with_names();
         write!(f, "{insn_name}")?;
         if fields.len() == 0 {
             return Ok(());
         }
-        let mut f = PrefixLinesWrapper {
-            writer: f,
-            at_beginning_of_line: false,
-            blank_line_prefix: "",
-            line_prefix: "    ",
-        };
         writeln!(f, " {{")?;
         for (field_name, field) in fields {
-            write!(f, "{field_name}: ")?;
+            write!(f, "    {field_name}: ")?;
             match field.kind {
                 InsnFieldKind::BranchTarget => match field.ty {
                     InsnFieldType::USize(&label_index) => {
@@ -265,100 +227,35 @@ impl Insn {
                 | InsnFieldKind::Output
                 | InsnFieldKind::Immediate => {}
             }
-            macro_rules! debug_fmt_state_part {
-                ($v:expr) => {
-                    $v.debug_fmt(&mut f, ",", " // ", "        // ", "", state_layout, state)
-                };
-            }
             match field.ty {
                 InsnFieldType::Memory(v) => {
-                    debug_fmt_state_part!(v)?;
+                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
                 }
                 InsnFieldType::SmallSlot(v) => {
-                    debug_fmt_state_part!(v)?;
+                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
                 }
                 InsnFieldType::BigSlot(v) => {
-                    debug_fmt_state_part!(v)?;
+                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
                 }
                 InsnFieldType::SmallSlotArrayIndexed(v) => {
-                    debug_fmt_state_part!(v)?;
+                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
                 }
                 InsnFieldType::BigSlotArrayIndexed(v) => {
-                    debug_fmt_state_part!(v)?;
+                    v.debug_fmt(f, ",", " // ", "", state_layout)?;
                 }
-                InsnFieldType::SmallUInt(v) => write!(f, "{v:#x}")?,
-                InsnFieldType::SmallSInt(v) => write!(f, "{v:#x}")?,
-                InsnFieldType::InternedBigInt(v) => write!(f, "{v:#x}")?,
-                InsnFieldType::U8(v) => write!(f, "{v:#x}")?,
-                InsnFieldType::USize(v) => write!(f, "{v}")?,
-                InsnFieldType::Empty(v) => write!(f, "{v:?}")?,
+                InsnFieldType::SmallUInt(v) => fmt::Debug::fmt(v, f)?,
+                InsnFieldType::SmallSInt(v) => fmt::Debug::fmt(v, f)?,
+                InsnFieldType::InternedBigInt(v) => fmt::Debug::fmt(v, f)?,
+                InsnFieldType::U8(v) => fmt::Debug::fmt(v, f)?,
+                InsnFieldType::USize(v) => fmt::Debug::fmt(v, f)?,
+                InsnFieldType::Empty(v) => fmt::Debug::fmt(v, f)?,
             }
             writeln!(f, ",")?;
         }
-        write!(f.writer, "}}")
+        write!(f, "}}")
     }
 }
 
-pub(crate) trait Breakpoints {
-    type Break;
-    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break>;
-}
-
-impl<T: ?Sized + Breakpoints> Breakpoints for &'_ mut T {
-    type Break = T::Break;
-    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
-        T::check_for_breakpoint(self, pc)
-    }
-}
-
-impl<T: ?Sized + Breakpoints> Breakpoints for Box<T> {
-    type Break = T::Break;
-    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
-        T::check_for_breakpoint(self, pc)
-    }
-}
-
-impl Breakpoints for () {
-    type Break = Infallible;
-    fn check_for_breakpoint(&mut self, _pc: usize) -> ControlFlow<Self::Break> {
-        ControlFlow::Continue(())
-    }
-}
-
-pub(crate) struct BreakpointsSet {
-    pub(crate) last_was_break: bool,
-    pub(crate) set: HashSet<usize>,
-    pub(crate) trace: bool,
-}
-
-#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
-pub(crate) enum BreakAction {
-    DumpStateAndContinue,
-    Continue,
-}
-
-impl Breakpoints for BreakpointsSet {
-    type Break = BreakAction;
-    fn check_for_breakpoint(&mut self, pc: usize) -> ControlFlow<Self::Break> {
-        let retval = if self.last_was_break {
-            ControlFlow::Continue(())
-        } else if self.set.contains(&pc) {
-            ControlFlow::Break(BreakAction::DumpStateAndContinue)
-        } else if self.trace {
-            ControlFlow::Break(BreakAction::Continue)
-        } else {
-            ControlFlow::Continue(())
-        };
-        self.last_was_break = retval.is_break();
-        retval
-    }
-}
-
-pub(crate) enum RunResult<Break, Return> {
-    Break(Break),
-    Return(Return),
-}
-
 macro_rules! impl_insns {
     (
         #[insn = $Insn:ident, next_macro = $next_macro:ident, branch_macro = $branch_macro:ident]
@@ -505,14 +402,11 @@ macro_rules! impl_insns {
         }
 
         impl $State {
-            $vis fn $run<B: Breakpoints>(&mut $self, mut breakpoints: B) -> RunResult<B::Break, $run_ret_ty> {
+            $vis fn $run(&mut $self) -> $run_ret_ty {
                 let mut $state = $state_init;
                 $($setup)*
                 let mut insn = $state.insns[$state.pc];
                 let retval = 'main_loop: loop {
-                    if let ControlFlow::Break(b) = breakpoints.check_for_breakpoint($state.pc) {
-                        break RunResult::Break(b);
-                    }
                     macro_rules! $next_macro {
                         () => {
                             $state.pc += 1;
@@ -648,7 +542,6 @@ struct InsnsDebug<'a, BK: InsnsBuildingKind> {
     insn_source_locations: &'a [SourceLocation],
     labels: &'a BK::Labels,
     state_layout: &'a StateLayout<BK>,
-    state: Option<&'a State>,
 }
 
 struct InsnDebug<'a, BK: InsnsBuildingKind> {
@@ -657,7 +550,6 @@ struct InsnDebug<'a, BK: InsnsBuildingKind> {
     insn: &'a Insn,
     labels: Option<&'a Labels>,
     state_layout: &'a StateLayout<BK>,
-    state: Option<&'a State>,
 }
 
 impl<BK: InsnsBuildingKind> fmt::Debug for InsnDebug<'_, BK> {
@@ -673,9 +565,7 @@ impl<BK: InsnsBuildingKind> fmt::Debug for InsnDebug<'_, BK> {
         if let Some(source_location) = self.source_location {
             writeln!(f, "// at: {source_location}")?;
         }
-        write!(f, "{}: ", self.address)?;
-        self.insn
-            .debug_fmt(f, self.labels, Some(self.state_layout), self.state)
+        self.insn.debug_fmt(f, self.labels, Some(self.state_layout))
     }
 }
 
@@ -700,7 +590,6 @@ impl<'a, BK: InsnsBuildingKind> fmt::Debug for InsnsDebug<'a, BK> {
                 insn,
                 labels,
                 state_layout: self.state_layout,
-                state: self.state,
             });
             last_source_location = Some(source_location);
         }
@@ -708,45 +597,8 @@ impl<'a, BK: InsnsBuildingKind> fmt::Debug for InsnsDebug<'a, BK> {
     }
 }
 
-impl<BK: InsnsBuildingKind> Insns<BK> {
-    pub(crate) fn debug_insn_at<'a>(
-        &'a self,
-        address: usize,
-        state: Option<&'a State>,
-    ) -> impl fmt::Debug + 'a {
-        let Self {
-            insns,
-            insn_source_locations,
-            labels,
-            state_layout,
-        } = self;
-        InsnDebug {
-            address,
-            source_location: Some(insn_source_locations[address]),
-            insn: &insns[address],
-            labels: BK::labels(labels),
-            state_layout,
-            state,
-        }
-    }
-}
-
-impl State {
-    pub(crate) fn debug_insn_at(&self, address: usize) -> impl fmt::Debug + '_ {
-        self.insns.debug_insn_at(address, Some(self))
-    }
-}
-
-struct InsnsOfState<'a>(&'a State);
-
-impl fmt::Debug for InsnsOfState<'_> {
+impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.0.insns.debug_fmt(Some(self.0), f)
-    }
-}
-
-impl<BK: InsnsBuildingKind> Insns<BK> {
-    fn debug_fmt(&self, state: Option<&State>, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         let Self {
             insns,
             insn_source_locations,
@@ -762,19 +614,12 @@ impl<BK: InsnsBuildingKind> Insns<BK> {
                     insn_source_locations,
                     labels,
                     state_layout,
-                    state,
                 },
             )
             .finish_non_exhaustive()
     }
 }
 
-impl<BK: InsnsBuildingKind> fmt::Debug for Insns<BK> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.debug_fmt(None, f)
-    }
-}
-
 pub(crate) trait StatePartKind:
     Send + Sync + Ord + Hash + fmt::Debug + 'static + Copy + Default
 {
@@ -789,11 +634,6 @@ pub(crate) trait StatePartKind:
         state_layout: &StateLayout<BK>,
         part_index: StatePartIndex<Self>,
     ) -> Option<&Self::DebugData>;
-    fn debug_fmt_state_value(
-        state: &State,
-        index: StatePartIndex<Self>,
-        f: &mut impl fmt::Write,
-    ) -> fmt::Result;
 }
 
 pub(crate) trait StatePartsValue {
@@ -1146,39 +986,19 @@ macro_rules! make_state_part_kinds {
             }
         }
 
+        #[derive(Debug)]
         pub(crate) struct State {
             pub(crate) insns: Interned<Insns<InsnsBuildingDone>>,
             pub(crate) pc: usize,
-            pub(crate) memory_write_log: Vec<(StatePartIndex<StatePartKindMemories>, usize)>,
             $(pub(crate) $state_field: StatePart<$StateKind>,)*
             $(pub(crate) $type_field: StatePart<$TypeKind>,)*
         }
 
-        impl fmt::Debug for State {
-            fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-                let Self {
-                    insns: _,
-                    pc,
-                    memory_write_log,
-                    $($state_field,)*
-                    $($type_field,)*
-                } = self;
-                f.debug_struct("State")
-                    .field("insns", &InsnsOfState(self))
-                    .field("pc", pc)
-                    .field("memory_write_log", memory_write_log)
-                    $(.field(stringify!($state_field), $state_field))*
-                    $(.field(stringify!($type_field), $type_field))*
-                    .finish()
-            }
-        }
-
         impl State {
             pub(crate) fn new(insns: Interned<Insns<InsnsBuildingDone>>) -> Self {
                 Self {
                     insns,
                     pc: 0,
-                    memory_write_log: Vec::with_capacity(32),
                     $($state_field: StatePart::new(&insns.state_layout.$state_field.layout_data),)*
                     $($type_field: StatePart::new(&insns.state_layout.ty.$type_field.layout_data),)*
                 }
@@ -1189,7 +1009,6 @@ macro_rules! make_state_part_kinds {
                     insns: &self.insns.insns,
                     pc: self.pc,
                     orig_pc: &mut self.pc,
-                    memory_write_log: &mut self.memory_write_log,
                     $($state_field: self.$state_field.borrow(),)*
                     $($type_field: self.$type_field.borrow(),)*
                 }
@@ -1202,7 +1021,6 @@ macro_rules! make_state_part_kinds {
             pub(crate) insns: &'a [Insn],
             pub(crate) orig_pc: &'a mut usize,
             pub(crate) pc: usize,
-            pub(crate) memory_write_log: &'a mut Vec<(StatePartIndex<StatePartKindMemories>, usize)>,
             $(pub(crate) $state_field: BorrowedStatePart<'a, $StateKind>,)*
             $(pub(crate) $type_field: BorrowedStatePart<'a, $TypeKind>,)*
         }
@@ -1376,25 +1194,6 @@ macro_rules! make_state_part_kinds {
     };
 }
 
-#[derive(Copy, Clone, Hash, PartialEq, Eq)]
-pub(crate) struct MemoryData<T: Deref<Target = BitSlice>> {
-    pub(crate) array_type: Array,
-    pub(crate) data: T,
-}
-
-impl<T: Deref<Target = BitSlice>> fmt::Debug for MemoryData<T> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        let Self { array_type, data } = self;
-        f.debug_struct("MemoryData")
-            .field("array_type", array_type)
-            .field(
-                "data",
-                &crate::memory::DebugMemoryData::from_bit_slice(*array_type, data),
-            )
-            .finish()
-    }
-}
-
 make_state_part_kinds! {
     /*#[state, field = small_stack]
     impl StatePartKind for StatePartKindSmallStack {
@@ -1440,14 +1239,11 @@ make_state_part_kinds! {
     impl StatePartKind for StatePartKindMemories {
         const NAME: &'static str = "Memories";
         type DebugData = ();
-        type LayoutData = MemoryData<Interned<BitSlice>>;
-        type State = Box<[MemoryData<BitBox>]>;
-        type BorrowedState<'a> = &'a mut [MemoryData<BitBox>];
+        type LayoutData = Interned<BitSlice>;
+        type State = Box<[BitBox]>;
+        type BorrowedState<'a> = &'a mut [BitBox];
         fn new_state(layout_data: &[Self::LayoutData]) -> Self::State {
-            layout_data.iter().map(|MemoryData { array_type, data }| MemoryData {
-                array_type: *array_type,
-                data: BitBox::from_bitslice(data),
-            }).collect()
+            layout_data.iter().map(|initial_data| BitBox::from_bitslice(initial_data)).collect()
         }
         fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> {
             state
@@ -1458,13 +1254,6 @@ make_state_part_kinds! {
         ) -> Option<&Self::DebugData> {
             state_layout.memories.debug_data.get(part_index.as_usize())
         }
-        fn debug_fmt_state_value(
-            state: &State,
-            index: StatePartIndex<Self>,
-            f: &mut impl fmt::Write,
-        ) -> fmt::Result {
-            write!(f, "{:#?}", &state.memories[index])
-        }
     }
     #[type, field = small_slots]
     impl StatePartKind for StatePartKindSmallSlots {
@@ -1485,15 +1274,6 @@ make_state_part_kinds! {
         ) -> Option<&Self::DebugData> {
             state_layout.ty.small_slots.debug_data.get(part_index.as_usize())
         }
-        fn debug_fmt_state_value(
-            state: &State,
-            index: StatePartIndex<Self>,
-            f: &mut impl fmt::Write,
-        ) -> fmt::Result {
-            let value = state.small_slots[index];
-            write!(f, "{value:#x} {}", value as SmallSInt)?;
-            Ok(())
-        }
     }
     #[type, field = big_slots]
     impl StatePartKind for StatePartKindBigSlots {
@@ -1514,13 +1294,6 @@ make_state_part_kinds! {
         ) -> Option<&Self::DebugData> {
             state_layout.ty.big_slots.debug_data.get(part_index.as_usize())
         }
-        fn debug_fmt_state_value(
-            state: &State,
-            index: StatePartIndex<Self>,
-            f: &mut impl fmt::Write,
-        ) -> fmt::Result {
-            write!(f, "{:#x}", state.big_slots[index])
-        }
     }
 }
 
@@ -1696,32 +1469,37 @@ pub(crate) struct StatePartArrayIndexed<K: StatePartKind> {
 impl<K: StatePartKind> StatePartArrayIndexed<K> {
     pub(crate) fn debug_fmt<BK: InsnsBuildingKind>(
         &self,
-        f: &mut impl fmt::Write,
+        f: &mut fmt::Formatter<'_>,
         before_debug_info_text: &str,
         comment_start: &str,
-        comment_line_start: &str,
         comment_end: &str,
         state_layout: Option<&StateLayout<BK>>,
-        state: Option<&State>,
     ) -> fmt::Result {
-        let Self { base, indexes } = *self;
-        if indexes.is_empty() {
-            base.debug_fmt(
-                f,
-                before_debug_info_text,
-                comment_start,
-                comment_line_start,
-                comment_end,
-                state_layout,
-                state,
-            )
-        } else {
-            base.debug_fmt(f, "", " /* ", "", " */ ", state_layout, state)?;
-            for StatePartArrayIndex { index, len, stride } in indexes {
-                f.write_str("[")?;
-                index.debug_fmt(f, "", " /* ", "", " */ ", state_layout, state)?;
-                write!(f, ", len={len}, stride={}]", stride.value)?;
+        if let Some(state_layout) = state_layout {
+            let Self { base, indexes } = *self;
+            if indexes.is_empty() {
+                base.debug_fmt(
+                    f,
+                    before_debug_info_text,
+                    comment_start,
+                    comment_end,
+                    Some(state_layout),
+                )
+            } else {
+                base.debug_fmt(f, "", " /* ", " */ ", Some(state_layout))?;
+                for StatePartArrayIndex { index, len, stride } in indexes {
+                    f.write_str("[")?;
+                    index.debug_fmt(f, "", " /* ", " */ ", Some(state_layout))?;
+                    write!(f, ", len={len}, stride={}]", stride.value)?;
+                }
+                f.write_str(before_debug_info_text)
             }
+        } else {
+            let Self { base, indexes } = self;
+            f.debug_struct("StatePartArrayIndexed")
+                .field("base", base)
+                .field("indexes", indexes)
+                .finish()?;
             f.write_str(before_debug_info_text)
         }
     }
@@ -1729,7 +1507,7 @@ impl<K: StatePartKind> StatePartArrayIndexed<K> {
 
 impl<K: StatePartKind + fmt::Debug> fmt::Debug for StatePartArrayIndexed<K> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", "", None, None)
+        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", None)
     }
 }
 
@@ -1796,40 +1574,18 @@ impl<K: StatePartKind> StatePartIndex<K> {
     }
     pub(crate) fn debug_fmt<BK: InsnsBuildingKind>(
         &self,
-        f: &mut impl fmt::Write,
+        f: &mut fmt::Formatter<'_>,
         before_debug_info_text: &str,
         comment_start: &str,
-        comment_line_start: &str,
         comment_end: &str,
         state_layout: Option<&StateLayout<BK>>,
-        state: Option<&State>,
     ) -> fmt::Result {
         write!(f, "StatePartIndex<{}>({})", K::NAME, self.value)?;
         f.write_str(before_debug_info_text)?;
-        let debug_data =
-            state_layout.and_then(|state_layout| K::part_debug_data(state_layout, *self));
-        if state.is_some() || debug_data.is_some() {
-            f.write_str(comment_start)?;
-        }
-        let mut f = PrefixLinesWrapper {
-            writer: f,
-            at_beginning_of_line: false,
-            blank_line_prefix: comment_line_start.trim_end(),
-            line_prefix: comment_line_start,
-        };
-        if let Some(state) = state {
-            f.write_str("(")?;
-            K::debug_fmt_state_value(state, *self, &mut f)?;
-            f.write_str(")")?;
-        }
-        if state.is_some() && debug_data.is_some() {
-            f.write_str(" ")?;
-        }
-        if let Some(debug_data) = debug_data {
-            write!(f, "{debug_data:?}")?;
-        }
-        if state.is_some() || debug_data.is_some() {
-            f.writer.write_str(comment_end)?;
+        if let Some(state_layout) = state_layout {
+            if let Some(debug_data) = K::part_debug_data(state_layout, *self) {
+                write!(f, "{comment_start}{debug_data:?}{comment_end}")?;
+            }
         }
         Ok(())
     }
@@ -1837,7 +1593,7 @@ impl<K: StatePartKind> StatePartIndex<K> {
 
 impl<K: StatePartKind> fmt::Debug for StatePartIndex<K> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", "", None, None)
+        self.debug_fmt::<InsnsBuildingDone>(f, "", "", "", None)
     }
 }
 
@@ -1951,7 +1707,7 @@ impl<K: StatePartKind, BK: InsnsBuildingKind> fmt::Debug for StatePartLayout<K,
             layout_data,
             _phantom: _,
         } = self;
-        write!(f, "StatePartLayout<{}>", K::NAME)?;
+        write!(f, "StatePartAllocationLayout<{}>", K::NAME)?;
         let mut debug_struct = f.debug_struct("");
         debug_struct
             .field("len", &debug_data.len())
@@ -2390,7 +2146,6 @@ impl State {
         let Self {
             insns: _,
             pc,
-            memory_write_log: _,
             memories: _,
             small_slots: _,
             big_slots: _,
@@ -2417,18 +2172,6 @@ impl BorrowedState<'_> {
         }
         Some(retval)
     }
-    fn log_memory_write(&mut self, memory: StatePartIndex<StatePartKindMemories>, addr: SmallUInt) {
-        let Ok(addr) = usize::try_from(addr) else {
-            return;
-        };
-        if addr < self.memories[memory].array_type.len() {
-            let log_entry = (memory, addr);
-            if self.memory_write_log.last().copied() == Some(log_entry) {
-                return;
-            }
-            self.memory_write_log.push(log_entry);
-        }
-    }
 }
 
 impl TypeIndexRange {
@@ -2760,18 +2503,6 @@ impl_insns! {
         state.big_slots[dest] = value;
         next!();
     }
-    XorSmallImmediate {
-        #[kind = Output]
-        dest: StatePartIndex<StatePartKindSmallSlots>,
-        #[kind = Input]
-        lhs: StatePartIndex<StatePartKindSmallSlots>,
-        #[kind = Immediate]
-        rhs: SmallUInt,
-    } => {
-        let value = state.small_slots[lhs] ^ rhs;
-        state.small_slots[dest] = value;
-        next!();
-    }
     NotS {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
@@ -2794,6 +2525,16 @@ impl_insns! {
         state.big_slots[dest] = value;
         next!();
     }
+    NotSmall {
+        #[kind = Output]
+        dest: StatePartIndex<StatePartKindSmallSlots>,
+        #[kind = Input]
+        src: StatePartIndex<StatePartKindSmallSlots>,
+    } => {
+        let value = !state.small_slots[src];
+        state.small_slots[dest] = value;
+        next!();
+    }
     Neg {
         #[kind = Output]
         dest: StatePartIndex<StatePartKindBigSlots>,
@@ -3120,7 +2861,7 @@ impl_insns! {
         width: usize,
     } => {
         let addr = state.small_slots[addr];
-        state.big_slots[dest] = memory_read_big::<UInt>(&mut state.memories[memory].data, addr, stride, start, width).unwrap_or_default();
+        state.big_slots[dest] = memory_read_big::<UInt>(&mut state.memories[memory], addr, stride, start, width).unwrap_or_default();
         next!();
     }
     MemoryReadSInt {
@@ -3138,7 +2879,7 @@ impl_insns! {
         width: usize,
     } => {
         let addr = state.small_slots[addr];
-        state.big_slots[dest] = memory_read_big::<SInt>(&mut state.memories[memory].data, addr, stride, start, width).unwrap_or_default();
+        state.big_slots[dest] = memory_read_big::<SInt>(&mut state.memories[memory], addr, stride, start, width).unwrap_or_default();
         next!();
     }
     MemoryWriteUInt {
@@ -3156,8 +2897,7 @@ impl_insns! {
         width: usize,
     } => {
         let addr = state.small_slots[addr];
-        memory_write_big::<UInt>(&mut state.memories[memory].data, addr, stride, start, width, &mut state.big_slots[value]);
-        state.log_memory_write(memory, addr);
+        memory_write_big::<UInt>(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]);
         next!();
     }
     MemoryWriteSInt {
@@ -3175,11 +2915,10 @@ impl_insns! {
         width: usize,
     } => {
         let addr = state.small_slots[addr];
-        memory_write_big::<SInt>(&mut state.memories[memory].data, addr, stride, start, width, &mut state.big_slots[value]);
-        state.log_memory_write(memory, addr);
+        memory_write_big::<SInt>(&mut state.memories[memory], addr, stride, start, width, &mut state.big_slots[value]);
         next!();
     }
     Return => {
-        break RunResult::Return(());
+        break;
     }
 }
diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs
index b8248e3..0779b5c 100644
--- a/crates/fayalite/src/sim/vcd.rs
+++ b/crates/fayalite/src/sim/vcd.rs
@@ -9,14 +9,13 @@ use crate::{
         time::{SimDuration, SimInstant},
         TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl,
         TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance,
-        TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation, TraceModule,
-        TraceModuleIO, TraceReg, TraceSInt, TraceScalar, TraceScalarId, TraceScope, TraceSyncReset,
-        TraceUInt, TraceWire, TraceWriter, TraceWriterDecls,
+        TraceMemPort, TraceModule, TraceModuleIO, TraceReg, TraceSInt, TraceScalar, TraceScalarId,
+        TraceScope, TraceSyncReset, TraceUInt, TraceWire, TraceWriter, TraceWriterDecls,
     },
 };
-use bitvec::{order::Lsb0, slice::BitSlice};
+use bitvec::slice::BitSlice;
 use std::{
-    fmt,
+    fmt::{self, Display},
     io::{self, Write},
     mem,
 };
@@ -113,20 +112,20 @@ macro_rules! trait_arg {
     (
         trait $Arg:ident {
             $(
-                fn $fn:ident(&mut self) -> $ty:ty;
+                fn $fn:ident(self) -> $ty:ty;
             )*
         }
     ) => {
         trait $Arg: Sized {
-            $(fn $fn(&mut self) -> $ty {
+            $(fn $fn(self) -> $ty {
                 unreachable!()
             })*
         }
 
         $(
             impl $Arg for $ty {
-                fn $fn(&mut self) -> $ty {
-                    self.reborrow()
+                fn $fn(self) -> $ty {
+                    self
                 }
             }
         )*
@@ -135,52 +134,21 @@ macro_rules! trait_arg {
 
 trait_arg! {
     trait Arg {
-        fn module(&mut self) -> ArgModule<'_>;
-        fn module_body(&mut self) -> ArgModuleBody<'_>;
-        fn in_type(&mut self) -> ArgInType<'_>;
+        fn module(self) -> ArgModule;
+        fn module_body(self) -> ArgModuleBody;
+        fn in_type(self) -> ArgInType;
     }
 }
 
-struct ArgModule<'a> {
-    properties: &'a mut VcdWriterProperties,
-}
+struct ArgModule {}
 
-impl<'a> ArgModule<'a> {
-    fn reborrow(&mut self) -> ArgModule<'_> {
-        ArgModule {
-            properties: self.properties,
-        }
-    }
-}
+struct ArgModuleBody {}
 
-struct ArgModuleBody<'a> {
-    properties: &'a mut VcdWriterProperties,
-}
-
-impl<'a> ArgModuleBody<'a> {
-    fn reborrow(&mut self) -> ArgModuleBody<'_> {
-        ArgModuleBody {
-            properties: self.properties,
-        }
-    }
-}
-
-struct ArgInType<'a> {
+#[derive(Clone, Copy)]
+struct ArgInType {
     source_var_type: &'static str,
     sink_var_type: &'static str,
     duplex_var_type: &'static str,
-    properties: &'a mut VcdWriterProperties,
-}
-
-impl<'a> ArgInType<'a> {
-    fn reborrow(&mut self) -> ArgInType<'_> {
-        ArgInType {
-            source_var_type: self.source_var_type,
-            sink_var_type: self.sink_var_type,
-            duplex_var_type: self.duplex_var_type,
-            properties: self.properties,
-        }
-    }
 }
 
 trait WriteTrace: Copy {
@@ -211,10 +179,11 @@ impl WriteTrace for TraceScalar {
     }
 }
 
-fn write_vcd_id<W: io::Write>(writer: &mut W, mut id: usize) -> io::Result<()> {
+fn write_scalar_id<W: io::Write>(writer: &mut W, id: TraceScalarId) -> io::Result<()> {
     let min_char = b'!';
     let max_char = b'~';
     let base = (max_char - min_char + 1) as usize;
+    let mut id = id.as_usize();
     loop {
         let digit = (id % base) as u8 + min_char;
         id /= base;
@@ -226,7 +195,7 @@ fn write_vcd_id<W: io::Write>(writer: &mut W, mut id: usize) -> io::Result<()> {
     Ok(())
 }
 
-fn write_escaped<W: io::Write>(writer: &mut W, value: impl fmt::Display) -> io::Result<()> {
+fn write_escaped<W: io::Write>(writer: &mut W, value: impl Display) -> io::Result<()> {
     // escaping rules from function GTKWave uses to decode VCD strings:
     // https://github.com/gtkwave/gtkwave/blob/491f24d7e8619cfc1fcc65704ee5c967d1083c18/lib/libfst/fstapi.c#L7090
     struct Wrapper<W>(W);
@@ -278,47 +247,14 @@ fn is_unescaped_verilog_identifier(ident: &str) -> bool {
 }
 
 fn write_vcd_var<W: io::Write>(
-    properties: &mut VcdWriterProperties,
-    memory_element_part_body: MemoryElementPartBody,
     writer: &mut W,
     var_type: &str,
     size: usize,
-    location: TraceLocation,
+    id: TraceScalarId,
     name: &str,
 ) -> io::Result<()> {
-    let id = match location {
-        TraceLocation::Scalar(id) => id.as_usize(),
-        TraceLocation::Memory(TraceMemoryLocation {
-            id,
-            depth,
-            stride: _,
-            start,
-            len,
-        }) => {
-            let MemoryProperties {
-                element_parts,
-                element_part_index,
-                element_index,
-            } = &mut properties.memory_properties[id.as_usize()];
-            let first_id;
-            if let Some(element_part) = element_parts.get(*element_part_index) {
-                first_id = element_part.first_id;
-            } else {
-                first_id = properties.next_scalar_id;
-                properties.next_scalar_id += depth;
-                element_parts.push(MemoryElementPart {
-                    first_id,
-                    start,
-                    len,
-                    body: memory_element_part_body,
-                });
-            }
-            *element_part_index += 1;
-            first_id + *element_index
-        }
-    };
     write!(writer, "$var {var_type} {size} ")?;
-    write_vcd_id(writer, id)?;
+    write_scalar_id(writer, id)?;
     writer.write_all(b" ")?;
     if !is_unescaped_verilog_identifier(name) {
         writer.write_all(b"\\")?;
@@ -328,49 +264,31 @@ fn write_vcd_var<W: io::Write>(
 }
 
 impl WriteTrace for TraceUInt {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
         let ArgInType {
             source_var_type,
             sink_var_type,
             duplex_var_type,
-            properties,
         } = arg.in_type();
-        let Self {
-            location,
-            name,
-            ty,
-            flow,
-        } = self;
-        let mut var_type = match flow {
+        let Self { id, name, ty, flow } = self;
+        let var_type = match flow {
             Flow::Source => source_var_type,
             Flow::Sink => sink_var_type,
             Flow::Duplex => duplex_var_type,
         };
         if ty.width() == 0 {
-            var_type = "string";
+            write_vcd_var(writer, "string", ty.width(), id, &name)
+        } else {
+            write_vcd_var(writer, var_type, ty.width(), id, &name)
         }
-        write_vcd_var(
-            properties,
-            MemoryElementPartBody::Scalar,
-            writer,
-            var_type,
-            ty.width(),
-            location,
-            &name,
-        )
     }
 }
 
 impl WriteTrace for TraceSInt {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            ty,
-            flow,
-        } = self;
+        let Self { id, name, ty, flow } = self;
         TraceUInt {
-            location,
+            id,
             name,
             ty: UInt::new_dyn(ty.width()),
             flow,
@@ -381,13 +299,9 @@ impl WriteTrace for TraceSInt {
 
 impl WriteTrace for TraceBool {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            flow,
-        } = self;
+        let Self { id, name, flow } = self;
         TraceUInt {
-            location,
+            id,
             name,
             flow,
             ty: UInt::new_dyn(1),
@@ -398,93 +312,46 @@ impl WriteTrace for TraceBool {
 
 impl WriteTrace for TraceFieldlessEnum {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            ty,
-            flow,
-        } = self;
-        TraceEnumDiscriminant {
-            location,
-            name,
-            ty,
-            flow,
-        }
-        .write_trace(writer, arg)
+        let Self { id, name, ty, flow } = self;
+        TraceEnumDiscriminant { id, name, ty, flow }.write_trace(writer, arg)
     }
 }
 
 impl WriteTrace for TraceEnumDiscriminant {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
         let ArgInType {
             source_var_type: _,
             sink_var_type: _,
             duplex_var_type: _,
-            properties,
         } = arg.in_type();
         let Self {
-            location,
+            id,
             name,
-            ty,
+            ty: _,
             flow: _,
         } = self;
-        write_vcd_var(
-            properties,
-            MemoryElementPartBody::EnumDiscriminant { ty },
-            writer,
-            "string",
-            1,
-            location,
-            &name,
-        )
+        write_vcd_var(writer, "string", 1, id, &name)
     }
 }
 
 impl WriteTrace for TraceClock {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            flow,
-        } = self;
-        TraceBool {
-            location,
-            name,
-            flow,
-        }
-        .write_trace(writer, arg)
+        let Self { id, name, flow } = self;
+        TraceBool { id, name, flow }.write_trace(writer, arg)
     }
 }
 
 impl WriteTrace for TraceSyncReset {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            flow,
-        } = self;
-        TraceBool {
-            location,
-            name,
-            flow,
-        }
-        .write_trace(writer, arg)
+        let Self { id, name, flow } = self;
+        TraceBool { id, name, flow }.write_trace(writer, arg)
     }
 }
 
 impl WriteTrace for TraceAsyncReset {
     fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
-        let Self {
-            location,
-            name,
-            flow,
-        } = self;
-        TraceBool {
-            location,
-            name,
-            flow,
-        }
-        .write_trace(writer, arg)
+        let Self { id, name, flow } = self;
+        TraceBool { id, name, flow }.write_trace(writer, arg)
     }
 }
 
@@ -493,7 +360,6 @@ impl WriteTrace for TraceScope {
         match self {
             Self::Module(v) => v.write_trace(writer, arg),
             Self::Instance(v) => v.write_trace(writer, arg),
-            Self::Mem(v) => v.write_trace(writer, arg),
             Self::MemPort(v) => v.write_trace(writer, arg),
             Self::Wire(v) => v.write_trace(writer, arg),
             Self::Reg(v) => v.write_trace(writer, arg),
@@ -506,12 +372,12 @@ impl WriteTrace for TraceScope {
 }
 
 impl WriteTrace for TraceModule {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModule { properties } = arg.module();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let ArgModule {} = arg.module();
         let Self { name, children } = self;
         write_vcd_scope(writer, "module", &name, |writer| {
             for child in children {
-                child.write_trace(writer, ArgModuleBody { properties })?;
+                child.write_trace(writer, ArgModuleBody {})?;
             }
             Ok(())
         })
@@ -519,8 +385,8 @@ impl WriteTrace for TraceModule {
 }
 
 impl WriteTrace for TraceInstance {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let ArgModuleBody {} = arg.module_body();
         let Self {
             name: _,
             instance_io,
@@ -533,74 +399,21 @@ impl WriteTrace for TraceInstance {
                 source_var_type: "wire",
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
-                properties,
             },
         )?;
-        module.write_trace(writer, ArgModule { properties })
-    }
-}
-
-impl WriteTrace for TraceMem {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
-        let Self {
-            id,
-            name,
-            stride: _,
-            element_type,
-            ports,
-            array_type,
-        } = self;
-        write_vcd_scope(writer, "struct", &*name, |writer| {
-            write_vcd_scope(writer, "struct", "contents", |writer| {
-                for element_index in 0..array_type.len() {
-                    write_vcd_scope(writer, "struct", &format!("[{element_index}]"), |writer| {
-                        properties.memory_properties[id.as_usize()].element_index = element_index;
-                        properties.memory_properties[id.as_usize()].element_part_index = 0;
-                        element_type.write_trace(
-                            writer,
-                            ArgInType {
-                                source_var_type: "reg",
-                                sink_var_type: "reg",
-                                duplex_var_type: "reg",
-                                properties,
-                            },
-                        )
-                    })?;
-                }
-                Ok(())
-            })?;
-            for port in ports {
-                port.write_trace(writer, ArgModuleBody { properties })?;
-            }
-            Ok(())
-        })
+        module.write_trace(writer, ArgModule {})
     }
 }
 
 impl WriteTrace for TraceMemPort {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
-        let Self {
-            name: _,
-            bundle,
-            ty: _,
-        } = self;
-        bundle.write_trace(
-            writer,
-            ArgInType {
-                source_var_type: "wire",
-                sink_var_type: "wire",
-                duplex_var_type: "wire",
-                properties,
-            },
-        )
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        todo!()
     }
 }
 
 impl WriteTrace for TraceWire {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let ArgModuleBody {} = arg.module_body();
         let Self {
             name: _,
             child,
@@ -612,15 +425,14 @@ impl WriteTrace for TraceWire {
                 source_var_type: "wire",
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
-                properties,
             },
         )
     }
 }
 
 impl WriteTrace for TraceReg {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let ArgModuleBody {} = arg.module_body();
         let Self {
             name: _,
             child,
@@ -632,15 +444,14 @@ impl WriteTrace for TraceReg {
                 source_var_type: "reg",
                 sink_var_type: "reg",
                 duplex_var_type: "reg",
-                properties,
             },
         )
     }
 }
 
 impl WriteTrace for TraceModuleIO {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let ArgModuleBody { properties } = arg.module_body();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let ArgModuleBody {} = arg.module_body();
         let Self {
             name: _,
             child,
@@ -653,15 +464,14 @@ impl WriteTrace for TraceModuleIO {
                 source_var_type: "wire",
                 sink_var_type: "wire",
                 duplex_var_type: "wire",
-                properties,
             },
         )
     }
 }
 
 impl WriteTrace for TraceBundle {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let mut arg = arg.in_type();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let arg = arg.in_type();
         let Self {
             name,
             fields,
@@ -670,7 +480,7 @@ impl WriteTrace for TraceBundle {
         } = self;
         write_vcd_scope(writer, "struct", &name, |writer| {
             for field in fields {
-                field.write_trace(writer, arg.reborrow())?;
+                field.write_trace(writer, arg)?;
             }
             Ok(())
         })
@@ -678,8 +488,8 @@ impl WriteTrace for TraceBundle {
 }
 
 impl WriteTrace for TraceArray {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let mut arg = arg.in_type();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let arg = arg.in_type();
         let Self {
             name,
             elements,
@@ -688,7 +498,7 @@ impl WriteTrace for TraceArray {
         } = self;
         write_vcd_scope(writer, "struct", &name, |writer| {
             for element in elements {
-                element.write_trace(writer, arg.reborrow())?;
+                element.write_trace(writer, arg)?;
             }
             Ok(())
         })
@@ -696,8 +506,8 @@ impl WriteTrace for TraceArray {
 }
 
 impl WriteTrace for TraceEnumWithFields {
-    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, mut arg: A) -> io::Result<()> {
-        let mut arg = arg.in_type();
+    fn write_trace<W: io::Write, A: Arg>(self, writer: &mut W, arg: A) -> io::Result<()> {
+        let arg = arg.in_type();
         let Self {
             name,
             discriminant,
@@ -706,9 +516,9 @@ impl WriteTrace for TraceEnumWithFields {
             flow: _,
         } = self;
         write_vcd_scope(writer, "struct", &name, |writer| {
-            discriminant.write_trace(writer, arg.reborrow())?;
+            discriminant.write_trace(writer, arg)?;
             for field in non_empty_fields {
-                field.write_trace(writer, arg.reborrow())?;
+                field.write_trace(writer, arg)?;
             }
             Ok(())
         })
@@ -719,184 +529,76 @@ impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
     type Error = io::Error;
     type TraceWriter = VcdWriter<W>;
 
-    fn write_decls(
-        self,
-        module: TraceModule,
-        trace_scalar_id_count: usize,
-        trace_memory_id_count: usize,
-    ) -> Result<Self::TraceWriter, Self::Error> {
+    fn write_decls(self, module: TraceModule) -> Result<Self::TraceWriter, Self::Error> {
         let Self {
             mut writer,
             timescale,
         } = self;
         writeln!(writer, "$timescale {} $end", vcd_timescale(timescale))?;
-        let mut properties = VcdWriterProperties {
-            next_scalar_id: trace_scalar_id_count,
-            memory_properties: (0..trace_memory_id_count)
-                .map(|_| MemoryProperties {
-                    element_parts: Vec::with_capacity(8),
-                    element_part_index: 0,
-                    element_index: 0,
-                })
-                .collect(),
-        };
-        module.write_trace(
-            &mut writer,
-            ArgModule {
-                properties: &mut properties,
-            },
-        )?;
+        module.write_trace(&mut writer, ArgModule {})?;
         writeln!(writer, "$enddefinitions $end")?;
         writeln!(writer, "$dumpvars")?;
         Ok(VcdWriter {
             writer,
             finished_init: false,
             timescale,
-            properties,
         })
     }
 }
 
-enum MemoryElementPartBody {
-    Scalar,
-    EnumDiscriminant { ty: Enum },
-}
-
-struct MemoryElementPart {
-    first_id: usize,
-    start: usize,
-    len: usize,
-    body: MemoryElementPartBody,
-}
-
-struct MemoryProperties {
-    element_parts: Vec<MemoryElementPart>,
-    element_part_index: usize,
-    element_index: usize,
-}
-
-struct VcdWriterProperties {
-    next_scalar_id: usize,
-    memory_properties: Box<[MemoryProperties]>,
-}
-
 pub struct VcdWriter<W: io::Write + 'static> {
     writer: W,
     finished_init: bool,
     timescale: SimDuration,
-    properties: VcdWriterProperties,
 }
 
 impl<W: io::Write + 'static> VcdWriter<W> {
     pub fn timescale(&self) -> SimDuration {
         self.timescale
     }
-}
-
-fn write_string_value_change(
-    writer: &mut impl io::Write,
-    value: impl fmt::Display,
-    id: usize,
-) -> io::Result<()> {
-    writer.write_all(b"s")?;
-    write_escaped(writer, value)?;
-    writer.write_all(b" ")?;
-    write_vcd_id(writer, id)?;
-    writer.write_all(b"\n")
-}
-
-fn write_bits_value_change(
-    writer: &mut impl io::Write,
-    value: &BitSlice,
-    id: usize,
-) -> io::Result<()> {
-    match value.len() {
-        0 => writer.write_all(b"s0 ")?,
-        1 => writer.write_all(if value[0] { b"1" } else { b"0" })?,
-        _ => {
-            writer.write_all(b"b")?;
-            let mut any_ones = false;
-            for bit in value.iter().rev() {
-                if *bit {
-                    any_ones = true;
-                    writer.write_all(b"1")?;
-                } else if any_ones {
-                    writer.write_all(b"0")?;
-                }
-            }
-            if !any_ones {
-                writer.write_all(b"0")?;
-            }
-            writer.write_all(b" ")?;
-        }
+    fn write_string_value_change(
+        &mut self,
+        value: impl Display,
+        id: TraceScalarId,
+    ) -> io::Result<()> {
+        self.writer.write_all(b"s")?;
+        write_escaped(&mut self.writer, value)?;
+        self.writer.write_all(b" ")?;
+        write_scalar_id(&mut self.writer, id)?;
+        self.writer.write_all(b"\n")
     }
-    write_vcd_id(writer, id)?;
-    writer.write_all(b"\n")
-}
-
-fn write_enum_discriminant_value_change(
-    writer: &mut impl io::Write,
-    variant_index: usize,
-    ty: Enum,
-    id: usize,
-) -> io::Result<()> {
-    write_string_value_change(
-        writer,
-        format_args!(
-            "{} ({variant_index})",
-            ty.variants()
-                .get(variant_index)
-                .map(|v| &*v.name)
-                .unwrap_or("<invalid>"),
-        ),
-        id,
-    )
 }
 
 impl<W: io::Write> TraceWriter for VcdWriter<W> {
     type Error = io::Error;
 
-    fn set_memory_element(
-        &mut self,
-        memory: TraceMemoryId,
-        element_index: usize,
-        element_data: &BitSlice,
-    ) -> Result<(), Self::Error> {
-        for &MemoryElementPart {
-            first_id,
-            start,
-            len,
-            ref body,
-        } in &self.properties.memory_properties[memory.as_usize()].element_parts
-        {
-            match body {
-                MemoryElementPartBody::Scalar => write_bits_value_change(
-                    &mut self.writer,
-                    &element_data[start..start + len],
-                    first_id + element_index,
-                )?,
-                MemoryElementPartBody::EnumDiscriminant { ty } => {
-                    let mut variant_index = 0;
-                    BitSlice::<usize, Lsb0>::from_element_mut(&mut variant_index)[..len]
-                        .clone_from_bitslice(&element_data[start..start + len]);
-                    write_enum_discriminant_value_change(
-                        &mut self.writer,
-                        variant_index,
-                        *ty,
-                        first_id + element_index,
-                    )?
+    fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
+        match value.len() {
+            0 => self.writer.write_all(b"s0 ")?,
+            1 => self.writer.write_all(if value[0] { b"1" } else { b"0" })?,
+            _ => {
+                self.writer.write_all(b"b")?;
+                let mut any_ones = false;
+                for bit in value.iter().rev() {
+                    if *bit {
+                        any_ones = true;
+                        self.writer.write_all(b"1")?;
+                    } else if any_ones {
+                        self.writer.write_all(b"0")?;
+                    }
                 }
+                if !any_ones {
+                    self.writer.write_all(b"0")?;
+                }
+                self.writer.write_all(b" ")?;
             }
         }
-        Ok(())
-    }
-
-    fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
-        write_bits_value_change(&mut self.writer, value, id.as_usize())
+        write_scalar_id(&mut self.writer, id)?;
+        self.writer.write_all(b"\n")
     }
 
     fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
-        write_bits_value_change(&mut self.writer, value, id.as_usize())
+        self.set_signal_uint(id, value)
     }
 
     fn finish_init(&mut self) -> Result<(), Self::Error> {
@@ -928,7 +630,16 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
         variant_index: usize,
         ty: Enum,
     ) -> Result<(), Self::Error> {
-        write_enum_discriminant_value_change(&mut self.writer, variant_index, ty, id.as_usize())
+        self.write_string_value_change(
+            format_args!(
+                "{} ({variant_index})",
+                ty.variants()
+                    .get(variant_index)
+                    .map(|v| &*v.name)
+                    .unwrap_or("<invalid>"),
+            ),
+            id,
+        )
     }
 }
 
@@ -938,7 +649,6 @@ impl<W: io::Write> fmt::Debug for VcdWriter<W> {
             writer: _,
             finished_init,
             timescale,
-            properties: _,
         } = self;
         f.debug_struct("VcdWriter")
             .field("finished_init", finished_init)
diff --git a/crates/fayalite/tests/formal.rs b/crates/fayalite/tests/formal.rs
index 65264dc..46b8292 100644
--- a/crates/fayalite/tests/formal.rs
+++ b/crates/fayalite/tests/formal.rs
@@ -7,13 +7,12 @@ use fayalite::{
     clock::{Clock, ClockDomain},
     expr::{CastTo, HdlPartialEq},
     firrtl::ExportOptions,
-    formal::{any_const, any_seq, formal_reset, hdl_assert, hdl_assume},
-    hdl, hdl_module,
-    int::{Bool, DynSize, Size, UInt, UIntType},
-    module::{connect, connect_any, instance, memory, reg_builder, wire},
+    formal::{any_seq, formal_reset, hdl_assert, hdl_assume},
+    hdl_module,
+    int::{Bool, UInt},
+    module::{connect, connect_any, reg_builder, wire},
     reset::ToReset,
     testing::assert_formal,
-    ty::StaticType,
 };
 
 /// Test hidden state
@@ -132,164 +131,3 @@ mod hidden_state {
         );
     }
 }
-
-/// Formal verification of designs containing memories
-///
-/// There is a trick for memories, described in the [Zipcpu blog].
-/// First, select a fixed but arbitrary memory address, monitoring all reads
-/// and writes made to it. Then, assert that anything read from that location
-/// matches the last stored value.
-///
-/// A difficulty for induction is that the memory represents [hidden_state]. A
-/// solution is to include an additional read port to the memory and assert
-/// that the memory location effectively contains the last stored value.
-/// This additional debug port is present only to assist the proof and is
-/// unused (optimized out) in actual use.
-///
-/// [Zipcpu blog]: <https://zipcpu.com/zipcpu/2018/07/13/memories.html>
-mod memory {
-    use super::*;
-
-    /// Test a simple 8-bit SRAM model
-    #[test]
-    fn test_sram() {
-        #[hdl]
-        struct WritePort<AddrWidth: Size> {
-            addr: UIntType<AddrWidth>,
-            data: UInt<8>,
-            en: Bool,
-        }
-        #[hdl]
-        struct ReadPort<AddrWidth: Size> {
-            addr: UIntType<AddrWidth>,
-            #[hdl(flip)]
-            data: UInt<8>,
-        }
-        /// This debug port is only meant to assist the proof.
-        /// For normal use in a design, a wrapper could be provided,
-        /// omitting this port.
-        /// The implementation is forbidden to use any information
-        /// provided on this port in its internal workings.
-        #[hdl]
-        struct DebugPort<AddrWidth: Size> {
-            selected: UIntType<AddrWidth>,
-            stored: UInt<8>,
-            wrote: Bool,
-        }
-        /// simple 1R1W SRAM model (one asynchronous read port and one
-        /// independent write port) with `n`-bit address width
-        #[hdl_module]
-        fn example_sram(n: usize) {
-            #[hdl]
-            let wr: WritePort<DynSize> = m.input(WritePort[n]);
-            #[hdl]
-            let rd: ReadPort<DynSize> = m.input(ReadPort[n]);
-            #[hdl]
-            let cd: ClockDomain = m.input();
-
-            // declare and connect the backing memory
-            #[hdl]
-            let mut mem = memory();
-            mem.depth(1 << n);
-            let read_port = mem.new_read_port();
-            let write_port = mem.new_write_port();
-            connect(write_port.clk, cd.clk);
-            connect(write_port.addr, wr.addr);
-            connect(write_port.en, wr.en);
-            connect(write_port.data, wr.data);
-            connect(write_port.mask, true);
-            connect(read_port.clk, cd.clk);
-            connect(read_port.addr, rd.addr);
-            connect(read_port.en, true);
-            connect(rd.data, read_port.data);
-
-            // To assist with induction, ensure that the chosen memory location
-            // really contains, always, the last value written to it.
-            #[hdl]
-            let dbg: DebugPort<DynSize> = m.input(DebugPort[n]);
-            let debug_port = mem.new_read_port();
-            connect(debug_port.en, true);
-            connect(debug_port.clk, cd.clk);
-            connect(debug_port.addr, dbg.selected);
-            #[hdl]
-            if dbg.wrote {
-                hdl_assert(cd.clk, debug_port.data.cmp_eq(dbg.stored), "");
-                // Try commenting out the assert above, induction will fail.
-                // Opening the trace, it can be seen that the memory contents
-                // and the stored value don't match, which is an unreachable
-                // state. By asserting the above, it will become invalid
-                // as well, so induction will skip this kind of situation.
-            }
-        }
-
-        /// formal verification of the SRAM module, parametrized by the
-        /// address bit-width
-        #[hdl_module]
-        fn test_module(n: usize) {
-            #[hdl]
-            let clk: Clock = m.input();
-            let cd = #[hdl]
-            ClockDomain {
-                clk,
-                rst: formal_reset().to_reset(),
-            };
-
-            // instantiate the SRAM model, connecting its inputs to
-            // a random sequence
-            #[hdl]
-            let rd: ReadPort<DynSize> = wire(ReadPort[n]);
-            connect(rd.addr, any_seq(UInt[n]));
-            #[hdl]
-            let wr: WritePort<DynSize> = wire(WritePort[n]);
-            connect(wr.addr, any_seq(UInt[n]));
-            connect(wr.data, any_seq(UInt::<8>::TYPE));
-            connect(wr.en, any_seq(Bool));
-            #[hdl]
-            let dut = instance(example_sram(n));
-            connect(dut.cd, cd);
-            connect(dut.rd, rd);
-            connect(dut.wr, wr);
-
-            // select a fixed but arbitrary test address
-            #[hdl]
-            let selected = wire(UInt[n]);
-            connect(selected, any_const(UInt[n]));
-            // store the last value written to that address
-            #[hdl]
-            let stored: UInt<8> = reg_builder().clock_domain(cd).reset(0u8);
-            // since memories are not initialized, track whether we wrote to the
-            // memory at least once
-            #[hdl]
-            let wrote: Bool = reg_builder().clock_domain(cd).reset(false);
-            // on a write, capture the last written value
-            #[hdl]
-            if wr.en & wr.addr.cmp_eq(selected) {
-                connect(stored, wr.data);
-                connect(wrote, true);
-            }
-            // on a read, assert that the read value is the same which was stored
-            #[hdl]
-            if rd.addr.cmp_eq(selected) & wrote {
-                hdl_assert(clk, rd.data.cmp_eq(stored), "");
-            }
-
-            // to assist induction, pass our state to the underlying instance
-            let dbg = #[hdl]
-            DebugPort {
-                selected,
-                stored,
-                wrote,
-            };
-            connect(dut.dbg, dbg);
-        }
-
-        assert_formal(
-            "sram",
-            test_module(8),
-            FormalMode::Prove,
-            2,
-            None,
-            ExportOptions::default(),
-        );
-    }
-}
diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs
index a249235..a8b23f2 100644
--- a/crates/fayalite/tests/sim.rs
+++ b/crates/fayalite/tests/sim.rs
@@ -1,15 +1,12 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
-
 use fayalite::{
     int::UIntValue,
     prelude::*,
     reset::ResetType,
-    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation, ToSimValue},
-    ty::StaticType,
+    sim::{time::SimDuration, vcd::VcdWriterDecls, Simulation},
     util::RcWriter,
 };
-use std::num::NonZeroUsize;
 
 #[hdl_module(outline_generated)]
 pub fn connect_const() {
@@ -255,14 +252,8 @@ fn test_shift_register() {
     let mut sim = Simulation::new(shift_register());
     let mut writer = RcWriter::default();
     sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
-    sim.write(
-        sim.io().cd,
-        #[hdl]
-        ClockDomain {
-            clk: false.to_clock(),
-            rst: true.to_sync_reset(),
-        },
-    );
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
     sim.write_bool(sim.io().d, false);
     sim.advance_time(SimDuration::from_micros(1));
     sim.write_clock(sim.io().cd.clk, true);
@@ -278,7 +269,7 @@ fn test_shift_register() {
                 assert_eq!(
                     *expected,
                     sim.read_bool(sim.io().q),
-                    "vcd:\n{}\ncycle: {cycle}",
+                    "cycle: {cycle}\nvcd:\n{}",
                     String::from_utf8(writer.take()).unwrap(),
                 );
             }
@@ -316,8 +307,6 @@ pub fn enums() {
     let which_out: UInt<2> = m.output();
     #[hdl]
     let data_out: UInt<4> = m.output();
-    #[hdl]
-    let b_out: HdlOption<(UInt<1>, Bool)> = m.output();
 
     #[hdl]
     struct MyStruct<T> {
@@ -357,8 +346,6 @@ pub fn enums() {
         }
     }
 
-    connect(b_out, HdlNone());
-
     #[hdl]
     match the_reg {
         MyEnum::A => {
@@ -368,7 +355,6 @@ pub fn enums() {
         MyEnum::B(v) => {
             connect(which_out, 1_hdl_u2);
             connect_any(data_out, v.0 | (v.1.cast_to_static::<UInt<1>>() << 1));
-            connect(b_out, HdlSome(v));
         }
         MyEnum::C(v) => {
             connect(which_out, 2_hdl_u2);
@@ -394,33 +380,13 @@ fn test_enums() {
     sim.advance_time(SimDuration::from_nanos(100));
     sim.write_reset(sim.io().cd.rst, false);
     sim.advance_time(SimDuration::from_nanos(900));
-    type BOutTy = HdlOption<(UInt<1>, Bool)>;
-    #[derive(Debug)]
+    #[derive(Debug, PartialEq, Eq)]
     struct IO {
         en: bool,
         which_in: u8,
         data_in: u8,
         which_out: u8,
         data_out: u8,
-        b_out: Expr<BOutTy>,
-    }
-    impl PartialEq for IO {
-        fn eq(&self, other: &Self) -> bool {
-            let Self {
-                en,
-                which_in,
-                data_in,
-                which_out,
-                data_out,
-                b_out,
-            } = *self;
-            en == other.en
-                && which_in == other.which_in
-                && data_in == other.data_in
-                && which_out == other.which_out
-                && data_out == other.data_out
-                && b_out.to_sim_value(BOutTy::TYPE) == other.b_out.to_sim_value(BOutTy::TYPE)
-        }
     }
     let io_cycles = [
         IO {
@@ -429,7 +395,6 @@ fn test_enums() {
             data_in: 0,
             which_out: 0,
             data_out: 0,
-            b_out: HdlNone(),
         },
         IO {
             en: true,
@@ -437,7 +402,6 @@ fn test_enums() {
             data_in: 0,
             which_out: 0,
             data_out: 0,
-            b_out: HdlNone(),
         },
         IO {
             en: false,
@@ -445,7 +409,6 @@ fn test_enums() {
             data_in: 0,
             which_out: 1,
             data_out: 0,
-            b_out: HdlSome((0_hdl_u1, false)),
         },
         IO {
             en: true,
@@ -453,7 +416,6 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 1,
             data_out: 0,
-            b_out: HdlSome((0_hdl_u1, false)),
         },
         IO {
             en: true,
@@ -461,7 +423,6 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 1,
             data_out: 0x3,
-            b_out: HdlSome((1_hdl_u1, true)),
         },
         IO {
             en: true,
@@ -469,7 +430,6 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 1,
             data_out: 0x3,
-            b_out: HdlSome((1_hdl_u1, true)),
         },
         IO {
             en: true,
@@ -477,7 +437,6 @@ fn test_enums() {
             data_in: 0xF,
             which_out: 2,
             data_out: 0xF,
-            b_out: HdlNone(),
         },
     ];
     for (
@@ -488,7 +447,6 @@ fn test_enums() {
             data_in,
             which_out: _,
             data_out: _,
-            b_out: _,
         },
     ) in io_cycles.into_iter().enumerate()
     {
@@ -509,12 +467,11 @@ fn test_enums() {
                 .to_bigint()
                 .try_into()
                 .expect("known to be in range"),
-            b_out: sim.read(sim.io().b_out).to_expr(),
         };
         assert_eq!(
             expected,
             io,
-            "vcd:\n{}\ncycle: {cycle}",
+            "cycle: {cycle}\nvcd:\n{}",
             String::from_utf8(writer.take()).unwrap(),
         );
         sim.write_clock(sim.io().cd.clk, false);
@@ -535,714 +492,4 @@ fn test_enums() {
     }
 }
 
-#[hdl_module(outline_generated)]
-pub fn memories() {
-    #[hdl]
-    let r: fayalite::memory::ReadStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
-    #[hdl]
-    let w: fayalite::memory::WriteStruct<(UInt<8>, SInt<8>), ConstUsize<4>> = m.input();
-    #[hdl]
-    let mut mem = memory_with_init([(0x01u8, 0x23i8); 16]);
-    mem.read_latency(0);
-    mem.write_latency(NonZeroUsize::new(1).unwrap());
-    mem.read_under_write(ReadUnderWrite::Old);
-    connect_any(mem.new_read_port(), r);
-    connect_any(mem.new_write_port(), w);
-}
-
-#[hdl]
-#[test]
-fn test_memories() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let mut sim = Simulation::new(memories());
-    let mut writer = RcWriter::default();
-    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
-    sim.write_clock(sim.io().r.clk, false);
-    sim.write_clock(sim.io().w.clk, false);
-    #[derive(Debug, PartialEq, Eq)]
-    struct IO {
-        r_addr: u8,
-        r_en: bool,
-        r_data: (u8, i8),
-        w_addr: u8,
-        w_en: bool,
-        w_data: (u8, i8),
-        w_mask: (bool, bool),
-    }
-    let io_cycles = [
-        IO {
-            r_addr: 0,
-            r_en: false,
-            r_data: (0, 0),
-            w_addr: 0,
-            w_en: false,
-            w_data: (0, 0),
-            w_mask: (false, false),
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: (0x1, 0x23),
-            w_addr: 0,
-            w_en: true,
-            w_data: (0x10, 0x20),
-            w_mask: (true, true),
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: (0x10, 0x20),
-            w_addr: 0,
-            w_en: true,
-            w_data: (0x30, 0x40),
-            w_mask: (false, true),
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: (0x10, 0x40),
-            w_addr: 0,
-            w_en: true,
-            w_data: (0x50, 0x60),
-            w_mask: (true, false),
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: (0x50, 0x40),
-            w_addr: 0,
-            w_en: true,
-            w_data: (0x70, -0x80),
-            w_mask: (false, false),
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: (0x50, 0x40),
-            w_addr: 0,
-            w_en: false,
-            w_data: (0x90, 0xA0u8 as i8),
-            w_mask: (false, false),
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: (0x50, 0x40),
-            w_addr: 1,
-            w_en: true,
-            w_data: (0x90, 0xA0u8 as i8),
-            w_mask: (true, true),
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: (0x50, 0x40),
-            w_addr: 2,
-            w_en: true,
-            w_data: (0xB0, 0xC0u8 as i8),
-            w_mask: (true, true),
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: (0x50, 0x40),
-            w_addr: 2,
-            w_en: false,
-            w_data: (0xD0, 0xE0u8 as i8),
-            w_mask: (true, true),
-        },
-        IO {
-            r_addr: 1,
-            r_en: true,
-            r_data: (0x90, 0xA0u8 as i8),
-            w_addr: 2,
-            w_en: false,
-            w_data: (0xD0, 0xE0u8 as i8),
-            w_mask: (true, true),
-        },
-        IO {
-            r_addr: 2,
-            r_en: true,
-            r_data: (0xB0, 0xC0u8 as i8),
-            w_addr: 2,
-            w_en: false,
-            w_data: (0xD0, 0xE0u8 as i8),
-            w_mask: (true, true),
-        },
-    ];
-    for (
-        cycle,
-        expected @ IO {
-            r_addr,
-            r_en,
-            r_data: _,
-            w_addr,
-            w_en,
-            w_data,
-            w_mask,
-        },
-    ) in io_cycles.into_iter().enumerate()
-    {
-        sim.write_bool_or_int(sim.io().r.addr, r_addr.cast_to_static());
-        sim.write_bool(sim.io().r.en, r_en);
-        sim.write_bool_or_int(sim.io().w.addr, w_addr.cast_to_static());
-        sim.write_bool(sim.io().w.en, w_en);
-        sim.write_bool_or_int(sim.io().w.data.0, w_data.0);
-        sim.write_bool_or_int(sim.io().w.data.1, w_data.1);
-        sim.write_bool(sim.io().w.mask.0, w_mask.0);
-        sim.write_bool(sim.io().w.mask.1, w_mask.1);
-        let io = IO {
-            r_addr,
-            r_en,
-            r_data: (
-                sim.read_bool_or_int(sim.io().r.data.0)
-                    .to_bigint()
-                    .try_into()
-                    .expect("known to be in range"),
-                sim.read_bool_or_int(sim.io().r.data.1)
-                    .to_bigint()
-                    .try_into()
-                    .expect("known to be in range"),
-            ),
-            w_addr,
-            w_en,
-            w_data,
-            w_mask,
-        };
-        assert_eq!(
-            expected,
-            io,
-            "vcd:\n{}\ncycle: {cycle}",
-            String::from_utf8(writer.take()).unwrap(),
-        );
-        sim.advance_time(SimDuration::from_micros(1));
-        sim.write_clock(sim.io().r.clk, true);
-        sim.write_clock(sim.io().w.clk, true);
-        sim.advance_time(SimDuration::from_micros(1));
-        sim.write_clock(sim.io().r.clk, false);
-        sim.write_clock(sim.io().w.clk, false);
-    }
-    sim.flush_traces().unwrap();
-    let vcd = String::from_utf8(writer.take()).unwrap();
-    println!("####### VCD:\n{vcd}\n#######");
-    if vcd != include_str!("sim/expected/memories.vcd") {
-        panic!();
-    }
-    let sim_debug = format!("{sim:#?}");
-    println!("#######\n{sim_debug}\n#######");
-    if sim_debug != include_str!("sim/expected/memories.txt") {
-        panic!();
-    }
-}
-
-#[hdl_module(outline_generated)]
-pub fn memories2() {
-    #[hdl]
-    let rw: fayalite::memory::ReadWriteStruct<UInt<2>, ConstUsize<3>> = m.input();
-    #[hdl]
-    let mut mem = memory_with_init([HdlSome(true); 5]);
-    mem.read_latency(1);
-    mem.write_latency(NonZeroUsize::new(1).unwrap());
-    mem.read_under_write(ReadUnderWrite::New);
-    let rw_port = mem.new_rw_port();
-    connect_any(rw_port.addr, rw.addr);
-    connect(rw_port.en, rw.en);
-    connect(rw_port.clk, rw.clk);
-    connect_any(rw.rdata, rw_port.rdata.cast_to_bits());
-    connect(rw_port.wmode, rw.wmode);
-    connect(rw_port.wdata, HdlNone());
-    #[hdl]
-    if rw.wdata[0] {
-        connect(rw_port.wdata, HdlSome(rw.wdata[1]));
-    }
-    connect(rw_port.wmask, rw.wmask);
-}
-
-#[hdl]
-#[test]
-fn test_memories2() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let mut sim = Simulation::new(memories2());
-    let mut writer = RcWriter::default();
-    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
-    sim.write_clock(sim.io().rw.clk, false);
-    #[derive(Debug, PartialEq, Eq)]
-    struct IO {
-        addr: u8,
-        en: bool,
-        rdata: u8,
-        wmode: bool,
-        wdata: u8,
-        wmask: bool,
-    }
-    let io_cycles = [
-        IO {
-            addr: 0,
-            en: false,
-            rdata: 0,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 0,
-            en: true,
-            rdata: 0x3,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 0,
-            en: false,
-            rdata: 0,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 0,
-            en: true,
-            rdata: 0,
-            wmode: true,
-            wdata: 0,
-            wmask: true,
-        },
-        IO {
-            addr: 0,
-            en: true,
-            rdata: 0,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 0,
-            en: true,
-            rdata: 0,
-            wmode: true,
-            wdata: 3,
-            wmask: false,
-        },
-        IO {
-            addr: 1,
-            en: true,
-            rdata: 0,
-            wmode: true,
-            wdata: 1,
-            wmask: true,
-        },
-        IO {
-            addr: 2,
-            en: true,
-            rdata: 0,
-            wmode: true,
-            wdata: 2,
-            wmask: true,
-        },
-        IO {
-            addr: 3,
-            en: true,
-            rdata: 0,
-            wmode: true,
-            wdata: 3,
-            wmask: true,
-        },
-        IO {
-            addr: 4,
-            en: true,
-            rdata: 0,
-            wmode: true,
-            wdata: 2,
-            wmask: true,
-        },
-        IO {
-            addr: 5,
-            en: true,
-            rdata: 0,
-            wmode: true,
-            wdata: 1,
-            wmask: true,
-        },
-        IO {
-            addr: 6,
-            en: true,
-            rdata: 0,
-            wmode: true,
-            wdata: 1,
-            wmask: true,
-        },
-        IO {
-            addr: 7,
-            en: true,
-            rdata: 0,
-            wmode: true,
-            wdata: 1,
-            wmask: true,
-        },
-        IO {
-            addr: 7,
-            en: true,
-            rdata: 0,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 6,
-            en: true,
-            rdata: 0,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 5,
-            en: true,
-            rdata: 0,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 4,
-            en: true,
-            rdata: 0,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 3,
-            en: true,
-            rdata: 3,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 2,
-            en: true,
-            rdata: 0,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 0,
-            en: true,
-            rdata: 0,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 1,
-            en: true,
-            rdata: 1,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-        IO {
-            addr: 0,
-            en: false,
-            rdata: 0,
-            wmode: false,
-            wdata: 0,
-            wmask: false,
-        },
-    ];
-    for (
-        cycle,
-        expected @ IO {
-            addr,
-            en,
-            rdata: _,
-            wmode,
-            wdata,
-            wmask,
-        },
-    ) in io_cycles.into_iter().enumerate()
-    {
-        sim.write_bool_or_int(sim.io().rw.addr, addr.cast_to_static());
-        sim.write_bool(sim.io().rw.en, en);
-        sim.write_bool(sim.io().rw.wmode, wmode);
-        sim.write_bool_or_int(sim.io().rw.wdata, wdata.cast_to_static());
-        sim.write_bool(sim.io().rw.wmask, wmask);
-        sim.advance_time(SimDuration::from_nanos(250));
-        sim.write_clock(sim.io().rw.clk, true);
-        sim.advance_time(SimDuration::from_nanos(250));
-        let io = IO {
-            addr,
-            en,
-            rdata: sim
-                .read_bool_or_int(sim.io().rw.rdata)
-                .to_bigint()
-                .try_into()
-                .expect("known to be in range"),
-            wmode,
-            wdata,
-            wmask,
-        };
-        assert_eq!(
-            expected,
-            io,
-            "vcd:\n{}\ncycle: {cycle}",
-            String::from_utf8(writer.take()).unwrap(),
-        );
-        sim.advance_time(SimDuration::from_nanos(250));
-        sim.write_clock(sim.io().rw.clk, false);
-        sim.advance_time(SimDuration::from_nanos(250));
-    }
-    sim.flush_traces().unwrap();
-    let vcd = String::from_utf8(writer.take()).unwrap();
-    println!("####### VCD:\n{vcd}\n#######");
-    if vcd != include_str!("sim/expected/memories2.vcd") {
-        panic!();
-    }
-    let sim_debug = format!("{sim:#?}");
-    println!("#######\n{sim_debug}\n#######");
-    if sim_debug != include_str!("sim/expected/memories2.txt") {
-        panic!();
-    }
-}
-
-#[hdl_module(outline_generated)]
-pub fn memories3() {
-    #[hdl]
-    let r: fayalite::memory::ReadStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
-    #[hdl]
-    let w: fayalite::memory::WriteStruct<Array<UInt<8>, 8>, ConstUsize<3>> = m.input();
-    #[hdl]
-    let mut mem: MemBuilder<Array<UInt<8>, 8>> = memory();
-    mem.depth(8);
-    mem.read_latency(2);
-    mem.write_latency(NonZeroUsize::new(2).unwrap());
-    mem.read_under_write(ReadUnderWrite::Old);
-    connect_any(mem.new_read_port(), r);
-    connect_any(mem.new_write_port(), w);
-}
-
-#[hdl]
-#[test]
-fn test_memories3() {
-    let _n = SourceLocation::normalize_files_for_tests();
-    let mut sim = Simulation::new(memories3());
-    let mut writer = RcWriter::default();
-    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
-    sim.write_clock(sim.io().r.clk, false);
-    sim.write_clock(sim.io().w.clk, false);
-    #[derive(Debug, PartialEq, Eq, Clone, Copy)]
-    struct IO {
-        r_addr: u8,
-        r_en: bool,
-        r_data: [u8; 8],
-        w_addr: u8,
-        w_en: bool,
-        w_data: [u8; 8],
-        w_mask: [bool; 8],
-    }
-    let io_cycles = [
-        IO {
-            r_addr: 0,
-            r_en: false,
-            r_data: [0; 8],
-            w_addr: 0,
-            w_en: true,
-            w_data: [0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0],
-            w_mask: [false, true, false, true, true, false, false, true],
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: [0; 8],
-            w_addr: 1,
-            w_en: false,
-            w_data: [0; 8],
-            w_mask: [false; 8],
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0],
-            w_addr: 1,
-            w_en: false,
-            w_data: [0; 8],
-            w_mask: [false; 8],
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0],
-            w_addr: 0,
-            w_en: true,
-            w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
-            w_mask: [true; 8],
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: [0, 0x34, 0, 0x78, 0x9A, 0, 0, 0xF0],
-            w_addr: 0,
-            w_en: true,
-            w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
-            w_mask: [true; 8],
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
-            w_addr: 0,
-            w_en: true,
-            w_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
-            w_mask: [true; 8],
-        },
-        IO {
-            r_addr: 0,
-            r_en: false,
-            r_data: [0; 8],
-            w_addr: 1,
-            w_en: true,
-            w_data: [0x13, 0x57, 0x9B, 0xDF, 0x02, 0x46, 0x8A, 0xCE],
-            w_mask: [true; 8],
-        },
-        IO {
-            r_addr: 0,
-            r_en: false,
-            r_data: [0; 8],
-            w_addr: 2,
-            w_en: true,
-            w_data: *b"testing!",
-            w_mask: [true; 8],
-        },
-        IO {
-            r_addr: 0,
-            r_en: false,
-            r_data: [0; 8],
-            w_addr: 3,
-            w_en: true,
-            w_data: *b"more tst",
-            w_mask: [true; 8],
-        },
-        IO {
-            r_addr: 0,
-            r_en: true,
-            r_data: [0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10],
-            w_addr: 0,
-            w_en: false,
-            w_data: [0; 8],
-            w_mask: [false; 8],
-        },
-        IO {
-            r_addr: 1,
-            r_en: true,
-            r_data: [0x13, 0x57, 0x9B, 0xDF, 0x02, 0x46, 0x8A, 0xCE],
-            w_addr: 0,
-            w_en: false,
-            w_data: [0; 8],
-            w_mask: [false; 8],
-        },
-        IO {
-            r_addr: 2,
-            r_en: true,
-            r_data: *b"testing!",
-            w_addr: 0,
-            w_en: false,
-            w_data: [0; 8],
-            w_mask: [false; 8],
-        },
-        IO {
-            r_addr: 3,
-            r_en: true,
-            r_data: *b"more tst",
-            w_addr: 0,
-            w_en: false,
-            w_data: [0; 8],
-            w_mask: [false; 8],
-        },
-    ];
-    for cycle in 0..io_cycles.len() + 2 {
-        {
-            let IO {
-                r_addr,
-                r_en,
-                r_data: _,
-                w_addr,
-                w_en,
-                w_data,
-                w_mask,
-            } = io_cycles.get(cycle).copied().unwrap_or(IO {
-                r_addr: 0,
-                r_en: false,
-                r_data: [0; 8],
-                w_addr: 0,
-                w_en: false,
-                w_data: [0; 8],
-                w_mask: [false; 8],
-            });
-            sim.write_bool_or_int(sim.io().r.addr, r_addr.cast_to_static());
-            sim.write_bool(sim.io().r.en, r_en);
-            sim.write_bool_or_int(sim.io().w.addr, w_addr.cast_to_static());
-            sim.write_bool(sim.io().w.en, w_en);
-            for (i, v) in w_data.into_iter().enumerate() {
-                sim.write_bool_or_int(sim.io().w.data[i], v);
-            }
-            for (i, v) in w_mask.into_iter().enumerate() {
-                sim.write_bool_or_int(sim.io().w.mask[i], v);
-            }
-        }
-        sim.advance_time(SimDuration::from_nanos(250));
-        sim.write_clock(sim.io().r.clk, true);
-        sim.write_clock(sim.io().w.clk, true);
-        sim.advance_time(SimDuration::from_nanos(250));
-        if let Some(
-            expected @ IO {
-                r_addr,
-                r_en,
-                r_data: _,
-                w_addr,
-                w_en,
-                w_data,
-                w_mask,
-            },
-        ) = cycle.checked_sub(1).and_then(|i| io_cycles.get(i).copied())
-        {
-            let io = IO {
-                r_addr,
-                r_en,
-                r_data: std::array::from_fn(|i| {
-                    sim.read_bool_or_int(sim.io().r.data[i])
-                        .to_bigint()
-                        .try_into()
-                        .expect("known to be in range")
-                }),
-                w_addr,
-                w_en,
-                w_data,
-                w_mask,
-            };
-            assert_eq!(
-                expected,
-                io,
-                "vcd:\n{}\ncycle: {cycle}",
-                String::from_utf8(writer.take()).unwrap(),
-            );
-        }
-        sim.advance_time(SimDuration::from_nanos(250));
-        sim.write_clock(sim.io().r.clk, false);
-        sim.write_clock(sim.io().w.clk, false);
-        sim.advance_time(SimDuration::from_nanos(250));
-    }
-    sim.flush_traces().unwrap();
-    let vcd = String::from_utf8(writer.take()).unwrap();
-    println!("####### VCD:\n{vcd}\n#######");
-    if vcd != include_str!("sim/expected/memories3.vcd") {
-        panic!();
-    }
-    let sim_debug = format!("{sim:#?}");
-    println!("#######\n{sim_debug}\n#######");
-    if sim_debug != include_str!("sim/expected/memories3.txt") {
-        panic!();
-    }
-}
+// TODO: add tests for memories
diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt
index e44c50d..f361cc3 100644
--- a/crates/fayalite/tests/sim/expected/connect_const.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const.txt
@@ -3,12 +3,12 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 2,
                         debug_data: [
                             SlotDebugData {
@@ -23,7 +23,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartLayout<Memories> {
+                memories: StatePartAllocationLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -32,22 +32,21 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
-                0: Const {
-                    dest: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
-                    value: 0x5,
+                Const {
+                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
+                    value: 5,
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(0), // (0x5) SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(1), // (0x5) SlotDebugData { name: "", ty: UInt<8> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const: connect_const).connect_const::o", ty: UInt<8> },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "", ty: UInt<8> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                2: Return,
+                Return,
             ],
             ..
         },
         pc: 2,
-        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
@@ -80,12 +79,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<8>,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -113,7 +112,7 @@ Simulation {
             TraceModuleIO {
                 name: "o",
                 child: TraceUInt {
-                    location: TraceScalarId(0),
+                    id: TraceScalarId(0),
                     name: "o",
                     ty: UInt<8>,
                     flow: Sink,
@@ -134,9 +133,7 @@ Simulation {
             last_state: 0x05,
         },
     ],
-    trace_memories: {},
     trace_writers: [],
     instant: 0 s,
     clocks_triggered: [],
-    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
index d1ab998..0b0c043 100644
--- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt
+++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt
@@ -3,12 +3,12 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 5,
                         debug_data: [
                             SlotDebugData {
@@ -35,7 +35,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartLayout<Memories> {
+                memories: StatePartAllocationLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -44,36 +44,35 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
-                0: Const {
-                    dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    value: 0x1,
+                Const {
+                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    value: 1,
                 },
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
-                    src: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
+                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                2: Copy {
-                    dest: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
-                    src: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "", ty: AsyncReset },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
+                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
-                    src: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                5: Return,
+                Return,
             ],
             ..
         },
         pc: 5,
-        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
@@ -109,12 +108,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Bool,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -143,12 +142,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: AsyncReset,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -176,7 +175,7 @@ Simulation {
             TraceModuleIO {
                 name: "reset_out",
                 child: TraceAsyncReset {
-                    location: TraceScalarId(0),
+                    id: TraceScalarId(0),
                     name: "reset_out",
                     flow: Sink,
                 },
@@ -186,7 +185,7 @@ Simulation {
             TraceModuleIO {
                 name: "bit_out",
                 child: TraceBool {
-                    location: TraceScalarId(1),
+                    id: TraceScalarId(1),
                     name: "bit_out",
                     flow: Sink,
                 },
@@ -213,7 +212,6 @@ Simulation {
             last_state: 0x1,
         },
     ],
-    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {
@@ -225,5 +223,4 @@ Simulation {
     ],
     instant: 1 μs,
     clocks_triggered: [],
-    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt
index 2e005a0..0f49e80 100644
--- a/crates/fayalite/tests/sim/expected/counter_async.txt
+++ b/crates/fayalite/tests/sim/expected/counter_async.txt
@@ -3,7 +3,7 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 4,
                         debug_data: [
                             SlotDebugData {
@@ -25,7 +25,7 @@ Simulation {
                         ],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 10,
                         debug_data: [
                             SlotDebugData {
@@ -72,7 +72,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartLayout<Memories> {
+                memories: StatePartAllocationLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -81,101 +81,99 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
-                0: Const {
-                    dest: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    value: 0x1,
+                Const {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
+                    value: 1,
                 },
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                2: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                3: Const {
-                    dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
-                    value: 0x3,
+                Const {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 3,
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                4: BranchIfZero {
+                BranchIfZero {
                     target: 6,
-                    value: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                 },
-                5: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                6: Add {
-                    dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
-                    lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Add {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                7: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
                     dest_width: 4,
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                8: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                9: Copy {
-                    dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                10: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
                 },
-                11: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
                 },
-                12: BranchIfSmallNonZero {
+                BranchIfSmallNonZero {
                     target: 16,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                13: BranchIfSmallZero {
+                BranchIfSmallZero {
                     target: 17,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                14: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                 },
-                15: Branch {
+                Branch {
                     target: 17,
                 },
-                16: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
                 },
-                17: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
+                NotSmall {
+                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                18: Return,
+                Return,
             ],
             ..
         },
         pc: 18,
-        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
         small_slots: StatePart {
             value: [
-                0,
+                18446744073709551614,
                 0,
                 1,
                 0,
@@ -220,12 +218,12 @@ Simulation {
                     rst: AsyncReset,
                 },
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 2,
                         debug_data: [
                             SlotDebugData {
@@ -250,12 +248,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: Clock,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -277,12 +275,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: AsyncReset,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -315,12 +313,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Clock,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -349,12 +347,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: AsyncReset,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -383,12 +381,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -419,12 +417,12 @@ Simulation {
                     name: "cd",
                     fields: [
                         TraceClock {
-                            location: TraceScalarId(0),
+                            id: TraceScalarId(0),
                             name: "clk",
                             flow: Source,
                         },
                         TraceAsyncReset {
-                            location: TraceScalarId(1),
+                            id: TraceScalarId(1),
                             name: "rst",
                             flow: Source,
                         },
@@ -448,7 +446,7 @@ Simulation {
             TraceModuleIO {
                 name: "count",
                 child: TraceUInt {
-                    location: TraceScalarId(2),
+                    id: TraceScalarId(2),
                     name: "count",
                     ty: UInt<4>,
                     flow: Sink,
@@ -459,7 +457,7 @@ Simulation {
             TraceReg {
                 name: "count_reg",
                 child: TraceUInt {
-                    location: TraceScalarId(3),
+                    id: TraceScalarId(3),
                     name: "count_reg",
                     ty: UInt<4>,
                     flow: Duplex,
@@ -504,7 +502,6 @@ Simulation {
             last_state: 0x3,
         },
     ],
-    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {
@@ -518,5 +515,4 @@ Simulation {
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
     ],
-    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt
index 78fc200..30b84b2 100644
--- a/crates/fayalite/tests/sim/expected/counter_sync.txt
+++ b/crates/fayalite/tests/sim/expected/counter_sync.txt
@@ -3,7 +3,7 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 4,
                         debug_data: [
                             SlotDebugData {
@@ -25,7 +25,7 @@ Simulation {
                         ],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 9,
                         debug_data: [
                             SlotDebugData {
@@ -68,7 +68,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartLayout<Memories> {
+                memories: StatePartAllocationLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -77,87 +77,85 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:6:1
-                0: Copy {
-                    dest: StatePartIndex<BigSlots>(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                1: Const {
-                    dest: StatePartIndex<BigSlots>(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    value: 0x1,
+                Const {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
+                    value: 1,
                 },
-                2: Add {
-                    dest: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
-                    lhs: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(6), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Add {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
+                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                3: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<5> },
                     dest_width: 4,
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                5: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                6: Const {
-                    dest: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
-                    value: 0x3,
+                Const {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 3,
                 },
                 // at: module-XXXXXXXXXX.rs:3:1
-                7: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
                 },
-                8: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
                 },
-                9: BranchIfSmallZero {
+                BranchIfSmallZero {
                     target: 14,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                10: BranchIfSmallNonZero {
+                BranchIfSmallNonZero {
                     target: 13,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                11: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
                 },
-                12: Branch {
+                Branch {
                     target: 14,
                 },
-                13: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
                 },
-                14: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
+                NotSmall {
+                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                15: Return,
+                Return,
             ],
             ..
         },
         pc: 15,
-        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
         small_slots: StatePart {
             value: [
-                0,
+                18446744073709551614,
                 0,
                 1,
                 0,
@@ -201,12 +199,12 @@ Simulation {
                     rst: SyncReset,
                 },
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 2,
                         debug_data: [
                             SlotDebugData {
@@ -231,12 +229,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: Clock,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -258,12 +256,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: SyncReset,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -296,12 +294,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Clock,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -330,12 +328,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: SyncReset,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -364,12 +362,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -400,12 +398,12 @@ Simulation {
                     name: "cd",
                     fields: [
                         TraceClock {
-                            location: TraceScalarId(0),
+                            id: TraceScalarId(0),
                             name: "clk",
                             flow: Source,
                         },
                         TraceSyncReset {
-                            location: TraceScalarId(1),
+                            id: TraceScalarId(1),
                             name: "rst",
                             flow: Source,
                         },
@@ -429,7 +427,7 @@ Simulation {
             TraceModuleIO {
                 name: "count",
                 child: TraceUInt {
-                    location: TraceScalarId(2),
+                    id: TraceScalarId(2),
                     name: "count",
                     ty: UInt<4>,
                     flow: Sink,
@@ -440,7 +438,7 @@ Simulation {
             TraceReg {
                 name: "count_reg",
                 child: TraceUInt {
-                    location: TraceScalarId(3),
+                    id: TraceScalarId(3),
                     name: "count_reg",
                     ty: UInt<4>,
                     flow: Duplex,
@@ -485,7 +483,6 @@ Simulation {
             last_state: 0x3,
         },
     ],
-    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {
@@ -499,5 +496,4 @@ Simulation {
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
     ],
-    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt
index ebfae3e..69c94dd 100644
--- a/crates/fayalite/tests/sim/expected/enums.txt
+++ b/crates/fayalite/tests/sim/expected/enums.txt
@@ -3,16 +3,9 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 6,
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
+                        len: 5,
                         debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome,
-                                },
-                            },
                             SlotDebugData {
                                 name: "",
                                 ty: Bool,
@@ -40,8 +33,8 @@ Simulation {
                         ],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 103,
+                    big_slots: StatePartAllocationLayout<BigSlots> {
+                        len: 82,
                         debug_data: [
                             SlotDebugData {
                                 name: "InstantiatedModule(enums: enums).enums::cd.clk",
@@ -71,41 +64,6 @@ Simulation {
                                 name: "InstantiatedModule(enums: enums).enums::data_out",
                                 ty: UInt<4>,
                             },
-                            SlotDebugData {
-                                name: "InstantiatedModule(enums: enums).enums::b_out",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
-                                },
-                            },
-                            SlotDebugData {
-                                name: ".0",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: ".1",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
                             SlotDebugData {
                                 name: "InstantiatedModule(enums: enums).enums::the_reg",
                                 ty: Enum {
@@ -386,17 +344,6 @@ Simulation {
                                     C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>}),
                                 },
                             },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
-                                },
-                            },
                             SlotDebugData {
                                 name: "",
                                 ty: UInt<4>,
@@ -417,53 +364,6 @@ Simulation {
                                 name: "",
                                 ty: UInt<4>,
                             },
-                            SlotDebugData {
-                                name: ".0",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: ".1.0",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: ".1.1",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
-                                },
-                            },
                             SlotDebugData {
                                 name: "",
                                 ty: UInt<2>,
@@ -488,7 +388,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartLayout<Memories> {
+                memories: StatePartAllocationLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -497,603 +397,490 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:1:1
-                0: Const {
-                    dest: StatePartIndex<BigSlots>(90), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    value: 0x1,
+                Const {
+                    dest: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 0,
                 },
-                1: Const {
-                    dest: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
-                    value: 0x0,
-                },
-                2: Const {
-                    dest: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
-                    value: 0x0,
-                },
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                    src: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
-                },
-                // at: module-XXXXXXXXXX.rs:16:1
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                    src: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                5: SliceInt {
-                    dest: StatePartIndex<BigSlots>(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 2,
                     len: 2,
                 },
-                6: CastToSInt {
-                    dest: StatePartIndex<BigSlots>(70), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                CastToSInt {
+                    dest: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(61), // SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 2,
                 },
-                7: Const {
-                    dest: StatePartIndex<BigSlots>(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    value: 0x2,
+                Const {
+                    dest: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
+                    value: 2,
                 },
-                8: SliceInt {
-                    dest: StatePartIndex<BigSlots>(49), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 1,
                     len: 1,
                 },
-                9: Copy {
-                    dest: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(49), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(41), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                10: Copy {
-                    dest: StatePartIndex<BigSlots>(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: "", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
                 },
-                11: SliceInt {
-                    dest: StatePartIndex<BigSlots>(46), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(4), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_in", ty: UInt<4> },
                     start: 0,
                     len: 1,
                 },
-                12: Copy {
-                    dest: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(46), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(38), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                13: Copy {
-                    dest: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(47), // (0x1) SlotDebugData { name: "", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(39), // SlotDebugData { name: "", ty: Bool },
                 },
-                14: Copy {
-                    dest: StatePartIndex<BigSlots>(44), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                15: Copy {
-                    dest: StatePartIndex<BigSlots>(45), // (0x1) SlotDebugData { name: ".1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(50), // (0x1) SlotDebugData { name: "", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(42), // SlotDebugData { name: "", ty: Bool },
                 },
-                16: Copy {
-                    dest: StatePartIndex<BigSlots>(66), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(40), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                17: Copy {
-                    dest: StatePartIndex<BigSlots>(67), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(60), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                18: Copy {
-                    dest: StatePartIndex<BigSlots>(63), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(66), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(58), // SlotDebugData { name: "[0]", ty: UInt<1> },
                 },
-                19: Copy {
-                    dest: StatePartIndex<BigSlots>(64), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(67), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(59), // SlotDebugData { name: "[1]", ty: UInt<1> },
                 },
-                20: Copy {
-                    dest: StatePartIndex<BigSlots>(65), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(70), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(62), // SlotDebugData { name: "", ty: SInt<2> },
                 },
-                21: Copy {
-                    dest: StatePartIndex<BigSlots>(58), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                22: Copy {
-                    dest: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(63), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(55), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
                 },
-                23: Copy {
-                    dest: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(64), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(56), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
                 },
-                24: Copy {
-                    dest: StatePartIndex<BigSlots>(61), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(65), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(57), // SlotDebugData { name: ".b", ty: SInt<2> },
                 },
-                25: Shl {
-                    dest: StatePartIndex<BigSlots>(71), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(60), // (0x1) SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(52), // SlotDebugData { name: ".1.a[1]", ty: UInt<1> },
                     rhs: 1,
                 },
-                26: Or {
-                    dest: StatePartIndex<BigSlots>(72), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(59), // (0x1) SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(71), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                Or {
+                    dest: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(51), // SlotDebugData { name: ".1.a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(63), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                27: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(73), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(61), // (-0x1) SlotDebugData { name: ".1.b", ty: SInt<2> },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(53), // SlotDebugData { name: ".1.b", ty: SInt<2> },
                     dest_width: 2,
                 },
-                28: Shl {
-                    dest: StatePartIndex<BigSlots>(74), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(73), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(65), // SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
-                29: Or {
-                    dest: StatePartIndex<BigSlots>(75), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(72), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(74), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                Or {
+                    dest: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(64), // SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(66), // SlotDebugData { name: "", ty: UInt<4> },
                 },
-                30: Shl {
-                    dest: StatePartIndex<BigSlots>(76), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
-                    lhs: StatePartIndex<BigSlots>(75), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(67), // SlotDebugData { name: "", ty: UInt<4> },
                     rhs: 2,
                 },
-                31: Or {
-                    dest: StatePartIndex<BigSlots>(77), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
-                    lhs: StatePartIndex<BigSlots>(58), // (0x2) SlotDebugData { name: ".0", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(76), // (0x3c) SlotDebugData { name: "", ty: UInt<6> },
+                Or {
+                    dest: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
+                    lhs: StatePartIndex<BigSlots>(50), // SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(68), // SlotDebugData { name: "", ty: UInt<6> },
                 },
-                32: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(78), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(77), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(69), // SlotDebugData { name: "", ty: UInt<6> },
                     dest_width: 6,
                 },
-                33: Copy {
-                    dest: StatePartIndex<BigSlots>(79), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(78), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(70), // SlotDebugData { name: "", ty: UInt<6> },
                 },
-                34: Const {
-                    dest: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
-                    value: 0x1,
+                Const {
+                    dest: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
+                    value: 1,
                 },
-                35: CmpEq {
-                    dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                CmpEq {
+                    dest: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                36: Copy {
-                    dest: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                37: Copy {
-                    dest: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(44), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(36), // SlotDebugData { name: ".0", ty: UInt<1> },
                 },
-                38: Copy {
-                    dest: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(45), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(37), // SlotDebugData { name: ".1", ty: Bool },
                 },
-                39: Copy {
-                    dest: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(43), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(35), // SlotDebugData { name: ".1.1", ty: Bool },
                 },
-                40: Shl {
-                    dest: StatePartIndex<BigSlots>(52), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(51), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(43), // SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 1,
                 },
-                41: Or {
-                    dest: StatePartIndex<BigSlots>(53), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(42), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(52), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                Or {
+                    dest: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(34), // SlotDebugData { name: ".1.0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(44), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                42: Shl {
-                    dest: StatePartIndex<BigSlots>(54), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(53), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(45), // SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
-                43: Or {
-                    dest: StatePartIndex<BigSlots>(55), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(41), // (0x1) SlotDebugData { name: ".0", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(54), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
+                Or {
+                    dest: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(33), // SlotDebugData { name: ".0", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(46), // SlotDebugData { name: "", ty: UInt<4> },
                 },
-                44: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(56), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(55), // (0xd) SlotDebugData { name: "", ty: UInt<4> },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(47), // SlotDebugData { name: "", ty: UInt<4> },
                     dest_width: 6,
                 },
-                45: Copy {
-                    dest: StatePartIndex<BigSlots>(57), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(56), // (0xd) SlotDebugData { name: "", ty: UInt<6> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(48), // SlotDebugData { name: "", ty: UInt<6> },
                 },
-                46: Const {
-                    dest: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                    value: 0x0,
+                Const {
+                    dest: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
+                    value: 0,
                 },
-                47: CmpEq {
-                    dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(3), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
+                CmpEq {
+                    dest: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_in", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                48: Copy {
-                    dest: StatePartIndex<BigSlots>(21), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
-                    src: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
+                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
                 },
-                49: SliceInt {
-                    dest: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(21), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
                     start: 2,
                     len: 2,
                 },
-                50: SliceInt {
-                    dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
-                51: SliceInt {
-                    dest: StatePartIndex<BigSlots>(24), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
-                52: Copy {
-                    dest: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(24), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                53: Copy {
-                    dest: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                54: Copy {
-                    dest: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: ".1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(25), // (0x1) SlotDebugData { name: "", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(17), // SlotDebugData { name: "", ty: Bool },
                 },
-                55: Copy {
-                    dest: StatePartIndex<BigSlots>(83), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: ".1", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: ".1", ty: Bool },
                 },
-                56: Shl {
-                    dest: StatePartIndex<BigSlots>(84), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(83), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(73), // SlotDebugData { name: "", ty: UInt<1> },
                     rhs: 1,
                 },
-                57: Or {
-                    dest: StatePartIndex<BigSlots>(85), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(84), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                Or {
+                    dest: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(11), // SlotDebugData { name: ".0", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(74), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                58: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(86), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(85), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(75), // SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 4,
                 },
-                59: Copy {
-                    dest: StatePartIndex<BigSlots>(87), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(90), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                60: Copy {
-                    dest: StatePartIndex<BigSlots>(88), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(19), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                },
-                61: Copy {
-                    dest: StatePartIndex<BigSlots>(89), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(20), // (0x1) SlotDebugData { name: ".1", ty: Bool },
-                },
-                62: Copy {
-                    dest: StatePartIndex<BigSlots>(91), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(89), // (0x1) SlotDebugData { name: ".1.1", ty: Bool },
-                },
-                63: Shl {
-                    dest: StatePartIndex<BigSlots>(92), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(91), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    rhs: 1,
-                },
-                64: Or {
-                    dest: StatePartIndex<BigSlots>(93), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(88), // (0x1) SlotDebugData { name: ".1.0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(92), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                65: Shl {
-                    dest: StatePartIndex<BigSlots>(94), // (0x6) SlotDebugData { name: "", ty: UInt<3> },
-                    lhs: StatePartIndex<BigSlots>(93), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    rhs: 1,
-                },
-                66: Or {
-                    dest: StatePartIndex<BigSlots>(95), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
-                    lhs: StatePartIndex<BigSlots>(87), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(94), // (0x6) SlotDebugData { name: "", ty: UInt<3> },
-                },
-                67: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(96), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
-                    src: StatePartIndex<BigSlots>(95), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
-                    dest_width: 3,
-                },
-                68: Copy {
-                    dest: StatePartIndex<BigSlots>(97), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                    src: StatePartIndex<BigSlots>(96), // (0x7) SlotDebugData { name: "", ty: UInt<3> },
-                },
-                69: SliceInt {
-                    dest: StatePartIndex<BigSlots>(31), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(21), // (0x3e) SlotDebugData { name: "", ty: UInt<6> },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<6> },
                     start: 2,
                     len: 4,
                 },
-                70: SliceInt {
-                    dest: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(31), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
                     start: 0,
                     len: 2,
                 },
-                71: SliceInt {
-                    dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
                     start: 0,
                     len: 1,
                 },
-                72: SliceInt {
-                    dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(24), // SlotDebugData { name: "", ty: UInt<2> },
                     start: 1,
                     len: 1,
                 },
-                73: Copy {
-                    dest: StatePartIndex<BigSlots>(29), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(25), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                74: Copy {
-                    dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(26), // SlotDebugData { name: "", ty: UInt<1> },
                 },
-                75: SliceInt {
-                    dest: StatePartIndex<BigSlots>(35), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(31), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                SliceInt {
+                    dest: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(23), // SlotDebugData { name: "", ty: UInt<4> },
                     start: 2,
                     len: 2,
                 },
-                76: CastToSInt {
-                    dest: StatePartIndex<BigSlots>(36), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(35), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                CastToSInt {
+                    dest: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(27), // SlotDebugData { name: "", ty: UInt<2> },
                     dest_width: 2,
                 },
-                77: Copy {
-                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(29), // (0x1) SlotDebugData { name: "[0]", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(21), // SlotDebugData { name: "[0]", ty: UInt<1> },
                 },
-                78: Copy {
-                    dest: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "[1]", ty: UInt<1> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                    src: StatePartIndex<BigSlots>(22), // SlotDebugData { name: "[1]", ty: UInt<1> },
                 },
-                79: Copy {
-                    dest: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(36), // (-0x1) SlotDebugData { name: "", ty: SInt<2> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(28), // SlotDebugData { name: "", ty: SInt<2> },
                 },
-                80: Shl {
-                    dest: StatePartIndex<BigSlots>(98), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".a[1]", ty: UInt<1> },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(19), // SlotDebugData { name: ".a[1]", ty: UInt<1> },
                     rhs: 1,
                 },
-                81: Or {
-                    dest: StatePartIndex<BigSlots>(99), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".a[0]", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(98), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
+                Or {
+                    dest: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
+                    lhs: StatePartIndex<BigSlots>(18), // SlotDebugData { name: ".a[0]", ty: UInt<1> },
+                    rhs: StatePartIndex<BigSlots>(77), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                82: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(100), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(28), // (-0x1) SlotDebugData { name: ".b", ty: SInt<2> },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(20), // SlotDebugData { name: ".b", ty: SInt<2> },
                     dest_width: 2,
                 },
-                83: Shl {
-                    dest: StatePartIndex<BigSlots>(101), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(100), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
+                Shl {
+                    dest: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(79), // SlotDebugData { name: "", ty: UInt<2> },
                     rhs: 2,
                 },
-                84: Or {
-                    dest: StatePartIndex<BigSlots>(102), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    lhs: StatePartIndex<BigSlots>(99), // (0x3) SlotDebugData { name: "", ty: UInt<2> },
-                    rhs: StatePartIndex<BigSlots>(101), // (0xc) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:9:1
-                85: AndBigWithSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    lhs: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    rhs: 0x3,
-                },
-                // at: module-XXXXXXXXXX.rs:17:1
-                86: BranchIfSmallNeImmediate {
-                    target: 89,
-                    lhs: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 0x0,
-                },
-                // at: module-XXXXXXXXXX.rs:18:1
-                87: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:19:1
-                88: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:17:1
-                89: BranchIfSmallNeImmediate {
-                    target: 93,
-                    lhs: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:20:1
-                90: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(39), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:21:1
-                91: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(86), // (0x3) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:22:1
-                92: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                    src: StatePartIndex<BigSlots>(97), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                },
-                // at: module-XXXXXXXXXX.rs:17:1
-                93: BranchIfSmallNeImmediate {
-                    target: 96,
-                    lhs: StatePartIndex<SmallSlots>(5), // (0x2 2) SlotDebugData { name: "", ty: Enum {A, B, C} },
-                    rhs: 0x2,
-                },
-                // at: module-XXXXXXXXXX.rs:23:1
-                94: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:24:1
-                95: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(102), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:9:1
-                96: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                97: Const {
-                    dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
-                    value: 0x0,
-                },
-                98: Copy {
-                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<6> },
-                },
-                // at: module-XXXXXXXXXX.rs:10:1
-                99: BranchIfZero {
-                    target: 107,
-                    value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:11:1
-                100: BranchIfZero {
-                    target: 102,
-                    value: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                101: Copy {
-                    dest: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                },
-                // at: module-XXXXXXXXXX.rs:11:1
-                102: BranchIfNonZero {
-                    target: 107,
-                    value: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:13:1
-                103: BranchIfZero {
-                    target: 105,
-                    value: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:14:1
-                104: Copy {
-                    dest: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(57), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                },
-                // at: module-XXXXXXXXXX.rs:13:1
-                105: BranchIfNonZero {
-                    target: 107,
-                    value: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:15:1
-                106: Copy {
-                    dest: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(79), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                },
-                // at: module-XXXXXXXXXX.rs:9:1
-                107: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
-                },
-                108: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                109: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
-                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                },
-                110: SliceInt {
-                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> },
-                    start: 1,
-                    len: 2,
-                },
-                111: SliceInt {
-                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                    start: 0,
-                    len: 1,
-                },
-                112: SliceInt {
-                    dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                    start: 1,
-                    len: 1,
-                },
-                113: Copy {
-                    dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                114: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                115: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: ".1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: Bool },
+                Or {
+                    dest: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
+                    lhs: StatePartIndex<BigSlots>(78), // SlotDebugData { name: "", ty: UInt<2> },
+                    rhs: StatePartIndex<BigSlots>(80), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                116: AndBigWithSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
-                    lhs: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} },
-                    rhs: 0x1,
+                AndBigWithSmallImmediate {
+                    dest: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    lhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    rhs: 3,
                 },
-                // at: module-XXXXXXXXXX.rs:9:1
-                117: BranchIfSmallZero {
-                    target: 122,
-                    value: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                // at: module-XXXXXXXXXX.rs:15:1
+                BranchIfSmallNeImmediate {
+                    target: 75,
+                    lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 0,
                 },
-                118: BranchIfSmallNonZero {
-                    target: 121,
-                    value: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                // at: module-XXXXXXXXXX.rs:16:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(29), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                119: Copy {
-                    dest: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(16), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                // at: module-XXXXXXXXXX.rs:17:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(72), // SlotDebugData { name: "", ty: UInt<4> },
                 },
-                120: Branch {
-                    target: 122,
+                // at: module-XXXXXXXXXX.rs:15:1
+                BranchIfSmallNeImmediate {
+                    target: 78,
+                    lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 1,
                 },
-                121: Copy {
-                    dest: StatePartIndex<BigSlots>(15), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
-                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                // at: module-XXXXXXXXXX.rs:18:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(31), // SlotDebugData { name: "", ty: UInt<2> },
                 },
-                122: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
+                // at: module-XXXXXXXXXX.rs:19:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(76), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:15:1
+                BranchIfSmallNeImmediate {
+                    target: 81,
+                    lhs: StatePartIndex<SmallSlots>(4), // SlotDebugData { name: "", ty: Enum {A, B, C} },
+                    rhs: 2,
+                },
+                // at: module-XXXXXXXXXX.rs:20:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::which_out", ty: UInt<2> },
+                    src: StatePartIndex<BigSlots>(54), // SlotDebugData { name: "", ty: UInt<2> },
+                },
+                // at: module-XXXXXXXXXX.rs:21:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::data_out", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(81), // SlotDebugData { name: "", ty: UInt<4> },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                123: Return,
+                Const {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
+                    value: 0,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<6> },
+                },
+                // at: module-XXXXXXXXXX.rs:9:1
+                BranchIfZero {
+                    target: 92,
+                    value: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                BranchIfZero {
+                    target: 87,
+                    value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:11:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:10:1
+                BranchIfNonZero {
+                    target: 92,
+                    value: StatePartIndex<BigSlots>(30), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                BranchIfZero {
+                    target: 90,
+                    value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:13:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(49), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:12:1
+                BranchIfNonZero {
+                    target: 92,
+                    value: StatePartIndex<BigSlots>(32), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:14:1
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(71), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                // at: module-XXXXXXXXXX.rs:8:1
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock },
+                },
+                AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallZero {
+                    target: 99,
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                },
+                BranchIfSmallNonZero {
+                    target: 98,
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                Branch {
+                    target: 99,
+                },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array<UInt<1>, 2>, b: SInt<2>})} },
+                },
+                NotSmall {
+                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                },
+                // at: module-XXXXXXXXXX.rs:1:1
+                Return,
             ],
             ..
         },
-        pc: 123,
-        memory_write_log: [],
+        pc: 100,
         memories: StatePart {
             value: [],
         },
         small_slots: StatePart {
             value: [
-                0,
-                0,
+                18446744073709551614,
                 0,
                 1,
                 0,
@@ -1109,14 +896,6 @@ Simulation {
                 15,
                 2,
                 15,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
                 62,
                 62,
                 0,
@@ -1183,23 +962,10 @@ Simulation {
                 62,
                 62,
                 0,
-                0,
-                0,
                 1,
                 2,
                 3,
                 3,
-                1,
-                1,
-                1,
-                1,
-                1,
-                2,
-                3,
-                6,
-                7,
-                7,
-                7,
                 2,
                 3,
                 3,
@@ -1217,46 +983,6 @@ Simulation {
     },
     uninitialized_inputs: {},
     io_targets: {
-        Instance {
-            name: <simulator>::enums,
-            instantiated: Module {
-                name: enums,
-                ..
-            },
-        }.b_out: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Enum {
-                    HdlNone,
-                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(enums: enums).enums::b_out",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
-                                },
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 7, len: 1 },
-            },
-            write: None,
-        },
         Instance {
             name: <simulator>::enums,
             instantiated: Module {
@@ -1272,12 +998,12 @@ Simulation {
                     rst: SyncReset,
                 },
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 2,
                         debug_data: [
                             SlotDebugData {
@@ -1302,12 +1028,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: Clock,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -1329,12 +1055,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: SyncReset,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -1367,12 +1093,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Clock,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1401,12 +1127,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: SyncReset,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1435,12 +1161,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1469,12 +1195,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1503,12 +1229,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Bool,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1537,12 +1263,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<2>,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1571,12 +1297,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<2>,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -1607,12 +1333,12 @@ Simulation {
                     name: "cd",
                     fields: [
                         TraceClock {
-                            location: TraceScalarId(0),
+                            id: TraceScalarId(0),
                             name: "clk",
                             flow: Source,
                         },
                         TraceSyncReset {
-                            location: TraceScalarId(1),
+                            id: TraceScalarId(1),
                             name: "rst",
                             flow: Source,
                         },
@@ -1636,7 +1362,7 @@ Simulation {
             TraceModuleIO {
                 name: "en",
                 child: TraceBool {
-                    location: TraceScalarId(2),
+                    id: TraceScalarId(2),
                     name: "en",
                     flow: Source,
                 },
@@ -1646,7 +1372,7 @@ Simulation {
             TraceModuleIO {
                 name: "which_in",
                 child: TraceUInt {
-                    location: TraceScalarId(3),
+                    id: TraceScalarId(3),
                     name: "which_in",
                     ty: UInt<2>,
                     flow: Source,
@@ -1657,7 +1383,7 @@ Simulation {
             TraceModuleIO {
                 name: "data_in",
                 child: TraceUInt {
-                    location: TraceScalarId(4),
+                    id: TraceScalarId(4),
                     name: "data_in",
                     ty: UInt<4>,
                     flow: Source,
@@ -1668,7 +1394,7 @@ Simulation {
             TraceModuleIO {
                 name: "which_out",
                 child: TraceUInt {
-                    location: TraceScalarId(5),
+                    id: TraceScalarId(5),
                     name: "which_out",
                     ty: UInt<2>,
                     flow: Sink,
@@ -1679,7 +1405,7 @@ Simulation {
             TraceModuleIO {
                 name: "data_out",
                 child: TraceUInt {
-                    location: TraceScalarId(6),
+                    id: TraceScalarId(6),
                     name: "data_out",
                     ty: UInt<4>,
                     flow: Sink,
@@ -1687,62 +1413,12 @@ Simulation {
                 ty: UInt<4>,
                 flow: Sink,
             },
-            TraceModuleIO {
-                name: "b_out",
-                child: TraceEnumWithFields {
-                    name: "b_out",
-                    discriminant: TraceEnumDiscriminant {
-                        location: TraceScalarId(7),
-                        name: "$tag",
-                        ty: Enum {
-                            HdlNone,
-                            HdlSome(Bundle {0: UInt<1>, 1: Bool}),
-                        },
-                        flow: Sink,
-                    },
-                    non_empty_fields: [
-                        TraceBundle {
-                            name: "HdlSome",
-                            fields: [
-                                TraceUInt {
-                                    location: TraceScalarId(8),
-                                    name: "0",
-                                    ty: UInt<1>,
-                                    flow: Source,
-                                },
-                                TraceBool {
-                                    location: TraceScalarId(9),
-                                    name: "1",
-                                    flow: Source,
-                                },
-                            ],
-                            ty: Bundle {
-                                /* offset = 0 */
-                                0: UInt<1>,
-                                /* offset = 1 */
-                                1: Bool,
-                            },
-                            flow: Source,
-                        },
-                    ],
-                    ty: Enum {
-                        HdlNone,
-                        HdlSome(Bundle {0: UInt<1>, 1: Bool}),
-                    },
-                    flow: Sink,
-                },
-                ty: Enum {
-                    HdlNone,
-                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
-                },
-                flow: Sink,
-            },
             TraceReg {
                 name: "the_reg",
                 child: TraceEnumWithFields {
                     name: "the_reg",
                     discriminant: TraceEnumDiscriminant {
-                        location: TraceScalarId(10),
+                        id: TraceScalarId(7),
                         name: "$tag",
                         ty: Enum {
                             A,
@@ -1756,13 +1432,13 @@ Simulation {
                             name: "B",
                             fields: [
                                 TraceUInt {
-                                    location: TraceScalarId(11),
+                                    id: TraceScalarId(8),
                                     name: "0",
                                     ty: UInt<1>,
                                     flow: Source,
                                 },
                                 TraceBool {
-                                    location: TraceScalarId(12),
+                                    id: TraceScalarId(9),
                                     name: "1",
                                     flow: Source,
                                 },
@@ -1782,13 +1458,13 @@ Simulation {
                                     name: "a",
                                     elements: [
                                         TraceUInt {
-                                            location: TraceScalarId(13),
+                                            id: TraceScalarId(10),
                                             name: "[0]",
                                             ty: UInt<1>,
                                             flow: Source,
                                         },
                                         TraceUInt {
-                                            location: TraceScalarId(14),
+                                            id: TraceScalarId(11),
                                             name: "[1]",
                                             ty: UInt<1>,
                                             flow: Source,
@@ -1798,7 +1474,7 @@ Simulation {
                                     flow: Source,
                                 },
                                 TraceSInt {
-                                    location: TraceScalarId(15),
+                                    id: TraceScalarId(12),
                                     name: "b",
                                     ty: SInt<2>,
                                     flow: Source,
@@ -1892,36 +1568,7 @@ Simulation {
         SimTrace {
             id: TraceScalarId(7),
             kind: EnumDiscriminant {
-                index: StatePartIndex<SmallSlots>(0),
-                ty: Enum {
-                    HdlNone,
-                    HdlSome(Bundle {0: UInt<1>, 1: Bool}),
-                },
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(8),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(8),
-                ty: UInt<1>,
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(9),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(9),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(10),
-            kind: EnumDiscriminant {
-                index: StatePartIndex<SmallSlots>(5),
+                index: StatePartIndex<SmallSlots>(4),
                 ty: Enum {
                     A,
                     B(Bundle {0: UInt<1>, 1: Bool}),
@@ -1931,6 +1578,32 @@ Simulation {
             state: 0x2,
             last_state: 0x2,
         },
+        SimTrace {
+            id: TraceScalarId(8),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(11),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(9),
+            kind: BigBool {
+                index: StatePartIndex<BigSlots>(12),
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(10),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(18),
+                ty: UInt<1>,
+            },
+            state: 0x1,
+            last_state: 0x1,
+        },
         SimTrace {
             id: TraceScalarId(11),
             kind: BigUInt {
@@ -1942,41 +1615,14 @@ Simulation {
         },
         SimTrace {
             id: TraceScalarId(12),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(20),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(13),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(26),
-                ty: UInt<1>,
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(14),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(27),
-                ty: UInt<1>,
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(15),
             kind: BigSInt {
-                index: StatePartIndex<BigSlots>(28),
+                index: StatePartIndex<BigSlots>(20),
                 ty: SInt<2>,
             },
             state: 0x3,
             last_state: 0x3,
         },
     ],
-    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {
@@ -1988,7 +1634,6 @@ Simulation {
     ],
     instant: 16 μs,
     clocks_triggered: [
-        StatePartIndex<SmallSlots>(2),
+        StatePartIndex<SmallSlots>(1),
     ],
-    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/enums.vcd b/crates/fayalite/tests/sim/expected/enums.vcd
index 07cbd32..48a493b 100644
--- a/crates/fayalite/tests/sim/expected/enums.vcd
+++ b/crates/fayalite/tests/sim/expected/enums.vcd
@@ -9,25 +9,18 @@ $var wire 2 $ which_in $end
 $var wire 4 % data_in $end
 $var wire 2 & which_out $end
 $var wire 4 ' data_out $end
-$scope struct b_out $end
-$var string 1 ( \$tag $end
-$scope struct HdlSome $end
-$var wire 1 ) \0 $end
-$var wire 1 * \1 $end
-$upscope $end
-$upscope $end
 $scope struct the_reg $end
-$var string 1 + \$tag $end
+$var string 1 ( \$tag $end
 $scope struct B $end
-$var reg 1 , \0 $end
-$var reg 1 - \1 $end
+$var reg 1 ) \0 $end
+$var reg 1 * \1 $end
 $upscope $end
 $scope struct C $end
 $scope struct a $end
-$var reg 1 . \[0] $end
-$var reg 1 / \[1] $end
+$var reg 1 + \[0] $end
+$var reg 1 , \[1] $end
 $upscope $end
-$var reg 2 0 b $end
+$var reg 2 - b $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -40,15 +33,12 @@ b0 $
 b0 %
 b0 &
 b0 '
-sHdlNone\x20(0) (
+sA\x20(0) (
 0)
 0*
-sA\x20(0) +
+0+
 0,
-0-
-0.
-0/
-b0 0
+b0 -
 $end
 #1000000
 1!
@@ -65,8 +55,7 @@ b1 $
 #5000000
 1!
 b1 &
-sHdlSome\x20(1) (
-sB\x20(1) +
+sB\x20(1) (
 #6000000
 0#
 b0 $
@@ -83,10 +72,8 @@ b1111 %
 b11 '
 1)
 1*
+1+
 1,
-1-
-1.
-1/
 #10000000
 0!
 #11000000
@@ -98,11 +85,8 @@ b10 $
 1!
 b10 &
 b1111 '
-sHdlNone\x20(0) (
-0)
-0*
-sC\x20(2) +
-b11 0
+sC\x20(2) (
+b11 -
 #14000000
 0!
 #15000000
diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt
deleted file mode 100644
index afccd8a..0000000
--- a/crates/fayalite/tests/sim/expected/memories.txt
+++ /dev/null
@@ -1,2776 +0,0 @@
-Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 12,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 28,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.addr",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.data.0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.data.1",
-                                ty: SInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.addr",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.data.0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.data.1",
-                                ty: SInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.mask.0",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.mask.1",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::r0.addr",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::r0.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::r0.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1",
-                                ty: SInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::w1.addr",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::w1.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::w1.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1",
-                                ty: SInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: ".0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: ".1",
-                                ty: SInt<8>,
-                            },
-                            SlotDebugData {
-                                name: ".0",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: ".1",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                memories: StatePartLayout<Memories> {
-                    len: 1,
-                    debug_data: [
-                        (),
-                    ],
-                    layout_data: [
-                        MemoryData {
-                            array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
-                            data: [
-                                // len = 0x10
-                                [0x0]: 0x2301,
-                                [0x1]: 0x2301,
-                                [0x2]: 0x2301,
-                                [0x3]: 0x2301,
-                                [0x4]: 0x2301,
-                                [0x5]: 0x2301,
-                                [0x6]: 0x2301,
-                                [0x7]: 0x2301,
-                                [0x8]: 0x2301,
-                                [0x9]: 0x2301,
-                                [0xa]: 0x2301,
-                                [0xb]: 0x2301,
-                                [0xc]: 0x2301,
-                                [0xd]: 0x2301,
-                                [0xe]: 0x2301,
-                                [0xf]: 0x2301,
-                            ],
-                        },
-                    ],
-                    ..
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:8:1
-                0: Copy {
-                    dest: StatePartIndex<BigSlots>(17), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.addr", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(5), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.addr", ty: UInt<4> },
-                },
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.en", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.en", ty: Bool },
-                },
-                2: Copy {
-                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.clk", ty: Clock },
-                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.clk", ty: Clock },
-                },
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(20), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(8), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.data.0", ty: UInt<8> },
-                },
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(21), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1", ty: SInt<8> },
-                    src: StatePartIndex<BigSlots>(9), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.data.1", ty: SInt<8> },
-                },
-                5: Copy {
-                    dest: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0", ty: Bool },
-                    src: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.mask.0", ty: Bool },
-                },
-                6: Copy {
-                    dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::w.mask.1", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:6:1
-                7: Copy {
-                    dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.clk", ty: Clock },
-                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.clk", ty: Clock },
-                },
-                8: Copy {
-                    dest: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.en", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.en", ty: Bool },
-                },
-                9: Copy {
-                    dest: StatePartIndex<BigSlots>(12), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.addr", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(0), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.addr", ty: UInt<4> },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                10: CastBigToArrayIndex {
-                    dest: StatePartIndex<SmallSlots>(9), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(17), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.addr", ty: UInt<4> },
-                },
-                11: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.en", ty: Bool },
-                },
-                12: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.clk", ty: Clock },
-                },
-                13: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                },
-                14: CastBigToArrayIndex {
-                    dest: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(12), // (0x2) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.addr", ty: UInt<4> },
-                },
-                15: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.en", ty: Bool },
-                },
-                16: BranchIfSmallZero {
-                    target: 20,
-                    value: StatePartIndex<SmallSlots>(3), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                },
-                17: MemoryReadUInt {
-                    dest: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
-                            //     data: [
-                            //         // len = 0x10
-                            //         [0x0]: 0x4050,
-                            //         [0x1]: 0xa090,
-                            //         [0x2]: 0xc0b0,
-                            //         [0x3]: 0x2301,
-                            //         [0x4]: 0x2301,
-                            //         [0x5]: 0x2301,
-                            //         [0x6]: 0x2301,
-                            //         [0x7]: 0x2301,
-                            //         [0x8]: 0x2301,
-                            //         [0x9]: 0x2301,
-                            //         [0xa]: 0x2301,
-                            //         [0xb]: 0x2301,
-                            //         [0xc]: 0x2301,
-                            //         [0xd]: 0x2301,
-                            //         [0xe]: 0x2301,
-                            //         [0xf]: 0x2301,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
-                    stride: 16,
-                    start: 0,
-                    width: 8,
-                },
-                18: MemoryReadSInt {
-                    dest: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
-                            //     data: [
-                            //         // len = 0x10
-                            //         [0x0]: 0x4050,
-                            //         [0x1]: 0xa090,
-                            //         [0x2]: 0xc0b0,
-                            //         [0x3]: 0x2301,
-                            //         [0x4]: 0x2301,
-                            //         [0x5]: 0x2301,
-                            //         [0x6]: 0x2301,
-                            //         [0x7]: 0x2301,
-                            //         [0x8]: 0x2301,
-                            //         [0x9]: 0x2301,
-                            //         [0xa]: 0x2301,
-                            //         [0xb]: 0x2301,
-                            //         [0xc]: 0x2301,
-                            //         [0xd]: 0x2301,
-                            //         [0xe]: 0x2301,
-                            //         [0xf]: 0x2301,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(4), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
-                    stride: 16,
-                    start: 8,
-                    width: 8,
-                },
-                19: Branch {
-                    target: 22,
-                },
-                20: Const {
-                    dest: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
-                    value: 0x0,
-                },
-                21: Const {
-                    dest: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
-                    value: 0x0,
-                },
-                // at: module-XXXXXXXXXX.rs:6:1
-                22: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.data.0", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(15), // (0xb0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.0", ty: UInt<8> },
-                },
-                23: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::r.data.1", ty: SInt<8> },
-                    src: StatePartIndex<BigSlots>(16), // (-0x40) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.data.1", ty: SInt<8> },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                24: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::r0.clk", ty: Clock },
-                },
-                25: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                },
-                26: BranchIfSmallZero {
-                    target: 27,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                27: BranchIfSmallZero {
-                    target: 39,
-                    value: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                28: CopySmall {
-                    dest: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<SmallSlots>(9), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
-                },
-                29: CopySmall {
-                    dest: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                30: Copy {
-                    dest: StatePartIndex<BigSlots>(24), // (0xd0) SlotDebugData { name: ".0", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(20), // (0xd0) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.0", ty: UInt<8> },
-                },
-                31: Copy {
-                    dest: StatePartIndex<BigSlots>(25), // (-0x20) SlotDebugData { name: ".1", ty: SInt<8> },
-                    src: StatePartIndex<BigSlots>(21), // (-0x20) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.data.1", ty: SInt<8> },
-                },
-                32: Copy {
-                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: Bool },
-                    src: StatePartIndex<BigSlots>(22), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.0", ty: Bool },
-                },
-                33: Copy {
-                    dest: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "InstantiatedModule(memories: memories).memories::mem::w1.mask.1", ty: Bool },
-                },
-                34: BranchIfSmallZero {
-                    target: 39,
-                    value: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                35: BranchIfZero {
-                    target: 37,
-                    value: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: Bool },
-                },
-                36: MemoryWriteUInt {
-                    value: StatePartIndex<BigSlots>(24), // (0xd0) SlotDebugData { name: ".0", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
-                            //     data: [
-                            //         // len = 0x10
-                            //         [0x0]: 0x4050,
-                            //         [0x1]: 0xa090,
-                            //         [0x2]: 0xc0b0,
-                            //         [0x3]: 0x2301,
-                            //         [0x4]: 0x2301,
-                            //         [0x5]: 0x2301,
-                            //         [0x6]: 0x2301,
-                            //         [0x7]: 0x2301,
-                            //         [0x8]: 0x2301,
-                            //         [0x9]: 0x2301,
-                            //         [0xa]: 0x2301,
-                            //         [0xb]: 0x2301,
-                            //         [0xc]: 0x2301,
-                            //         [0xd]: 0x2301,
-                            //         [0xe]: 0x2301,
-                            //         [0xf]: 0x2301,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
-                    stride: 16,
-                    start: 0,
-                    width: 8,
-                },
-                37: BranchIfZero {
-                    target: 39,
-                    value: StatePartIndex<BigSlots>(27), // (0x1) SlotDebugData { name: ".1", ty: Bool },
-                },
-                38: MemoryWriteSInt {
-                    value: StatePartIndex<BigSlots>(25), // (-0x20) SlotDebugData { name: ".1", ty: SInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
-                            //     data: [
-                            //         // len = 0x10
-                            //         [0x0]: 0x4050,
-                            //         [0x1]: 0xa090,
-                            //         [0x2]: 0xc0b0,
-                            //         [0x3]: 0x2301,
-                            //         [0x4]: 0x2301,
-                            //         [0x5]: 0x2301,
-                            //         [0x6]: 0x2301,
-                            //         [0x7]: 0x2301,
-                            //         [0x8]: 0x2301,
-                            //         [0x9]: 0x2301,
-                            //         [0xa]: 0x2301,
-                            //         [0xb]: 0x2301,
-                            //         [0xc]: 0x2301,
-                            //         [0xd]: 0x2301,
-                            //         [0xe]: 0x2301,
-                            //         [0xf]: 0x2301,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(10), // (0x2 2) SlotDebugData { name: "", ty: UInt<4> },
-                    stride: 16,
-                    start: 8,
-                    width: 8,
-                },
-                39: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
-                },
-                40: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                41: Return,
-            ],
-            ..
-        },
-        pc: 41,
-        memory_write_log: [],
-        memories: StatePart {
-            value: [
-                MemoryData {
-                    array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
-                    data: [
-                        // len = 0x10
-                        [0x0]: 0x4050,
-                        [0x1]: 0xa090,
-                        [0x2]: 0xc0b0,
-                        [0x3]: 0x2301,
-                        [0x4]: 0x2301,
-                        [0x5]: 0x2301,
-                        [0x6]: 0x2301,
-                        [0x7]: 0x2301,
-                        [0x8]: 0x2301,
-                        [0x9]: 0x2301,
-                        [0xa]: 0x2301,
-                        [0xb]: 0x2301,
-                        [0xc]: 0x2301,
-                        [0xd]: 0x2301,
-                        [0xe]: 0x2301,
-                        [0xf]: 0x2301,
-                    ],
-                },
-            ],
-        },
-        small_slots: StatePart {
-            value: [
-                1,
-                0,
-                0,
-                1,
-                2,
-                1,
-                0,
-                0,
-                0,
-                2,
-                2,
-                0,
-            ],
-        },
-        big_slots: StatePart {
-            value: [
-                2,
-                1,
-                0,
-                176,
-                -64,
-                2,
-                0,
-                0,
-                208,
-                -32,
-                1,
-                1,
-                2,
-                1,
-                0,
-                176,
-                -64,
-                2,
-                0,
-                0,
-                208,
-                -32,
-                1,
-                1,
-                208,
-                -32,
-                1,
-                1,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::memories,
-        instantiated: Module {
-            name: memories,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    addr: UInt<4>,
-                    /* offset = 4 */
-                    en: Bool,
-                    /* offset = 5 */
-                    clk: Clock,
-                    #[hdl(flip)] /* offset = 6 */
-                    data: Bundle {
-                        /* offset = 0 */
-                        0: UInt<8>,
-                        /* offset = 8 */
-                        1: SInt<8>,
-                    },
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 5,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.addr",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.data.0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::r.data.1",
-                                ty: SInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<4>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<4>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(2),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(3),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bundle {
-                                    /* offset = 0 */
-                                    0: UInt<8>,
-                                    /* offset = 8 */
-                                    1: SInt<8>,
-                                },
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 2,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: ".0",
-                                                ty: UInt<8>,
-                                            },
-                                            SlotDebugData {
-                                                name: ".1",
-                                                ty: SInt<8>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Bundle {
-                                    fields: [
-                                        CompiledBundleField {
-                                            offset: TypeIndex {
-                                                small_slots: StatePartIndex<SmallSlots>(0),
-                                                big_slots: StatePartIndex<BigSlots>(0),
-                                            },
-                                            ty: CompiledTypeLayout {
-                                                ty: UInt<8>,
-                                                layout: TypeLayout {
-                                                    small_slots: StatePartLayout<SmallSlots> {
-                                                        len: 0,
-                                                        debug_data: [],
-                                                        ..
-                                                    },
-                                                    big_slots: StatePartLayout<BigSlots> {
-                                                        len: 1,
-                                                        debug_data: [
-                                                            SlotDebugData {
-                                                                name: "",
-                                                                ty: UInt<8>,
-                                                            },
-                                                        ],
-                                                        ..
-                                                    },
-                                                },
-                                                body: Scalar,
-                                            },
-                                        },
-                                        CompiledBundleField {
-                                            offset: TypeIndex {
-                                                small_slots: StatePartIndex<SmallSlots>(0),
-                                                big_slots: StatePartIndex<BigSlots>(1),
-                                            },
-                                            ty: CompiledTypeLayout {
-                                                ty: SInt<8>,
-                                                layout: TypeLayout {
-                                                    small_slots: StatePartLayout<SmallSlots> {
-                                                        len: 0,
-                                                        debug_data: [],
-                                                        ..
-                                                    },
-                                                    big_slots: StatePartLayout<BigSlots> {
-                                                        len: 1,
-                                                        debug_data: [
-                                                            SlotDebugData {
-                                                                name: "",
-                                                                ty: SInt<8>,
-                                                            },
-                                                        ],
-                                                        ..
-                                                    },
-                                                },
-                                                body: Scalar,
-                                            },
-                                        },
-                                    ],
-                                },
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 5 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.addr: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<4>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<4>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.data: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    0: UInt<8>,
-                    /* offset = 8 */
-                    1: SInt<8>,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 2,
-                        debug_data: [
-                            SlotDebugData {
-                                name: ".0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: ".1",
-                                ty: SInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<8>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<8>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: SInt<8>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: SInt<8>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 2 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.data.0: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.data.1: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: SInt<8>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: SInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.r.en: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories,
-            instantiated: Module {
-                name: memories,
-                ..
-            },
-        }.w: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    addr: UInt<4>,
-                    /* offset = 4 */
-                    en: Bool,
-                    /* offset = 5 */
-                    clk: Clock,
-                    /* offset = 6 */
-                    data: Bundle {
-                        /* offset = 0 */
-                        0: UInt<8>,
-                        /* offset = 8 */
-                        1: SInt<8>,
-                    },
-                    /* offset = 22 */
-                    mask: Bundle {
-                        /* offset = 0 */
-                        0: Bool,
-                        /* offset = 1 */
-                        1: Bool,
-                    },
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 7,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.addr",
-                                ty: UInt<4>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.data.0",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.data.1",
-                                ty: SInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.mask.0",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories: memories).memories::w.mask.1",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<4>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<4>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
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-                stride: 16,
-                element_type: TraceBundle {
-                    name: "mem",
-                    fields: [
-                        TraceUInt {
-                            location: TraceMemoryLocation {
-                                id: TraceMemoryId(0),
-                                depth: 16,
-                                stride: 16,
-                                start: 0,
-                                len: 8,
-                            },
-                            name: "0",
-                            ty: UInt<8>,
-                            flow: Duplex,
-                        },
-                        TraceSInt {
-                            location: TraceMemoryLocation {
-                                id: TraceMemoryId(0),
-                                depth: 16,
-                                stride: 16,
-                                start: 8,
-                                len: 8,
-                            },
-                            name: "1",
-                            ty: SInt<8>,
-                            flow: Duplex,
-                        },
-                    ],
-                    ty: Bundle {
-                        /* offset = 0 */
-                        0: UInt<8>,
-                        /* offset = 8 */
-                        1: SInt<8>,
-                    },
-                    flow: Duplex,
-                },
-                ports: [
-                    TraceMemPort {
-                        name: "r0",
-                        bundle: TraceBundle {
-                            name: "r0",
-                            fields: [
-                                TraceUInt {
-                                    location: TraceScalarId(12),
-                                    name: "addr",
-                                    ty: UInt<4>,
-                                    flow: Sink,
-                                },
-                                TraceBool {
-                                    location: TraceScalarId(13),
-                                    name: "en",
-                                    flow: Sink,
-                                },
-                                TraceClock {
-                                    location: TraceScalarId(14),
-                                    name: "clk",
-                                    flow: Sink,
-                                },
-                                TraceBundle {
-                                    name: "data",
-                                    fields: [
-                                        TraceUInt {
-                                            location: TraceScalarId(15),
-                                            name: "0",
-                                            ty: UInt<8>,
-                                            flow: Source,
-                                        },
-                                        TraceSInt {
-                                            location: TraceScalarId(16),
-                                            name: "1",
-                                            ty: SInt<8>,
-                                            flow: Source,
-                                        },
-                                    ],
-                                    ty: Bundle {
-                                        /* offset = 0 */
-                                        0: UInt<8>,
-                                        /* offset = 8 */
-                                        1: SInt<8>,
-                                    },
-                                    flow: Source,
-                                },
-                            ],
-                            ty: Bundle {
-                                /* offset = 0 */
-                                addr: UInt<4>,
-                                /* offset = 4 */
-                                en: Bool,
-                                /* offset = 5 */
-                                clk: Clock,
-                                #[hdl(flip)] /* offset = 6 */
-                                data: Bundle {
-                                    /* offset = 0 */
-                                    0: UInt<8>,
-                                    /* offset = 8 */
-                                    1: SInt<8>,
-                                },
-                            },
-                            flow: Sink,
-                        },
-                        ty: Bundle {
-                            /* offset = 0 */
-                            addr: UInt<4>,
-                            /* offset = 4 */
-                            en: Bool,
-                            /* offset = 5 */
-                            clk: Clock,
-                            #[hdl(flip)] /* offset = 6 */
-                            data: Bundle {
-                                /* offset = 0 */
-                                0: UInt<8>,
-                                /* offset = 8 */
-                                1: SInt<8>,
-                            },
-                        },
-                    },
-                    TraceMemPort {
-                        name: "w1",
-                        bundle: TraceBundle {
-                            name: "w1",
-                            fields: [
-                                TraceUInt {
-                                    location: TraceScalarId(17),
-                                    name: "addr",
-                                    ty: UInt<4>,
-                                    flow: Sink,
-                                },
-                                TraceBool {
-                                    location: TraceScalarId(18),
-                                    name: "en",
-                                    flow: Sink,
-                                },
-                                TraceClock {
-                                    location: TraceScalarId(19),
-                                    name: "clk",
-                                    flow: Sink,
-                                },
-                                TraceBundle {
-                                    name: "data",
-                                    fields: [
-                                        TraceUInt {
-                                            location: TraceScalarId(20),
-                                            name: "0",
-                                            ty: UInt<8>,
-                                            flow: Sink,
-                                        },
-                                        TraceSInt {
-                                            location: TraceScalarId(21),
-                                            name: "1",
-                                            ty: SInt<8>,
-                                            flow: Sink,
-                                        },
-                                    ],
-                                    ty: Bundle {
-                                        /* offset = 0 */
-                                        0: UInt<8>,
-                                        /* offset = 8 */
-                                        1: SInt<8>,
-                                    },
-                                    flow: Sink,
-                                },
-                                TraceBundle {
-                                    name: "mask",
-                                    fields: [
-                                        TraceBool {
-                                            location: TraceScalarId(22),
-                                            name: "0",
-                                            flow: Sink,
-                                        },
-                                        TraceBool {
-                                            location: TraceScalarId(23),
-                                            name: "1",
-                                            flow: Sink,
-                                        },
-                                    ],
-                                    ty: Bundle {
-                                        /* offset = 0 */
-                                        0: Bool,
-                                        /* offset = 1 */
-                                        1: Bool,
-                                    },
-                                    flow: Sink,
-                                },
-                            ],
-                            ty: Bundle {
-                                /* offset = 0 */
-                                addr: UInt<4>,
-                                /* offset = 4 */
-                                en: Bool,
-                                /* offset = 5 */
-                                clk: Clock,
-                                /* offset = 6 */
-                                data: Bundle {
-                                    /* offset = 0 */
-                                    0: UInt<8>,
-                                    /* offset = 8 */
-                                    1: SInt<8>,
-                                },
-                                /* offset = 22 */
-                                mask: Bundle {
-                                    /* offset = 0 */
-                                    0: Bool,
-                                    /* offset = 1 */
-                                    1: Bool,
-                                },
-                            },
-                            flow: Sink,
-                        },
-                        ty: Bundle {
-                            /* offset = 0 */
-                            addr: UInt<4>,
-                            /* offset = 4 */
-                            en: Bool,
-                            /* offset = 5 */
-                            clk: Clock,
-                            /* offset = 6 */
-                            data: Bundle {
-                                /* offset = 0 */
-                                0: UInt<8>,
-                                /* offset = 8 */
-                                1: SInt<8>,
-                            },
-                            /* offset = 22 */
-                            mask: Bundle {
-                                /* offset = 0 */
-                                0: Bool,
-                                /* offset = 1 */
-                                1: Bool,
-                            },
-                        },
-                    },
-                ],
-                array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(0),
-                ty: UInt<4>,
-            },
-            state: 0x2,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(1),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(2),
-            },
-            state: 0x0,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(3),
-                ty: UInt<8>,
-            },
-            state: 0xb0,
-            last_state: 0xb0,
-        },
-        SimTrace {
-            id: TraceScalarId(4),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(4),
-                ty: SInt<8>,
-            },
-            state: 0xc0,
-            last_state: 0xc0,
-        },
-        SimTrace {
-            id: TraceScalarId(5),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(5),
-                ty: UInt<4>,
-            },
-            state: 0x2,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(6),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(6),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(7),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(7),
-            },
-            state: 0x0,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(8),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(8),
-                ty: UInt<8>,
-            },
-            state: 0xd0,
-            last_state: 0xd0,
-        },
-        SimTrace {
-            id: TraceScalarId(9),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(9),
-                ty: SInt<8>,
-            },
-            state: 0xe0,
-            last_state: 0xe0,
-        },
-        SimTrace {
-            id: TraceScalarId(10),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(10),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(11),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(11),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(12),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(12),
-                ty: UInt<4>,
-            },
-            state: 0x2,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(13),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(13),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(14),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(14),
-            },
-            state: 0x0,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(15),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(15),
-                ty: UInt<8>,
-            },
-            state: 0xb0,
-            last_state: 0xb0,
-        },
-        SimTrace {
-            id: TraceScalarId(16),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(16),
-                ty: SInt<8>,
-            },
-            state: 0xc0,
-            last_state: 0xc0,
-        },
-        SimTrace {
-            id: TraceScalarId(17),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(17),
-                ty: UInt<4>,
-            },
-            state: 0x2,
-            last_state: 0x2,
-        },
-        SimTrace {
-            id: TraceScalarId(18),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(18),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(19),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(19),
-            },
-            state: 0x0,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(20),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(20),
-                ty: UInt<8>,
-            },
-            state: 0xd0,
-            last_state: 0xd0,
-        },
-        SimTrace {
-            id: TraceScalarId(21),
-            kind: BigSInt {
-                index: StatePartIndex<BigSlots>(21),
-                ty: SInt<8>,
-            },
-            state: 0xe0,
-            last_state: 0xe0,
-        },
-        SimTrace {
-            id: TraceScalarId(22),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(22),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(23),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(23),
-            },
-            state: 0x1,
-            last_state: 0x1,
-        },
-    ],
-    trace_memories: {
-        StatePartIndex<Memories>(0): TraceMem {
-            id: TraceMemoryId(0),
-            name: "mem",
-            stride: 16,
-            element_type: TraceBundle {
-                name: "mem",
-                fields: [
-                    TraceUInt {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 16,
-                            stride: 16,
-                            start: 0,
-                            len: 8,
-                        },
-                        name: "0",
-                        ty: UInt<8>,
-                        flow: Duplex,
-                    },
-                    TraceSInt {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 16,
-                            stride: 16,
-                            start: 8,
-                            len: 8,
-                        },
-                        name: "1",
-                        ty: SInt<8>,
-                        flow: Duplex,
-                    },
-                ],
-                ty: Bundle {
-                    /* offset = 0 */
-                    0: UInt<8>,
-                    /* offset = 8 */
-                    1: SInt<8>,
-                },
-                flow: Duplex,
-            },
-            ports: [
-                TraceMemPort {
-                    name: "r0",
-                    bundle: TraceBundle {
-                        name: "r0",
-                        fields: [
-                            TraceUInt {
-                                location: TraceScalarId(12),
-                                name: "addr",
-                                ty: UInt<4>,
-                                flow: Sink,
-                            },
-                            TraceBool {
-                                location: TraceScalarId(13),
-                                name: "en",
-                                flow: Sink,
-                            },
-                            TraceClock {
-                                location: TraceScalarId(14),
-                                name: "clk",
-                                flow: Sink,
-                            },
-                            TraceBundle {
-                                name: "data",
-                                fields: [
-                                    TraceUInt {
-                                        location: TraceScalarId(15),
-                                        name: "0",
-                                        ty: UInt<8>,
-                                        flow: Source,
-                                    },
-                                    TraceSInt {
-                                        location: TraceScalarId(16),
-                                        name: "1",
-                                        ty: SInt<8>,
-                                        flow: Source,
-                                    },
-                                ],
-                                ty: Bundle {
-                                    /* offset = 0 */
-                                    0: UInt<8>,
-                                    /* offset = 8 */
-                                    1: SInt<8>,
-                                },
-                                flow: Source,
-                            },
-                        ],
-                        ty: Bundle {
-                            /* offset = 0 */
-                            addr: UInt<4>,
-                            /* offset = 4 */
-                            en: Bool,
-                            /* offset = 5 */
-                            clk: Clock,
-                            #[hdl(flip)] /* offset = 6 */
-                            data: Bundle {
-                                /* offset = 0 */
-                                0: UInt<8>,
-                                /* offset = 8 */
-                                1: SInt<8>,
-                            },
-                        },
-                        flow: Sink,
-                    },
-                    ty: Bundle {
-                        /* offset = 0 */
-                        addr: UInt<4>,
-                        /* offset = 4 */
-                        en: Bool,
-                        /* offset = 5 */
-                        clk: Clock,
-                        #[hdl(flip)] /* offset = 6 */
-                        data: Bundle {
-                            /* offset = 0 */
-                            0: UInt<8>,
-                            /* offset = 8 */
-                            1: SInt<8>,
-                        },
-                    },
-                },
-                TraceMemPort {
-                    name: "w1",
-                    bundle: TraceBundle {
-                        name: "w1",
-                        fields: [
-                            TraceUInt {
-                                location: TraceScalarId(17),
-                                name: "addr",
-                                ty: UInt<4>,
-                                flow: Sink,
-                            },
-                            TraceBool {
-                                location: TraceScalarId(18),
-                                name: "en",
-                                flow: Sink,
-                            },
-                            TraceClock {
-                                location: TraceScalarId(19),
-                                name: "clk",
-                                flow: Sink,
-                            },
-                            TraceBundle {
-                                name: "data",
-                                fields: [
-                                    TraceUInt {
-                                        location: TraceScalarId(20),
-                                        name: "0",
-                                        ty: UInt<8>,
-                                        flow: Sink,
-                                    },
-                                    TraceSInt {
-                                        location: TraceScalarId(21),
-                                        name: "1",
-                                        ty: SInt<8>,
-                                        flow: Sink,
-                                    },
-                                ],
-                                ty: Bundle {
-                                    /* offset = 0 */
-                                    0: UInt<8>,
-                                    /* offset = 8 */
-                                    1: SInt<8>,
-                                },
-                                flow: Sink,
-                            },
-                            TraceBundle {
-                                name: "mask",
-                                fields: [
-                                    TraceBool {
-                                        location: TraceScalarId(22),
-                                        name: "0",
-                                        flow: Sink,
-                                    },
-                                    TraceBool {
-                                        location: TraceScalarId(23),
-                                        name: "1",
-                                        flow: Sink,
-                                    },
-                                ],
-                                ty: Bundle {
-                                    /* offset = 0 */
-                                    0: Bool,
-                                    /* offset = 1 */
-                                    1: Bool,
-                                },
-                                flow: Sink,
-                            },
-                        ],
-                        ty: Bundle {
-                            /* offset = 0 */
-                            addr: UInt<4>,
-                            /* offset = 4 */
-                            en: Bool,
-                            /* offset = 5 */
-                            clk: Clock,
-                            /* offset = 6 */
-                            data: Bundle {
-                                /* offset = 0 */
-                                0: UInt<8>,
-                                /* offset = 8 */
-                                1: SInt<8>,
-                            },
-                            /* offset = 22 */
-                            mask: Bundle {
-                                /* offset = 0 */
-                                0: Bool,
-                                /* offset = 1 */
-                                1: Bool,
-                            },
-                        },
-                        flow: Sink,
-                    },
-                    ty: Bundle {
-                        /* offset = 0 */
-                        addr: UInt<4>,
-                        /* offset = 4 */
-                        en: Bool,
-                        /* offset = 5 */
-                        clk: Clock,
-                        /* offset = 6 */
-                        data: Bundle {
-                            /* offset = 0 */
-                            0: UInt<8>,
-                            /* offset = 8 */
-                            1: SInt<8>,
-                        },
-                        /* offset = 22 */
-                        mask: Bundle {
-                            /* offset = 0 */
-                            0: Bool,
-                            /* offset = 1 */
-                            1: Bool,
-                        },
-                    },
-                },
-            ],
-            array_type: Array<Bundle {0: UInt<8>, 1: SInt<8>}, 16>,
-        },
-    },
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 22 μs,
-    clocks_triggered: [
-        StatePartIndex<SmallSlots>(1),
-        StatePartIndex<SmallSlots>(6),
-    ],
-    ..
-}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/memories.vcd b/crates/fayalite/tests/sim/expected/memories.vcd
deleted file mode 100644
index 72af410..0000000
--- a/crates/fayalite/tests/sim/expected/memories.vcd
+++ /dev/null
@@ -1,408 +0,0 @@
-$timescale 1 ps $end
-$scope module memories $end
-$scope struct r $end
-$var wire 4 ! addr $end
-$var wire 1 " en $end
-$var wire 1 # clk $end
-$scope struct data $end
-$var wire 8 $ \0 $end
-$var wire 8 % \1 $end
-$upscope $end
-$upscope $end
-$scope struct w $end
-$var wire 4 & addr $end
-$var wire 1 ' en $end
-$var wire 1 ( clk $end
-$scope struct data $end
-$var wire 8 ) \0 $end
-$var wire 8 * \1 $end
-$upscope $end
-$scope struct mask $end
-$var wire 1 + \0 $end
-$var wire 1 , \1 $end
-$upscope $end
-$upscope $end
-$scope struct mem $end
-$scope struct contents $end
-$scope struct [0] $end
-$scope struct mem $end
-$var reg 8 9 \0 $end
-$var reg 8 I \1 $end
-$upscope $end
-$upscope $end
-$scope struct [1] $end
-$scope struct mem $end
-$var reg 8 : \0 $end
-$var reg 8 J \1 $end
-$upscope $end
-$upscope $end
-$scope struct [2] $end
-$scope struct mem $end
-$var reg 8 ; \0 $end
-$var reg 8 K \1 $end
-$upscope $end
-$upscope $end
-$scope struct [3] $end
-$scope struct mem $end
-$var reg 8 < \0 $end
-$var reg 8 L \1 $end
-$upscope $end
-$upscope $end
-$scope struct [4] $end
-$scope struct mem $end
-$var reg 8 = \0 $end
-$var reg 8 M \1 $end
-$upscope $end
-$upscope $end
-$scope struct [5] $end
-$scope struct mem $end
-$var reg 8 > \0 $end
-$var reg 8 N \1 $end
-$upscope $end
-$upscope $end
-$scope struct [6] $end
-$scope struct mem $end
-$var reg 8 ? \0 $end
-$var reg 8 O \1 $end
-$upscope $end
-$upscope $end
-$scope struct [7] $end
-$scope struct mem $end
-$var reg 8 @ \0 $end
-$var reg 8 P \1 $end
-$upscope $end
-$upscope $end
-$scope struct [8] $end
-$scope struct mem $end
-$var reg 8 A \0 $end
-$var reg 8 Q \1 $end
-$upscope $end
-$upscope $end
-$scope struct [9] $end
-$scope struct mem $end
-$var reg 8 B \0 $end
-$var reg 8 R \1 $end
-$upscope $end
-$upscope $end
-$scope struct [10] $end
-$scope struct mem $end
-$var reg 8 C \0 $end
-$var reg 8 S \1 $end
-$upscope $end
-$upscope $end
-$scope struct [11] $end
-$scope struct mem $end
-$var reg 8 D \0 $end
-$var reg 8 T \1 $end
-$upscope $end
-$upscope $end
-$scope struct [12] $end
-$scope struct mem $end
-$var reg 8 E \0 $end
-$var reg 8 U \1 $end
-$upscope $end
-$upscope $end
-$scope struct [13] $end
-$scope struct mem $end
-$var reg 8 F \0 $end
-$var reg 8 V \1 $end
-$upscope $end
-$upscope $end
-$scope struct [14] $end
-$scope struct mem $end
-$var reg 8 G \0 $end
-$var reg 8 W \1 $end
-$upscope $end
-$upscope $end
-$scope struct [15] $end
-$scope struct mem $end
-$var reg 8 H \0 $end
-$var reg 8 X \1 $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct r0 $end
-$var wire 4 - addr $end
-$var wire 1 . en $end
-$var wire 1 / clk $end
-$scope struct data $end
-$var wire 8 0 \0 $end
-$var wire 8 1 \1 $end
-$upscope $end
-$upscope $end
-$scope struct w1 $end
-$var wire 4 2 addr $end
-$var wire 1 3 en $end
-$var wire 1 4 clk $end
-$scope struct data $end
-$var wire 8 5 \0 $end
-$var wire 8 6 \1 $end
-$upscope $end
-$scope struct mask $end
-$var wire 1 7 \0 $end
-$var wire 1 8 \1 $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-b1 9
-b100011 I
-b1 :
-b100011 J
-b1 ;
-b100011 K
-b1 <
-b100011 L
-b1 =
-b100011 M
-b1 >
-b100011 N
-b1 ?
-b100011 O
-b1 @
-b100011 P
-b1 A
-b100011 Q
-b1 B
-b100011 R
-b1 C
-b100011 S
-b1 D
-b100011 T
-b1 E
-b100011 U
-b1 F
-b100011 V
-b1 G
-b100011 W
-b1 H
-b100011 X
-b0 !
-0"
-0#
-b0 $
-b0 %
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diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt
deleted file mode 100644
index 5d90815..0000000
--- a/crates/fayalite/tests/sim/expected/memories2.txt
+++ /dev/null
@@ -1,1694 +0,0 @@
-Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 11,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome,
-                                },
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome,
-                                },
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 36,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.addr",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bool),
-                                },
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bool),
-                                },
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bool),
-                                },
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bool),
-                                },
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: ".0",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: ".1",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<1>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bool),
-                                },
-                            },
-                        ],
-                        ..
-                    },
-                },
-                memories: StatePartLayout<Memories> {
-                    len: 1,
-                    debug_data: [
-                        (),
-                    ],
-                    layout_data: [
-                        MemoryData {
-                            array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
-                            data: [
-                                // len = 0x5
-                                [0x0]: 0x3,
-                                [0x1]: 0x3,
-                                [0x2]: 0x3,
-                                [0x3]: 0x3,
-                                [0x4]: 0x3,
-                            ],
-                        },
-                    ],
-                    ..
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:13:1
-                0: Copy {
-                    dest: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                1: SliceInt {
-                    dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> },
-                    start: 1,
-                    len: 1,
-                },
-                2: Copy {
-                    dest: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                3: Const {
-                    dest: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                    value: 0x1,
-                },
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(28), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                5: Copy {
-                    dest: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                6: Copy {
-                    dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: ".1", ty: Bool },
-                },
-                7: Shl {
-                    dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                    rhs: 1,
-                },
-                8: Or {
-                    dest: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
-                    lhs: StatePartIndex<BigSlots>(26), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
-                    rhs: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                9: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(33), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
-                    dest_width: 2,
-                },
-                10: Copy {
-                    dest: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
-                    src: StatePartIndex<BigSlots>(34), // (0x1) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                11: SliceInt {
-                    dest: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", ty: UInt<2> },
-                    start: 0,
-                    len: 1,
-                },
-                12: Copy {
-                    dest: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                13: Const {
-                    dest: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                    value: 0x0,
-                },
-                14: Copy {
-                    dest: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
-                    src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:10:1
-                15: Copy {
-                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
-                    src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
-                },
-                // at: module-XXXXXXXXXX.rs:11:1
-                16: BranchIfZero {
-                    target: 18,
-                    value: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:12:1
-                17: Copy {
-                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
-                    src: StatePartIndex<BigSlots>(35), // (0x1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
-                },
-                // at: module-XXXXXXXXXX.rs:9:1
-                18: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool },
-                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:7:1
-                19: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock },
-                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.clk", ty: Clock },
-                },
-                // at: module-XXXXXXXXXX.rs:6:1
-                20: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.en", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:5:1
-                21: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> },
-                    src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.addr", ty: UInt<3> },
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                22: BranchIfSmallZero {
-                    target: 26,
-                    value: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                23: BranchIfSmallNonZero {
-                    target: 26,
-                    value: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                24: MemoryReadUInt {
-                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
-                            //     data: [
-                            //         // len = 0x5
-                            //         [0x0]: 0x0,
-                            //         [0x1]: 0x1,
-                            //         [0x2]: 0x0,
-                            //         [0x3]: 0x3,
-                            //         [0x4]: 0x0,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 2,
-                    start: 0,
-                    width: 2,
-                },
-                25: Branch {
-                    target: 27,
-                },
-                26: Const {
-                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
-                    value: 0x0,
-                },
-                27: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmode", ty: Bool },
-                },
-                28: CastBigToArrayIndex {
-                    dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.addr", ty: UInt<3> },
-                },
-                29: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.en", ty: Bool },
-                },
-                30: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.clk", ty: Clock },
-                },
-                31: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                32: Copy {
-                    dest: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
-                },
-                33: SliceInt {
-                    dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                    start: 1,
-                    len: 1,
-                },
-                34: Copy {
-                    dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                35: AndBigWithSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
-                    lhs: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                36: Copy {
-                    dest: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
-                },
-                37: SliceInt {
-                    dest: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                    start: 1,
-                    len: 1,
-                },
-                38: Copy {
-                    dest: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> },
-                },
-                // at: module-XXXXXXXXXX.rs:8:1
-                39: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata", ty: UInt<2> },
-                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "", ty: UInt<2> },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                40: AndBigWithSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
-                    lhs: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.rdata", ty: Enum {HdlNone, HdlSome(Bool)} },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:3:1
-                41: BranchIfSmallZero {
-                    target: 51,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                42: CopySmall {
-                    dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    src: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                },
-                43: CopySmall {
-                    dest: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(5), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                44: Copy {
-                    dest: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
-                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wdata", ty: Enum {HdlNone, HdlSome(Bool)} },
-                },
-                45: Copy {
-                    dest: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories2: memories2).memories2::mem::rw0.wmask", ty: Bool },
-                },
-                46: CopySmall {
-                    dest: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                47: BranchIfSmallZero {
-                    target: 51,
-                    value: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                48: BranchIfSmallZero {
-                    target: 51,
-                    value: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                49: BranchIfZero {
-                    target: 51,
-                    value: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "", ty: Bool },
-                },
-                50: MemoryWriteUInt {
-                    value: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(Bool)} },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
-                            //     data: [
-                            //         // len = 0x5
-                            //         [0x0]: 0x0,
-                            //         [0x1]: 0x1,
-                            //         [0x2]: 0x0,
-                            //         [0x3]: 0x3,
-                            //         [0x4]: 0x0,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 2,
-                    start: 0,
-                    width: 2,
-                },
-                51: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                52: Return,
-            ],
-            ..
-        },
-        pc: 52,
-        memory_write_log: [],
-        memories: StatePart {
-            value: [
-                MemoryData {
-                    array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
-                    data: [
-                        // len = 0x5
-                        [0x0]: 0x0,
-                        [0x1]: 0x1,
-                        [0x2]: 0x0,
-                        [0x3]: 0x3,
-                        [0x4]: 0x0,
-                    ],
-                },
-            ],
-        },
-        small_slots: StatePart {
-            value: [
-                0,
-                0,
-                1,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-            ],
-        },
-        big_slots: StatePart {
-            value: [
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                1,
-                0,
-                1,
-                0,
-                0,
-                0,
-                0,
-                1,
-                1,
-                1,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::memories2,
-        instantiated: Module {
-            name: memories2,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    addr: UInt<3>,
-                    /* offset = 3 */
-                    en: Bool,
-                    /* offset = 4 */
-                    clk: Clock,
-                    #[hdl(flip)] /* offset = 5 */
-                    rdata: UInt<2>,
-                    /* offset = 7 */
-                    wmode: Bool,
-                    /* offset = 8 */
-                    wdata: UInt<2>,
-                    /* offset = 10 */
-                    wmask: Bool,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 7,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.addr",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata",
-                                ty: UInt<2>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<3>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<3>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(1),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(2),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Clock,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Clock,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(3),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<2>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<2>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(4),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(5),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<2>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<2>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(6),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: Bool,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: Bool,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                    ],
-                },
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 7 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.addr: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<3>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.clk: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Clock,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Clock,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.en: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.rdata: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 3, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.wdata: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: UInt<2>,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<2>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 5, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.wmask: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 6, len: 1 },
-            },
-            write: None,
-        },
-        Instance {
-            name: <simulator>::memories2,
-            instantiated: Module {
-                name: memories2,
-                ..
-            },
-        }.rw.wmode: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bool,
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 1,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Scalar,
-            },
-            range: TypeIndexRange {
-                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
-            },
-            write: None,
-        },
-    },
-    made_initial_step: true,
-    needs_settle: false,
-    trace_decls: TraceModule {
-        name: "memories2",
-        children: [
-            TraceModuleIO {
-                name: "rw",
-                child: TraceBundle {
-                    name: "rw",
-                    fields: [
-                        TraceUInt {
-                            location: TraceScalarId(0),
-                            name: "addr",
-                            ty: UInt<3>,
-                            flow: Source,
-                        },
-                        TraceBool {
-                            location: TraceScalarId(1),
-                            name: "en",
-                            flow: Source,
-                        },
-                        TraceClock {
-                            location: TraceScalarId(2),
-                            name: "clk",
-                            flow: Source,
-                        },
-                        TraceUInt {
-                            location: TraceScalarId(3),
-                            name: "rdata",
-                            ty: UInt<2>,
-                            flow: Sink,
-                        },
-                        TraceBool {
-                            location: TraceScalarId(4),
-                            name: "wmode",
-                            flow: Source,
-                        },
-                        TraceUInt {
-                            location: TraceScalarId(5),
-                            name: "wdata",
-                            ty: UInt<2>,
-                            flow: Source,
-                        },
-                        TraceBool {
-                            location: TraceScalarId(6),
-                            name: "wmask",
-                            flow: Source,
-                        },
-                    ],
-                    ty: Bundle {
-                        /* offset = 0 */
-                        addr: UInt<3>,
-                        /* offset = 3 */
-                        en: Bool,
-                        /* offset = 4 */
-                        clk: Clock,
-                        #[hdl(flip)] /* offset = 5 */
-                        rdata: UInt<2>,
-                        /* offset = 7 */
-                        wmode: Bool,
-                        /* offset = 8 */
-                        wdata: UInt<2>,
-                        /* offset = 10 */
-                        wmask: Bool,
-                    },
-                    flow: Source,
-                },
-                ty: Bundle {
-                    /* offset = 0 */
-                    addr: UInt<3>,
-                    /* offset = 3 */
-                    en: Bool,
-                    /* offset = 4 */
-                    clk: Clock,
-                    #[hdl(flip)] /* offset = 5 */
-                    rdata: UInt<2>,
-                    /* offset = 7 */
-                    wmode: Bool,
-                    /* offset = 8 */
-                    wdata: UInt<2>,
-                    /* offset = 10 */
-                    wmask: Bool,
-                },
-                flow: Source,
-            },
-            TraceMem {
-                id: TraceMemoryId(0),
-                name: "mem",
-                stride: 2,
-                element_type: TraceEnumWithFields {
-                    name: "mem",
-                    discriminant: TraceEnumDiscriminant {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 5,
-                            stride: 2,
-                            start: 0,
-                            len: 1,
-                        },
-                        name: "$tag",
-                        ty: Enum {
-                            HdlNone,
-                            HdlSome(Bool),
-                        },
-                        flow: Duplex,
-                    },
-                    non_empty_fields: [
-                        TraceBool {
-                            location: TraceMemoryLocation {
-                                id: TraceMemoryId(0),
-                                depth: 5,
-                                stride: 2,
-                                start: 1,
-                                len: 1,
-                            },
-                            name: "HdlSome",
-                            flow: Duplex,
-                        },
-                    ],
-                    ty: Enum {
-                        HdlNone,
-                        HdlSome(Bool),
-                    },
-                    flow: Duplex,
-                },
-                ports: [
-                    TraceMemPort {
-                        name: "rw0",
-                        bundle: TraceBundle {
-                            name: "rw0",
-                            fields: [
-                                TraceUInt {
-                                    location: TraceScalarId(7),
-                                    name: "addr",
-                                    ty: UInt<3>,
-                                    flow: Sink,
-                                },
-                                TraceBool {
-                                    location: TraceScalarId(8),
-                                    name: "en",
-                                    flow: Sink,
-                                },
-                                TraceClock {
-                                    location: TraceScalarId(9),
-                                    name: "clk",
-                                    flow: Sink,
-                                },
-                                TraceEnumWithFields {
-                                    name: "rdata",
-                                    discriminant: TraceEnumDiscriminant {
-                                        location: TraceScalarId(10),
-                                        name: "$tag",
-                                        ty: Enum {
-                                            HdlNone,
-                                            HdlSome(Bool),
-                                        },
-                                        flow: Source,
-                                    },
-                                    non_empty_fields: [
-                                        TraceBool {
-                                            location: TraceScalarId(11),
-                                            name: "HdlSome",
-                                            flow: Source,
-                                        },
-                                    ],
-                                    ty: Enum {
-                                        HdlNone,
-                                        HdlSome(Bool),
-                                    },
-                                    flow: Source,
-                                },
-                                TraceBool {
-                                    location: TraceScalarId(12),
-                                    name: "wmode",
-                                    flow: Sink,
-                                },
-                                TraceEnumWithFields {
-                                    name: "wdata",
-                                    discriminant: TraceEnumDiscriminant {
-                                        location: TraceScalarId(13),
-                                        name: "$tag",
-                                        ty: Enum {
-                                            HdlNone,
-                                            HdlSome(Bool),
-                                        },
-                                        flow: Sink,
-                                    },
-                                    non_empty_fields: [
-                                        TraceBool {
-                                            location: TraceScalarId(14),
-                                            name: "HdlSome",
-                                            flow: Source,
-                                        },
-                                    ],
-                                    ty: Enum {
-                                        HdlNone,
-                                        HdlSome(Bool),
-                                    },
-                                    flow: Sink,
-                                },
-                                TraceBool {
-                                    location: TraceScalarId(15),
-                                    name: "wmask",
-                                    flow: Sink,
-                                },
-                            ],
-                            ty: Bundle {
-                                /* offset = 0 */
-                                addr: UInt<3>,
-                                /* offset = 3 */
-                                en: Bool,
-                                /* offset = 4 */
-                                clk: Clock,
-                                #[hdl(flip)] /* offset = 5 */
-                                rdata: Enum {
-                                    HdlNone,
-                                    HdlSome(Bool),
-                                },
-                                /* offset = 7 */
-                                wmode: Bool,
-                                /* offset = 8 */
-                                wdata: Enum {
-                                    HdlNone,
-                                    HdlSome(Bool),
-                                },
-                                /* offset = 10 */
-                                wmask: Bool,
-                            },
-                            flow: Sink,
-                        },
-                        ty: Bundle {
-                            /* offset = 0 */
-                            addr: UInt<3>,
-                            /* offset = 3 */
-                            en: Bool,
-                            /* offset = 4 */
-                            clk: Clock,
-                            #[hdl(flip)] /* offset = 5 */
-                            rdata: Enum {
-                                HdlNone,
-                                HdlSome(Bool),
-                            },
-                            /* offset = 7 */
-                            wmode: Bool,
-                            /* offset = 8 */
-                            wdata: Enum {
-                                HdlNone,
-                                HdlSome(Bool),
-                            },
-                            /* offset = 10 */
-                            wmask: Bool,
-                        },
-                    },
-                ],
-                array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
-            },
-        ],
-    },
-    traces: [
-        SimTrace {
-            id: TraceScalarId(0),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(0),
-                ty: UInt<3>,
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(1),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(1),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(2),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(2),
-            },
-            state: 0x0,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(3),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(3),
-                ty: UInt<2>,
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(4),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(4),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(5),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(5),
-                ty: UInt<2>,
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(6),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(6),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(7),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(7),
-                ty: UInt<3>,
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(8),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(8),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(9),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(9),
-            },
-            state: 0x0,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(10),
-            kind: EnumDiscriminant {
-                index: StatePartIndex<SmallSlots>(0),
-                ty: Enum {
-                    HdlNone,
-                    HdlSome(Bool),
-                },
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(11),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(16),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(12),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(11),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(13),
-            kind: EnumDiscriminant {
-                index: StatePartIndex<SmallSlots>(1),
-                ty: Enum {
-                    HdlNone,
-                    HdlSome(Bool),
-                },
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(14),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(19),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(15),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(13),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-    ],
-    trace_memories: {
-        StatePartIndex<Memories>(0): TraceMem {
-            id: TraceMemoryId(0),
-            name: "mem",
-            stride: 2,
-            element_type: TraceEnumWithFields {
-                name: "mem",
-                discriminant: TraceEnumDiscriminant {
-                    location: TraceMemoryLocation {
-                        id: TraceMemoryId(0),
-                        depth: 5,
-                        stride: 2,
-                        start: 0,
-                        len: 1,
-                    },
-                    name: "$tag",
-                    ty: Enum {
-                        HdlNone,
-                        HdlSome(Bool),
-                    },
-                    flow: Duplex,
-                },
-                non_empty_fields: [
-                    TraceBool {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 5,
-                            stride: 2,
-                            start: 1,
-                            len: 1,
-                        },
-                        name: "HdlSome",
-                        flow: Duplex,
-                    },
-                ],
-                ty: Enum {
-                    HdlNone,
-                    HdlSome(Bool),
-                },
-                flow: Duplex,
-            },
-            ports: [
-                TraceMemPort {
-                    name: "rw0",
-                    bundle: TraceBundle {
-                        name: "rw0",
-                        fields: [
-                            TraceUInt {
-                                location: TraceScalarId(7),
-                                name: "addr",
-                                ty: UInt<3>,
-                                flow: Sink,
-                            },
-                            TraceBool {
-                                location: TraceScalarId(8),
-                                name: "en",
-                                flow: Sink,
-                            },
-                            TraceClock {
-                                location: TraceScalarId(9),
-                                name: "clk",
-                                flow: Sink,
-                            },
-                            TraceEnumWithFields {
-                                name: "rdata",
-                                discriminant: TraceEnumDiscriminant {
-                                    location: TraceScalarId(10),
-                                    name: "$tag",
-                                    ty: Enum {
-                                        HdlNone,
-                                        HdlSome(Bool),
-                                    },
-                                    flow: Source,
-                                },
-                                non_empty_fields: [
-                                    TraceBool {
-                                        location: TraceScalarId(11),
-                                        name: "HdlSome",
-                                        flow: Source,
-                                    },
-                                ],
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bool),
-                                },
-                                flow: Source,
-                            },
-                            TraceBool {
-                                location: TraceScalarId(12),
-                                name: "wmode",
-                                flow: Sink,
-                            },
-                            TraceEnumWithFields {
-                                name: "wdata",
-                                discriminant: TraceEnumDiscriminant {
-                                    location: TraceScalarId(13),
-                                    name: "$tag",
-                                    ty: Enum {
-                                        HdlNone,
-                                        HdlSome(Bool),
-                                    },
-                                    flow: Sink,
-                                },
-                                non_empty_fields: [
-                                    TraceBool {
-                                        location: TraceScalarId(14),
-                                        name: "HdlSome",
-                                        flow: Source,
-                                    },
-                                ],
-                                ty: Enum {
-                                    HdlNone,
-                                    HdlSome(Bool),
-                                },
-                                flow: Sink,
-                            },
-                            TraceBool {
-                                location: TraceScalarId(15),
-                                name: "wmask",
-                                flow: Sink,
-                            },
-                        ],
-                        ty: Bundle {
-                            /* offset = 0 */
-                            addr: UInt<3>,
-                            /* offset = 3 */
-                            en: Bool,
-                            /* offset = 4 */
-                            clk: Clock,
-                            #[hdl(flip)] /* offset = 5 */
-                            rdata: Enum {
-                                HdlNone,
-                                HdlSome(Bool),
-                            },
-                            /* offset = 7 */
-                            wmode: Bool,
-                            /* offset = 8 */
-                            wdata: Enum {
-                                HdlNone,
-                                HdlSome(Bool),
-                            },
-                            /* offset = 10 */
-                            wmask: Bool,
-                        },
-                        flow: Sink,
-                    },
-                    ty: Bundle {
-                        /* offset = 0 */
-                        addr: UInt<3>,
-                        /* offset = 3 */
-                        en: Bool,
-                        /* offset = 4 */
-                        clk: Clock,
-                        #[hdl(flip)] /* offset = 5 */
-                        rdata: Enum {
-                            HdlNone,
-                            HdlSome(Bool),
-                        },
-                        /* offset = 7 */
-                        wmode: Bool,
-                        /* offset = 8 */
-                        wdata: Enum {
-                            HdlNone,
-                            HdlSome(Bool),
-                        },
-                        /* offset = 10 */
-                        wmask: Bool,
-                    },
-                },
-            ],
-            array_type: Array<Enum {HdlNone, HdlSome(Bool)}, 5>,
-        },
-    },
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 22 μs,
-    clocks_triggered: [
-        StatePartIndex<SmallSlots>(3),
-    ],
-    ..
-}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/memories2.vcd b/crates/fayalite/tests/sim/expected/memories2.vcd
deleted file mode 100644
index bd48f24..0000000
--- a/crates/fayalite/tests/sim/expected/memories2.vcd
+++ /dev/null
@@ -1,363 +0,0 @@
-$timescale 1 ps $end
-$scope module memories2 $end
-$scope struct rw $end
-$var wire 3 ! addr $end
-$var wire 1 " en $end
-$var wire 1 # clk $end
-$var wire 2 $ rdata $end
-$var wire 1 % wmode $end
-$var wire 2 & wdata $end
-$var wire 1 ' wmask $end
-$upscope $end
-$scope struct mem $end
-$scope struct contents $end
-$scope struct [0] $end
-$scope struct mem $end
-$var string 1 1 \$tag $end
-$var reg 1 6 HdlSome $end
-$upscope $end
-$upscope $end
-$scope struct [1] $end
-$scope struct mem $end
-$var string 1 2 \$tag $end
-$var reg 1 7 HdlSome $end
-$upscope $end
-$upscope $end
-$scope struct [2] $end
-$scope struct mem $end
-$var string 1 3 \$tag $end
-$var reg 1 8 HdlSome $end
-$upscope $end
-$upscope $end
-$scope struct [3] $end
-$scope struct mem $end
-$var string 1 4 \$tag $end
-$var reg 1 9 HdlSome $end
-$upscope $end
-$upscope $end
-$scope struct [4] $end
-$scope struct mem $end
-$var string 1 5 \$tag $end
-$var reg 1 : HdlSome $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct rw0 $end
-$var wire 3 ( addr $end
-$var wire 1 ) en $end
-$var wire 1 * clk $end
-$scope struct rdata $end
-$var string 1 + \$tag $end
-$var wire 1 , HdlSome $end
-$upscope $end
-$var wire 1 - wmode $end
-$scope struct wdata $end
-$var string 1 . \$tag $end
-$var wire 1 / HdlSome $end
-$upscope $end
-$var wire 1 0 wmask $end
-$upscope $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-sHdlSome\x20(1) 1
-16
-sHdlSome\x20(1) 2
-17
-sHdlSome\x20(1) 3
-18
-sHdlSome\x20(1) 4
-19
-sHdlSome\x20(1) 5
-1:
-b0 !
-0"
-0#
-b0 $
-0%
-b0 &
-0'
-b0 (
-0)
-0*
-sHdlNone\x20(0) +
-0,
-0-
-sHdlNone\x20(0) .
-0/
-00
-$end
-#250000
-1#
-1*
-#500000
-#750000
-0#
-0*
-#1000000
-1"
-1)
-#1250000
-1#
-1*
-b11 $
-sHdlSome\x20(1) +
-1,
-#1500000
-#1750000
-0#
-0*
-#2000000
-0"
-0)
-#2250000
-1#
-1*
-b0 $
-sHdlNone\x20(0) +
-0,
-#2500000
-#2750000
-0#
-0*
-#3000000
-1"
-1%
-1'
-1)
-1-
-10
-#3250000
-sHdlNone\x20(0) 1
-06
-1#
-1*
-#3500000
-#3750000
-0#
-0*
-#4000000
-0%
-0'
-0-
-00
-#4250000
-1#
-1*
-#4500000
-#4750000
-0#
-0*
-#5000000
-1%
-b11 &
-1-
-sHdlSome\x20(1) .
-1/
-#5250000
-1#
-1*
-#5500000
-#5750000
-0#
-0*
-#6000000
-b1 !
-b1 &
-1'
-b1 (
-0/
-10
-#6250000
-sHdlSome\x20(1) 2
-07
-1#
-1*
-#6500000
-#6750000
-0#
-0*
-#7000000
-b10 !
-b10 &
-b10 (
-sHdlNone\x20(0) .
-#7250000
-sHdlNone\x20(0) 3
-08
-1#
-1*
-#7500000
-#7750000
-0#
-0*
-#8000000
-b11 !
-b11 &
-b11 (
-sHdlSome\x20(1) .
-1/
-#8250000
-sHdlSome\x20(1) 4
-19
-1#
-1*
-#8500000
-#8750000
-0#
-0*
-#9000000
-b100 !
-b10 &
-b100 (
-sHdlNone\x20(0) .
-0/
-#9250000
-sHdlNone\x20(0) 5
-0:
-1#
-1*
-#9500000
-#9750000
-0#
-0*
-#10000000
-b101 !
-b1 &
-b101 (
-sHdlSome\x20(1) .
-#10250000
-1#
-1*
-#10500000
-#10750000
-0#
-0*
-#11000000
-b110 !
-b110 (
-#11250000
-1#
-1*
-#11500000
-#11750000
-0#
-0*
-#12000000
-b111 !
-b111 (
-#12250000
-1#
-1*
-#12500000
-#12750000
-0#
-0*
-#13000000
-0%
-b0 &
-0'
-0-
-sHdlNone\x20(0) .
-00
-#13250000
-1#
-1*
-#13500000
-#13750000
-0#
-0*
-#14000000
-b110 !
-b110 (
-#14250000
-1#
-1*
-#14500000
-#14750000
-0#
-0*
-#15000000
-b101 !
-b101 (
-#15250000
-1#
-1*
-#15500000
-#15750000
-0#
-0*
-#16000000
-b100 !
-b100 (
-#16250000
-1#
-1*
-#16500000
-#16750000
-0#
-0*
-#17000000
-b11 !
-b11 (
-#17250000
-1#
-1*
-b11 $
-sHdlSome\x20(1) +
-1,
-#17500000
-#17750000
-0#
-0*
-#18000000
-b10 !
-b10 (
-#18250000
-1#
-1*
-b0 $
-sHdlNone\x20(0) +
-0,
-#18500000
-#18750000
-0#
-0*
-#19000000
-b0 !
-b0 (
-#19250000
-1#
-1*
-#19500000
-#19750000
-0#
-0*
-#20000000
-b1 !
-b1 (
-#20250000
-1#
-1*
-b1 $
-sHdlSome\x20(1) +
-#20500000
-#20750000
-0#
-0*
-#21000000
-b0 !
-0"
-b0 (
-0)
-#21250000
-1#
-1*
-b0 $
-sHdlNone\x20(0) +
-#21500000
-#21750000
-0#
-0*
-#22000000
diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt
deleted file mode 100644
index 7860bc5..0000000
--- a/crates/fayalite/tests/sim/expected/memories3.txt
+++ /dev/null
@@ -1,4882 +0,0 @@
-Simulation {
-    state: State {
-        insns: Insns {
-            state_layout: StateLayout {
-                ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 14,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 108,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.addr",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.addr",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[7]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[7]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[7]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[7]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "[0]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[1]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[2]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[3]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[4]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[5]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[6]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[7]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[0]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[1]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[2]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[3]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[4]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[5]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[6]",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "[7]",
-                                ty: Bool,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                memories: StatePartLayout<Memories> {
-                    len: 1,
-                    debug_data: [
-                        (),
-                    ],
-                    layout_data: [
-                        MemoryData {
-                            array_type: Array<Array<UInt<8>, 8>, 8>,
-                            data: [
-                                // len = 0x8
-                                [0x0]: 0x0000000000000000,
-                                [0x1]: 0x0000000000000000,
-                                [0x2]: 0x0000000000000000,
-                                [0x3]: 0x0000000000000000,
-                                [0x4]: 0x0000000000000000,
-                                [0x5]: 0x0000000000000000,
-                                [0x6]: 0x0000000000000000,
-                                [0x7]: 0x0000000000000000,
-                            ],
-                        },
-                    ],
-                    ..
-                },
-            },
-            insns: [
-                // at: module-XXXXXXXXXX.rs:8:1
-                0: Copy {
-                    dest: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr", ty: UInt<3> },
-                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.addr", ty: UInt<3> },
-                },
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(58), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en", ty: Bool },
-                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.en", ty: Bool },
-                },
-                2: Copy {
-                    dest: StatePartIndex<BigSlots>(59), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk", ty: Clock },
-                    src: StatePartIndex<BigSlots>(13), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.clk", ty: Clock },
-                },
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(60), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(14), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]", ty: UInt<8> },
-                },
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(61), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(15), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]", ty: UInt<8> },
-                },
-                5: Copy {
-                    dest: StatePartIndex<BigSlots>(62), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(16), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]", ty: UInt<8> },
-                },
-                6: Copy {
-                    dest: StatePartIndex<BigSlots>(63), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(17), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]", ty: UInt<8> },
-                },
-                7: Copy {
-                    dest: StatePartIndex<BigSlots>(64), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]", ty: UInt<8> },
-                },
-                8: Copy {
-                    dest: StatePartIndex<BigSlots>(65), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]", ty: UInt<8> },
-                },
-                9: Copy {
-                    dest: StatePartIndex<BigSlots>(66), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(20), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]", ty: UInt<8> },
-                },
-                10: Copy {
-                    dest: StatePartIndex<BigSlots>(67), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(21), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]", ty: UInt<8> },
-                },
-                11: Copy {
-                    dest: StatePartIndex<BigSlots>(68), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(22), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]", ty: Bool },
-                },
-                12: Copy {
-                    dest: StatePartIndex<BigSlots>(69), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(23), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]", ty: Bool },
-                },
-                13: Copy {
-                    dest: StatePartIndex<BigSlots>(70), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(24), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]", ty: Bool },
-                },
-                14: Copy {
-                    dest: StatePartIndex<BigSlots>(71), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(25), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]", ty: Bool },
-                },
-                15: Copy {
-                    dest: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(26), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]", ty: Bool },
-                },
-                16: Copy {
-                    dest: StatePartIndex<BigSlots>(73), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(27), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]", ty: Bool },
-                },
-                17: Copy {
-                    dest: StatePartIndex<BigSlots>(74), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(28), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]", ty: Bool },
-                },
-                18: Copy {
-                    dest: StatePartIndex<BigSlots>(75), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]", ty: Bool },
-                },
-                // at: module-XXXXXXXXXX.rs:6:1
-                19: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]", ty: UInt<8> },
-                },
-                20: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]", ty: UInt<8> },
-                },
-                21: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]", ty: UInt<8> },
-                },
-                22: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]", ty: UInt<8> },
-                },
-                23: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]", ty: UInt<8> },
-                },
-                24: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]", ty: UInt<8> },
-                },
-                25: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]", ty: UInt<8> },
-                },
-                26: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]", ty: UInt<8> },
-                },
-                27: Copy {
-                    dest: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk", ty: Clock },
-                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.clk", ty: Clock },
-                },
-                28: Copy {
-                    dest: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.en", ty: Bool },
-                },
-                29: Copy {
-                    dest: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr", ty: UInt<3> },
-                    src: StatePartIndex<BigSlots>(0), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::r.addr", ty: UInt<3> },
-                },
-                // at: module-XXXXXXXXXX.rs:4:1
-                30: CastBigToArrayIndex {
-                    dest: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    src: StatePartIndex<BigSlots>(57), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.addr", ty: UInt<3> },
-                },
-                31: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(58), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.en", ty: Bool },
-                },
-                32: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(59), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.clk", ty: Clock },
-                },
-                33: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                },
-                34: CastBigToArrayIndex {
-                    dest: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    src: StatePartIndex<BigSlots>(30), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.addr", ty: UInt<3> },
-                },
-                35: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(31), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.en", ty: Bool },
-                },
-                36: BranchIfSmallZero {
-                    target: 46,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                37: MemoryReadUInt {
-                    dest: StatePartIndex<BigSlots>(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 0,
-                    width: 8,
-                },
-                38: MemoryReadUInt {
-                    dest: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 8,
-                    width: 8,
-                },
-                39: MemoryReadUInt {
-                    dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 16,
-                    width: 8,
-                },
-                40: MemoryReadUInt {
-                    dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 24,
-                    width: 8,
-                },
-                41: MemoryReadUInt {
-                    dest: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 32,
-                    width: 8,
-                },
-                42: MemoryReadUInt {
-                    dest: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 40,
-                    width: 8,
-                },
-                43: MemoryReadUInt {
-                    dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 48,
-                    width: 8,
-                },
-                44: MemoryReadUInt {
-                    dest: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 56,
-                    width: 8,
-                },
-                45: Branch {
-                    target: 54,
-                },
-                46: Const {
-                    dest: StatePartIndex<BigSlots>(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
-                    value: 0x0,
-                },
-                47: Const {
-                    dest: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
-                    value: 0x0,
-                },
-                48: Const {
-                    dest: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
-                    value: 0x0,
-                },
-                49: Const {
-                    dest: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
-                    value: 0x0,
-                },
-                50: Const {
-                    dest: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
-                    value: 0x0,
-                },
-                51: Const {
-                    dest: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
-                    value: 0x0,
-                },
-                52: Const {
-                    dest: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
-                    value: 0x0,
-                },
-                53: Const {
-                    dest: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
-                    value: 0x0,
-                },
-                54: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(32), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.clk", ty: Clock },
-                },
-                55: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                },
-                56: BranchIfSmallZero {
-                    target: 73,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                57: Copy {
-                    dest: StatePartIndex<BigSlots>(33), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[0]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
-                },
-                58: Copy {
-                    dest: StatePartIndex<BigSlots>(34), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[1]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
-                },
-                59: Copy {
-                    dest: StatePartIndex<BigSlots>(35), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[2]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
-                },
-                60: Copy {
-                    dest: StatePartIndex<BigSlots>(36), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[3]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(52), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
-                },
-                61: Copy {
-                    dest: StatePartIndex<BigSlots>(37), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[4]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
-                },
-                62: Copy {
-                    dest: StatePartIndex<BigSlots>(38), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[5]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
-                },
-                63: Copy {
-                    dest: StatePartIndex<BigSlots>(39), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[6]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
-                },
-                64: Copy {
-                    dest: StatePartIndex<BigSlots>(40), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::r0.data[7]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(56), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
-                },
-                65: Copy {
-                    dest: StatePartIndex<BigSlots>(49), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(41), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
-                },
-                66: Copy {
-                    dest: StatePartIndex<BigSlots>(50), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(42), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
-                },
-                67: Copy {
-                    dest: StatePartIndex<BigSlots>(51), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(43), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
-                },
-                68: Copy {
-                    dest: StatePartIndex<BigSlots>(52), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(44), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
-                },
-                69: Copy {
-                    dest: StatePartIndex<BigSlots>(53), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(45), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
-                },
-                70: Copy {
-                    dest: StatePartIndex<BigSlots>(54), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(46), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
-                },
-                71: Copy {
-                    dest: StatePartIndex<BigSlots>(55), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(47), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
-                },
-                72: Copy {
-                    dest: StatePartIndex<BigSlots>(56), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(48), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
-                },
-                73: BranchIfSmallZero {
-                    target: 127,
-                    value: StatePartIndex<SmallSlots>(6), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                74: CopySmall {
-                    dest: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    src: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                },
-                75: CopySmall {
-                    dest: StatePartIndex<SmallSlots>(10), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    src: StatePartIndex<SmallSlots>(9), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                },
-                76: CopySmall {
-                    dest: StatePartIndex<SmallSlots>(13), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(12), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                77: CopySmall {
-                    dest: StatePartIndex<SmallSlots>(12), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<SmallSlots>(8), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                78: Copy {
-                    dest: StatePartIndex<BigSlots>(84), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(76), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
-                },
-                79: Copy {
-                    dest: StatePartIndex<BigSlots>(85), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(77), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
-                },
-                80: Copy {
-                    dest: StatePartIndex<BigSlots>(86), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(78), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
-                },
-                81: Copy {
-                    dest: StatePartIndex<BigSlots>(87), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(79), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
-                },
-                82: Copy {
-                    dest: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
-                },
-                83: Copy {
-                    dest: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
-                },
-                84: Copy {
-                    dest: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
-                },
-                85: Copy {
-                    dest: StatePartIndex<BigSlots>(91), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(83), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
-                },
-                86: Copy {
-                    dest: StatePartIndex<BigSlots>(76), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(60), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[0]", ty: UInt<8> },
-                },
-                87: Copy {
-                    dest: StatePartIndex<BigSlots>(77), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(61), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[1]", ty: UInt<8> },
-                },
-                88: Copy {
-                    dest: StatePartIndex<BigSlots>(78), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(62), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[2]", ty: UInt<8> },
-                },
-                89: Copy {
-                    dest: StatePartIndex<BigSlots>(79), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(63), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[3]", ty: UInt<8> },
-                },
-                90: Copy {
-                    dest: StatePartIndex<BigSlots>(80), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(64), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[4]", ty: UInt<8> },
-                },
-                91: Copy {
-                    dest: StatePartIndex<BigSlots>(81), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(65), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[5]", ty: UInt<8> },
-                },
-                92: Copy {
-                    dest: StatePartIndex<BigSlots>(82), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(66), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[6]", ty: UInt<8> },
-                },
-                93: Copy {
-                    dest: StatePartIndex<BigSlots>(83), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
-                    src: StatePartIndex<BigSlots>(67), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.data[7]", ty: UInt<8> },
-                },
-                94: Copy {
-                    dest: StatePartIndex<BigSlots>(100), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(92), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
-                },
-                95: Copy {
-                    dest: StatePartIndex<BigSlots>(101), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(93), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
-                },
-                96: Copy {
-                    dest: StatePartIndex<BigSlots>(102), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(94), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
-                },
-                97: Copy {
-                    dest: StatePartIndex<BigSlots>(103), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(95), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
-                },
-                98: Copy {
-                    dest: StatePartIndex<BigSlots>(104), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(96), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
-                },
-                99: Copy {
-                    dest: StatePartIndex<BigSlots>(105), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(97), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
-                },
-                100: Copy {
-                    dest: StatePartIndex<BigSlots>(106), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(98), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
-                },
-                101: Copy {
-                    dest: StatePartIndex<BigSlots>(107), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(99), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
-                },
-                102: Copy {
-                    dest: StatePartIndex<BigSlots>(92), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(68), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[0]", ty: Bool },
-                },
-                103: Copy {
-                    dest: StatePartIndex<BigSlots>(93), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(69), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[1]", ty: Bool },
-                },
-                104: Copy {
-                    dest: StatePartIndex<BigSlots>(94), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(70), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[2]", ty: Bool },
-                },
-                105: Copy {
-                    dest: StatePartIndex<BigSlots>(95), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(71), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[3]", ty: Bool },
-                },
-                106: Copy {
-                    dest: StatePartIndex<BigSlots>(96), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(72), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[4]", ty: Bool },
-                },
-                107: Copy {
-                    dest: StatePartIndex<BigSlots>(97), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(73), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[5]", ty: Bool },
-                },
-                108: Copy {
-                    dest: StatePartIndex<BigSlots>(98), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(74), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[6]", ty: Bool },
-                },
-                109: Copy {
-                    dest: StatePartIndex<BigSlots>(99), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
-                    src: StatePartIndex<BigSlots>(75), // (0x0) SlotDebugData { name: "InstantiatedModule(memories3: memories3).memories3::mem::w1.mask[7]", ty: Bool },
-                },
-                110: BranchIfSmallZero {
-                    target: 127,
-                    value: StatePartIndex<SmallSlots>(13), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                },
-                111: BranchIfZero {
-                    target: 113,
-                    value: StatePartIndex<BigSlots>(100), // (0x0) SlotDebugData { name: "[0]", ty: Bool },
-                },
-                112: MemoryWriteUInt {
-                    value: StatePartIndex<BigSlots>(84), // (0x0) SlotDebugData { name: "[0]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 0,
-                    width: 8,
-                },
-                113: BranchIfZero {
-                    target: 115,
-                    value: StatePartIndex<BigSlots>(101), // (0x0) SlotDebugData { name: "[1]", ty: Bool },
-                },
-                114: MemoryWriteUInt {
-                    value: StatePartIndex<BigSlots>(85), // (0x0) SlotDebugData { name: "[1]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 8,
-                    width: 8,
-                },
-                115: BranchIfZero {
-                    target: 117,
-                    value: StatePartIndex<BigSlots>(102), // (0x0) SlotDebugData { name: "[2]", ty: Bool },
-                },
-                116: MemoryWriteUInt {
-                    value: StatePartIndex<BigSlots>(86), // (0x0) SlotDebugData { name: "[2]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 16,
-                    width: 8,
-                },
-                117: BranchIfZero {
-                    target: 119,
-                    value: StatePartIndex<BigSlots>(103), // (0x0) SlotDebugData { name: "[3]", ty: Bool },
-                },
-                118: MemoryWriteUInt {
-                    value: StatePartIndex<BigSlots>(87), // (0x0) SlotDebugData { name: "[3]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 24,
-                    width: 8,
-                },
-                119: BranchIfZero {
-                    target: 121,
-                    value: StatePartIndex<BigSlots>(104), // (0x0) SlotDebugData { name: "[4]", ty: Bool },
-                },
-                120: MemoryWriteUInt {
-                    value: StatePartIndex<BigSlots>(88), // (0x0) SlotDebugData { name: "[4]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 32,
-                    width: 8,
-                },
-                121: BranchIfZero {
-                    target: 123,
-                    value: StatePartIndex<BigSlots>(105), // (0x0) SlotDebugData { name: "[5]", ty: Bool },
-                },
-                122: MemoryWriteUInt {
-                    value: StatePartIndex<BigSlots>(89), // (0x0) SlotDebugData { name: "[5]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 40,
-                    width: 8,
-                },
-                123: BranchIfZero {
-                    target: 125,
-                    value: StatePartIndex<BigSlots>(106), // (0x0) SlotDebugData { name: "[6]", ty: Bool },
-                },
-                124: MemoryWriteUInt {
-                    value: StatePartIndex<BigSlots>(90), // (0x0) SlotDebugData { name: "[6]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 48,
-                    width: 8,
-                },
-                125: BranchIfZero {
-                    target: 127,
-                    value: StatePartIndex<BigSlots>(107), // (0x0) SlotDebugData { name: "[7]", ty: Bool },
-                },
-                126: MemoryWriteUInt {
-                    value: StatePartIndex<BigSlots>(91), // (0x0) SlotDebugData { name: "[7]", ty: UInt<8> },
-                    memory: StatePartIndex<Memories>(0), // (MemoryData {
-                            //     array_type: Array<Array<UInt<8>, 8>, 8>,
-                            //     data: [
-                            //         // len = 0x8
-                            //         [0x0]: 0x1032547698badcfe,
-                            //         [0x1]: 0xce8a4602df9b5713,
-                            //         [0x2]: 0x21676e6974736574,
-                            //         [0x3]: 0x7473742065726f6d,
-                            //         [0x4]: 0x0000000000000000,
-                            //         [0x5]: 0x0000000000000000,
-                            //         [0x6]: 0x0000000000000000,
-                            //         [0x7]: 0x0000000000000000,
-                            //     ],
-                            // }) (),
-                    addr: StatePartIndex<SmallSlots>(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<3> },
-                    stride: 64,
-                    start: 56,
-                    width: 8,
-                },
-                127: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
-                },
-                128: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(5), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(7), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
-                },
-                // at: module-XXXXXXXXXX.rs:1:1
-                129: Return,
-            ],
-            ..
-        },
-        pc: 129,
-        memory_write_log: [],
-        memories: StatePart {
-            value: [
-                MemoryData {
-                    array_type: Array<Array<UInt<8>, 8>, 8>,
-                    data: [
-                        // len = 0x8
-                        [0x0]: 0x1032547698badcfe,
-                        [0x1]: 0xce8a4602df9b5713,
-                        [0x2]: 0x21676e6974736574,
-                        [0x3]: 0x7473742065726f6d,
-                        [0x4]: 0x0000000000000000,
-                        [0x5]: 0x0000000000000000,
-                        [0x6]: 0x0000000000000000,
-                        [0x7]: 0x0000000000000000,
-                    ],
-                },
-            ],
-        },
-        small_slots: StatePart {
-            value: [
-                1,
-                0,
-                0,
-                0,
-                0,
-                1,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-            ],
-        },
-        big_slots: StatePart {
-            value: [
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-                0,
-            ],
-        },
-    },
-    io: Instance {
-        name: <simulator>::memories3,
-        instantiated: Module {
-            name: memories3,
-            ..
-        },
-    },
-    uninitialized_inputs: {},
-    io_targets: {
-        Instance {
-            name: <simulator>::memories3,
-            instantiated: Module {
-                name: memories3,
-                ..
-            },
-        }.r: CompiledValue {
-            layout: CompiledTypeLayout {
-                ty: Bundle {
-                    /* offset = 0 */
-                    addr: UInt<3>,
-                    /* offset = 3 */
-                    en: Bool,
-                    /* offset = 4 */
-                    clk: Clock,
-                    #[hdl(flip)] /* offset = 5 */
-                    data: Array<UInt<8>, 8>,
-                },
-                layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
-                        len: 0,
-                        debug_data: [],
-                        ..
-                    },
-                    big_slots: StatePartLayout<BigSlots> {
-                        len: 11,
-                        debug_data: [
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.addr",
-                                ty: UInt<3>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.en",
-                                ty: Bool,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.clk",
-                                ty: Clock,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]",
-                                ty: UInt<8>,
-                            },
-                            SlotDebugData {
-                                name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]",
-                                ty: UInt<8>,
-                            },
-                        ],
-                        ..
-                    },
-                },
-                body: Bundle {
-                    fields: [
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
-                                big_slots: StatePartIndex<BigSlots>(0),
-                            },
-                            ty: CompiledTypeLayout {
-                                ty: UInt<3>,
-                                layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
-                                        len: 0,
-                                        debug_data: [],
-                                        ..
-                                    },
-                                    big_slots: StatePartLayout<BigSlots> {
-                                        len: 1,
-                                        debug_data: [
-                                            SlotDebugData {
-                                                name: "",
-                                                ty: UInt<3>,
-                                            },
-                                        ],
-                                        ..
-                                    },
-                                },
-                                body: Scalar,
-                            },
-                        },
-                        CompiledBundleField {
-                            offset: TypeIndex {
-                                small_slots: StatePartIndex<SmallSlots>(0),
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-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(19),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(20),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(20),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(21),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(21),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(22),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(22),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(23),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(23),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(24),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(24),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(25),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(25),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(26),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(26),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(27),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(27),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(28),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(28),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(29),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(29),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(30),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(30),
-                ty: UInt<3>,
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(31),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(31),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(32),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(32),
-            },
-            state: 0x0,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(33),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(33),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(34),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(34),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(35),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(35),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(36),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(36),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(37),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(37),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(38),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(38),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(39),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(39),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(40),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(40),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(41),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(57),
-                ty: UInt<3>,
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(42),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(58),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(43),
-            kind: BigClock {
-                index: StatePartIndex<BigSlots>(59),
-            },
-            state: 0x0,
-            last_state: 0x1,
-        },
-        SimTrace {
-            id: TraceScalarId(44),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(60),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(45),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(61),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(46),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(62),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(47),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(63),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(48),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(64),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(49),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(65),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(50),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(66),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(51),
-            kind: BigUInt {
-                index: StatePartIndex<BigSlots>(67),
-                ty: UInt<8>,
-            },
-            state: 0x00,
-            last_state: 0x00,
-        },
-        SimTrace {
-            id: TraceScalarId(52),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(68),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(53),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(69),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(54),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(70),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(55),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(71),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(56),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(72),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(57),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(73),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(58),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(74),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-        SimTrace {
-            id: TraceScalarId(59),
-            kind: BigBool {
-                index: StatePartIndex<BigSlots>(75),
-            },
-            state: 0x0,
-            last_state: 0x0,
-        },
-    ],
-    trace_memories: {
-        StatePartIndex<Memories>(0): TraceMem {
-            id: TraceMemoryId(0),
-            name: "mem",
-            stride: 64,
-            element_type: TraceArray {
-                name: "mem",
-                elements: [
-                    TraceUInt {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 8,
-                            stride: 64,
-                            start: 0,
-                            len: 8,
-                        },
-                        name: "[0]",
-                        ty: UInt<8>,
-                        flow: Duplex,
-                    },
-                    TraceUInt {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 8,
-                            stride: 64,
-                            start: 8,
-                            len: 8,
-                        },
-                        name: "[1]",
-                        ty: UInt<8>,
-                        flow: Duplex,
-                    },
-                    TraceUInt {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 8,
-                            stride: 64,
-                            start: 16,
-                            len: 8,
-                        },
-                        name: "[2]",
-                        ty: UInt<8>,
-                        flow: Duplex,
-                    },
-                    TraceUInt {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 8,
-                            stride: 64,
-                            start: 24,
-                            len: 8,
-                        },
-                        name: "[3]",
-                        ty: UInt<8>,
-                        flow: Duplex,
-                    },
-                    TraceUInt {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 8,
-                            stride: 64,
-                            start: 32,
-                            len: 8,
-                        },
-                        name: "[4]",
-                        ty: UInt<8>,
-                        flow: Duplex,
-                    },
-                    TraceUInt {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 8,
-                            stride: 64,
-                            start: 40,
-                            len: 8,
-                        },
-                        name: "[5]",
-                        ty: UInt<8>,
-                        flow: Duplex,
-                    },
-                    TraceUInt {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 8,
-                            stride: 64,
-                            start: 48,
-                            len: 8,
-                        },
-                        name: "[6]",
-                        ty: UInt<8>,
-                        flow: Duplex,
-                    },
-                    TraceUInt {
-                        location: TraceMemoryLocation {
-                            id: TraceMemoryId(0),
-                            depth: 8,
-                            stride: 64,
-                            start: 56,
-                            len: 8,
-                        },
-                        name: "[7]",
-                        ty: UInt<8>,
-                        flow: Duplex,
-                    },
-                ],
-                ty: Array<UInt<8>, 8>,
-                flow: Duplex,
-            },
-            ports: [
-                TraceMemPort {
-                    name: "r0",
-                    bundle: TraceBundle {
-                        name: "r0",
-                        fields: [
-                            TraceUInt {
-                                location: TraceScalarId(30),
-                                name: "addr",
-                                ty: UInt<3>,
-                                flow: Sink,
-                            },
-                            TraceBool {
-                                location: TraceScalarId(31),
-                                name: "en",
-                                flow: Sink,
-                            },
-                            TraceClock {
-                                location: TraceScalarId(32),
-                                name: "clk",
-                                flow: Sink,
-                            },
-                            TraceArray {
-                                name: "data",
-                                elements: [
-                                    TraceUInt {
-                                        location: TraceScalarId(33),
-                                        name: "[0]",
-                                        ty: UInt<8>,
-                                        flow: Source,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(34),
-                                        name: "[1]",
-                                        ty: UInt<8>,
-                                        flow: Source,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(35),
-                                        name: "[2]",
-                                        ty: UInt<8>,
-                                        flow: Source,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(36),
-                                        name: "[3]",
-                                        ty: UInt<8>,
-                                        flow: Source,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(37),
-                                        name: "[4]",
-                                        ty: UInt<8>,
-                                        flow: Source,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(38),
-                                        name: "[5]",
-                                        ty: UInt<8>,
-                                        flow: Source,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(39),
-                                        name: "[6]",
-                                        ty: UInt<8>,
-                                        flow: Source,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(40),
-                                        name: "[7]",
-                                        ty: UInt<8>,
-                                        flow: Source,
-                                    },
-                                ],
-                                ty: Array<UInt<8>, 8>,
-                                flow: Source,
-                            },
-                        ],
-                        ty: Bundle {
-                            /* offset = 0 */
-                            addr: UInt<3>,
-                            /* offset = 3 */
-                            en: Bool,
-                            /* offset = 4 */
-                            clk: Clock,
-                            #[hdl(flip)] /* offset = 5 */
-                            data: Array<UInt<8>, 8>,
-                        },
-                        flow: Sink,
-                    },
-                    ty: Bundle {
-                        /* offset = 0 */
-                        addr: UInt<3>,
-                        /* offset = 3 */
-                        en: Bool,
-                        /* offset = 4 */
-                        clk: Clock,
-                        #[hdl(flip)] /* offset = 5 */
-                        data: Array<UInt<8>, 8>,
-                    },
-                },
-                TraceMemPort {
-                    name: "w1",
-                    bundle: TraceBundle {
-                        name: "w1",
-                        fields: [
-                            TraceUInt {
-                                location: TraceScalarId(41),
-                                name: "addr",
-                                ty: UInt<3>,
-                                flow: Sink,
-                            },
-                            TraceBool {
-                                location: TraceScalarId(42),
-                                name: "en",
-                                flow: Sink,
-                            },
-                            TraceClock {
-                                location: TraceScalarId(43),
-                                name: "clk",
-                                flow: Sink,
-                            },
-                            TraceArray {
-                                name: "data",
-                                elements: [
-                                    TraceUInt {
-                                        location: TraceScalarId(44),
-                                        name: "[0]",
-                                        ty: UInt<8>,
-                                        flow: Sink,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(45),
-                                        name: "[1]",
-                                        ty: UInt<8>,
-                                        flow: Sink,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(46),
-                                        name: "[2]",
-                                        ty: UInt<8>,
-                                        flow: Sink,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(47),
-                                        name: "[3]",
-                                        ty: UInt<8>,
-                                        flow: Sink,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(48),
-                                        name: "[4]",
-                                        ty: UInt<8>,
-                                        flow: Sink,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(49),
-                                        name: "[5]",
-                                        ty: UInt<8>,
-                                        flow: Sink,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(50),
-                                        name: "[6]",
-                                        ty: UInt<8>,
-                                        flow: Sink,
-                                    },
-                                    TraceUInt {
-                                        location: TraceScalarId(51),
-                                        name: "[7]",
-                                        ty: UInt<8>,
-                                        flow: Sink,
-                                    },
-                                ],
-                                ty: Array<UInt<8>, 8>,
-                                flow: Sink,
-                            },
-                            TraceArray {
-                                name: "mask",
-                                elements: [
-                                    TraceBool {
-                                        location: TraceScalarId(52),
-                                        name: "[0]",
-                                        flow: Sink,
-                                    },
-                                    TraceBool {
-                                        location: TraceScalarId(53),
-                                        name: "[1]",
-                                        flow: Sink,
-                                    },
-                                    TraceBool {
-                                        location: TraceScalarId(54),
-                                        name: "[2]",
-                                        flow: Sink,
-                                    },
-                                    TraceBool {
-                                        location: TraceScalarId(55),
-                                        name: "[3]",
-                                        flow: Sink,
-                                    },
-                                    TraceBool {
-                                        location: TraceScalarId(56),
-                                        name: "[4]",
-                                        flow: Sink,
-                                    },
-                                    TraceBool {
-                                        location: TraceScalarId(57),
-                                        name: "[5]",
-                                        flow: Sink,
-                                    },
-                                    TraceBool {
-                                        location: TraceScalarId(58),
-                                        name: "[6]",
-                                        flow: Sink,
-                                    },
-                                    TraceBool {
-                                        location: TraceScalarId(59),
-                                        name: "[7]",
-                                        flow: Sink,
-                                    },
-                                ],
-                                ty: Array<Bool, 8>,
-                                flow: Sink,
-                            },
-                        ],
-                        ty: Bundle {
-                            /* offset = 0 */
-                            addr: UInt<3>,
-                            /* offset = 3 */
-                            en: Bool,
-                            /* offset = 4 */
-                            clk: Clock,
-                            /* offset = 5 */
-                            data: Array<UInt<8>, 8>,
-                            /* offset = 69 */
-                            mask: Array<Bool, 8>,
-                        },
-                        flow: Sink,
-                    },
-                    ty: Bundle {
-                        /* offset = 0 */
-                        addr: UInt<3>,
-                        /* offset = 3 */
-                        en: Bool,
-                        /* offset = 4 */
-                        clk: Clock,
-                        /* offset = 5 */
-                        data: Array<UInt<8>, 8>,
-                        /* offset = 69 */
-                        mask: Array<Bool, 8>,
-                    },
-                },
-            ],
-            array_type: Array<Array<UInt<8>, 8>, 8>,
-        },
-    },
-    trace_writers: [
-        Running(
-            VcdWriter {
-                finished_init: true,
-                timescale: 1 ps,
-                ..
-            },
-        ),
-    ],
-    instant: 15 μs,
-    clocks_triggered: [
-        StatePartIndex<SmallSlots>(1),
-        StatePartIndex<SmallSlots>(6),
-    ],
-    ..
-}
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/memories3.vcd b/crates/fayalite/tests/sim/expected/memories3.vcd
deleted file mode 100644
index 328fcaa..0000000
--- a/crates/fayalite/tests/sim/expected/memories3.vcd
+++ /dev/null
@@ -1,836 +0,0 @@
-$timescale 1 ps $end
-$scope module memories3 $end
-$scope struct r $end
-$var wire 3 ! addr $end
-$var wire 1 " en $end
-$var wire 1 # clk $end
-$scope struct data $end
-$var wire 8 $ \[0] $end
-$var wire 8 % \[1] $end
-$var wire 8 & \[2] $end
-$var wire 8 ' \[3] $end
-$var wire 8 ( \[4] $end
-$var wire 8 ) \[5] $end
-$var wire 8 * \[6] $end
-$var wire 8 + \[7] $end
-$upscope $end
-$upscope $end
-$scope struct w $end
-$var wire 3 , addr $end
-$var wire 1 - en $end
-$var wire 1 . clk $end
-$scope struct data $end
-$var wire 8 / \[0] $end
-$var wire 8 0 \[1] $end
-$var wire 8 1 \[2] $end
-$var wire 8 2 \[3] $end
-$var wire 8 3 \[4] $end
-$var wire 8 4 \[5] $end
-$var wire 8 5 \[6] $end
-$var wire 8 6 \[7] $end
-$upscope $end
-$scope struct mask $end
-$var wire 1 7 \[0] $end
-$var wire 1 8 \[1] $end
-$var wire 1 9 \[2] $end
-$var wire 1 : \[3] $end
-$var wire 1 ; \[4] $end
-$var wire 1 < \[5] $end
-$var wire 1 = \[6] $end
-$var wire 1 > \[7] $end
-$upscope $end
-$upscope $end
-$scope struct mem $end
-$scope struct contents $end
-$scope struct [0] $end
-$scope struct mem $end
-$var reg 8 ] \[0] $end
-$var reg 8 e \[1] $end
-$var reg 8 m \[2] $end
-$var reg 8 u \[3] $end
-$var reg 8 } \[4] $end
-$var reg 8 '" \[5] $end
-$var reg 8 /" \[6] $end
-$var reg 8 7" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [1] $end
-$scope struct mem $end
-$var reg 8 ^ \[0] $end
-$var reg 8 f \[1] $end
-$var reg 8 n \[2] $end
-$var reg 8 v \[3] $end
-$var reg 8 ~ \[4] $end
-$var reg 8 (" \[5] $end
-$var reg 8 0" \[6] $end
-$var reg 8 8" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [2] $end
-$scope struct mem $end
-$var reg 8 _ \[0] $end
-$var reg 8 g \[1] $end
-$var reg 8 o \[2] $end
-$var reg 8 w \[3] $end
-$var reg 8 !" \[4] $end
-$var reg 8 )" \[5] $end
-$var reg 8 1" \[6] $end
-$var reg 8 9" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [3] $end
-$scope struct mem $end
-$var reg 8 ` \[0] $end
-$var reg 8 h \[1] $end
-$var reg 8 p \[2] $end
-$var reg 8 x \[3] $end
-$var reg 8 "" \[4] $end
-$var reg 8 *" \[5] $end
-$var reg 8 2" \[6] $end
-$var reg 8 :" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [4] $end
-$scope struct mem $end
-$var reg 8 a \[0] $end
-$var reg 8 i \[1] $end
-$var reg 8 q \[2] $end
-$var reg 8 y \[3] $end
-$var reg 8 #" \[4] $end
-$var reg 8 +" \[5] $end
-$var reg 8 3" \[6] $end
-$var reg 8 ;" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [5] $end
-$scope struct mem $end
-$var reg 8 b \[0] $end
-$var reg 8 j \[1] $end
-$var reg 8 r \[2] $end
-$var reg 8 z \[3] $end
-$var reg 8 $" \[4] $end
-$var reg 8 ," \[5] $end
-$var reg 8 4" \[6] $end
-$var reg 8 <" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [6] $end
-$scope struct mem $end
-$var reg 8 c \[0] $end
-$var reg 8 k \[1] $end
-$var reg 8 s \[2] $end
-$var reg 8 { \[3] $end
-$var reg 8 %" \[4] $end
-$var reg 8 -" \[5] $end
-$var reg 8 5" \[6] $end
-$var reg 8 =" \[7] $end
-$upscope $end
-$upscope $end
-$scope struct [7] $end
-$scope struct mem $end
-$var reg 8 d \[0] $end
-$var reg 8 l \[1] $end
-$var reg 8 t \[2] $end
-$var reg 8 | \[3] $end
-$var reg 8 &" \[4] $end
-$var reg 8 ." \[5] $end
-$var reg 8 6" \[6] $end
-$var reg 8 >" \[7] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct r0 $end
-$var wire 3 ? addr $end
-$var wire 1 @ en $end
-$var wire 1 A clk $end
-$scope struct data $end
-$var wire 8 B \[0] $end
-$var wire 8 C \[1] $end
-$var wire 8 D \[2] $end
-$var wire 8 E \[3] $end
-$var wire 8 F \[4] $end
-$var wire 8 G \[5] $end
-$var wire 8 H \[6] $end
-$var wire 8 I \[7] $end
-$upscope $end
-$upscope $end
-$scope struct w1 $end
-$var wire 3 J addr $end
-$var wire 1 K en $end
-$var wire 1 L clk $end
-$scope struct data $end
-$var wire 8 M \[0] $end
-$var wire 8 N \[1] $end
-$var wire 8 O \[2] $end
-$var wire 8 P \[3] $end
-$var wire 8 Q \[4] $end
-$var wire 8 R \[5] $end
-$var wire 8 S \[6] $end
-$var wire 8 T \[7] $end
-$upscope $end
-$scope struct mask $end
-$var wire 1 U \[0] $end
-$var wire 1 V \[1] $end
-$var wire 1 W \[2] $end
-$var wire 1 X \[3] $end
-$var wire 1 Y \[4] $end
-$var wire 1 Z \[5] $end
-$var wire 1 [ \[6] $end
-$var wire 1 \ \[7] $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-$dumpvars
-b0 ]
-b0 e
-b0 m
-b0 u
-b0 }
-b0 '"
-b0 /"
-b0 7"
-b0 ^
-b0 f
-b0 n
-b0 v
-b0 ~
-b0 ("
-b0 0"
-b0 8"
-b0 _
-b0 g
-b0 o
-b0 w
-b0 !"
-b0 )"
-b0 1"
-b0 9"
-b0 `
-b0 h
-b0 p
-b0 x
-b0 ""
-b0 *"
-b0 2"
-b0 :"
-b0 a
-b0 i
-b0 q
-b0 y
-b0 #"
-b0 +"
-b0 3"
-b0 ;"
-b0 b
-b0 j
-b0 r
-b0 z
-b0 $"
-b0 ,"
-b0 4"
-b0 <"
-b0 c
-b0 k
-b0 s
-b0 {
-b0 %"
-b0 -"
-b0 5"
-b0 ="
-b0 d
-b0 l
-b0 t
-b0 |
-b0 &"
-b0 ."
-b0 6"
-b0 >"
-b0 !
-0"
-0#
-b0 $
-b0 %
-b0 &
-b0 '
-b0 (
-b0 )
-b0 *
-b0 +
-b0 ,
-1-
-0.
-b10010 /
-b110100 0
-b1010110 1
-b1111000 2
-b10011010 3
-b10111100 4
-b11011110 5
-b11110000 6
-07
-18
-09
-1:
-1;
-0<
-0=
-1>
-b0 ?
-0@
-0A
-b0 B
-b0 C
-b0 D
-b0 E
-b0 F
-b0 G
-b0 H
-b0 I
-b0 J
-1K
-0L
-b10010 M
-b110100 N
-b1010110 O
-b1111000 P
-b10011010 Q
-b10111100 R
-b11011110 S
-b11110000 T
-0U
-1V
-0W
-1X
-1Y
-0Z
-0[
-1\
-$end
-#250000
-1#
-1.
-1A
-1L
-#500000
-#750000
-0#
-0.
-0A
-0L
-#1000000
-1"
-b1 ,
-0-
-b0 /
-b0 0
-b0 1
-b0 2
-b0 3
-b0 4
-b0 5
-b0 6
-08
-0:
-0;
-0>
-1@
-b1 J
-0K
-b0 M
-b0 N
-b0 O
-b0 P
-b0 Q
-b0 R
-b0 S
-b0 T
-0V
-0X
-0Y
-0\
-#1250000
-b0 ]
-b110100 e
-b0 m
-b1111000 u
-b10011010 }
-b0 '"
-b0 /"
-b11110000 7"
-1#
-1.
-1A
-1L
-#1500000
-#1750000
-0#
-0.
-0A
-0L
-#2000000
-#2250000
-1#
-1.
-1A
-1L
-#2500000
-#2750000
-0#
-0.
-0A
-0L
-#3000000
-b0 ,
-1-
-b11111110 /
-b11011100 0
-b10111010 1
-b10011000 2
-b1110110 3
-b1010100 4
-b110010 5
-b10000 6
-17
-18
-19
-1:
-1;
-1<
-1=
-1>
-b0 J
-1K
-b11111110 M
-b11011100 N
-b10111010 O
-b10011000 P
-b1110110 Q
-b1010100 R
-b110010 S
-b10000 T
-1U
-1V
-1W
-1X
-1Y
-1Z
-1[
-1\
-#3250000
-1#
-1.
-1A
-b110100 C
-b1111000 E
-b10011010 F
-b11110000 I
-1L
-b110100 %
-b1111000 '
-b10011010 (
-b11110000 +
-#3500000
-#3750000
-0#
-0.
-0A
-0L
-#4000000
-#4250000
-b11111110 ]
-b11011100 e
-b10111010 m
-b10011000 u
-b1110110 }
-b1010100 '"
-b110010 /"
-b10000 7"
-1#
-1.
-1A
-1L
-#4500000
-#4750000
-0#
-0.
-0A
-0L
-#5000000
-#5250000
-b11111110 ]
-b11011100 e
-b10111010 m
-b10011000 u
-b1110110 }
-b1010100 '"
-b110010 /"
-b10000 7"
-1#
-1.
-1A
-1L
-#5500000
-#5750000
-0#
-0.
-0A
-0L
-#6000000
-0"
-b1 ,
-b10011 /
-b1010111 0
-b10011011 1
-b11011111 2
-b10 3
-b1000110 4
-b10001010 5
-b11001110 6
-0@
-b1 J
-b10011 M
-b1010111 N
-b10011011 O
-b11011111 P
-b10 Q
-b1000110 R
-b10001010 S
-b11001110 T
-#6250000
-b11111110 ]
-b11011100 e
-b10111010 m
-b10011000 u
-b1110110 }
-b1010100 '"
-b110010 /"
-b10000 7"
-1#
-1.
-1A
-b11111110 B
-b11011100 C
-b10111010 D
-b10011000 E
-b1110110 F
-b1010100 G
-b110010 H
-b10000 I
-1L
-b11111110 $
-b11011100 %
-b10111010 &
-b10011000 '
-b1110110 (
-b1010100 )
-b110010 *
-b10000 +
-#6500000
-#6750000
-0#
-0.
-0A
-0L
-#7000000
-b10 ,
-b1110100 /
-b1100101 0
-b1110011 1
-b1110100 2
-b1101001 3
-b1101110 4
-b1100111 5
-b100001 6
-b10 J
-b1110100 M
-b1100101 N
-b1110011 O
-b1110100 P
-b1101001 Q
-b1101110 R
-b1100111 S
-b100001 T
-#7250000
-b10011 ^
-b1010111 f
-b10011011 n
-b11011111 v
-b10 ~
-b1000110 ("
-b10001010 0"
-b11001110 8"
-1#
-1.
-1A
-b0 B
-b0 C
-b0 D
-b0 E
-b0 F
-b0 G
-b0 H
-b0 I
-1L
-b0 $
-b0 %
-b0 &
-b0 '
-b0 (
-b0 )
-b0 *
-b0 +
-#7500000
-#7750000
-0#
-0.
-0A
-0L
-#8000000
-b11 ,
-b1101101 /
-b1101111 0
-b1110010 1
-b1100101 2
-b100000 3
-b1110100 4
-b1110011 5
-b1110100 6
-b11 J
-b1101101 M
-b1101111 N
-b1110010 O
-b1100101 P
-b100000 Q
-b1110100 R
-b1110011 S
-b1110100 T
-#8250000
-b1110100 _
-b1100101 g
-b1110011 o
-b1110100 w
-b1101001 !"
-b1101110 )"
-b1100111 1"
-b100001 9"
-1#
-1.
-1A
-1L
-#8500000
-#8750000
-0#
-0.
-0A
-0L
-#9000000
-1"
-b0 ,
-0-
-b0 /
-b0 0
-b0 1
-b0 2
-b0 3
-b0 4
-b0 5
-b0 6
-07
-08
-09
-0:
-0;
-0<
-0=
-0>
-1@
-b0 J
-0K
-b0 M
-b0 N
-b0 O
-b0 P
-b0 Q
-b0 R
-b0 S
-b0 T
-0U
-0V
-0W
-0X
-0Y
-0Z
-0[
-0\
-#9250000
-b1101101 `
-b1101111 h
-b1110010 p
-b1100101 x
-b100000 ""
-b1110100 *"
-b1110011 2"
-b1110100 :"
-1#
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-1A
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-b1 !
-b1 ?
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-1#
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-b11111110 B
-b11011100 C
-b10111010 D
-b10011000 E
-b1110110 F
-b1010100 G
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-b10000 I
-1L
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-b11011100 %
-b10111010 &
-b10011000 '
-b1110110 (
-b1010100 )
-b110010 *
-b10000 +
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-b10 !
-b10 ?
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-1#
-1.
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-b10011 B
-b1010111 C
-b10011011 D
-b11011111 E
-b10 F
-b1000110 G
-b10001010 H
-b11001110 I
-1L
-b10011 $
-b1010111 %
-b10011011 &
-b11011111 '
-b10 (
-b1000110 )
-b10001010 *
-b11001110 +
-#11500000
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-0#
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-b11 !
-b11 ?
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-1#
-1.
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-b1110100 B
-b1100101 C
-b1110011 D
-b1110100 E
-b1101001 F
-b1101110 G
-b1100111 H
-b100001 I
-1L
-b1110100 $
-b1100101 %
-b1110011 &
-b1110100 '
-b1101001 (
-b1101110 )
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-b100001 +
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-b1101101 $
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diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt
index 5c2b7eb..cf15b07 100644
--- a/crates/fayalite/tests/sim/expected/mod1.txt
+++ b/crates/fayalite/tests/sim/expected/mod1.txt
@@ -3,12 +3,12 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 17,
                         debug_data: [
                             SlotDebugData {
@@ -83,7 +83,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartLayout<Memories> {
+                memories: StatePartAllocationLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -92,95 +92,94 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:4:1
-                0: Copy {
-                    dest: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(2), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i2", ty: SInt<2> },
                 },
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(0), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.i", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:2:1
-                2: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(6), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i2", ty: SInt<2> },
                 },
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(4), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.i", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX-2.rs:1:1
-                4: Const {
-                    dest: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
-                    value: 0xf,
+                Const {
+                    dest: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 15,
                 },
-                5: Const {
-                    dest: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
-                    value: 0x5,
+                Const {
+                    dest: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
+                    value: 5,
                 },
-                6: CmpLt {
-                    dest: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<BigSlots>(14), // (0x5) SlotDebugData { name: "", ty: UInt<4> },
-                    rhs: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                CmpLt {
+                    dest: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<BigSlots>(14), // SlotDebugData { name: "", ty: UInt<4> },
+                    rhs: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
                 },
-                7: CastToUInt {
-                    dest: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(10), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
+                CastToUInt {
+                    dest: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i2", ty: SInt<2> },
                     dest_width: 4,
                 },
                 // at: module-XXXXXXXXXX-2.rs:7:1
-                8: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(13), // (0xe) SlotDebugData { name: "", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(13), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX-2.rs:8:1
-                9: BranchIfZero {
+                BranchIfZero {
                     target: 11,
-                    value: StatePartIndex<BigSlots>(15), // (0x1) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<BigSlots>(15), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX-2.rs:9:1
-                10: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(16), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(16), // SlotDebugData { name: "", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:2:1
-                11: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(11), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o2", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                12: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
-                    src: StatePartIndex<BigSlots>(7), // (0xf) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o2", ty: UInt<4> },
+                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o2", ty: UInt<4> },
                 },
                 // at: module-XXXXXXXXXX-2.rs:1:1
-                13: CastToSInt {
-                    dest: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(8), // (0xa) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
+                CastToSInt {
+                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::i", ty: UInt<4> },
                     dest_width: 2,
                 },
                 // at: module-XXXXXXXXXX-2.rs:6:1
-                14: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(12), // (-0x2) SlotDebugData { name: "", ty: SInt<2> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "", ty: SInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:2:1
-                15: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(9), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(mod1.child: mod1_child).mod1_child::o", ty: SInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:4:1
-                16: Copy {
-                    dest: StatePartIndex<BigSlots>(1), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
-                    src: StatePartIndex<BigSlots>(5), // (-0x2) SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::o.o", ty: SInt<2> },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(mod1: mod1).mod1::child.o", ty: SInt<2> },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                17: Return,
+                Return,
             ],
             ..
         },
         pc: 17,
-        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
@@ -237,12 +236,12 @@ Simulation {
                     o2: UInt<4>,
                 },
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 4,
                         debug_data: [
                             SlotDebugData {
@@ -275,12 +274,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: UInt<4>,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -302,12 +301,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: SInt<2>,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -329,12 +328,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: SInt<2>,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -356,12 +355,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: UInt<4>,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -394,12 +393,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -428,12 +427,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: SInt<2>,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -462,12 +461,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: SInt<2>,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -496,12 +495,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: UInt<4>,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -532,25 +531,25 @@ Simulation {
                     name: "o",
                     fields: [
                         TraceUInt {
-                            location: TraceScalarId(0),
+                            id: TraceScalarId(0),
                             name: "i",
                             ty: UInt<4>,
                             flow: Source,
                         },
                         TraceSInt {
-                            location: TraceScalarId(1),
+                            id: TraceScalarId(1),
                             name: "o",
                             ty: SInt<2>,
                             flow: Sink,
                         },
                         TraceSInt {
-                            location: TraceScalarId(2),
+                            id: TraceScalarId(2),
                             name: "i2",
                             ty: SInt<2>,
                             flow: Source,
                         },
                         TraceUInt {
-                            location: TraceScalarId(3),
+                            id: TraceScalarId(3),
                             name: "o2",
                             ty: UInt<4>,
                             flow: Sink,
@@ -586,25 +585,25 @@ Simulation {
                     name: "child",
                     fields: [
                         TraceUInt {
-                            location: TraceScalarId(8),
+                            id: TraceScalarId(8),
                             name: "i",
                             ty: UInt<4>,
                             flow: Sink,
                         },
                         TraceSInt {
-                            location: TraceScalarId(9),
+                            id: TraceScalarId(9),
                             name: "o",
                             ty: SInt<2>,
                             flow: Source,
                         },
                         TraceSInt {
-                            location: TraceScalarId(10),
+                            id: TraceScalarId(10),
                             name: "i2",
                             ty: SInt<2>,
                             flow: Sink,
                         },
                         TraceUInt {
-                            location: TraceScalarId(11),
+                            id: TraceScalarId(11),
                             name: "o2",
                             ty: UInt<4>,
                             flow: Source,
@@ -628,7 +627,7 @@ Simulation {
                         TraceModuleIO {
                             name: "i",
                             child: TraceUInt {
-                                location: TraceScalarId(4),
+                                id: TraceScalarId(4),
                                 name: "i",
                                 ty: UInt<4>,
                                 flow: Source,
@@ -639,7 +638,7 @@ Simulation {
                         TraceModuleIO {
                             name: "o",
                             child: TraceSInt {
-                                location: TraceScalarId(5),
+                                id: TraceScalarId(5),
                                 name: "o",
                                 ty: SInt<2>,
                                 flow: Sink,
@@ -650,7 +649,7 @@ Simulation {
                         TraceModuleIO {
                             name: "i2",
                             child: TraceSInt {
-                                location: TraceScalarId(6),
+                                id: TraceScalarId(6),
                                 name: "i2",
                                 ty: SInt<2>,
                                 flow: Source,
@@ -661,7 +660,7 @@ Simulation {
                         TraceModuleIO {
                             name: "o2",
                             child: TraceUInt {
-                                location: TraceScalarId(7),
+                                id: TraceScalarId(7),
                                 name: "o2",
                                 ty: UInt<4>,
                                 flow: Sink,
@@ -794,7 +793,6 @@ Simulation {
             last_state: 0xe,
         },
     ],
-    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {
@@ -806,5 +804,4 @@ Simulation {
     ],
     instant: 2 μs,
     clocks_triggered: [],
-    ..
 }
\ No newline at end of file
diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt
index 73f6263..e89351d 100644
--- a/crates/fayalite/tests/sim/expected/shift_register.txt
+++ b/crates/fayalite/tests/sim/expected/shift_register.txt
@@ -3,7 +3,7 @@ Simulation {
         insns: Insns {
             state_layout: StateLayout {
                 ty: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 4,
                         debug_data: [
                             SlotDebugData {
@@ -25,7 +25,7 @@ Simulation {
                         ],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 13,
                         debug_data: [
                             SlotDebugData {
@@ -84,7 +84,7 @@ Simulation {
                         ..
                     },
                 },
-                memories: StatePartLayout<Memories> {
+                memories: StatePartAllocationLayout<Memories> {
                     len: 0,
                     debug_data: [],
                     layout_data: [],
@@ -93,148 +93,146 @@ Simulation {
             },
             insns: [
                 // at: module-XXXXXXXXXX.rs:13:1
-                0: Copy {
-                    dest: StatePartIndex<BigSlots>(3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
-                    src: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool },
+                    src: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:12:1
-                1: Copy {
-                    dest: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:10:1
-                2: Copy {
-                    dest: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:8:1
-                3: Copy {
-                    dest: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:6:1
-                4: Copy {
-                    dest: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
-                    src: StatePartIndex<BigSlots>(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                    src: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                5: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                6: Const {
-                    dest: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
-                    value: 0x0,
+                Const {
+                    dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
+                    value: 0,
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                7: IsNonZeroDestIsSmall {
-                    dest: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    src: StatePartIndex<BigSlots>(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
+                IsNonZeroDestIsSmall {
+                    dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock },
                 },
-                8: AndSmall {
-                    dest: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                AndSmall {
+                    dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
+                    lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
+                    rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
                 },
-                9: BranchIfSmallZero {
+                BranchIfSmallZero {
                     target: 14,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                10: BranchIfSmallNonZero {
+                BranchIfSmallNonZero {
                     target: 13,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                11: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
-                    src: StatePartIndex<BigSlots>(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool },
                 },
-                12: Branch {
+                Branch {
                     target: 14,
                 },
-                13: Copy {
-                    dest: StatePartIndex<BigSlots>(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:7:1
-                14: BranchIfSmallZero {
+                BranchIfSmallZero {
                     target: 19,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                15: BranchIfSmallNonZero {
+                BranchIfSmallNonZero {
                     target: 18,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                16: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool },
                 },
-                17: Branch {
+                Branch {
                     target: 19,
                 },
-                18: Copy {
-                    dest: StatePartIndex<BigSlots>(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:9:1
-                19: BranchIfSmallZero {
+                BranchIfSmallZero {
                     target: 24,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                20: BranchIfSmallNonZero {
+                BranchIfSmallNonZero {
                     target: 23,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                21: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
-                    src: StatePartIndex<BigSlots>(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(10), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool },
                 },
-                22: Branch {
+                Branch {
                     target: 24,
                 },
-                23: Copy {
-                    dest: StatePartIndex<BigSlots>(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:11:1
-                24: BranchIfSmallZero {
+                BranchIfSmallZero {
                     target: 29,
-                    value: StatePartIndex<SmallSlots>(1), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
                 },
-                25: BranchIfSmallNonZero {
+                BranchIfSmallNonZero {
                     target: 28,
-                    value: StatePartIndex<SmallSlots>(3), // (0x0 0) SlotDebugData { name: "", ty: Bool },
+                    value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
                 },
-                26: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
-                    src: StatePartIndex<BigSlots>(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                    src: StatePartIndex<BigSlots>(12), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool },
                 },
-                27: Branch {
+                Branch {
                     target: 29,
                 },
-                28: Copy {
-                    dest: StatePartIndex<BigSlots>(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
-                    src: StatePartIndex<BigSlots>(6), // (0x0) SlotDebugData { name: "", ty: Bool },
+                Copy {
+                    dest: StatePartIndex<BigSlots>(11), // SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool },
+                    src: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:5:1
-                29: XorSmallImmediate {
-                    dest: StatePartIndex<SmallSlots>(0), // (0x0 0) SlotDebugData { name: "", ty: Bool },
-                    lhs: StatePartIndex<SmallSlots>(2), // (0x1 1) SlotDebugData { name: "", ty: Bool },
-                    rhs: 0x1,
+                NotSmall {
+                    dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
+                    src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
                 },
                 // at: module-XXXXXXXXXX.rs:1:1
-                30: Return,
+                Return,
             ],
             ..
         },
         pc: 30,
-        memory_write_log: [],
         memories: StatePart {
             value: [],
         },
         small_slots: StatePart {
             value: [
-                0,
+                18446744073709551614,
                 0,
                 1,
                 0,
@@ -282,12 +280,12 @@ Simulation {
                     rst: SyncReset,
                 },
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 2,
                         debug_data: [
                             SlotDebugData {
@@ -312,12 +310,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: Clock,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -339,12 +337,12 @@ Simulation {
                             ty: CompiledTypeLayout {
                                 ty: SyncReset,
                                 layout: TypeLayout {
-                                    small_slots: StatePartLayout<SmallSlots> {
+                                    small_slots: StatePartAllocationLayout<SmallSlots> {
                                         len: 0,
                                         debug_data: [],
                                         ..
                                     },
-                                    big_slots: StatePartLayout<BigSlots> {
+                                    big_slots: StatePartAllocationLayout<BigSlots> {
                                         len: 1,
                                         debug_data: [
                                             SlotDebugData {
@@ -377,12 +375,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Clock,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -411,12 +409,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: SyncReset,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -445,12 +443,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Bool,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -479,12 +477,12 @@ Simulation {
             layout: CompiledTypeLayout {
                 ty: Bool,
                 layout: TypeLayout {
-                    small_slots: StatePartLayout<SmallSlots> {
+                    small_slots: StatePartAllocationLayout<SmallSlots> {
                         len: 0,
                         debug_data: [],
                         ..
                     },
-                    big_slots: StatePartLayout<BigSlots> {
+                    big_slots: StatePartAllocationLayout<BigSlots> {
                         len: 1,
                         debug_data: [
                             SlotDebugData {
@@ -515,12 +513,12 @@ Simulation {
                     name: "cd",
                     fields: [
                         TraceClock {
-                            location: TraceScalarId(0),
+                            id: TraceScalarId(0),
                             name: "clk",
                             flow: Source,
                         },
                         TraceSyncReset {
-                            location: TraceScalarId(1),
+                            id: TraceScalarId(1),
                             name: "rst",
                             flow: Source,
                         },
@@ -544,7 +542,7 @@ Simulation {
             TraceModuleIO {
                 name: "d",
                 child: TraceBool {
-                    location: TraceScalarId(2),
+                    id: TraceScalarId(2),
                     name: "d",
                     flow: Source,
                 },
@@ -554,7 +552,7 @@ Simulation {
             TraceModuleIO {
                 name: "q",
                 child: TraceBool {
-                    location: TraceScalarId(3),
+                    id: TraceScalarId(3),
                     name: "q",
                     flow: Sink,
                 },
@@ -564,7 +562,7 @@ Simulation {
             TraceReg {
                 name: "reg0",
                 child: TraceBool {
-                    location: TraceScalarId(4),
+                    id: TraceScalarId(4),
                     name: "reg0",
                     flow: Duplex,
                 },
@@ -573,7 +571,7 @@ Simulation {
             TraceReg {
                 name: "reg1",
                 child: TraceBool {
-                    location: TraceScalarId(5),
+                    id: TraceScalarId(5),
                     name: "reg1",
                     flow: Duplex,
                 },
@@ -582,7 +580,7 @@ Simulation {
             TraceReg {
                 name: "reg2",
                 child: TraceBool {
-                    location: TraceScalarId(6),
+                    id: TraceScalarId(6),
                     name: "reg2",
                     flow: Duplex,
                 },
@@ -591,7 +589,7 @@ Simulation {
             TraceReg {
                 name: "reg3",
                 child: TraceBool {
-                    location: TraceScalarId(7),
+                    id: TraceScalarId(7),
                     name: "reg3",
                     flow: Duplex,
                 },
@@ -665,7 +663,6 @@ Simulation {
             last_state: 0x0,
         },
     ],
-    trace_memories: {},
     trace_writers: [
         Running(
             VcdWriter {
@@ -679,5 +676,4 @@ Simulation {
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
     ],
-    ..
 }
\ No newline at end of file