From a8a541b35723b4dbc936d99978ffc489f65301cf Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 24 Mar 2026 23:26:47 -0700 Subject: [PATCH 01/10] sim/compiler: fix registers so they properly retain their old value when not written --- crates/fayalite/src/sim/compiler.rs | 9 + .../tests/sim/expected/counter_async.txt | 34 ++-- .../tests/sim/expected/counter_sync.txt | 44 ++--- crates/fayalite/tests/sim/expected/enums.txt | 90 +++++----- .../tests/sim/expected/ripple_counter.txt | 165 ++++++++++-------- .../tests/sim/expected/shift_register.txt | 113 +++++++----- .../tests/sim/expected/sim_only_connects.txt | 101 ++++++----- 7 files changed, 311 insertions(+), 245 deletions(-) diff --git a/crates/fayalite/src/sim/compiler.rs b/crates/fayalite/src/sim/compiler.rs index 07621c5..e85ff0f 100644 --- a/crates/fayalite/src/sim/compiler.rs +++ b/crates/fayalite/src/sim/compiler.rs @@ -4087,6 +4087,15 @@ impl Compiler { let init = self.compiled_expr_to_value(init, reg.source_location()); (reg.clock_domain().rst, init) }); + + // next value defaults to current value + self.compile_simple_connect( + [].intern_slice(), + value.into(), + value, + reg.source_location(), + ); + self.compile_reg( clk, reset_and_init, diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index 86bde88..2bdd665 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -123,58 +123,62 @@ Simulation { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, + 8: Copy { + dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Add { + 9: Add { dest: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, rhs: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, - 9: CastToUInt { + 10: CastToUInt { dest: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, // at: module-XXXXXXXXXX.rs:4:1 - 10: Copy { + 11: Copy { dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, src: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:6:1 - 11: Copy { + 12: Copy { dest: StatePartIndex(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:3:1 - 12: BranchIfSmallNonZero { - target: 16, + 13: BranchIfSmallNonZero { + target: 17, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 13: BranchIfSmallZero { - target: 17, + 14: BranchIfSmallZero { + target: 18, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 14: Copy { + 15: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, }, - 15: Branch { - target: 17, + 16: Branch { + target: 18, }, - 16: Copy { + 17: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, - 17: XorSmallImmediate { + 18: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 18: Return, + 19: Return, ], .. }, - pc: 18, + pc: 19, memory_write_log: [], memories: StatePart { value: [], diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index 0a7517e..87c2098 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -102,61 +102,65 @@ Simulation { src: StatePartIndex(7), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, - // at: module-XXXXXXXXXX.rs:4:1 - 4: Copy { - dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, - src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, - }, // at: module-XXXXXXXXXX.rs:3:1 - 5: IsNonZeroDestIsSmall { + 4: IsNonZeroDestIsSmall { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset }, }, - 6: IsNonZeroDestIsSmall { + 5: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, }, - 7: AndSmall { + 6: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + 7: Copy { + dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 8: Copy { + dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, + src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Const { + 9: Const { dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, value: 0x3, }, // at: module-XXXXXXXXXX.rs:3:1 - 9: BranchIfSmallZero { - target: 14, + 10: BranchIfSmallZero { + target: 15, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 10: BranchIfSmallNonZero { - target: 13, + 11: BranchIfSmallNonZero { + target: 14, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 11: Copy { + 12: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, }, - 12: Branch { - target: 14, + 13: Branch { + target: 15, }, - 13: Copy { + 14: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, - 14: XorSmallImmediate { + 15: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 15: Return, + 16: Return, ], .. }, - pc: 15, + pc: 16, memory_write_log: [], memories: StatePart { value: [], diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index a193e92..a3a52cb 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1012,173 +1012,177 @@ Simulation { lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + 99: Copy { + dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + src: StatePartIndex(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 99: Const { + 100: Const { dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, value: 0x0, }, - 100: Copy { + 101: Copy { dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:12:1 - 101: BranchIfZero { - target: 109, + 102: BranchIfZero { + target: 110, value: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:13:1 - 102: BranchIfZero { - target: 104, + 103: BranchIfZero { + target: 105, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:14:1 - 103: Copy { + 104: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:13:1 - 104: BranchIfNonZero { - target: 109, + 105: BranchIfNonZero { + target: 110, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:15:1 - 105: BranchIfZero { - target: 107, + 106: BranchIfZero { + target: 108, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:16:1 - 106: Copy { + 107: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:15:1 - 107: BranchIfNonZero { - target: 109, + 108: BranchIfNonZero { + target: 110, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:17:1 - 108: Copy { + 109: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:10:1 - 109: Copy { + 110: Copy { dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, }, // at: module-XXXXXXXXXX.rs:1:1 - 110: Copy { + 111: Copy { dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, }, - 111: SliceInt { + 112: SliceInt { dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, src: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, start: 1, len: 2, }, - 112: SliceInt { + 113: SliceInt { dest: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 0, len: 1, }, - 113: SliceInt { + 114: SliceInt { dest: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 1, len: 1, }, - 114: Copy { + 115: Copy { dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 115: Copy { + 116: Copy { dest: StatePartIndex(16), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, src: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 116: Copy { + 117: Copy { dest: StatePartIndex(17), // (0x0) SlotDebugData { name: ".1", ty: Bool }, src: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:9:1 - 117: AndBigWithSmallImmediate { + 118: AndBigWithSmallImmediate { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, lhs: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 118: Copy { + 119: Copy { dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, }, - 119: SliceInt { + 120: SliceInt { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, src: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, start: 1, len: 2, }, - 120: SliceInt { + 121: SliceInt { dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 0, len: 1, }, - 121: SliceInt { + 122: SliceInt { dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, start: 1, len: 1, }, - 122: Copy { + 123: Copy { dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 123: Copy { + 124: Copy { dest: StatePartIndex(8), // (0x0) SlotDebugData { name: ".0", ty: UInt<1> }, src: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 124: Copy { + 125: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: ".1", ty: Bool }, src: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:8:1 - 125: AndBigWithSmallImmediate { + 126: AndBigWithSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, lhs: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:11:1 - 126: BranchIfSmallZero { - target: 131, + 127: BranchIfSmallZero { + target: 132, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 127: BranchIfSmallNonZero { - target: 130, + 128: BranchIfSmallNonZero { + target: 131, value: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 128: Copy { + 129: Copy { dest: StatePartIndex(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, - 129: Branch { - target: 131, + 130: Branch { + target: 132, }, - 130: Copy { + 131: Copy { dest: StatePartIndex(23), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, - 131: XorSmallImmediate { + 132: XorSmallImmediate { dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 132: Return, + 133: Return, ], .. }, - pc: 132, + pc: 133, memory_write_log: [], memories: StatePart { value: [], diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt index 2be69b5..1fb5fee 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.txt +++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt @@ -314,55 +314,56 @@ Simulation { src: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, width: 1, }, - // at: module-XXXXXXXXXX.rs:8:1 - 3: Copy { - dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, - src: StatePartIndex(52), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:7:1 - 4: Copy { + 3: Copy { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, src: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 5: Copy { + 4: Copy { dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:10:1 - 6: Copy { + 5: Copy { dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock }, src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Clock }, }, // at: module-XXXXXXXXXX.rs:9:1 - 7: Copy { + 6: Copy { dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", ty: Clock }, src: StatePartIndex(53), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_5.clk", ty: Clock }, }, + // at: module-XXXXXXXXXX.rs:6:1 + 7: Copy { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, + src: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:8:1 8: Copy { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, + src: StatePartIndex(52), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 9: Copy { dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool }, src: StatePartIndex(45), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 - 9: Copy { + 10: Copy { dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, src: StatePartIndex(43), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 10: Copy { + 11: Copy { dest: StatePartIndex(51), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, }, - 11: NotU { + 12: NotU { dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, width: 1, }, - // at: module-XXXXXXXXXX.rs:8:1 - 12: Copy { - dest: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, - src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:7:1 13: Copy { dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool }, @@ -383,241 +384,257 @@ Simulation { dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", ty: Clock }, src: StatePartIndex(42), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_3.clk", ty: Clock }, }, + // at: module-XXXXXXXXXX.rs:6:1 17: Copy { + dest: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 18: Copy { + dest: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 19: Copy { dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool }, src: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 - 18: Copy { + 20: Copy { dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, src: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.o", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 19: Copy { + 21: Copy { dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, }, - 20: NotU { + 22: NotU { dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, width: 1, }, - // at: module-XXXXXXXXXX.rs:8:1 - 21: Copy { - dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, - src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:7:1 - 22: Copy { + 23: Copy { dest: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 23: Copy { + 24: Copy { dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Clock }, src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:10:1 - 24: Copy { + 25: Copy { dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock }, src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Clock }, }, // at: module-XXXXXXXXXX.rs:9:1 - 25: Copy { + 26: Copy { dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", ty: Clock }, src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_1.clk", ty: Clock }, }, + // at: module-XXXXXXXXXX.rs:6:1 + 27: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 28: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 26: Const { + 29: Const { dest: StatePartIndex(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, value: 0x0, }, - 27: Copy { + 30: Copy { dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, src: StatePartIndex(28), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, }, - 28: Copy { + 31: Copy { dest: StatePartIndex(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::clk", ty: Clock }, }, - 29: Copy { + 32: Copy { dest: StatePartIndex(27), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:6:1 - 30: IsNonZeroDestIsSmall { + 33: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(26), // (0x1) SlotDebugData { name: ".clk", ty: Clock }, }, - 31: AndSmall { + 34: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 32: Copy { + 35: Copy { dest: StatePartIndex(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Clock }, }, - 33: Copy { + 36: Copy { dest: StatePartIndex(39), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:6:1 - 34: IsNonZeroDestIsSmall { + 37: IsNonZeroDestIsSmall { dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(38), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, }, - 35: AndSmall { + 38: AndSmall { dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 36: Copy { + 39: Copy { dest: StatePartIndex(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, src: StatePartIndex(51), // (0x0) SlotDebugData { name: "", ty: Clock }, }, - 37: Copy { + 40: Copy { dest: StatePartIndex(50), // (0x0) SlotDebugData { name: ".rst", ty: SyncReset }, src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:6:1 - 38: IsNonZeroDestIsSmall { + 41: IsNonZeroDestIsSmall { dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(49), // (0x0) SlotDebugData { name: ".clk", ty: Clock }, }, - 39: AndSmall { + 42: AndSmall { dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:1:1 - 40: Copy { + 43: Copy { dest: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[5]", ty: Bool }, }, - 41: Shl { + 44: Shl { dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, lhs: StatePartIndex(21), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 5, }, - 42: Copy { + 45: Copy { dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[4]", ty: Bool }, }, - 43: Shl { + 46: Shl { dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 4, }, - 44: Copy { + 47: Copy { dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[3]", ty: Bool }, }, - 45: Shl { + 48: Shl { dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, lhs: StatePartIndex(15), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 3, }, - 46: Copy { + 49: Copy { dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[2]", ty: Bool }, }, - 47: Shl { + 50: Shl { dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, lhs: StatePartIndex(12), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 2, }, - 48: Copy { + 51: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[1]", ty: Bool }, }, - 49: Shl { + 52: Shl { dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, lhs: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: 1, }, - 50: Copy { + 53: Copy { dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bits[0]", ty: Bool }, }, - 51: Or { + 54: Or { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, lhs: StatePartIndex(8), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, rhs: StatePartIndex(10), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, }, - 52: Or { + 55: Or { dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, lhs: StatePartIndex(11), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, rhs: StatePartIndex(13), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, }, - 53: Or { + 56: Or { dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, lhs: StatePartIndex(14), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, rhs: StatePartIndex(16), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, }, - 54: Or { + 57: Or { dest: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(17), // (0x0) SlotDebugData { name: "", ty: UInt<4> }, rhs: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, }, - 55: Or { + 58: Or { dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, lhs: StatePartIndex(20), // (0x0) SlotDebugData { name: "", ty: UInt<5> }, rhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:5:1 - 56: Copy { + 59: Copy { dest: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::o", ty: UInt<6> }, src: StatePartIndex(23), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:6:1 - 57: BranchIfSmallZero { - target: 59, + 60: BranchIfSmallZero { + target: 62, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 58: Copy { + 61: Copy { dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0", ty: Bool }, src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_0$next", ty: Bool }, }, - 59: BranchIfSmallZero { - target: 61, + 62: BranchIfSmallZero { + target: 64, value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 60: Copy { + 63: Copy { dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2", ty: Bool }, src: StatePartIndex(37), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_2$next", ty: Bool }, }, - 61: BranchIfSmallZero { - target: 63, + 64: BranchIfSmallZero { + target: 66, value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 62: Copy { + 65: Copy { dest: StatePartIndex(47), // (0x0) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4", ty: Bool }, src: StatePartIndex(48), // (0x1) SlotDebugData { name: "InstantiatedModule(ripple_counter: ripple_counter).ripple_counter::bit_reg_4$next", ty: Bool }, }, - 63: XorSmallImmediate { + 66: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, - 64: XorSmallImmediate { + 67: XorSmallImmediate { dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, - 65: XorSmallImmediate { + 68: XorSmallImmediate { dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 66: Return, + 69: Return, ], .. }, - pc: 66, + pc: 69, memory_write_log: [], memories: StatePart { value: [], diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt index 7dcf26c..2e1b176 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -103,137 +103,156 @@ Simulation { dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::q", ty: Bool }, src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, }, - // at: module-XXXXXXXXXX.rs:12:1 + // at: module-XXXXXXXXXX.rs:11:1 1: Copy { + dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:12:1 + 2: Copy { dest: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, src: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, }, + // at: module-XXXXXXXXXX.rs:9:1 + 3: Copy { + dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, + src: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:10:1 - 2: Copy { + 4: Copy { dest: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, }, + // at: module-XXXXXXXXXX.rs:7:1 + 5: Copy { + dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:8:1 - 3: Copy { + 6: Copy { dest: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, }, - // at: module-XXXXXXXXXX.rs:6:1 - 4: Copy { - dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, - src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:5:1 - 5: IsNonZeroDestIsSmall { + 7: IsNonZeroDestIsSmall { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset }, }, - 6: IsNonZeroDestIsSmall { + 8: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, }, - 7: AndSmall { + 9: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + 10: Copy { + dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, + src: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 11: Copy { + dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::d", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Const { + 12: Const { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, value: 0x0, }, // at: module-XXXXXXXXXX.rs:5:1 - 9: BranchIfSmallZero { - target: 14, + 13: BranchIfSmallZero { + target: 18, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 10: BranchIfSmallNonZero { - target: 13, + 14: BranchIfSmallNonZero { + target: 17, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 11: Copy { + 15: Copy { dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, src: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0$next", ty: Bool }, }, - 12: Branch { - target: 14, + 16: Branch { + target: 18, }, - 13: Copy { + 17: Copy { dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg0", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:7:1 - 14: BranchIfSmallZero { - target: 19, + 18: BranchIfSmallZero { + target: 23, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 15: BranchIfSmallNonZero { - target: 18, + 19: BranchIfSmallNonZero { + target: 22, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 16: Copy { + 20: Copy { dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1$next", ty: Bool }, }, - 17: Branch { - target: 19, + 21: Branch { + target: 23, }, - 18: Copy { + 22: Copy { dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg1", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:9:1 - 19: BranchIfSmallZero { - target: 24, + 23: BranchIfSmallZero { + target: 28, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 20: BranchIfSmallNonZero { - target: 23, + 24: BranchIfSmallNonZero { + target: 27, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 21: Copy { + 25: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, src: StatePartIndex(10), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2$next", ty: Bool }, }, - 22: Branch { - target: 24, + 26: Branch { + target: 28, }, - 23: Copy { + 27: Copy { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg2", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:11:1 - 24: BranchIfSmallZero { - target: 29, + 28: BranchIfSmallZero { + target: 33, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 25: BranchIfSmallNonZero { - target: 28, + 29: BranchIfSmallNonZero { + target: 32, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 26: Copy { + 30: Copy { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, src: StatePartIndex(12), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3$next", ty: Bool }, }, - 27: Branch { - target: 29, + 31: Branch { + target: 33, }, - 28: Copy { + 32: Copy { dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::reg3", ty: Bool }, src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:5:1 - 29: XorSmallImmediate { + 33: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 30: Return, + 34: Return, ], .. }, - pc: 30, + pc: 34, memory_write_log: [], memories: StatePart { value: [], diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.txt b/crates/fayalite/tests/sim/expected/sim_only_connects.txt index af41fe2..827f3cc 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.txt +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.txt @@ -212,55 +212,55 @@ Simulation { dest: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: Bool }, value: 0x0, }, - // at: module-XXXXXXXXXX.rs:17:1 - 7: Copy { - dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, - src: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:16:1 - 8: CloneSimOnly { - dest: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, - src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, - }, // at: module-XXXXXXXXXX.rs:12:1 - 9: CloneSimOnly { + 7: CloneSimOnly { dest: StatePartIndex(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly>> }, src: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:13:1 - 10: BranchIfZero { - target: 12, + 8: BranchIfZero { + target: 10, value: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:15:1 - 11: CloneSimOnly { + 9: CloneSimOnly { dest: StatePartIndex(1), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out1", ty: SimOnly>> }, src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:11:1 - 12: CloneSimOnly { + 10: CloneSimOnly { dest: StatePartIndex(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly>> }, src: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:13:1 - 13: BranchIfZero { - target: 15, + 11: BranchIfZero { + target: 13, value: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:14:1 - 14: CloneSimOnly { + 12: CloneSimOnly { dest: StatePartIndex(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly>> }, src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:10:1 - 15: Copy { + 13: Copy { dest: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.clk", ty: Clock }, }, - 16: Copy { + 14: Copy { dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::cd.rst", ty: SyncReset }, }, + // at: module-XXXXXXXXXX.rs:9:1 + 15: Copy { + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:17:1 + 16: Copy { + dest: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, + src: StatePartIndex(9), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 17: Const { dest: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, @@ -280,91 +280,100 @@ Simulation { lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - // at: module-XXXXXXXXXX.rs:7:1 21: CloneSimOnly { + dest: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, + src: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, + }, + // at: module-XXXXXXXXXX.rs:16:1 + 22: CloneSimOnly { + dest: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, + src: StatePartIndex(0), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::inp", ty: SimOnly>> }, + }, + // at: module-XXXXXXXXXX.rs:7:1 + 23: CloneSimOnly { dest: StatePartIndex(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly>> }, src: StatePartIndex(7), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::out", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:18:1 - 22: CloneSimOnly { + 24: CloneSimOnly { dest: StatePartIndex(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly>> }, src: StatePartIndex(5), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.out", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:21:1 - 23: CloneSimOnly { + 25: CloneSimOnly { dest: StatePartIndex(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly>> }, src: StatePartIndex(2), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::out2", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:19:1 - 24: CloneSimOnly { + 26: CloneSimOnly { dest: StatePartIndex(13), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly>> }, src: StatePartIndex(11), // ({"bar": "", "extra": "value", "foo": "baz"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper2.inp", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:7:1 - 25: CloneSimOnly { + 27: CloneSimOnly { dest: StatePartIndex(6), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::inp", ty: SimOnly>> }, src: StatePartIndex(4), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.inp", ty: SimOnly>> }, }, - 26: Copy { + 28: Copy { dest: StatePartIndex(4), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock }, src: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.clk", ty: Clock }, }, - 27: Copy { + 29: Copy { dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.rst", ty: SyncReset }, src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::helper1.cd.rst", ty: SyncReset }, }, // at: module-XXXXXXXXXX.rs:8:1 - 28: BranchIfSmallZero { - target: 33, + 30: BranchIfSmallZero { + target: 35, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 29: BranchIfSmallNonZero { - target: 32, + 31: BranchIfSmallNonZero { + target: 34, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 30: CloneSimOnly { + 32: CloneSimOnly { dest: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, src: StatePartIndex(9), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1$next", ty: SimOnly>> }, }, - 31: Branch { - target: 33, + 33: Branch { + target: 35, }, - 32: CloneSimOnly { + 34: CloneSimOnly { dest: StatePartIndex(8), // ({"extra": "value"}) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1", ty: SimOnly>> }, src: StatePartIndex(10), // ({}) SlotDebugData { name: "", ty: SimOnly>> }, }, // at: module-XXXXXXXXXX.rs:9:1 - 33: BranchIfSmallZero { - target: 38, + 35: BranchIfSmallZero { + target: 40, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 34: BranchIfSmallNonZero { - target: 37, + 36: BranchIfSmallNonZero { + target: 39, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, - 35: Copy { + 37: Copy { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty$next", ty: Bool }, }, - 36: Branch { - target: 38, + 38: Branch { + target: 40, }, - 37: Copy { + 39: Copy { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_only_connects: sim_only_connects).sim_only_connects::delay1_empty", ty: Bool }, src: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:8:1 - 38: XorSmallImmediate { + 40: XorSmallImmediate { dest: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: 0x1, }, // at: module-XXXXXXXXXX.rs:1:1 - 39: Return, + 41: Return, ], .. }, - pc: 39, + pc: 41, memory_write_log: [], memories: StatePart { value: [], From a0b2dc085c00fdc5fe06ad175e6b2f7144fb3404 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 24 Mar 2026 23:28:37 -0700 Subject: [PATCH 02/10] add test that simulator handles last-connect semantics properly --- crates/fayalite/tests/sim.rs | 70 ++ .../tests/sim/expected/last_connect.txt | 701 ++++++++++++++++++ .../tests/sim/expected/last_connect.vcd | 104 +++ 3 files changed, 875 insertions(+) create mode 100644 crates/fayalite/tests/sim/expected/last_connect.txt create mode 100644 crates/fayalite/tests/sim/expected/last_connect.vcd diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index cbe0b58..d93b9cf 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -2495,3 +2495,73 @@ fn test_sim_read_past() { panic!(); } } + +#[hdl_module(outline_generated)] +pub fn last_connect() { + #[hdl] + let inp: HdlOption> = m.input(); + #[hdl] + let out: HdlOption> = m.output(); + connect(out, HdlNone()); + #[hdl] + if let HdlSome(v) = inp { + #[hdl] + let w = wire(); + connect(out, HdlSome(w)); + connect(w, v.len() as u8); + for (i, v) in v.into_iter().enumerate() { + #[hdl] + if v { + connect(w, i as u8); + } + } + } +} + +#[hdl] +#[test] +fn test_last_connect() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(last_connect()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + let bools = [false, true]; + sim.write(sim.io().inp, HdlNone()); + sim.advance_time(SimDuration::from_micros(1)); + let expected: SimValue>> = #[hdl(sim)] + HdlNone(); + assert_eq!(sim.read(sim.io().out), expected); + for a in bools { + for b in bools { + for c in bools { + for d in bools { + let inp = [a, b, c, d]; + sim.write(sim.io().inp, HdlSome(inp)); + sim.advance_time(SimDuration::from_micros(1)); + let mut expected = inp.len() as u8; + for (i, v) in inp.into_iter().enumerate() { + if v { + expected = i as u8; + } + } + let expected: SimValue>> = #[hdl(sim)] + HdlSome(expected); + let out = sim.read(sim.io().out); + println!("expected={expected:?} out={out:?} inp={inp:?}"); + assert_eq!(expected, out); + } + } + } + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/last_connect.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/last_connect.txt") { + panic!(); + } +} diff --git a/crates/fayalite/tests/sim/expected/last_connect.txt b/crates/fayalite/tests/sim/expected/last_connect.txt new file mode 100644 index 0000000..6a43497 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/last_connect.txt @@ -0,0 +1,701 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 2, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 33, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", + ty: Enum { + HdlNone, + HdlSome(Array), + }, + }, + SlotDebugData { + name: "[0]", + ty: Bool, + }, + SlotDebugData { + name: "[1]", + ty: Bool, + }, + SlotDebugData { + name: "[2]", + ty: Bool, + }, + SlotDebugData { + name: "[3]", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<5>, + }, + SlotDebugData { + name: "", + ty: UInt<4>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(last_connect: last_connect).last_connect::out", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(last_connect: last_connect).last_connect::w", + ty: UInt<8>, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + 0: Const { + dest: StatePartIndex(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x3, + }, + 1: Const { + dest: StatePartIndex(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x2, + }, + 2: Const { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x1, + }, + 3: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + 4: Const { + dest: StatePartIndex(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x4, + }, + // at: module-XXXXXXXXXX.rs:8:1 + 5: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 6: Const { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 7: Const { + dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 8: Copy { + dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 9: Copy { + dest: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 10: Copy { + dest: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + src: StatePartIndex(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array)} }, + }, + 11: SliceInt { + dest: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + src: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> }, + start: 1, + len: 4, + }, + 12: SliceInt { + dest: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 0, + len: 1, + }, + 13: Copy { + dest: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: SliceInt { + dest: StatePartIndex(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 1, + len: 1, + }, + 15: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: SliceInt { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 2, + len: 1, + }, + 17: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: SliceInt { + dest: StatePartIndex(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> }, + start: 3, + len: 1, + }, + 19: Copy { + dest: StatePartIndex(14), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 20: Copy { + dest: StatePartIndex(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool }, + src: StatePartIndex(8), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 21: Copy { + dest: StatePartIndex(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool }, + src: StatePartIndex(10), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 22: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 23: Copy { + dest: StatePartIndex(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool }, + src: StatePartIndex(14), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 24: BranchIfZero { + target: 26, + value: StatePartIndex(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 25: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 26: BranchIfZero { + target: 28, + value: StatePartIndex(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 27: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 28: BranchIfZero { + target: 30, + value: StatePartIndex(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 29: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:9:1 + 30: BranchIfZero { + target: 32, + value: StatePartIndex(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:10:1 + 31: Copy { + dest: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + src: StatePartIndex(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 32: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 33: Copy { + dest: StatePartIndex(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> }, + }, + 34: Shl { + dest: StatePartIndex(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 35: Or { + dest: StatePartIndex(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> }, + }, + 36: CastToUInt { + dest: StatePartIndex(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 37: Copy { + dest: StatePartIndex(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + 38: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array)} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 39: BranchIfSmallNeImmediate { + target: 41, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:7:1 + 40: Copy { + dest: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 41: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 42: Copy { + dest: StatePartIndex(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 43: SliceInt { + dest: StatePartIndex(17), // (0x3) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + 44: Return, + ], + .. + }, + pc: 44, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [ + 1, + 1, + ], + }, + big_slots: StatePart { + value: [ + 31, + 1, + 1, + 1, + 1, + 31, + 15, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 1, + 7, + 7, + 3, + 0, + 0, + 3, + 1, + 3, + 1, + 6, + 7, + 7, + 7, + 4, + 0, + 1, + 2, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.inp, + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.out, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.inp, + Instance { + name: ::last_connect, + instantiated: Module { + name: last_connect, + .. + }, + }.out, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "last_connect", + children: [ + TraceModuleIO { + name: "inp", + child: TraceEnumWithFields { + name: "inp", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(0), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(Array), + }, + flow: Source, + }, + non_empty_fields: [ + TraceArray { + name: "HdlSome", + elements: [ + TraceBool { + location: TraceScalarId(1), + name: "[0]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(2), + name: "[1]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(3), + name: "[2]", + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "[3]", + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(Array), + }, + flow: Source, + }, + ty: Enum { + HdlNone, + HdlSome(Array), + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceEnumWithFields { + name: "out", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceWire { + name: "w", + child: TraceUInt { + location: TraceScalarId(7), + name: "w", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(Array), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigBool { + index: StatePartIndex(1), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigBool { + index: StatePartIndex(2), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(4), + }, + state: 0x1, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(17), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x02, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigUInt { + index: StatePartIndex(20), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x02, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 17 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/last_connect.vcd b/crates/fayalite/tests/sim/expected/last_connect.vcd new file mode 100644 index 0000000..b8b2f56 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/last_connect.vcd @@ -0,0 +1,104 @@ +$timescale 1 ps $end +$scope module last_connect $end +$scope struct inp $end +$var string 1 !C&}* \$tag $end +$scope struct HdlSome $end +$var wire 1 D_viZ \[0] $end +$var wire 1 b5gFK \[1] $end +$var wire 1 xUBRH \[2] $end +$var wire 1 Gp7Xm \[3] $end +$upscope $end +$upscope $end +$scope struct out $end +$var string 1 ^Z_p3 \$tag $end +$var wire 8 rz~), HdlSome $end +$upscope $end +$var wire 8 dlea> w $end +$upscope $end +$enddefinitions $end +$dumpvars +sHdlNone\x20(0) !C&}* +0D_viZ +0b5gFK +0xUBRH +0Gp7Xm +sHdlNone\x20(0) ^Z_p3 +b0 rz~), +b100 dlea> +$end +#1000000 +sHdlSome\x20(1) !C&}* +sHdlSome\x20(1) ^Z_p3 +b100 rz~), +#2000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#3000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#4000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#5000000 +1b5gFK +0xUBRH +0Gp7Xm +b1 rz~), +b1 dlea> +#6000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#7000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#8000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#9000000 +1D_viZ +0b5gFK +0xUBRH +0Gp7Xm +b0 rz~), +b0 dlea> +#10000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#11000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#12000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#13000000 +1b5gFK +0xUBRH +0Gp7Xm +b1 rz~), +b1 dlea> +#14000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#15000000 +1xUBRH +0Gp7Xm +b10 rz~), +b10 dlea> +#16000000 +1Gp7Xm +b11 rz~), +b11 dlea> +#17000000 From 2aa41137d4eec592bd591fddb558bc78a52c635c Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 24 Mar 2026 23:30:15 -0700 Subject: [PATCH 03/10] add simulator tests for queue() --- crates/fayalite/tests/sim.rs | 278 ++- .../sim/expected/queue_1_false_false.txt | 2134 ++++++++++++++++ .../sim/expected/queue_1_false_false.vcd | 1916 +++++++++++++++ .../tests/sim/expected/queue_1_false_true.txt | 2113 ++++++++++++++++ .../tests/sim/expected/queue_1_false_true.vcd | 1836 ++++++++++++++ .../tests/sim/expected/queue_1_true_false.txt | 2144 ++++++++++++++++ .../tests/sim/expected/queue_1_true_false.vcd | 1821 ++++++++++++++ .../tests/sim/expected/queue_1_true_true.txt | 2123 ++++++++++++++++ .../tests/sim/expected/queue_1_true_true.vcd | 1804 ++++++++++++++ .../sim/expected/queue_2_false_false.txt | 2152 ++++++++++++++++ .../sim/expected/queue_2_false_false.vcd | 2117 ++++++++++++++++ .../tests/sim/expected/queue_2_false_true.txt | 2131 ++++++++++++++++ .../tests/sim/expected/queue_2_false_true.vcd | 2075 ++++++++++++++++ .../tests/sim/expected/queue_2_true_false.txt | 2162 ++++++++++++++++ .../tests/sim/expected/queue_2_true_false.vcd | 2035 +++++++++++++++ .../tests/sim/expected/queue_2_true_true.txt | 2141 ++++++++++++++++ .../tests/sim/expected/queue_2_true_true.vcd | 2043 ++++++++++++++++ .../sim/expected/queue_3_false_false.txt | 2162 ++++++++++++++++ .../sim/expected/queue_3_false_false.vcd | 1990 +++++++++++++++ .../tests/sim/expected/queue_3_false_true.txt | 2141 ++++++++++++++++ .../tests/sim/expected/queue_3_false_true.vcd | 2002 +++++++++++++++ .../tests/sim/expected/queue_3_true_false.txt | 2172 +++++++++++++++++ .../tests/sim/expected/queue_3_true_false.vcd | 1949 +++++++++++++++ .../tests/sim/expected/queue_3_true_true.txt | 2151 ++++++++++++++++ .../tests/sim/expected/queue_3_true_true.vcd | 1935 +++++++++++++++ .../sim/expected/queue_4_false_false.txt | 2160 ++++++++++++++++ .../sim/expected/queue_4_false_false.vcd | 2025 +++++++++++++++ .../tests/sim/expected/queue_4_false_true.txt | 2139 ++++++++++++++++ .../tests/sim/expected/queue_4_false_true.vcd | 2021 +++++++++++++++ .../tests/sim/expected/queue_4_true_false.txt | 2170 ++++++++++++++++ .../tests/sim/expected/queue_4_true_false.vcd | 1993 +++++++++++++++ .../tests/sim/expected/queue_4_true_true.txt | 2149 ++++++++++++++++ .../tests/sim/expected/queue_4_true_true.vcd | 1989 +++++++++++++++ 33 files changed, 66172 insertions(+), 1 deletion(-) create mode 100644 crates/fayalite/tests/sim/expected/queue_1_false_false.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_1_false_false.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_1_false_true.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_1_false_true.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_1_true_false.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_1_true_false.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_1_true_true.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_1_true_true.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_2_false_false.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_2_false_false.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_2_false_true.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_2_false_true.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_2_true_false.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_2_true_false.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_2_true_true.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_2_true_true.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_3_false_false.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_3_false_false.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_3_false_true.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_3_false_true.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_3_true_false.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_3_true_false.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_3_true_true.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_3_true_true.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_4_false_false.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_4_false_false.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_4_false_true.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_4_false_true.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_4_true_false.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_4_true_false.vcd create mode 100644 crates/fayalite/tests/sim/expected/queue_4_true_true.txt create mode 100644 crates/fayalite/tests/sim/expected/queue_4_true_true.vcd diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index d93b9cf..e57c064 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -7,7 +7,7 @@ use fayalite::{ prelude::*, reset::ResetType, sim::vcd::VcdWriterDecls, - util::RcWriter, + util::{RcWriter, ready_valid::queue}, }; use std::{collections::BTreeMap, num::NonZeroUsize, rc::Rc}; @@ -2565,3 +2565,279 @@ fn test_last_connect() { panic!(); } } + +#[track_caller] +#[hdl] +fn test_queue_helper( + capacity: usize, + inp_ready_is_comb: bool, + out_valid_is_comb: bool, + expected_vcd: &str, + expected_sim_debug: &str, +) { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(queue( + UInt::<8>::new_static(), + NonZeroUsize::new(capacity).expect("capacity should be non-zero"), + inp_ready_is_comb, + out_valid_is_comb, + )); + let writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + struct DumpVcdOnDrop { + writer: Option, + } + impl Drop for DumpVcdOnDrop { + fn drop(&mut self) { + if let Some(mut writer) = self.writer.take() { + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + } + } + } + let mut writer = DumpVcdOnDrop { + writer: Some(writer), + }; + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, true); + let mut input_value = 0u8; + let mut expected_output_value = 0u8; + /// deterministic random numbers + fn rand(mut v: u32) -> bool { + // random 32-bit primes + v = v.wrapping_mul(0xF807B7EF).rotate_left(16); + v ^= 0xA1E24BBA; // random 32-bit constant + v = v.wrapping_mul(0xE9D30017).rotate_left(16); + v = v.wrapping_mul(0x3895AFFB).rotate_left(16); + v & 1 != 0 + } + for cycle in 0..100u32 { + println!("cycle: {cycle}"); + sim.write( + sim.io().inp.data, + if rand(cycle) { + #[hdl(sim)] + HdlSome(input_value) + } else { + #[hdl(sim)] + HdlNone() + }, + ); + sim.write_bool(sim.io().out.ready, rand(u32::MAX / 2 + cycle)); + sim.advance_time(SimDuration::from_nanos(500)); + if !sim.read_reset(sim.io().cd.rst) { + let inp_ready = sim.read_bool(sim.io().inp.ready); + if inp_ready { + #[hdl(sim)] + if let HdlSome(v) = sim.read(sim.io().inp.data) { + println!("enqueued {v}, expected {input_value:#x}"); + assert_eq!(v.as_int(), input_value); + input_value = input_value.wrapping_add(1); + } + } + let out_valid = #[hdl(sim)] + if let HdlSome(v) = sim.read(sim.io().out.data) { + if sim.read_bool(sim.io().out.ready) { + println!("dequeued {v}, expected {expected_output_value:#x}"); + assert_eq!(v.as_int(), expected_output_value); + expected_output_value = expected_output_value.wrapping_add(1); + } + true + } else { + false + }; + assert!(inp_ready || out_valid, "queue isn't making progress"); + } + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_nanos(500)); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, false); + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != expected_vcd { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != expected_sim_debug { + panic!(); + } +} + +#[test] +fn test_queue_1_false_false() { + test_queue_helper( + 1, + false, + false, + include_str!("sim/expected/queue_1_false_false.vcd"), + include_str!("sim/expected/queue_1_false_false.txt"), + ); +} + +#[test] +fn test_queue_1_false_true() { + test_queue_helper( + 1, + false, + true, + include_str!("sim/expected/queue_1_false_true.vcd"), + include_str!("sim/expected/queue_1_false_true.txt"), + ); +} + +#[test] +fn test_queue_1_true_false() { + test_queue_helper( + 1, + true, + false, + include_str!("sim/expected/queue_1_true_false.vcd"), + include_str!("sim/expected/queue_1_true_false.txt"), + ); +} + +#[test] +fn test_queue_1_true_true() { + test_queue_helper( + 1, + true, + true, + include_str!("sim/expected/queue_1_true_true.vcd"), + include_str!("sim/expected/queue_1_true_true.txt"), + ); +} + +#[test] +fn test_queue_2_false_false() { + test_queue_helper( + 2, + false, + false, + include_str!("sim/expected/queue_2_false_false.vcd"), + include_str!("sim/expected/queue_2_false_false.txt"), + ); +} + +#[test] +fn test_queue_2_false_true() { + test_queue_helper( + 2, + false, + true, + include_str!("sim/expected/queue_2_false_true.vcd"), + include_str!("sim/expected/queue_2_false_true.txt"), + ); +} + +#[test] +fn test_queue_2_true_false() { + test_queue_helper( + 2, + true, + false, + include_str!("sim/expected/queue_2_true_false.vcd"), + include_str!("sim/expected/queue_2_true_false.txt"), + ); +} + +#[test] +fn test_queue_2_true_true() { + test_queue_helper( + 2, + true, + true, + include_str!("sim/expected/queue_2_true_true.vcd"), + include_str!("sim/expected/queue_2_true_true.txt"), + ); +} + +#[test] +fn test_queue_3_false_false() { + test_queue_helper( + 3, + false, + false, + include_str!("sim/expected/queue_3_false_false.vcd"), + include_str!("sim/expected/queue_3_false_false.txt"), + ); +} + +#[test] +fn test_queue_3_false_true() { + test_queue_helper( + 3, + false, + true, + include_str!("sim/expected/queue_3_false_true.vcd"), + include_str!("sim/expected/queue_3_false_true.txt"), + ); +} + +#[test] +fn test_queue_3_true_false() { + test_queue_helper( + 3, + true, + false, + include_str!("sim/expected/queue_3_true_false.vcd"), + include_str!("sim/expected/queue_3_true_false.txt"), + ); +} + +#[test] +fn test_queue_3_true_true() { + test_queue_helper( + 3, + true, + true, + include_str!("sim/expected/queue_3_true_true.vcd"), + include_str!("sim/expected/queue_3_true_true.txt"), + ); +} + +#[test] +fn test_queue_4_false_false() { + test_queue_helper( + 4, + false, + false, + include_str!("sim/expected/queue_4_false_false.vcd"), + include_str!("sim/expected/queue_4_false_false.txt"), + ); +} + +#[test] +fn test_queue_4_false_true() { + test_queue_helper( + 4, + false, + true, + include_str!("sim/expected/queue_4_false_true.vcd"), + include_str!("sim/expected/queue_4_false_true.txt"), + ); +} + +#[test] +fn test_queue_4_true_false() { + test_queue_helper( + 4, + true, + false, + include_str!("sim/expected/queue_4_true_false.vcd"), + include_str!("sim/expected/queue_4_true_false.txt"), + ); +} + +#[test] +fn test_queue_4_true_true() { + test_queue_helper( + 4, + true, + true, + include_str!("sim/expected/queue_4_true_true.vcd"), + include_str!("sim/expected/queue_4_true_true.txt"), + ); +} diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_false.txt b/crates/fayalite/tests/sim/expected/queue_1_false_false.txt new file mode 100644 index 0000000..570c08d --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_false_false.txt @@ -0,0 +1,2134 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 10: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 11: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 12: Add { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Add { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 16: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 17: Copy { + dest: StatePartIndex(42), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 18: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 19: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 20: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 21: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 22: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 23: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 24: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 25: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 26: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 27: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 29: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 31: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 32: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 34: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 35: BranchIfZero { + target: 38, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 37: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 38: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 39: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 40: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 41: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 42: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 43: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 44: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 45: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 46: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 47: BranchIfZero { + target: 50, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 48: BranchIfNonZero { + target: 50, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 49: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 50: BranchIfNonZero { + target: 52, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 51: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 52: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 57: BranchIfSmallZero { + target: 60, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: MemoryReadUInt { + dest: StatePartIndex(14), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x19, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 59: Branch { + target: 61, + }, + 60: Const { + dest: StatePartIndex(14), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 61: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 62: Copy { + dest: StatePartIndex(47), // (0x19) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 63: Shl { + dest: StatePartIndex(49), // (0x32) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x19) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 64: Or { + dest: StatePartIndex(50), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x32) SlotDebugData { name: "", ty: UInt<9> }, + }, + 65: CastToUInt { + dest: StatePartIndex(51), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 66: Copy { + dest: StatePartIndex(52), // (0x33) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 67: BranchIfZero { + target: 69, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 68: Copy { + dest: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x33) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 69: BranchIfNonZero { + target: 71, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 70: Copy { + dest: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 71: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 72: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 73: Copy { + dest: StatePartIndex(8), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 74: SliceInt { + dest: StatePartIndex(9), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 75: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 76: BranchIfSmallNeImmediate { + target: 78, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 77: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 78: BranchIfSmallNeImmediate { + target: 80, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 79: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 80: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 81: BranchIfZero { + target: 86, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 82: BranchIfZero { + target: 84, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 83: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 84: BranchIfNonZero { + target: 86, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 85: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 86: Copy { + dest: StatePartIndex(4), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 87: SliceInt { + dest: StatePartIndex(5), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x33) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 88: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x33) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 89: BranchIfSmallNeImmediate { + target: 91, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 90: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 91: BranchIfSmallNeImmediate { + target: 93, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 92: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 93: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 94: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 95: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 96: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 97: BranchIfZero { + target: 99, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 98: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 99: BranchIfZero { + target: 104, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 101: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 102: BranchIfNonZero { + target: 104, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 103: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 104: BranchIfSmallNeImmediate { + target: 106, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 105: Copy { + dest: StatePartIndex(42), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 106: Copy { + dest: StatePartIndex(18), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 107: BranchIfSmallZero { + target: 112, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: BranchIfSmallNonZero { + target: 111, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 110: Branch { + target: 112, + }, + 111: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 122: BranchIfSmallZero { + target: 123, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallZero { + target: 131, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 125: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: Copy { + dest: StatePartIndex(20), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x19) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 127: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 131, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 129: BranchIfZero { + target: 131, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 130: MemoryWriteUInt { + value: StatePartIndex(20), // (0x19) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x19, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 133: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 134: Return, + ], + .. + }, + pc: 134, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x19, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 51, + 0, + 51, + 25, + 51, + 0, + 51, + 25, + 1, + 0, + 1, + 0, + 25, + 0, + 0, + 0, + 25, + 1, + 25, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 25, + 0, + 0, + 1, + 1, + 25, + 1, + 50, + 51, + 51, + 51, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x19, + last_state: 0x19, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_1_false_false.vcd new file mode 100644 index 0000000..30dbbec --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_false_false.vcd @@ -0,0 +1,1916 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 68, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 10: Add { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 11: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 12: Add { + dest: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 15: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 16: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 17: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 18: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 19: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 20: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 21: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 22: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 23: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 24: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 25: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 26: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 27: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 29: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 30: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 32: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 33: BranchIfZero { + target: 36, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 34: BranchIfZero { + target: 36, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 35: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 36: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 37: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 38: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 39: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 40: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 41: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 42: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 43: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 44: CastToUInt { + dest: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 45: BranchIfZero { + target: 48, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 46: BranchIfNonZero { + target: 48, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 47: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 48: BranchIfNonZero { + target: 50, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 49: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 50: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 55: BranchIfSmallZero { + target: 58, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: MemoryReadUInt { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 57: Branch { + target: 59, + }, + 58: Const { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 59: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 60: Copy { + dest: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 61: Shl { + dest: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 62: Or { + dest: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + }, + 63: CastToUInt { + dest: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 64: Copy { + dest: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 65: BranchIfZero { + target: 67, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 66: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 67: BranchIfNonZero { + target: 69, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 68: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 69: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 70: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 71: Copy { + dest: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 72: SliceInt { + dest: StatePartIndex(9), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 73: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 74: BranchIfSmallNeImmediate { + target: 76, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 75: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 76: BranchIfSmallNeImmediate { + target: 78, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 77: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 78: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 79: BranchIfZero { + target: 84, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 80: BranchIfZero { + target: 82, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 81: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 82: BranchIfNonZero { + target: 84, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 83: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 84: Copy { + dest: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 85: SliceInt { + dest: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 86: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 87: BranchIfSmallNeImmediate { + target: 89, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 88: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 89: BranchIfSmallNeImmediate { + target: 91, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 90: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 91: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 92: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 93: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 94: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 95: BranchIfZero { + target: 97, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 96: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 97: BranchIfZero { + target: 102, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 99: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 100: BranchIfNonZero { + target: 102, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 101: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 102: BranchIfSmallNeImmediate { + target: 104, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 103: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 104: Copy { + dest: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 105: BranchIfSmallZero { + target: 110, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 106: BranchIfSmallNonZero { + target: 109, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 107: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 108: Branch { + target: 110, + }, + 109: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 120: BranchIfSmallZero { + target: 121, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallZero { + target: 129, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 123: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: Copy { + dest: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 125: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 129, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 127: BranchIfZero { + target: 129, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 128: MemoryWriteUInt { + value: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 129: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 130: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 131: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 132: Return, + ], + .. + }, + pc: 132, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x1f, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 63, + 0, + 63, + 31, + 63, + 0, + 63, + 31, + 1, + 0, + 1, + 0, + 31, + 0, + 0, + 0, + 31, + 1, + 31, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 31, + 0, + 0, + 1, + 1, + 31, + 1, + 62, + 63, + 63, + 63, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(64), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_1_false_true.vcd new file mode 100644 index 0000000..cc36d02 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_false_true.vcd @@ -0,0 +1,1836 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 10: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 11: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 12: Add { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Add { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 16: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 17: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 18: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 19: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 20: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 21: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 22: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 23: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 24: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 25: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 26: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 27: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 29: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 31: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 32: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 34: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 35: BranchIfZero { + target: 37, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 36: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 37: BranchIfZero { + target: 40, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 39: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 40: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 41: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 42: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 43: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 44: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 45: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 46: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 47: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 48: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 49: BranchIfZero { + target: 52, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 50: BranchIfNonZero { + target: 52, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 51: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 52: BranchIfNonZero { + target: 54, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 53: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 54: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 56: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 58: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 59: BranchIfSmallZero { + target: 62, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 60: MemoryReadUInt { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 61: Branch { + target: 63, + }, + 62: Const { + dest: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 63: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 64: Copy { + dest: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 65: Shl { + dest: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x1f) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 66: Or { + dest: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x3e) SlotDebugData { name: "", ty: UInt<9> }, + }, + 67: CastToUInt { + dest: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 68: Copy { + dest: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 69: BranchIfZero { + target: 71, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 70: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x3f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 71: BranchIfNonZero { + target: 73, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 72: Copy { + dest: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 73: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 74: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 75: Copy { + dest: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 76: SliceInt { + dest: StatePartIndex(9), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 77: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 78: BranchIfSmallNeImmediate { + target: 80, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 79: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 80: BranchIfSmallNeImmediate { + target: 82, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 81: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 82: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 83: BranchIfZero { + target: 88, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 84: BranchIfZero { + target: 86, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 85: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 86: BranchIfNonZero { + target: 88, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 87: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 88: Copy { + dest: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 89: SliceInt { + dest: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x3f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 90: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x3f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 91: BranchIfSmallNeImmediate { + target: 93, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 92: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 93: BranchIfSmallNeImmediate { + target: 95, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 94: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 95: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 96: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 97: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 98: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 99: BranchIfZero { + target: 101, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 100: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 101: BranchIfZero { + target: 106, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 102: BranchIfZero { + target: 104, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 103: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 104: BranchIfNonZero { + target: 106, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 105: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 106: BranchIfSmallNeImmediate { + target: 108, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 107: Copy { + dest: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 108: Copy { + dest: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 109: BranchIfSmallZero { + target: 114, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: BranchIfSmallNonZero { + target: 113, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 112: Branch { + target: 114, + }, + 113: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 114: BranchIfSmallZero { + target: 119, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: BranchIfSmallNonZero { + target: 118, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 117: Branch { + target: 119, + }, + 118: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 119: BranchIfSmallZero { + target: 124, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: BranchIfSmallNonZero { + target: 123, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 122: Branch { + target: 124, + }, + 123: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 124: BranchIfSmallZero { + target: 125, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: BranchIfSmallZero { + target: 133, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 127: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 128: Copy { + dest: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x1f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 129: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 130: BranchIfSmallZero { + target: 133, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 131: BranchIfZero { + target: 133, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 132: MemoryWriteUInt { + value: StatePartIndex(20), // (0x1f) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x1f, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 135: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 136: Return, + ], + .. + }, + pc: 136, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x1f, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 63, + 0, + 63, + 31, + 63, + 0, + 63, + 31, + 1, + 0, + 1, + 0, + 31, + 0, + 0, + 0, + 31, + 1, + 31, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 31, + 0, + 0, + 1, + 1, + 31, + 1, + 62, + 63, + 63, + 63, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x1f, + last_state: 0x1f, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_1_true_false.vcd new file mode 100644 index 0000000..0ddf51e --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_true_false.vcd @@ -0,0 +1,1821 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 68, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + dest_width: 1, + }, + 1: CastToUInt { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + dest_width: 0, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<0> }, + dest_width: 1, + }, + 4: Const { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 5: CastToUInt { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 1, + }, + 6: Const { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x0, + }, + 7: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 8: CmpEq { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: UInt<64> }, + }, + 9: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 10: Add { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 11: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 12: Add { + dest: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 13: CastToUInt { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 0, + }, + 14: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 15: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 16: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 17: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:114:5 + 18: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 19: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 20: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 21: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 22: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 23: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 24: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:104:5 + 25: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 26: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 27: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 29: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 30: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 32: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 33: BranchIfZero { + target: 35, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 34: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 35: BranchIfZero { + target: 38, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 37: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 38: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 39: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 40: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:84:31 + 41: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 42: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 43: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 44: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 45: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 46: CastToUInt { + dest: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + // at: ready_valid.rs:166:5 + 47: BranchIfZero { + target: 50, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 48: BranchIfNonZero { + target: 50, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 49: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(63), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:166:5 + 50: BranchIfNonZero { + target: 52, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 51: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<1> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:91:19 + 52: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<0> }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<0> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 57: BranchIfSmallZero { + target: 60, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: MemoryReadUInt { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x23, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 59: Branch { + target: 61, + }, + 60: Const { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 61: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 62: Copy { + dest: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 63: Shl { + dest: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 64: Or { + dest: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + }, + 65: CastToUInt { + dest: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 66: Copy { + dest: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 67: BranchIfZero { + target: 69, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 68: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 69: BranchIfNonZero { + target: 71, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 70: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 71: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 72: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 73: Copy { + dest: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 74: SliceInt { + dest: StatePartIndex(9), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 75: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 76: BranchIfSmallNeImmediate { + target: 78, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 77: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 78: BranchIfSmallNeImmediate { + target: 80, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 79: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 80: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 81: BranchIfZero { + target: 86, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 82: BranchIfZero { + target: 84, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 83: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:158:9 + 84: BranchIfNonZero { + target: 86, + value: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 85: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:64:1 + 86: Copy { + dest: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 87: SliceInt { + dest: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 88: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 89: BranchIfSmallNeImmediate { + target: 91, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 90: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 91: BranchIfSmallNeImmediate { + target: 93, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 92: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 93: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 94: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 95: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 96: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 97: BranchIfZero { + target: 99, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 98: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 99: BranchIfZero { + target: 104, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 101: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:148:9 + 102: BranchIfNonZero { + target: 104, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 103: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:118:30 + 104: BranchIfSmallNeImmediate { + target: 106, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 105: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 106: Copy { + dest: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 107: BranchIfSmallZero { + target: 112, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: BranchIfSmallNonZero { + target: 111, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<0> }, + }, + 110: Branch { + target: 112, + }, + 111: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:86:25 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<0> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<0> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: ready_valid.rs:88:26 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 122: BranchIfSmallZero { + target: 123, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallZero { + target: 131, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + }, + 125: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: Copy { + dest: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 127: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 131, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 129: BranchIfZero { + target: 131, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 130: MemoryWriteUInt { + value: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 1>, + // data: [ + // // len = 0x1 + // [0x0]: 0x23, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + stride: 8, + start: 0, + width: 8, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 133: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 134: Return, + ], + .. + }, + pc: 134, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 1>, + data: [ + // len = 0x1 + [0x0]: 0x23, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 71, + 0, + 71, + 35, + 71, + 0, + 71, + 35, + 1, + 0, + 1, + 0, + 35, + 0, + 0, + 0, + 35, + 1, + 35, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 35, + 0, + 0, + 1, + 1, + 35, + 1, + 70, + 71, + 71, + 71, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<1>, + flow: Sink, + }, + ty: UInt<1>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<0>, + flow: Duplex, + }, + ty: UInt<0>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(64), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + /* offset = 2 */ + data: UInt<8>, + /* offset = 10 */ + mask: Bool, + }, + }, + ], + array_type: Array, 1>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_1_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_1_true_true.vcd new file mode 100644 index 0000000..9fc4356 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_1_true_true.vcd @@ -0,0 +1,1804 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 1 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var string 0 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var string 0 Xk?#v inp_index_reg $end +$var string 0 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(68), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Add { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(71), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x22, + // [0x1]: 0x23, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x23) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x46) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x47) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 71: Copy { + dest: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(64), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x47) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x47) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x23) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x23) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x22, + // [0x1]: 0x23, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x22, + [0x1]: 0x23, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 71, + 1, + 71, + 35, + 71, + 0, + 71, + 35, + 1, + 1, + 1, + 0, + 35, + 0, + 1, + 0, + 35, + 1, + 35, + 1, + 0, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 35, + 0, + 1, + 1, + 1, + 35, + 1, + 70, + 71, + 71, + 71, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 2, + 0, + 2, + 2, + 0, + 1, + 3, + 1, + 1, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x23, + last_state: 0x23, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_2_false_false.vcd new file mode 100644 index 0000000..92a7278 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_false_false.vcd @@ -0,0 +1,2117 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(67), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(68), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(66), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 15: Add { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 36: BranchIfZero { + target: 41, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 37: BranchIfZero { + target: 39, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 38: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfNonZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 40: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 42: Copy { + dest: StatePartIndex(10), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(69), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 43: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 44: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 45: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 46: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 47: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 48: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 49: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 51: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 53: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 54: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 56: BranchIfSmallZero { + target: 59, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: MemoryReadUInt { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x25, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 58: Branch { + target: 60, + }, + 59: Const { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 60: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 61: Copy { + dest: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 62: Shl { + dest: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 63: Or { + dest: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + }, + 64: CastToUInt { + dest: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 65: Copy { + dest: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 66: BranchIfZero { + target: 68, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 67: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfNonZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 69: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 70: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 71: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 72: Copy { + dest: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 73: SliceInt { + dest: StatePartIndex(9), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 74: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 75: BranchIfSmallNeImmediate { + target: 77, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 76: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 79: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 80: BranchIfZero { + target: 85, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 81: BranchIfZero { + target: 83, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 82: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfNonZero { + target: 85, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 84: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 85: Copy { + dest: StatePartIndex(4), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 86: SliceInt { + dest: StatePartIndex(5), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 87: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 88: BranchIfSmallNeImmediate { + target: 90, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 89: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 92: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 93: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 94: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 95: CmpNe { + dest: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 96: BranchIfZero { + target: 98, + value: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 97: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 98: BranchIfZero { + target: 103, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 99: BranchIfZero { + target: 101, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 100: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfNonZero { + target: 103, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 102: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 103: BranchIfSmallNeImmediate { + target: 105, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 104: Copy { + dest: StatePartIndex(42), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 105: Copy { + dest: StatePartIndex(18), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 106: BranchIfSmallZero { + target: 111, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 107: BranchIfSmallNonZero { + target: 110, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 109: Branch { + target: 111, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 111: BranchIfSmallZero { + target: 116, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: BranchIfSmallNonZero { + target: 115, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 114: Branch { + target: 116, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 116: BranchIfSmallZero { + target: 121, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: BranchIfSmallNonZero { + target: 120, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 119: Branch { + target: 121, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 121: BranchIfSmallZero { + target: 122, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: BranchIfSmallZero { + target: 130, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 124: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 125: Copy { + dest: StatePartIndex(20), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 126: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 127: BranchIfSmallZero { + target: 130, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfZero { + target: 130, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 129: MemoryWriteUInt { + value: StatePartIndex(20), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x25, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 130: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 132: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 133: Return, + ], + .. + }, + pc: 133, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x26, + [0x1]: 0x25, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 77, + 1, + 77, + 38, + 77, + 0, + 77, + 38, + 1, + 0, + 1, + 0, + 38, + 1, + 1, + 0, + 38, + 1, + 38, + 1, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 38, + 0, + 1, + 1, + 1, + 38, + 1, + 76, + 77, + 77, + 77, + 1, + 1, + 1, + 0, + 0, + 2, + 0, + 0, + 1, + 1, + 2, + 2, + 0, + 1, + 1, + 1, + 1, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_2_false_true.vcd new file mode 100644 index 0000000..55da6e1 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_false_true.vcd @@ -0,0 +1,2075 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(56), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Add { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 39: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 40: BranchIfZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 42: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 44: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 45: BranchIfNonZero { + target: 47, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 46: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 47: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 48: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 49: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 50: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 54: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 55: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 57: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 59: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 60: BranchIfSmallZero { + target: 63, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 61: MemoryReadUInt { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x27, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 62: Branch { + target: 64, + }, + 63: Const { + dest: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 64: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 65: Copy { + dest: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x26) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 66: Shl { + dest: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x26) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 67: Or { + dest: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x4c) SlotDebugData { name: "", ty: UInt<9> }, + }, + 68: CastToUInt { + dest: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 69: Copy { + dest: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 71: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x4d) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfNonZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 73: Copy { + dest: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 74: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 75: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 76: Copy { + dest: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 77: SliceInt { + dest: StatePartIndex(9), // (0x26) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x4d) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 78: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x4d) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 83: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 84: BranchIfZero { + target: 89, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfZero { + target: 87, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 86: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfNonZero { + target: 89, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 88: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 89: Copy { + dest: StatePartIndex(4), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 90: SliceInt { + dest: StatePartIndex(5), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 91: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 95: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 96: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 97: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 98: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 99: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 101: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 102: BranchIfZero { + target: 107, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 104: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfNonZero { + target: 107, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 106: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 107: BranchIfSmallNeImmediate { + target: 109, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 108: Copy { + dest: StatePartIndex(42), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 109: Copy { + dest: StatePartIndex(18), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 120: BranchIfSmallZero { + target: 125, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallNonZero { + target: 124, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 123: Branch { + target: 125, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 125: BranchIfSmallZero { + target: 126, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 134, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + }, + 128: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: Copy { + dest: StatePartIndex(20), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 130: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 131: BranchIfSmallZero { + target: 134, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 132: BranchIfZero { + target: 134, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 133: MemoryWriteUInt { + value: StatePartIndex(20), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x26, + // [0x1]: 0x27, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 135: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 136: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 137: Return, + ], + .. + }, + pc: 137, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x26, + [0x1]: 0x27, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 79, + 0, + 79, + 39, + 77, + 0, + 77, + 38, + 2, + 0, + 1, + 0, + 38, + 0, + 0, + 0, + 39, + 1, + 39, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 39, + 0, + 0, + 1, + 1, + 38, + 1, + 76, + 77, + 77, + 77, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x26, + last_state: 0x26, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_2_true_false.vcd new file mode 100644 index 0000000..e54b985 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_true_false.vcd @@ -0,0 +1,2035 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<1>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x00, + [0x1]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + dest_width: 2, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<1> }, + dest_width: 2, + }, + 4: Const { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 1, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 9: Const { + dest: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x1, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(54), // (0x1) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 15: Add { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + dest_width: 1, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<1> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<1> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x2a, + // [0x1]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<1> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<1> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<1> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<1> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 2>, + // data: [ + // // len = 0x2 + // [0x0]: 0x2a, + // [0x1]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<1> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 2>, + data: [ + // len = 0x2 + [0x0]: 0x2a, + [0x1]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 85, + 0, + 85, + 42, + 83, + 0, + 83, + 41, + 2, + 1, + 1, + 0, + 41, + 1, + 0, + 0, + 42, + 1, + 42, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 42, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 1, + 1, + 0, + 0, + 2, + 0, + 1, + 2, + 0, + 2, + 2, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<1>, + flow: Duplex, + }, + ty: UInt<1>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<1>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<1>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 2, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + #[hdl(flip)] /* offset = 3 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<1>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<1>, + /* offset = 1 */ + en: Bool, + /* offset = 2 */ + clk: Clock, + /* offset = 3 */ + data: UInt<8>, + /* offset = 11 */ + mask: Bool, + }, + }, + ], + array_type: Array, 2>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_2_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_2_true_true.vcd new file mode 100644 index 0000000..f58f9ab --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_2_true_true.vcd @@ -0,0 +1,2043 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 1 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 1 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 1 Xk?#v inp_index_reg $end +$var reg 1 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 73, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(71), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(72), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(71), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(69), // (0x5) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x5) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 14: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 15: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 16: Add { + dest: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Add { + dest: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 19: CastToUInt { + dest: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 20: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 21: Copy { + dest: StatePartIndex(42), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 22: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 23: Copy { + dest: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 24: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 25: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 26: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 27: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 28: Copy { + dest: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 29: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 30: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 31: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 33: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 35: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 36: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 37: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 38: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 39: BranchIfZero { + target: 44, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 40: BranchIfZero { + target: 42, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 41: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 42: BranchIfNonZero { + target: 44, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 43: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 44: BranchIfNonZero { + target: 49, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 45: BranchIfZero { + target: 47, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 46: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 47: BranchIfNonZero { + target: 49, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 48: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(72), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 49: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 51: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 56: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 57: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 58: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 59: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 60: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 61: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 62: BranchIfSmallZero { + target: 65, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 63: MemoryReadUInt { + dest: StatePartIndex(14), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x27, + // [0x1]: 0x28, + // [0x2]: 0x26, + // ], + // }) (), + addr: StatePartIndex(6), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 64: Branch { + target: 66, + }, + 65: Const { + dest: StatePartIndex(14), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 66: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 67: Copy { + dest: StatePartIndex(47), // (0x27) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x27) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 68: Shl { + dest: StatePartIndex(49), // (0x4e) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x27) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 69: Or { + dest: StatePartIndex(50), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x4e) SlotDebugData { name: "", ty: UInt<9> }, + }, + 70: CastToUInt { + dest: StatePartIndex(51), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 71: Copy { + dest: StatePartIndex(52), // (0x4f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 73: Copy { + dest: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x4f) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 74: BranchIfNonZero { + target: 76, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 75: Copy { + dest: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 76: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 77: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 78: Copy { + dest: StatePartIndex(8), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 79: SliceInt { + dest: StatePartIndex(9), // (0x27) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x4f) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 80: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x4f) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 83: BranchIfSmallNeImmediate { + target: 85, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 84: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 85: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 86: BranchIfZero { + target: 91, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfZero { + target: 89, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 88: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 89: BranchIfNonZero { + target: 91, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 90: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 91: Copy { + dest: StatePartIndex(4), // (0x51) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x51) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 92: SliceInt { + dest: StatePartIndex(5), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x51) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 93: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x51) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 95: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 96: BranchIfSmallNeImmediate { + target: 98, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 97: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 98: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 99: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 100: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 101: CmpNe { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 102: BranchIfZero { + target: 104, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 103: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 104: BranchIfZero { + target: 109, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfZero { + target: 107, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 106: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 107: BranchIfNonZero { + target: 109, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 108: Copy { + dest: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 109: BranchIfSmallNeImmediate { + target: 111, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 110: Copy { + dest: StatePartIndex(42), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 111: Copy { + dest: StatePartIndex(18), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 122: BranchIfSmallZero { + target: 127, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallNonZero { + target: 126, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 125: Branch { + target: 127, + }, + 126: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 127: BranchIfSmallZero { + target: 128, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 136, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 130: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 131: Copy { + dest: StatePartIndex(20), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x28) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 132: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 133: BranchIfSmallZero { + target: 136, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 134: BranchIfZero { + target: 136, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 135: MemoryWriteUInt { + value: StatePartIndex(20), // (0x28) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x27, + // [0x1]: 0x28, + // [0x2]: 0x26, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 136: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 137: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 138: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 139: Return, + ], + .. + }, + pc: 139, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x27, + [0x1]: 0x28, + [0x2]: 0x26, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 1, + 0, + 0, + 1, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 81, + 1, + 81, + 40, + 79, + 0, + 79, + 39, + 2, + 0, + 1, + 0, + 39, + 2, + 1, + 0, + 40, + 1, + 40, + 1, + 2, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 40, + 0, + 1, + 1, + 1, + 39, + 1, + 78, + 79, + 79, + 79, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 3, + 3, + 0, + 1, + 1, + 3, + 3, + 0, + 5, + 5, + 1, + 2, + 2, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x28, + last_state: 0x28, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x27, + last_state: 0x27, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x28, + last_state: 0x28, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x28, + last_state: 0x28, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_3_false_false.vcd new file mode 100644 index 0000000..4481901 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_false_false.vcd @@ -0,0 +1,1990 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 71, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(65), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(67), // (0x2) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(68), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x2) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 14: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 16: Add { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 19: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 20: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 21: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 22: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 23: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 24: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 25: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 26: Copy { + dest: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 27: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 28: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 29: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 31: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 33: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 34: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 35: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 36: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 37: BranchIfZero { + target: 42, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 39: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 40: BranchIfNonZero { + target: 42, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 41: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 42: BranchIfNonZero { + target: 47, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 43: BranchIfZero { + target: 45, + value: StatePartIndex(65), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 44: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(68), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 45: BranchIfNonZero { + target: 47, + value: StatePartIndex(65), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 46: Copy { + dest: StatePartIndex(10), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 47: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 48: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 49: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 50: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 54: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 55: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 57: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 59: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 60: BranchIfSmallZero { + target: 63, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 61: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x28, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 62: Branch { + target: 64, + }, + 63: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 64: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 65: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 66: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 67: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 68: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 69: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfNonZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 73: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 74: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 75: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 76: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 77: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 78: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 83: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 84: BranchIfZero { + target: 89, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfZero { + target: 87, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 86: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfNonZero { + target: 89, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 88: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 89: Copy { + dest: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 90: SliceInt { + dest: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x55) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 91: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x55) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 93: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 95: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 96: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 97: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 98: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 99: CmpNe { + dest: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 101: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 102: BranchIfZero { + target: 107, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfZero { + target: 105, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 104: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfNonZero { + target: 107, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 106: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 107: BranchIfSmallNeImmediate { + target: 109, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 108: Copy { + dest: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 109: Copy { + dest: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 120: BranchIfSmallZero { + target: 125, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallNonZero { + target: 124, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 123: Branch { + target: 125, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 125: BranchIfSmallZero { + target: 126, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 134, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 128: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 129: Copy { + dest: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2a) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 130: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 131: BranchIfSmallZero { + target: 134, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 132: BranchIfZero { + target: 134, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 133: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2a) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x28, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 135: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 136: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 137: Return, + ], + .. + }, + pc: 137, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x2a, + [0x1]: 0x28, + [0x2]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 85, + 1, + 85, + 42, + 83, + 0, + 83, + 41, + 2, + 2, + 1, + 0, + 41, + 1, + 1, + 0, + 42, + 1, + 42, + 1, + 1, + 2, + 0, + 2, + 2, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 42, + 0, + 1, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 1, + 2, + 0, + 0, + 0, + 2, + 2, + 1, + 3, + 3, + 3, + 3, + 1, + 4, + 2, + 2, + 7, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2a, + last_state: 0x2a, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_3_false_true.vcd new file mode 100644 index 0000000..622613c --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_false_true.vcd @@ -0,0 +1,2002 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 73, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(72), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(65), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(68), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 14: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 15: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 16: Add { + dest: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Add { + dest: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 19: CastToUInt { + dest: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 20: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 21: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 22: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 23: Copy { + dest: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 24: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 25: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 26: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 27: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 28: Copy { + dest: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 29: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 30: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 31: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 33: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 35: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 36: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 37: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 38: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 40: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 41: BranchIfZero { + target: 46, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 42: BranchIfZero { + target: 44, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 43: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(66), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 44: BranchIfNonZero { + target: 46, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 45: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 46: BranchIfNonZero { + target: 51, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 47: BranchIfZero { + target: 49, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 48: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 49: BranchIfNonZero { + target: 51, + value: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 50: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(72), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 51: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 53: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 56: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 58: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 59: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 60: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 61: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 62: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 63: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 64: BranchIfSmallZero { + target: 67, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 65: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 66: Branch { + target: 68, + }, + 67: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 68: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 69: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 70: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 71: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 72: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 73: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 74: BranchIfZero { + target: 76, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 75: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 76: BranchIfNonZero { + target: 78, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 77: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 78: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 79: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 80: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 81: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 82: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 83: BranchIfSmallNeImmediate { + target: 85, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 84: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 85: BranchIfSmallNeImmediate { + target: 87, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 86: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 87: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 88: BranchIfZero { + target: 93, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 89: BranchIfZero { + target: 91, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 90: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 91: BranchIfNonZero { + target: 93, + value: StatePartIndex(62), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 92: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 93: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 94: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 95: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 96: BranchIfSmallNeImmediate { + target: 98, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 97: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 98: BranchIfSmallNeImmediate { + target: 100, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 99: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 100: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 101: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 102: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 103: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 104: BranchIfZero { + target: 106, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 105: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 106: BranchIfZero { + target: 111, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 107: BranchIfZero { + target: 109, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 108: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 109: BranchIfNonZero { + target: 111, + value: StatePartIndex(57), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 110: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 111: BranchIfSmallNeImmediate { + target: 113, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 112: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 113: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 114: BranchIfSmallZero { + target: 119, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: BranchIfSmallNonZero { + target: 118, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 117: Branch { + target: 119, + }, + 118: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 119: BranchIfSmallZero { + target: 124, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: BranchIfSmallNonZero { + target: 123, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 122: Branch { + target: 124, + }, + 123: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 124: BranchIfSmallZero { + target: 129, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: BranchIfSmallNonZero { + target: 128, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 127: Branch { + target: 129, + }, + 128: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 129: BranchIfSmallZero { + target: 130, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfSmallZero { + target: 138, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 131: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 132: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 133: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 134: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 135: BranchIfSmallZero { + target: 138, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 136: BranchIfZero { + target: 138, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 137: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 138: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 139: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 140: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 141: Return, + ], + .. + }, + pc: 141, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x2a, + [0x1]: 0x2b, + [0x2]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 0, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 0, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 2, + 1, + 0, + 41, + 2, + 0, + 0, + 43, + 1, + 43, + 1, + 2, + 2, + 0, + 2, + 2, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 43, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 0, + 0, + 2, + 1, + 0, + 0, + 3, + 3, + 1, + 3, + 3, + 3, + 3, + 0, + 5, + 3, + 3, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_3_true_false.vcd new file mode 100644 index 0000000..53d6937 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_true_false.vcd @@ -0,0 +1,1949 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 71, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<65>, + }, + SlotDebugData { + name: "", + ty: UInt<66>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 2: CmpLt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + 3: Const { + dest: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 4: CastToUInt { + dest: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 2, + }, + 5: Add { + dest: StatePartIndex(66), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(63), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 6: SubU { + dest: StatePartIndex(67), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + lhs: StatePartIndex(66), // (0x5) SlotDebugData { name: "", ty: UInt<65> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 66, + }, + 7: CastToUInt { + dest: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x3) SlotDebugData { name: "", ty: UInt<66> }, + dest_width: 2, + }, + 8: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 9: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 10: Const { + dest: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x2, + }, + 11: CmpEq { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: CmpEq { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x2) SlotDebugData { name: "", ty: UInt<64> }, + }, + 13: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 14: Add { + dest: StatePartIndex(58), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 15: CastToUInt { + dest: StatePartIndex(59), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 16: Add { + dest: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 17: CastToUInt { + dest: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 18: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 19: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 20: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 21: Copy { + dest: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 22: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 23: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 24: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 25: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 26: Copy { + dest: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 27: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 28: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 29: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 30: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 31: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 32: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 33: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 34: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 35: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 36: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 37: BranchIfZero { + target: 39, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 38: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 39: BranchIfZero { + target: 44, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 40: BranchIfZero { + target: 42, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 41: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(64), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:168:9 + 42: BranchIfNonZero { + target: 44, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 43: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:166:5 + 44: BranchIfNonZero { + target: 49, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:186:13 + 45: BranchIfZero { + target: 47, + value: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:187:17 + 46: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:186:13 + 47: BranchIfNonZero { + target: 49, + value: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:189:17 + 48: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<2> }, + src: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 49: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 51: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 53: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 54: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 55: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 56: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 57: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 58: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 59: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 60: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 61: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 62: BranchIfSmallZero { + target: 65, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 63: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(6), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 64: Branch { + target: 66, + }, + 65: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 66: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 67: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 68: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 69: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 70: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 71: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 73: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 74: BranchIfNonZero { + target: 76, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 75: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 76: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 77: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 78: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 79: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 80: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 83: BranchIfSmallNeImmediate { + target: 85, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 84: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 85: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 86: BranchIfZero { + target: 91, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfZero { + target: 89, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 88: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 89: BranchIfNonZero { + target: 91, + value: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 90: Copy { + dest: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 91: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 92: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 93: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 95: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 96: BranchIfSmallNeImmediate { + target: 98, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 97: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 98: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 99: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 100: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 101: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 102: BranchIfZero { + target: 104, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 103: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 104: BranchIfZero { + target: 109, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfZero { + target: 107, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 106: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 107: BranchIfNonZero { + target: 109, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 108: Copy { + dest: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 109: BranchIfSmallNeImmediate { + target: 111, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 110: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 111: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 112: BranchIfSmallZero { + target: 117, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: BranchIfSmallNonZero { + target: 116, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 115: Branch { + target: 117, + }, + 116: Copy { + dest: StatePartIndex(22), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 117: BranchIfSmallZero { + target: 122, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: BranchIfSmallNonZero { + target: 121, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 120: Branch { + target: 122, + }, + 121: Copy { + dest: StatePartIndex(25), // (0x2) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 122: BranchIfSmallZero { + target: 127, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: BranchIfSmallNonZero { + target: 126, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 125: Branch { + target: 127, + }, + 126: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 127: BranchIfSmallZero { + target: 128, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfSmallZero { + target: 136, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: CopySmall { + dest: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x2 2) SlotDebugData { name: "", ty: UInt<2> }, + }, + 130: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 131: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 132: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 133: BranchIfSmallZero { + target: 136, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 134: BranchIfZero { + target: 136, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 135: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 3>, + // data: [ + // // len = 0x3 + // [0x0]: 0x2a, + // [0x1]: 0x2b, + // [0x2]: 0x29, + // ], + // }) (), + addr: StatePartIndex(12), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 136: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 137: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 138: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 139: Return, + ], + .. + }, + pc: 139, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 3>, + data: [ + // len = 0x3 + [0x0]: 0x2a, + [0x1]: 0x2b, + [0x2]: 0x29, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 2, + 1, + 0, + 0, + 0, + 2, + 1, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 0, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 2, + 1, + 0, + 41, + 2, + 0, + 0, + 43, + 1, + 43, + 1, + 2, + 2, + 0, + 2, + 2, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 43, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 2, + 1, + 0, + 0, + 3, + 3, + 1, + 3, + 3, + 3, + 3, + 0, + 5, + 3, + 3, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<2>, + flow: Sink, + }, + ty: UInt<2>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x2, + last_state: 0x2, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 3, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 3>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_3_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_3_true_true.vcd new file mode 100644 index 0000000..1c178a6 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_3_true_true.vcd @@ -0,0 +1,1935 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 2 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(70), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(68), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Add { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(71), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(55), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x28, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 3, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 1, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 1, + 1, + 0, + 41, + 0, + 1, + 0, + 43, + 1, + 43, + 1, + 0, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 43, + 0, + 1, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 0, + 1, + 3, + 0, + 0, + 0, + 1, + 1, + 0, + 2, + 2, + 4, + 4, + 0, + 3, + 7, + 3, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_false_false.vcd b/crates/fayalite/tests/sim/expected/queue_4_false_false.vcd new file mode 100644 index 0000000..5373a84 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_false_false.vcd @@ -0,0 +1,2025 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x7) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(68), // (0x3) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(66), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x1) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 15: Add { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 36: BranchIfZero { + target: 41, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 37: BranchIfZero { + target: 39, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 38: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfNonZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 40: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(34), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 42: Copy { + dest: StatePartIndex(10), // (0x3) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(69), // (0x3) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 43: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 44: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 45: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 46: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 47: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 48: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 49: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 50: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 51: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 52: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 53: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 54: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 55: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 56: BranchIfSmallZero { + target: 59, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 57: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 58: Branch { + target: 60, + }, + 59: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 60: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 61: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 62: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 63: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 64: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 65: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 66: BranchIfZero { + target: 68, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 67: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfNonZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 70: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 71: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 72: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 73: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 74: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 75: BranchIfSmallNeImmediate { + target: 77, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 76: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 79: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 80: BranchIfZero { + target: 85, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 81: BranchIfZero { + target: 83, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 82: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfNonZero { + target: 85, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 85: Copy { + dest: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 86: SliceInt { + dest: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x57) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 87: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x57) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 88: BranchIfSmallNeImmediate { + target: 90, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 89: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 91: Copy { + dest: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 92: Copy { + dest: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 93: Copy { + dest: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 94: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 95: CmpNe { + dest: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 96: BranchIfZero { + target: 98, + value: StatePartIndex(53), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 97: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 98: BranchIfZero { + target: 103, + value: StatePartIndex(30), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 99: BranchIfZero { + target: 101, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 100: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfNonZero { + target: 103, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x1) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 103: BranchIfSmallNeImmediate { + target: 105, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 104: Copy { + dest: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 105: Copy { + dest: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 106: BranchIfSmallZero { + target: 111, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 107: BranchIfSmallNonZero { + target: 110, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 108: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 109: Branch { + target: 111, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 111: BranchIfSmallZero { + target: 116, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: BranchIfSmallNonZero { + target: 115, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 113: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 114: Branch { + target: 116, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 116: BranchIfSmallZero { + target: 121, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: BranchIfSmallNonZero { + target: 120, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 118: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 119: Branch { + target: 121, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 121: BranchIfSmallZero { + target: 122, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: BranchIfSmallZero { + target: 130, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 123: CopySmall { + dest: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + }, + 124: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 125: Copy { + dest: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2b) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 126: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 127: BranchIfSmallZero { + target: 130, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 128: BranchIfZero { + target: 130, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 129: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2b) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x28, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x3 3) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 130: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 131: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 132: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 133: Return, + ], + .. + }, + pc: 133, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x28, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 1, + 0, + 3, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 87, + 1, + 87, + 43, + 83, + 0, + 83, + 41, + 3, + 1, + 1, + 0, + 41, + 0, + 1, + 0, + 43, + 1, + 43, + 1, + 0, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 43, + 0, + 1, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 1, + 3, + 0, + 0, + 0, + 1, + 1, + 0, + 2, + 2, + 4, + 4, + 0, + 3, + 7, + 3, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + state: 0x3, + last_state: 0x3, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2b, + last_state: 0x2b, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<2>, + }, + state: 0x3, + last_state: 0x3, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_false_true.vcd b/crates/fayalite/tests/sim/expected/queue_4_false_true.vcd new file mode 100644 index 0000000..bed1241 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_false_true.vcd @@ -0,0 +1,2021 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 72, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(70), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(65), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(58), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(56), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + value: 0x0, + }, + 13: Copy { + dest: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: UInt<9> }, + }, + 14: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 15: Add { + dest: StatePartIndex(60), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(60), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Add { + dest: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 18: CastToUInt { + dest: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(63), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 19: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 20: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 21: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 22: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 23: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 24: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 25: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 26: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 27: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 28: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 29: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 30: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 32: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 33: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 34: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 35: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 36: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 38: BranchIfZero { + target: 40, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 39: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 40: BranchIfZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 42: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(66), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 44: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 45: BranchIfNonZero { + target: 47, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 46: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(71), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 47: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 48: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 49: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 50: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 51: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 52: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 53: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 54: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 55: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 56: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 57: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 58: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 59: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 60: BranchIfSmallZero { + target: 63, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 61: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 62: Branch { + target: 64, + }, + 63: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 64: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 65: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 66: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 67: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 68: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 69: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 72: BranchIfNonZero { + target: 74, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:136:13 + 73: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(54), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 74: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 75: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 76: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 77: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 78: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 81: BranchIfSmallNeImmediate { + target: 83, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 82: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 83: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 84: BranchIfZero { + target: 89, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfZero { + target: 87, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 87: BranchIfNonZero { + target: 89, + value: StatePartIndex(62), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 88: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(64), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 89: Copy { + dest: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 90: SliceInt { + dest: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 91: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 94: BranchIfSmallNeImmediate { + target: 96, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 95: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 96: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 97: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 98: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 99: CmpNe { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 100: BranchIfZero { + target: 102, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 101: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 102: BranchIfZero { + target: 107, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfZero { + target: 105, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 105: BranchIfNonZero { + target: 107, + value: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 106: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 107: BranchIfSmallNeImmediate { + target: 109, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 108: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 109: Copy { + dest: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 110: BranchIfSmallZero { + target: 115, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 111: BranchIfSmallNonZero { + target: 114, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 113: Branch { + target: 115, + }, + 114: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 115: BranchIfSmallZero { + target: 120, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 116: BranchIfSmallNonZero { + target: 119, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 118: Branch { + target: 120, + }, + 119: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 120: BranchIfSmallZero { + target: 125, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 121: BranchIfSmallNonZero { + target: 124, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 123: Branch { + target: 125, + }, + 124: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 125: BranchIfSmallZero { + target: 126, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 126: BranchIfSmallZero { + target: 134, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 128: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 129: Copy { + dest: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 130: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 131: BranchIfSmallZero { + target: 134, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 132: BranchIfZero { + target: 134, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 133: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 134: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 135: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 136: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 137: Return, + ], + .. + }, + pc: 137, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x2c, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 89, + 0, + 89, + 44, + 83, + 0, + 83, + 41, + 4, + 1, + 1, + 0, + 41, + 1, + 0, + 0, + 44, + 1, + 44, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 44, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 0, + 0, + 3, + 0, + 0, + 0, + 2, + 2, + 0, + 2, + 2, + 4, + 4, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + state: 0x4, + last_state: 0x4, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(68), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_true_false.vcd b/crates/fayalite/tests/sim/expected/queue_4_true_false.vcd new file mode 100644 index 0000000..842a353 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_true_false.vcd @@ -0,0 +1,1993 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ { + len: 18, + debug_data: [ + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome, + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 70, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.data", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out.ready", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::r0.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.data", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", + ty: UInt<2>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::inp_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::out_firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::firing", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::indexes_equal", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::empty", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::full", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: ".0", + ty: UInt<1>, + }, + SlotDebugData { + name: ".1", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<1>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: UInt<9>, + }, + SlotDebugData { + name: "", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<64>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "InstantiatedModule(queue: queue).queue::count_lower", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + SlotDebugData { + name: "", + ty: UInt<2>, + }, + SlotDebugData { + name: "", + ty: UInt<3>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x00, + [0x1]: 0x00, + [0x2]: 0x00, + [0x3]: 0x00, + ], + }, + ], + .. + }, + }, + insns: [ + // at: ready_valid.rs:64:1 + 0: SubU { + dest: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + dest_width: 3, + }, + 1: CastToUInt { + dest: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(67), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + // at: ready_valid.rs:178:13 + 2: Copy { + dest: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + src: StatePartIndex(68), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 3: CastToUInt { + dest: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(66), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count_lower", ty: UInt<2> }, + dest_width: 3, + }, + 4: Const { + dest: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x4, + }, + 5: CastToUInt { + dest: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(63), // (0x4) SlotDebugData { name: "", ty: UInt<64> }, + dest_width: 3, + }, + 6: Const { + dest: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + value: 0x0, + }, + 7: CastToUInt { + dest: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 2, + }, + 8: CastToUInt { + dest: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + src: StatePartIndex(56), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + dest_width: 3, + }, + 9: Const { + dest: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + value: 0x3, + }, + 10: CmpEq { + dest: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 11: CmpEq { + dest: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(54), // (0x3) SlotDebugData { name: "", ty: UInt<64> }, + }, + 12: Const { + dest: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + value: 0x1, + }, + 13: Add { + dest: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 14: CastToUInt { + dest: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(58), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 15: Add { + dest: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + lhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 16: CastToUInt { + dest: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(61), // (0x2) SlotDebugData { name: "", ty: UInt<3> }, + dest_width: 2, + }, + 17: Const { + dest: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:118:30 + 18: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(43), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:117:5 + 19: Copy { + dest: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:115:5 + 20: Copy { + dest: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:114:5 + 21: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + // at: ready_valid.rs:64:1 + 22: Const { + dest: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + value: 0x1, + }, + // at: ready_valid.rs:113:5 + 23: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:119:5 + 24: Copy { + dest: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:112:5 + 25: Copy { + dest: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 26: NotU { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + width: 1, + }, + 27: CmpEq { + dest: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + rhs: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:104:5 + 28: Copy { + dest: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + src: StatePartIndex(35), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 29: And { + dest: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(37), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:107:5 + 30: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + src: StatePartIndex(38), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 31: NotU { + dest: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::empty", ty: Bool }, + width: 1, + }, + 32: And { + dest: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + rhs: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:110:5 + 33: Copy { + dest: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + src: StatePartIndex(40), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 34: NotU { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(39), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::full", ty: Bool }, + width: 1, + }, + // at: ready_valid.rs:121:5 + 35: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(44), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:124:9 + 36: BranchIfZero { + target: 38, + value: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:125:13 + 37: Copy { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + src: StatePartIndex(41), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:166:5 + 38: BranchIfZero { + target: 43, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:168:9 + 39: BranchIfZero { + target: 41, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:169:13 + 40: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(64), // (0x4) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:168:9 + 41: BranchIfNonZero { + target: 43, + value: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:171:13 + 42: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(65), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:166:5 + 43: BranchIfNonZero { + target: 45, + value: StatePartIndex(34), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::indexes_equal", ty: Bool }, + }, + // at: ready_valid.rs:182:13 + 44: Copy { + dest: StatePartIndex(10), // (0x4) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::count", ty: UInt<3> }, + src: StatePartIndex(69), // (0x0) SlotDebugData { name: "", ty: UInt<3> }, + }, + // at: ready_valid.rs:88:26 + 45: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 46: Const { + dest: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: ready_valid.rs:86:25 + 47: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:84:31 + 48: IsNonZeroDestIsSmall { + dest: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.rst", ty: SyncReset }, + }, + 49: IsNonZeroDestIsSmall { + dest: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::cd.clk", ty: Clock }, + }, + 50: AndSmall { + dest: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 52: Const { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + value: 0x0, + }, + // at: ready_valid.rs:91:19 + 53: CastBigToArrayIndex { + dest: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(15), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.addr", ty: UInt<2> }, + }, + 54: IsNonZeroDestIsSmall { + dest: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(17), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.clk", ty: Clock }, + }, + 55: AndSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 56: CastBigToArrayIndex { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.addr", ty: UInt<2> }, + }, + 57: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.en", ty: Bool }, + }, + 58: BranchIfSmallZero { + target: 61, + value: StatePartIndex(5), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 59: MemoryReadUInt { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 60: Branch { + target: 62, + }, + 61: Const { + dest: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + value: 0x0, + }, + // at: ready_valid.rs:64:1 + 62: Copy { + dest: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + src: StatePartIndex(48), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, + }, + 63: Copy { + dest: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + src: StatePartIndex(14), // (0x29) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.data", ty: UInt<8> }, + }, + 64: Shl { + dest: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(47), // (0x29) SlotDebugData { name: ".1", ty: UInt<8> }, + rhs: 1, + }, + 65: Or { + dest: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + lhs: StatePartIndex(46), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> }, + rhs: StatePartIndex(49), // (0x52) SlotDebugData { name: "", ty: UInt<9> }, + }, + 66: CastToUInt { + dest: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(50), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + dest_width: 9, + }, + 67: Copy { + dest: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(51), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + }, + // at: ready_valid.rs:130:5 + 68: BranchIfZero { + target: 70, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:131:9 + 69: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(52), // (0x53) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:130:5 + 70: BranchIfNonZero { + target: 72, + value: StatePartIndex(45), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:134:13 + 71: Copy { + dest: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + src: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + // at: ready_valid.rs:91:19 + 72: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::r0.clk", ty: Clock }, + }, + 73: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 74: Copy { + dest: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 75: SliceInt { + dest: StatePartIndex(9), // (0x29) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(8), // (0x53) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:79:32 + 76: AndBigWithSmallImmediate { + dest: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(6), // (0x53) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 77: BranchIfSmallNeImmediate { + target: 79, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 78: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 79: BranchIfSmallNeImmediate { + target: 81, + lhs: StatePartIndex(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 80: Copy { + dest: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(7), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out.ready", ty: Bool }, + }, + // at: ready_valid.rs:101:5 + 81: Copy { + dest: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + src: StatePartIndex(33), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:156:5 + 82: BranchIfZero { + target: 87, + value: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:158:9 + 83: BranchIfZero { + target: 85, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:159:13 + 84: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:158:9 + 85: BranchIfNonZero { + target: 87, + value: StatePartIndex(60), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:161:13 + 86: Copy { + dest: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(62), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:64:1 + 87: Copy { + dest: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + src: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + }, + 88: SliceInt { + dest: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(4), // (0x59) SlotDebugData { name: "", ty: UInt<9> }, + start: 1, + len: 8, + }, + // at: ready_valid.rs:77:32 + 89: AndBigWithSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + lhs: StatePartIndex(2), // (0x59) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.data", ty: Enum {HdlNone, HdlSome(UInt<8>)} }, + rhs: 0x1, + }, + // at: ready_valid.rs:19:9 + 90: BranchIfSmallNeImmediate { + target: 92, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x0, + }, + // at: ready_valid.rs:20:24 + 91: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:19:9 + 92: BranchIfSmallNeImmediate { + target: 94, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + // at: ready_valid.rs:21:27 + 93: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp.ready", ty: Bool }, + }, + // at: ready_valid.rs:98:5 + 94: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + src: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::firing", ty: Bool }, + }, + // at: ready_valid.rs:116:5 + 95: Copy { + dest: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 96: IsNonZeroDestIsSmall { + dest: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(16), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.en", ty: Bool }, + }, + // at: ready_valid.rs:64:1 + 97: CmpNe { + dest: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + rhs: StatePartIndex(32), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_firing", ty: Bool }, + }, + // at: ready_valid.rs:141:5 + 98: BranchIfZero { + target: 100, + value: StatePartIndex(53), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:142:9 + 99: Copy { + dest: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + src: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:146:5 + 100: BranchIfZero { + target: 105, + value: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_firing", ty: Bool }, + }, + // at: ready_valid.rs:148:9 + 101: BranchIfZero { + target: 103, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:149:13 + 102: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(57), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:148:9 + 103: BranchIfNonZero { + target: 105, + value: StatePartIndex(55), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:151:13 + 104: Copy { + dest: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + src: StatePartIndex(59), // (0x2) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:118:30 + 105: BranchIfSmallNeImmediate { + target: 107, + lhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} }, + rhs: 0x1, + }, + 106: Copy { + dest: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + src: StatePartIndex(5), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + }, + // at: ready_valid.rs:118:5 + 107: Copy { + dest: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + src: StatePartIndex(42), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::unwrap_or_else_out", ty: UInt<8> }, + }, + // at: ready_valid.rs:84:31 + 108: BranchIfSmallZero { + target: 113, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 109: BranchIfSmallNonZero { + target: 112, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 110: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(23), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg$next", ty: UInt<2> }, + }, + 111: Branch { + target: 113, + }, + 112: Copy { + dest: StatePartIndex(22), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::inp_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:86:25 + 113: BranchIfSmallZero { + target: 118, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 114: BranchIfSmallNonZero { + target: 117, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 115: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(26), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg$next", ty: UInt<2> }, + }, + 116: Branch { + target: 118, + }, + 117: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::out_index_reg", ty: UInt<2> }, + src: StatePartIndex(24), // (0x0) SlotDebugData { name: "", ty: UInt<2> }, + }, + // at: ready_valid.rs:88:26 + 118: BranchIfSmallZero { + target: 123, + value: StatePartIndex(15), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 119: BranchIfSmallNonZero { + target: 122, + value: StatePartIndex(17), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 120: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(28), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg$next", ty: Bool }, + }, + 121: Branch { + target: 123, + }, + 122: Copy { + dest: StatePartIndex(27), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::maybe_full_reg", ty: Bool }, + src: StatePartIndex(29), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: ready_valid.rs:91:19 + 123: BranchIfSmallZero { + target: 124, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 124: BranchIfSmallZero { + target: 132, + value: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 125: CopySmall { + dest: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + src: StatePartIndex(11), // (0x1 1) SlotDebugData { name: "", ty: UInt<2> }, + }, + 126: CopySmall { + dest: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(10), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 127: Copy { + dest: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + src: StatePartIndex(18), // (0x2c) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.data", ty: UInt<8> }, + }, + 128: Copy { + dest: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(19), // (0x1) SlotDebugData { name: "InstantiatedModule(queue: queue).queue::mem::w1.mask", ty: Bool }, + }, + 129: BranchIfSmallZero { + target: 132, + value: StatePartIndex(13), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 130: BranchIfZero { + target: 132, + value: StatePartIndex(21), // (0x1) SlotDebugData { name: "", ty: Bool }, + }, + 131: MemoryWriteUInt { + value: StatePartIndex(20), // (0x2c) SlotDebugData { name: "", ty: UInt<8> }, + memory: StatePartIndex(0), // (MemoryData { + // array_type: Array, 4>, + // data: [ + // // len = 0x4 + // [0x0]: 0x2c, + // [0x1]: 0x29, + // [0x2]: 0x2a, + // [0x3]: 0x2b, + // ], + // }) (), + addr: StatePartIndex(12), // (0x0 0) SlotDebugData { name: "", ty: UInt<2> }, + stride: 8, + start: 0, + width: 8, + }, + 132: XorSmallImmediate { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 133: XorSmallImmediate { + dest: StatePartIndex(7), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(9), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:84:31 + 134: XorSmallImmediate { + dest: StatePartIndex(14), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(16), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: ready_valid.rs:64:1 + 135: Return, + ], + .. + }, + pc: 135, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, 4>, + data: [ + // len = 0x4 + [0x0]: 0x2c, + [0x1]: 0x29, + [0x2]: 0x2a, + [0x3]: 0x2b, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 1, + 1, + 0, + 0, + 1, + 1, + 1, + 0, + 0, + 0, + 1, + 0, + 1, + 1, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 89, + 0, + 89, + 44, + 83, + 0, + 83, + 41, + 4, + 1, + 1, + 0, + 41, + 1, + 0, + 0, + 44, + 1, + 44, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 0, + 0, + 0, + 0, + 0, + 1, + 1, + 0, + 0, + 0, + 1, + 1, + 1, + 44, + 0, + 0, + 1, + 1, + 41, + 1, + 82, + 83, + 83, + 83, + 0, + 3, + 0, + 0, + 0, + 2, + 2, + 0, + 2, + 2, + 4, + 4, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.clk, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.cd.rst, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.count, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.inp.ready, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.data, + Instance { + name: ::queue, + instantiated: Module { + name: queue, + .. + }, + }.out.ready, + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "queue", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "inp", + child: TraceBundle { + name: "inp", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(2), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(3), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Source, + }, + TraceBool { + location: TraceScalarId(4), + name: "ready", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceBundle { + name: "out", + fields: [ + TraceEnumWithFields { + name: "data", + discriminant: TraceEnumDiscriminant { + location: TraceScalarId(5), + name: "$tag", + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + non_empty_fields: [ + TraceUInt { + location: TraceScalarId(6), + name: "HdlSome", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(7), + name: "ready", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + data: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + #[hdl(flip)] /* offset = 9 */ + ready: Bool, + }, + flow: Sink, + }, + TraceModuleIO { + name: "count", + child: TraceUInt { + location: TraceScalarId(8), + name: "count", + ty: UInt<3>, + flow: Sink, + }, + ty: UInt<3>, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + TraceReg { + name: "inp_index_reg", + child: TraceUInt { + location: TraceScalarId(18), + name: "inp_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "out_index_reg", + child: TraceUInt { + location: TraceScalarId(19), + name: "out_index_reg", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + TraceReg { + name: "maybe_full_reg", + child: TraceBool { + location: TraceScalarId(20), + name: "maybe_full_reg", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "inp_firing", + child: TraceBool { + location: TraceScalarId(21), + name: "inp_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(22), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "out_firing", + child: TraceBool { + location: TraceScalarId(23), + name: "out_firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "firing", + child: TraceBool { + location: TraceScalarId(24), + name: "firing", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "indexes_equal", + child: TraceBool { + location: TraceScalarId(25), + name: "indexes_equal", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "empty", + child: TraceBool { + location: TraceScalarId(26), + name: "empty", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "full", + child: TraceBool { + location: TraceScalarId(27), + name: "full", + flow: Duplex, + }, + ty: Bool, + }, + TraceWire { + name: "unwrap_or_else_out", + child: TraceUInt { + location: TraceScalarId(28), + name: "unwrap_or_else_out", + ty: UInt<8>, + flow: Duplex, + }, + ty: UInt<8>, + }, + TraceWire { + name: "count_lower", + child: TraceUInt { + location: TraceScalarId(29), + name: "count_lower", + ty: UInt<2>, + flow: Duplex, + }, + ty: UInt<2>, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: EnumDiscriminant { + index: StatePartIndex(0), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigBool { + index: StatePartIndex(3), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: EnumDiscriminant { + index: StatePartIndex(1), + ty: Enum { + HdlNone, + HdlSome(UInt<8>), + }, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigBool { + index: StatePartIndex(7), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<3>, + }, + state: 0x4, + last_state: 0x4, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigBool { + index: StatePartIndex(12), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigClock { + index: StatePartIndex(13), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(12), + kind: BigUInt { + index: StatePartIndex(14), + ty: UInt<8>, + }, + state: 0x29, + last_state: 0x29, + }, + SimTrace { + id: TraceScalarId(13), + kind: BigUInt { + index: StatePartIndex(15), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(14), + kind: BigBool { + index: StatePartIndex(16), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(15), + kind: BigClock { + index: StatePartIndex(17), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(16), + kind: BigUInt { + index: StatePartIndex(18), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(17), + kind: BigBool { + index: StatePartIndex(19), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(18), + kind: BigUInt { + index: StatePartIndex(22), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(19), + kind: BigUInt { + index: StatePartIndex(25), + ty: UInt<2>, + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(20), + kind: BigBool { + index: StatePartIndex(27), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(21), + kind: BigBool { + index: StatePartIndex(30), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(22), + kind: BigBool { + index: StatePartIndex(31), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(23), + kind: BigBool { + index: StatePartIndex(32), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(24), + kind: BigBool { + index: StatePartIndex(33), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(25), + kind: BigBool { + index: StatePartIndex(34), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(26), + kind: BigBool { + index: StatePartIndex(36), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(27), + kind: BigBool { + index: StatePartIndex(39), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(28), + kind: BigUInt { + index: StatePartIndex(42), + ty: UInt<8>, + }, + state: 0x2c, + last_state: 0x2c, + }, + SimTrace { + id: TraceScalarId(29), + kind: BigUInt { + index: StatePartIndex(66), + ty: UInt<2>, + }, + state: 0x0, + last_state: 0x0, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 8, + element_type: TraceUInt { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 4, + stride: 8, + start: 0, + len: 8, + }, + name: "mem", + ty: UInt<8>, + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(9), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(10), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(11), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(12), + name: "data", + ty: UInt<8>, + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + #[hdl(flip)] /* offset = 4 */ + data: UInt<8>, + }, + }, + TraceMemPort { + name: "w1", + bundle: TraceBundle { + name: "w1", + fields: [ + TraceUInt { + location: TraceScalarId(13), + name: "addr", + ty: UInt<2>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(14), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(15), + name: "clk", + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(16), + name: "data", + ty: UInt<8>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(17), + name: "mask", + flow: Sink, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<2>, + /* offset = 2 */ + en: Bool, + /* offset = 3 */ + clk: Clock, + /* offset = 4 */ + data: UInt<8>, + /* offset = 12 */ + mask: Bool, + }, + }, + ], + array_type: Array, 4>, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(3), + StatePartIndex(8), + StatePartIndex(15), + ], + event_queue: EventQueue(EventQueueData { + instant: 100 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/queue_4_true_true.vcd b/crates/fayalite/tests/sim/expected/queue_4_true_true.vcd new file mode 100644 index 0000000..f4a2232 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/queue_4_true_true.vcd @@ -0,0 +1,1989 @@ +$timescale 1 ps $end +$scope module queue $end +$scope struct cd $end +$var wire 1 11z(a clk $end +$var wire 1 q1t|f rst $end +$upscope $end +$scope struct inp $end +$scope struct data $end +$var string 1 j|a-9 \$tag $end +$var wire 8 pjN&T HdlSome $end +$upscope $end +$var wire 1 *x8M* ready $end +$upscope $end +$scope struct out $end +$scope struct data $end +$var string 1 'Aa8} \$tag $end +$var wire 8 1b%.O HdlSome $end +$upscope $end +$var wire 1 vZD*c ready $end +$upscope $end +$var wire 3 rf7Xh count $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var reg 8 (.Juw mem $end +$upscope $end +$scope struct \[1] $end +$var reg 8 5F$iE mem $end +$upscope $end +$scope struct \[2] $end +$var reg 8 !BEt5 mem $end +$upscope $end +$scope struct \[3] $end +$var reg 8 C7]kZ mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var wire 2 K]Dkr addr $end +$var wire 1 P|=HX en $end +$var wire 1 z+ft% clk $end +$var wire 8 m+9ec data $end +$upscope $end +$scope struct w1 $end +$var wire 2 8Oa@o addr $end +$var wire 1 VaM[2 en $end +$var wire 1 aH[{] clk $end +$var wire 8 8|1uZ data $end +$var wire 1 DYq.y mask $end +$upscope $end +$upscope $end +$var reg 2 Xk?#v inp_index_reg $end +$var reg 2 p19yW out_index_reg $end +$var reg 1 kEQiI maybe_full_reg $end +$var wire 1 *gdL1 inp_firing $end +$var wire 1 ;HWUJ firing $end +$var wire 1 Ph#@^ out_firing $end +$var wire 1 ;HWUJ" firing_2 $end +$var wire 1 i[~ Date: Thu, 26 Mar 2026 18:21:14 -0700 Subject: [PATCH 04/10] change vcd output to have module contents under instance's name, more closely matching how it works in verilog --- crates/fayalite/src/sim/vcd.rs | 159 +++++++--- crates/fayalite/tests/sim/expected/mod1.vcd | 15 +- .../tests/sim/expected/ripple_counter.vcd | 276 +----------------- .../tests/sim/expected/sim_only_connects.vcd | 64 +--- 4 files changed, 120 insertions(+), 394 deletions(-) diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs index d970eb0..ad3e974 100644 --- a/crates/fayalite/src/sim/vcd.rs +++ b/crates/fayalite/src/sim/vcd.rs @@ -26,6 +26,7 @@ use std::{ collections::BTreeMap, fmt::{self, Write as _}, io, mem, + num::NonZeroU64, }; #[derive(Default, Clone)] @@ -186,6 +187,26 @@ impl fmt::Debug for VcdWriterDecls { } } +/// pass in scope to ensure it's not available in child scope +fn try_write_vcd_scope( + writer: &mut W, + scope_type: &str, + scope_name: Interned, + scope: Option<&mut Scope>, + f: impl FnOnce(&mut W, Option<&mut Scope>) -> io::Result, +) -> io::Result { + let Some(scope) = scope else { + return f(writer, None); + }; + write_vcd_scope( + writer, + scope_type, + scope_name, + scope, + move |writer, scope| f(writer, Some(scope)), + ) +} + /// pass in scope to ensure it's not available in child scope fn write_vcd_scope( writer: &mut W, @@ -237,6 +258,7 @@ trait_arg! { struct ArgModule<'a> { properties: &'a mut VcdWriterProperties, scope: &'a mut Scope, + instance_name: Option>, } impl<'a> ArgModule<'a> { @@ -244,6 +266,7 @@ impl<'a> ArgModule<'a> { ArgModule { properties: self.properties, scope: self.scope, + instance_name: self.instance_name, } } } @@ -267,7 +290,7 @@ struct ArgInType<'a> { sink_var_type: &'static str, duplex_var_type: &'static str, properties: &'a mut VcdWriterProperties, - scope: &'a mut Scope, + scope: Option<&'a mut Scope>, } impl<'a> ArgInType<'a> { @@ -277,7 +300,7 @@ impl<'a> ArgInType<'a> { sink_var_type: self.sink_var_type, duplex_var_type: self.duplex_var_type, properties: self.properties, - scope: self.scope, + scope: self.scope.as_deref_mut(), } } } @@ -314,7 +337,7 @@ impl WriteTrace for TraceScalar { #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] #[repr(transparent)] -struct VcdId(u64); +struct VcdId(NonZeroU64); impl VcdId { const CHAR_RANGE: std::ops::RangeInclusive = b'!'..=b'~'; @@ -344,11 +367,14 @@ impl VcdId { }; retval = v; } + let Some(retval) = NonZeroU64::new(retval) else { + return None; + }; Some(Self(retval)) } #[must_use] const fn write(self, out: &mut [u8]) -> usize { - let mut id = self.0; + let mut id = self.0.get(); let mut len = 0; loop { let digit = (id % Self::BASE as u64) as u8 + *Self::CHAR_RANGE.start(); @@ -363,7 +389,7 @@ impl VcdId { } len } - const MAX_ID_LEN: usize = Self(u64::MAX).write(&mut []); + const MAX_ID_LEN: usize = Self(NonZeroU64::MAX).write(&mut []); } /// check that VcdId properly round-trips @@ -423,7 +449,7 @@ impl fmt::Display for Escaped { fn write_vcd_var( properties: &mut VcdWriterProperties, - scope: &mut Scope, + scope: Option<&mut Scope>, memory_element_part_body: MemoryElementPartBody, writer: &mut W, var_type: &str, @@ -431,8 +457,6 @@ fn write_vcd_var( location: TraceLocation, name: Interned, ) -> io::Result<()> { - let path_hash = scope.path_hash.clone().joined(name); - let name = scope.new_identifier(name); let id = match location { TraceLocation::Scalar(id) => id.as_usize(), TraceLocation::Memory(TraceMemoryLocation { @@ -464,12 +488,21 @@ fn write_vcd_var( first_id + *element_index } }; - let id = properties - .scalar_id_to_vcd_id_map - .builder_get_or_insert(id, &path_hash); - write!(writer, "$var {var_type} {size} ")?; - write_vcd_id(writer, id)?; - writeln!(writer, " {name} $end") + if let Some(scope) = scope { + let path_hash = scope.path_hash.clone().joined(name); + let name = scope.new_identifier(name); + let id = properties + .scalar_id_to_vcd_id_map + .builder_get_or_insert(id, &path_hash); + write!(writer, "$var {var_type} {size} ")?; + write_vcd_id(writer, id)?; + writeln!(writer, " {name} $end") + } else { + properties + .scalar_id_to_vcd_id_map + .builder_unused_scalar_id(id); + Ok(()) + } } impl WriteTrace for TraceUInt { @@ -712,14 +745,24 @@ impl WriteTrace for TraceScope { impl WriteTrace for TraceModule { fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { - let ArgModule { properties, scope } = arg.module(); + let ArgModule { + properties, + scope, + instance_name, + } = arg.module(); let Self { name, children } = self; - write_vcd_scope(writer, "module", name, scope, |writer, scope| { - for child in children { - child.write_trace(writer, ArgModuleBody { properties, scope })?; - } - Ok(()) - }) + write_vcd_scope( + writer, + "module", + instance_name.unwrap_or(name), + scope, + |writer, scope| { + for child in children { + child.write_trace(writer, ArgModuleBody { properties, scope })?; + } + Ok(()) + }, + ) } } @@ -727,7 +770,7 @@ impl WriteTrace for TraceInstance { fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { let ArgModuleBody { properties, scope } = arg.module_body(); let Self { - name: _, + name, instance_io, module, ty: _, @@ -739,10 +782,17 @@ impl WriteTrace for TraceInstance { sink_var_type: "wire", duplex_var_type: "wire", properties, - scope, + scope: None, }, )?; - module.write_trace(writer, ArgModule { properties, scope }) + module.write_trace( + writer, + ArgModule { + properties, + scope, + instance_name: Some(name), + }, + ) } } @@ -781,7 +831,7 @@ impl WriteTrace for TraceMem { sink_var_type: "reg", duplex_var_type: "reg", properties, - scope, + scope: Some(scope), }, ) }, @@ -813,7 +863,7 @@ impl WriteTrace for TraceMemPort { sink_var_type: "wire", duplex_var_type: "wire", properties, - scope, + scope: Some(scope), }, ) } @@ -834,7 +884,7 @@ impl WriteTrace for TraceWire { sink_var_type: "wire", duplex_var_type: "wire", properties, - scope, + scope: Some(scope), }, ) } @@ -855,7 +905,7 @@ impl WriteTrace for TraceReg { sink_var_type: "reg", duplex_var_type: "reg", properties, - scope, + scope: Some(scope), }, ) } @@ -877,7 +927,7 @@ impl WriteTrace for TraceModuleIO { sink_var_type: "wire", duplex_var_type: "wire", properties, - scope, + scope: Some(scope), }, ) } @@ -898,7 +948,7 @@ impl WriteTrace for TraceBundle { ty: _, flow: _, } = self; - write_vcd_scope(writer, "struct", name, scope, |writer, scope| { + try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| { for field in fields { field.write_trace( writer, @@ -907,7 +957,7 @@ impl WriteTrace for TraceBundle { sink_var_type, duplex_var_type, properties, - scope, + scope: scope.as_deref_mut(), }, )?; } @@ -931,7 +981,7 @@ impl WriteTrace for TraceArray { ty: _, flow: _, } = self; - write_vcd_scope(writer, "struct", name, scope, |writer, scope| { + try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| { for element in elements { element.write_trace( writer, @@ -940,7 +990,7 @@ impl WriteTrace for TraceArray { sink_var_type, duplex_var_type, properties, - scope, + scope: scope.as_deref_mut(), }, )?; } @@ -965,7 +1015,7 @@ impl WriteTrace for TraceEnumWithFields { ty: _, flow: _, } = self; - write_vcd_scope(writer, "struct", name, scope, |writer, scope| { + try_write_vcd_scope(writer, "struct", name, scope, |writer, mut scope| { discriminant.write_trace( writer, ArgInType { @@ -973,7 +1023,7 @@ impl WriteTrace for TraceEnumWithFields { sink_var_type, duplex_var_type, properties, - scope, + scope: scope.as_deref_mut(), }, )?; for field in non_empty_fields { @@ -984,7 +1034,7 @@ impl WriteTrace for TraceEnumWithFields { sink_var_type, duplex_var_type, properties, - scope, + scope: scope.as_deref_mut(), }, )?; } @@ -1026,6 +1076,7 @@ impl TraceWriterDecls for VcdWriterDecls { ArgModule { properties: &mut properties, scope: &mut Scope::new(PathHash::default()), + instance_name: None, }, )?; let ScalarIdToVcdIdMapOrBuilder::Builder(scalar_id_to_vcd_id_map_builder) = @@ -1065,23 +1116,29 @@ struct MemoryProperties { } struct ScalarIdToVcdIdMap { - scalar_id_to_vcd_id_map: Box<[VcdId]>, + scalar_id_to_vcd_id_map: Box<[Option]>, } #[derive(Default)] struct ScalarIdToVcdIdMapBuilder { - scalar_id_to_vcd_id_map: BTreeMap, + scalar_id_to_vcd_id_map: BTreeMap>, lower_half_to_next_upper_half_map: HashMap, } impl ScalarIdToVcdIdMapBuilder { + fn unused_scalar_id(&mut self, scalar_id: usize) { + self.scalar_id_to_vcd_id_map + .entry(scalar_id) + .or_insert(None); + } /// `VcdId`s are based off of `path_hash` (and not `scalar_id`) since the hash doesn't change /// when unrelated variables are added/removed, making the generated VCD more friendly for git diff. fn get_or_insert(&mut self, scalar_id: usize, path_hash: &PathHash) -> VcdId { *self .scalar_id_to_vcd_id_map .entry(scalar_id) - .or_insert_with(|| { + .or_insert(None) + .get_or_insert_with(|| { let hash = u128::from_le_bytes( *path_hash .0 @@ -1094,7 +1151,7 @@ impl ScalarIdToVcdIdMapBuilder { let next_upper_half = self .lower_half_to_next_upper_half_map .entry(lower_half) - .or_insert(0); + .or_insert(if lower_half == 0 { 1 } else { 0 }); let upper_half = *next_upper_half; *next_upper_half += 1; let Some(id) = upper_half @@ -1103,7 +1160,7 @@ impl ScalarIdToVcdIdMapBuilder { else { panic!("too many VcdIds"); }; - VcdId(id) + VcdId(NonZeroU64::new(id).expect("known to not be zero")) }) } fn build(self) -> ScalarIdToVcdIdMap { @@ -1129,7 +1186,7 @@ enum ScalarIdToVcdIdMapOrBuilder { } impl ScalarIdToVcdIdMapOrBuilder { - fn built_scalar_id_to_vcd_id(&self, scalar_id: usize) -> VcdId { + fn built_scalar_id_to_vcd_id(&self, scalar_id: usize) -> Option { let Self::Built(v) = self else { panic!("ScalarIdToVcdIdMap isn't built yet"); }; @@ -1141,6 +1198,12 @@ impl ScalarIdToVcdIdMapOrBuilder { }; v.get_or_insert(scalar_id, path_hash) } + fn builder_unused_scalar_id(&mut self, scalar_id: usize) { + let Self::Builder(v) = self else { + panic!("ScalarIdToVcdIdMap is already built"); + }; + v.unused_scalar_id(scalar_id) + } } struct VcdWriterProperties { @@ -1165,8 +1228,11 @@ impl VcdWriter { fn write_string_value_change( writer: &mut impl io::Write, value: impl fmt::Display, - id: VcdId, + id: Option, ) -> io::Result<()> { + let Some(id) = id else { + return Ok(()); + }; write!(writer, "s{} ", Escaped(value))?; write_vcd_id(writer, id)?; writer.write_all(b"\n") @@ -1175,8 +1241,11 @@ fn write_string_value_change( fn write_bits_value_change( writer: &mut impl io::Write, value: &BitSlice, - id: VcdId, + id: Option, ) -> io::Result<()> { + let Some(id) = id else { + return Ok(()); + }; match value.len() { 0 => writer.write_all(b"s0 ")?, 1 => writer.write_all(if value[0] { b"1" } else { b"0" })?, @@ -1205,7 +1274,7 @@ fn write_enum_discriminant_value_change( writer: &mut impl io::Write, variant_index: usize, ty: Enum, - id: VcdId, + id: Option, ) -> io::Result<()> { write_string_value_change( writer, diff --git a/crates/fayalite/tests/sim/expected/mod1.vcd b/crates/fayalite/tests/sim/expected/mod1.vcd index bd8676f..b12db8f 100644 --- a/crates/fayalite/tests/sim/expected/mod1.vcd +++ b/crates/fayalite/tests/sim/expected/mod1.vcd @@ -6,18 +6,12 @@ $var wire 2 Q2~aG o $end $var wire 2 DXK'| i2 $end $var wire 4 cPuix o2 $end $upscope $end -$scope struct child $end +$scope module child $end $var wire 4 ($5K7 i $end $var wire 2 %6Wv" o $end $var wire 2 +|-AU i2 $end $var wire 4 Hw?%j o2 $end $upscope $end -$scope module mod1_child $end -$var wire 4 4}s%= i $end -$var wire 2 }IY?g o $end -$var wire 2 of42K i2 $end -$var wire 4 D9]&= o2 $end -$upscope $end $upscope $end $enddefinitions $end $dumpvars @@ -25,10 +19,6 @@ b11 avK(^ b11 Q2~aG b10 DXK'| b1110 cPuix -b11 4}s%= -b11 }IY?g -b10 of42K -b1110 D9]&= b11 ($5K7 b11 %6Wv" b10 +|-AU @@ -38,9 +28,6 @@ $end b1010 avK(^ b10 Q2~aG b1111 cPuix -b1010 4}s%= -b10 }IY?g -b1111 D9]&= b1010 ($5K7 b10 %6Wv" b1111 Hw?%j diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.vcd b/crates/fayalite/tests/sim/expected/ripple_counter.vcd index 8071550..b800282 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.vcd +++ b/crates/fayalite/tests/sim/expected/ripple_counter.vcd @@ -11,32 +11,20 @@ $var wire 1 d,)j~ \[4] $end $var wire 1 7?<~c \[5] $end $upscope $end $var reg 1 5Vse~ bit_reg_0 $end -$scope struct bit_reg_1 $end +$scope module bit_reg_1 $end $var wire 1 3GuTz clk $end $var wire 1 UHkx. o $end $upscope $end -$scope module sw_reg $end -$var wire 1 -3~F" clk $end -$var wire 1 `Z15M o $end -$upscope $end $var reg 1 .$$fF bit_reg_2 $end -$scope struct bit_reg_3 $end +$scope module bit_reg_3 $end $var wire 1 .Wa21 clk $end $var wire 1 _`|^x o $end $upscope $end -$scope module sw_reg_2 $end -$var wire 1 -3~F"" clk $end -$var wire 1 `Z15M" o $end -$upscope $end $var reg 1 eTSbN bit_reg_4 $end -$scope struct bit_reg_5 $end +$scope module bit_reg_5 $end $var wire 1 %U['n clk $end $var wire 1 ?Kpc. o $end $upscope $end -$scope module sw_reg_3 $end -$var wire 1 -3~F"# clk $end -$var wire 1 `Z15M# o $end -$upscope $end $upscope $end $enddefinitions $end $dumpvars @@ -49,18 +37,12 @@ b0 f0Cen 0d,)j~ 07?<~c 05Vse~ -0-3~F" -0`Z15M 03GuTz 0UHkx. 0.$$fF -0-3~F"" -0`Z15M" 0.Wa21 0_`|^x 0eTSbN -0-3~F"# -0`Z15M# 0%U['n 0?Kpc. $end @@ -69,27 +51,21 @@ $end b1 f0Cen 1-$(J- 15Vse~ -1-3~F" 13GuTz b111 f0Cen 1 out2 $end $var string 1 8(7-4 out3 $end -$scope struct helper1 $end +$scope module helper1 $end $scope struct cd $end $var wire 1 $Kwp\ clk $end $var wire 1 nmVq' rst $end @@ -16,17 +16,9 @@ $upscope $end $var string 1 qS)@z inp $end $var string 1 ~je// out $end $upscope $end -$scope module sim_only_connects_helper $end -$scope struct cd $end -$var wire 1 %uCn6 clk $end -$var wire 1 Apu`K rst $end -$upscope $end -$var string 1 $U*lA inp $end -$var string 1 !prwC out $end -$upscope $end $var string 1 CyjVm delay1 $end $var reg 1 z~g{\ delay1_empty $end -$scope struct helper2 $end +$scope module helper2 $end $scope struct cd $end $var wire 1 Ph.=# clk $end $var wire 1 !GXK\ rst $end @@ -34,14 +26,6 @@ $upscope $end $var string 1 /YVv: inp $end $var string 1 Kk*{# out $end $upscope $end -$scope module sim_only_connects_helper_2 $end -$scope struct cd $end -$var wire 1 %uCn6" clk $end -$var wire 1 Apu`K" rst $end -$upscope $end -$var string 1 $U*lA" inp $end -$var string 1 !prwC" out $end -$upscope $end $upscope $end $enddefinitions $end $dumpvars @@ -51,20 +35,12 @@ s{\"extra\":\x20\"value\"} g:xf? s{} [OKKg s{} 9pB-> s{} 8(7-4 -0%uCn6 -1Apu`K -s{} $U*lA -s{} !prwC 0$Kwp\ 1nmVq' s{} qS)@z s{} ~je// s{} CyjVm 0z~g{\ -0%uCn6" -1Apu`K" -s{} $U*lA" -s{} !prwC" 0Ph.=# 1!GXK\ s{} /YVv: @@ -73,110 +49,74 @@ $end #1000000 1tq:(w s{\"extra\":\x20\"value\"} [OKKg -1%uCn6 -s{\"extra\":\x20\"value\"} $U*lA 1$Kwp\ s{\"extra\":\x20\"value\"} qS)@z 1z~g{\ -1%uCn6" 1Ph.=# s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 9pB-> -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} !prwC s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} ~je// -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} $U*lA" s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} /YVv: s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8(7-4 -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} !prwC" s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} Kk*{# #2000000 0tq:(w 0FVlgb -0%uCn6 -0Apu`K 0$Kwp\ 0nmVq' -0%uCn6" -0Apu`K" 0Ph.=# 0!GXK\ #3000000 1tq:(w -1%uCn6 1$Kwp\ s{\"extra\":\x20\"value\"} CyjVm 0z~g{\ -1%uCn6" 1Ph.=# #4000000 0tq:(w -0%uCn6 0$Kwp\ -0%uCn6" 0Ph.=# #5000000 1tq:(w -1%uCn6 1$Kwp\ -1%uCn6" 1Ph.=# #6000000 0tq:(w -0%uCn6 0$Kwp\ -0%uCn6" 0Ph.=# #7000000 1tq:(w -1%uCn6 1$Kwp\ -1%uCn6" 1Ph.=# #8000000 0tq:(w -0%uCn6 0$Kwp\ -0%uCn6" 0Ph.=# #9000000 1tq:(w -1%uCn6 1$Kwp\ -1%uCn6" 1Ph.=# #10000000 0tq:(w -0%uCn6 0$Kwp\ -0%uCn6" 0Ph.=# #11000000 1tq:(w -1%uCn6 1$Kwp\ -1%uCn6" 1Ph.=# #12000000 0tq:(w -0%uCn6 0$Kwp\ -0%uCn6" 0Ph.=# #13000000 1tq:(w -1%uCn6 1$Kwp\ -1%uCn6" 1Ph.=# #14000000 0tq:(w -0%uCn6 0$Kwp\ -0%uCn6" 0Ph.=# #15000000 1tq:(w -1%uCn6 1$Kwp\ -1%uCn6" 1Ph.=# #16000000 From 8cff3687f790a128cafd3034ff10774c343986a4 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 14 Feb 2026 18:41:37 -0300 Subject: [PATCH 05/10] Run Rocq tests. --- .forgejo/workflows/test.yml | 1 + rocq-demo/.gitignore | 8 ++++++++ rocq-demo/Makefile | 31 +++++++++++++++++++++++++++++++ rocq-demo/_CoqProject | 5 +++++ scripts/check-copyright.sh | 2 +- 5 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 rocq-demo/.gitignore create mode 100644 rocq-demo/Makefile create mode 100644 rocq-demo/_CoqProject diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml index 30e5419..b7b1924 100644 --- a/.forgejo/workflows/test.yml +++ b/.forgejo/workflows/test.yml @@ -18,6 +18,7 @@ jobs: save-if: ${{ github.ref == 'refs/heads/master' }} - run: rustup override set 1.93.0 - run: rustup component add rust-src + - run: make -C rocq-demo - run: cargo test - run: cargo build --tests --features=unstable-doc - run: cargo test --doc --features=unstable-doc diff --git a/rocq-demo/.gitignore b/rocq-demo/.gitignore new file mode 100644 index 0000000..0182113 --- /dev/null +++ b/rocq-demo/.gitignore @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: LGPL-3.0-or-later +# See Notices.txt for copyright information +.CoqMakefile.d +*.aux +CoqMakefile +CoqMakefile.conf +*.glob +*.vo* diff --git a/rocq-demo/Makefile b/rocq-demo/Makefile new file mode 100644 index 0000000..d0d5c9e --- /dev/null +++ b/rocq-demo/Makefile @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: LGPL-3.0-or-later +# See Notices.txt for copyright information +# +# Example Makefile wrapper as given on the Rocq documentation +# https://rocq-prover.org/doc/V9.1.0/refman/practical-tools/utilities.html#building-a-rocq-project-with-rocq-makefile-details + +# KNOWNTARGETS will not be passed along to CoqMakefile +KNOWNTARGETS := CoqMakefile +# KNOWNFILES will not get implicit targets from the final rule, and so +# depending on them won't invoke the submake +# Warning: These files get declared as PHONY, so any targets depending +# on them always get rebuilt +KNOWNFILES := Makefile _CoqProject + +.DEFAULT_GOAL := invoke-coq-makefile + +CoqMakefile: Makefile _CoqProject + $(COQBIN)rocq makefile -f _CoqProject -o CoqMakefile + +invoke-coq-makefile: CoqMakefile + $(MAKE) --no-print-directory -f CoqMakefile $(filter-out $(KNOWNTARGETS),$(MAKECMDGOALS)) + +.PHONY: invoke-coq-makefile $(KNOWNFILES) + +#################################################################### +## Your targets here ## +#################################################################### + +# This should be the last rule, to handle any targets not declared above +%: invoke-coq-makefile + @true diff --git a/rocq-demo/_CoqProject b/rocq-demo/_CoqProject new file mode 100644 index 0000000..be10420 --- /dev/null +++ b/rocq-demo/_CoqProject @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: LGPL-3.0-or-later +# See Notices.txt for copyright information + +-Q . RocqDemo +. diff --git a/scripts/check-copyright.sh b/scripts/check-copyright.sh index 023cd21..99205bb 100755 --- a/scripts/check-copyright.sh +++ b/scripts/check-copyright.sh @@ -50,7 +50,7 @@ function main() /crates/fayalite/tests/ui/*.stderr|/crates/fayalite/tests/sim/expected/*.vcd|/crates/fayalite/tests/sim/expected/*.txt) # file that can't contain copyright header ;; - /.forgejo/workflows/*.yml|*/.gitignore|*.toml) + /.forgejo/workflows/*.yml|*/.gitignore|*.toml|*/Makefile|*/_CoqProject) check_file "$file" "${POUND_HEADER[@]}" ;; *.md) From 402f457c68547ef5e0400926527bf0e3118af27f Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 30 Apr 2026 19:06:01 -0700 Subject: [PATCH 06/10] sim: Speed up updating traces by tracking which traces are written to --- crates/fayalite/src/sim.rs | 49 ++- crates/fayalite/src/sim/compiler.rs | 1 + crates/fayalite/src/sim/interpreter.rs | 53 +-- crates/fayalite/src/sim/interpreter/parts.rs | 263 ++++++++++++- .../fayalite/tests/sim/expected/array_rw.txt | 59 ++- .../expected/conditional_assignment_last.txt | 6 +- .../tests/sim/expected/connect_const.txt | 3 +- .../sim/expected/connect_const_reset.txt | 8 +- .../tests/sim/expected/counter_async.txt | 24 +- .../tests/sim/expected/counter_sync.txt | 22 +- .../tests/sim/expected/duplicate_names.txt | 6 +- crates/fayalite/tests/sim/expected/enums.txt | 217 ++++++----- .../tests/sim/expected/extern_module.txt | 2 + .../tests/sim/expected/extern_module2.txt | 5 +- .../tests/sim/expected/last_connect.txt | 62 +-- .../tests/sim/expected/many_memories.txt | 368 ++++++++++++------ .../fayalite/tests/sim/expected/memories.txt | 56 ++- .../fayalite/tests/sim/expected/memories2.txt | 78 ++-- .../fayalite/tests/sim/expected/memories3.txt | 184 ++++++--- crates/fayalite/tests/sim/expected/mod1.txt | 22 +- .../tests/sim/expected/phantom_const.txt | 26 +- .../sim/expected/queue_1_false_false.txt | 166 ++++---- .../tests/sim/expected/queue_1_false_true.txt | 162 ++++---- .../tests/sim/expected/queue_1_true_false.txt | 166 ++++---- .../tests/sim/expected/queue_1_true_true.txt | 162 ++++---- .../sim/expected/queue_2_false_false.txt | 170 ++++---- .../tests/sim/expected/queue_2_false_true.txt | 166 ++++---- .../tests/sim/expected/queue_2_true_false.txt | 170 ++++---- .../tests/sim/expected/queue_2_true_true.txt | 166 ++++---- .../sim/expected/queue_3_false_false.txt | 173 ++++---- .../tests/sim/expected/queue_3_false_true.txt | 169 ++++---- .../tests/sim/expected/queue_3_true_false.txt | 173 ++++---- .../tests/sim/expected/queue_3_true_true.txt | 169 ++++---- .../sim/expected/queue_4_false_false.txt | 170 ++++---- .../tests/sim/expected/queue_4_false_true.txt | 166 ++++---- .../tests/sim/expected/queue_4_true_false.txt | 170 ++++---- .../tests/sim/expected/queue_4_true_true.txt | 166 ++++---- .../tests/sim/expected/ripple_counter.txt | 127 +++--- .../tests/sim/expected/shift_register.txt | 26 +- .../tests/sim/expected/sim_fork_join.txt | 14 +- .../sim/expected/sim_fork_join_scope.txt | 14 +- .../tests/sim/expected/sim_only_connects.txt | 50 ++- .../tests/sim/expected/sim_read_past.txt | 122 +++--- .../expected/sim_resettable_counter_async.txt | 7 +- ...settable_counter_async_immediate_reset.txt | 7 +- .../expected/sim_resettable_counter_sync.txt | 5 +- ...esettable_counter_sync_immediate_reset.txt | 5 +- 47 files changed, 2888 insertions(+), 1687 deletions(-) diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 45691ea..b3e4cd6 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -828,6 +828,7 @@ where #[derive(Clone, PartialEq, Eq, Hash, Debug)] pub(crate) struct SimTrace { kind: K, + maybe_changed: bool, state: S, last_state: S, } @@ -848,12 +849,14 @@ impl SimTraceDebug for SimTrace { fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { kind, + maybe_changed, state, last_state, } = self; f.debug_struct("SimTrace") .field("id", &id) .field("kind", kind) + .field("maybe_changed", maybe_changed) .field("state", state) .field("last_state", last_state) .finish() @@ -864,12 +867,14 @@ impl SimTraceDebug for SimTrace fn fmt(&self, id: TraceScalarId, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { kind, + maybe_changed, state, last_state, } = self; f.debug_struct("SimTrace") .field("id", &id) .field("kind", kind) + .field("maybe_changed", maybe_changed) .field("state", state) .field("last_state", last_state) .finish() @@ -2078,10 +2083,12 @@ impl SimulationImpl { traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map( |&SimTrace { kind, + maybe_changed: _, state: _, last_state: _, }| SimTrace { kind, + maybe_changed: true, state: kind.make_state(), last_state: kind.make_state(), }, @@ -2126,13 +2133,16 @@ impl SimulationImpl { id, &SimTrace { kind, + maybe_changed, ref state, ref last_state, }, ) in self.traces.0.iter().enumerate() { - if ONLY_IF_CHANGED && state == last_state { - continue; + if ONLY_IF_CHANGED { + if !(maybe_changed && state != last_state) { + continue; + } } let id = TraceScalarId(id); match kind { @@ -2193,10 +2203,45 @@ impl SimulationImpl { fn read_traces(&mut self) { for &mut SimTrace { kind, + ref mut maybe_changed, ref mut state, ref mut last_state, } in &mut self.traces.0 { + let new_maybe_changed = match kind { + SimTraceKind::BigUInt { index, ty: _ } + | SimTraceKind::BigSInt { index, ty: _ } + | SimTraceKind::BigBool { index } + | SimTraceKind::BigAsyncReset { index } + | SimTraceKind::BigSyncReset { index } + | SimTraceKind::BigClock { index } => self + .state + .big_slots + .state_index_fetch_and_clear_maybe_modified_flag(index), + SimTraceKind::SmallUInt { index, ty: _ } + | SimTraceKind::SmallSInt { index, ty: _ } + | SimTraceKind::SmallBool { index } + | SimTraceKind::SmallAsyncReset { index } + | SimTraceKind::SmallSyncReset { index } + | SimTraceKind::SmallClock { index } + | SimTraceKind::EnumDiscriminant { index, ty: _ } => self + .state + .small_slots + .state_index_fetch_and_clear_maybe_modified_flag(index), + SimTraceKind::SimOnly { index, ty: _ } => self + .state + .sim_only_slots + .state_index_fetch_and_clear_maybe_modified_flag(index), + SimTraceKind::PhantomConst { ty: _ } => IS_INITIAL_STEP, + }; + if !new_maybe_changed && !IS_INITIAL_STEP { + if *maybe_changed { + last_state.clone_from(state); + } + *maybe_changed = false; + continue; + } + *maybe_changed = new_maybe_changed; if !IS_INITIAL_STEP { mem::swap(state, last_state); } diff --git a/crates/fayalite/src/sim/compiler.rs b/crates/fayalite/src/sim/compiler.rs index e85ff0f..dbdbffb 100644 --- a/crates/fayalite/src/sim/compiler.rs +++ b/crates/fayalite/src/sim/compiler.rs @@ -2234,6 +2234,7 @@ impl Compiler { let id = TraceScalarId(self.traces.0.len()); self.traces.0.push(SimTrace { kind, + maybe_changed: true, state: (), last_state: (), }); diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs index 2b121b5..0cf98d0 100644 --- a/crates/fayalite/src/sim/interpreter.rs +++ b/crates/fayalite/src/sim/interpreter.rs @@ -17,12 +17,11 @@ use bitvec::slice::BitSlice; use num_bigint::BigInt; use num_traits::{One, Signed, ToPrimitive, Zero}; use std::{ - borrow::BorrowMut, convert::Infallible, fmt::{self, Write}, hash::Hash, marker::PhantomData, - ops::{ControlFlow, Deref, DerefMut, Index, IndexMut}, + ops::{ControlFlow, Deref, Index, IndexMut}, }; use vec_map::VecMap; @@ -915,6 +914,12 @@ impl StatePart { value: K::borrow_state(&mut self.value), } } + pub(crate) fn state_index_fetch_and_clear_maybe_modified_flag( + &mut self, + part_index: StatePartIndex, + ) -> bool { + K::state_index_fetch_and_clear_maybe_modified_flag(&mut self.value, part_index) + } } #[derive(Clone, PartialEq, Eq, Hash, Debug)] @@ -922,56 +927,38 @@ pub(crate) struct BorrowedStatePart<'a, K: StatePartKind> { pub(crate) value: K::BorrowedState<'a>, } -impl< - 'a, - K: StatePartKind< - BorrowedState<'a>: DerefMut + BorrowMut<[T]>>, - >, - T, -> BorrowedStatePart<'a, K> -{ +impl BorrowedStatePart<'_, K> { pub(crate) fn get_disjoint_mut( &mut self, indexes: [StatePartIndex; N], - ) -> [&mut T; N] { - (*self.value) - .borrow_mut() - .get_disjoint_mut(indexes.map(|v| v.value as usize)) - .expect("indexes are disjoint") + ) -> [&mut K::StateElement; N] { + K::borrowed_state_get_disjoint_mut(&mut self.value, indexes) } } -impl>>, T> Index> - for StatePart -{ - type Output = T; +impl Index> for StatePart { + type Output = K::StateElement; fn index(&self, index: StatePartIndex) -> &Self::Output { - &self.value[index.value as usize] + K::state_index(&self.value, index) } } -impl>>, T> - IndexMut> for StatePart -{ +impl IndexMut> for StatePart { fn index_mut(&mut self, index: StatePartIndex) -> &mut Self::Output { - &mut self.value[index.value as usize] + K::state_index_mut(&mut self.value, index) } } -impl<'a, K: StatePartKind: Deref>>, T> - Index> for BorrowedStatePart<'a, K> -{ - type Output = T; +impl Index> for BorrowedStatePart<'_, K> { + type Output = K::StateElement; fn index(&self, index: StatePartIndex) -> &Self::Output { - &self.value[index.value as usize] + K::borrowed_state_index(&self.value, index) } } -impl<'a, K: StatePartKind: DerefMut>>, T> - IndexMut> for BorrowedStatePart<'a, K> -{ +impl IndexMut> for BorrowedStatePart<'_, K> { fn index_mut(&mut self, index: StatePartIndex) -> &mut Self::Output { - &mut self.value[index.value as usize] + K::borrowed_state_index_mut(&mut self.value, index) } } diff --git a/crates/fayalite/src/sim/interpreter/parts.rs b/crates/fayalite/src/sim/interpreter/parts.rs index 75427c9..d9e4214 100644 --- a/crates/fayalite/src/sim/interpreter/parts.rs +++ b/crates/fayalite/src/sim/interpreter/parts.rs @@ -236,6 +236,7 @@ pub(crate) trait StatePartKind: type LayoutData: Send + Sync + Eq + Hash + fmt::Debug + 'static + Copy; type State: fmt::Debug + 'static + Clone; type BorrowedState<'a>: 'a; + type StateElement; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State; fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a>; fn part_debug_data( @@ -247,6 +248,30 @@ pub(crate) trait StatePartKind: index: StatePartIndex, f: &mut impl fmt::Write, ) -> fmt::Result; + fn state_index<'a>( + state: &'a Self::State, + part_index: StatePartIndex, + ) -> &'a Self::StateElement; + fn state_index_mut<'a>( + state: &'a mut Self::State, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement; + fn state_index_fetch_and_clear_maybe_modified_flag( + state: &mut Self::State, + part_index: StatePartIndex, + ) -> bool; + fn borrowed_state_index<'a, 'b>( + state: &'a Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a Self::StateElement; + fn borrowed_state_index_mut<'a, 'b>( + state: &'a mut Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement; + fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( + state: &'a mut Self::BorrowedState<'b>, + part_indexes: [StatePartIndex; N], + ) -> [&'a mut Self::StateElement; N]; } macro_rules! make_state_part_kinds { @@ -272,6 +297,7 @@ impl StatePartKind for StatePartKindMemories { type LayoutData = MemoryData>; type State = Box<[MemoryData]>; type BorrowedState<'a> = &'a mut [MemoryData]; + type StateElement = MemoryData; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { layout_data .iter() @@ -297,19 +323,88 @@ impl StatePartKind for StatePartKindMemories { ) -> fmt::Result { write!(f, "{:#?}", &state.memories[index]) } + fn state_index<'a>( + state: &'a Self::State, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state[part_index.as_usize()] + } + fn state_index_mut<'a>( + state: &'a mut Self::State, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + &mut state[part_index.as_usize()] + } + fn state_index_fetch_and_clear_maybe_modified_flag( + _state: &mut Self::State, + _part_index: StatePartIndex, + ) -> bool { + true + } + fn borrowed_state_index<'a, 'b>( + state: &'a Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state[part_index.as_usize()] + } + fn borrowed_state_index_mut<'a, 'b>( + state: &'a mut Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + &mut state[part_index.as_usize()] + } + fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( + state: &'a mut Self::BorrowedState<'b>, + part_indexes: [StatePartIndex; N], + ) -> [&'a mut Self::StateElement; N] { + state + .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) + .expect("indexes are disjoint") + } +} + +#[derive(Copy, Clone, PartialEq, Eq, Hash, Default)] +pub(crate) struct StateAndModified { + pub(crate) state: T, + pub(crate) modified: M, +} + +impl, M: Deref, E: fmt::Debug> fmt::Debug + for StateAndModified +{ + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_list() + .entries(self.state.iter().zip(self.modified.iter().copied()).map( + |(state, modified)| { + fmt::from_fn(move |f| { + state.fmt(f)?; + if modified { + f.write_str(" (modified)")?; + } + Ok(()) + }) + }, + )) + .finish() + } } impl StatePartKind for StatePartKindSmallSlots { const NAME: &'static str = "SmallSlots"; type DebugData = SlotDebugData; type LayoutData = (); - type State = Box<[SmallUInt]>; - type BorrowedState<'a> = &'a mut [SmallUInt]; + type State = StateAndModified, Box<[bool]>>; + type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>; + type StateElement = SmallUInt; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { - vec![0; layout_data.len()].into_boxed_slice() + StateAndModified { + state: vec![0; layout_data.len()].into_boxed_slice(), + modified: vec![false; layout_data.len()].into_boxed_slice(), + } } fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> { - state + let StateAndModified { state, modified } = state; + StateAndModified { state, modified } } fn part_debug_data( state_layout: &StateLayout, @@ -330,19 +425,69 @@ impl StatePartKind for StatePartKindSmallSlots { write!(f, "{value:#x} {}", value as SmallSInt)?; Ok(()) } + fn state_index<'a>( + state: &'a Self::State, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn state_index_mut<'a>( + state: &'a mut Self::State, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn state_index_fetch_and_clear_maybe_modified_flag( + state: &mut Self::State, + part_index: StatePartIndex, + ) -> bool { + std::mem::replace(&mut state.modified[part_index.as_usize()], false) + } + fn borrowed_state_index<'a, 'b>( + state: &'a Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn borrowed_state_index_mut<'a, 'b>( + state: &'a mut Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( + state: &'a mut Self::BorrowedState<'b>, + part_indexes: [StatePartIndex; N], + ) -> [&'a mut Self::StateElement; N] { + for part_index in part_indexes { + state.modified[part_index.as_usize()] = true; + } + state + .state + .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) + .expect("indexes are disjoint") + } } impl StatePartKind for StatePartKindBigSlots { const NAME: &'static str = "BigSlots"; type DebugData = SlotDebugData; type LayoutData = (); - type State = Box<[BigInt]>; - type BorrowedState<'a> = &'a mut [BigInt]; + type State = StateAndModified, Box<[bool]>>; + type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>; + type StateElement = BigInt; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { - layout_data.iter().map(|_| BigInt::default()).collect() + let state: Box<[_]> = layout_data.iter().map(|_| BigInt::default()).collect(); + StateAndModified { + modified: vec![false; state.len()].into_boxed_slice(), + state, + } } fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> { - state + let StateAndModified { state, modified } = state; + StateAndModified { state, modified } } fn part_debug_data( state_layout: &StateLayout, @@ -361,19 +506,69 @@ impl StatePartKind for StatePartKindBigSlots { ) -> fmt::Result { write!(f, "{:#x}", state.big_slots[index]) } + fn state_index<'a>( + state: &'a Self::State, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn state_index_mut<'a>( + state: &'a mut Self::State, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn state_index_fetch_and_clear_maybe_modified_flag( + state: &mut Self::State, + part_index: StatePartIndex, + ) -> bool { + std::mem::replace(&mut state.modified[part_index.as_usize()], false) + } + fn borrowed_state_index<'a, 'b>( + state: &'a Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn borrowed_state_index_mut<'a, 'b>( + state: &'a mut Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( + state: &'a mut Self::BorrowedState<'b>, + part_indexes: [StatePartIndex; N], + ) -> [&'a mut Self::StateElement; N] { + for part_index in part_indexes { + state.modified[part_index.as_usize()] = true; + } + state + .state + .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) + .expect("indexes are disjoint") + } } impl StatePartKind for StatePartKindSimOnlySlots { const NAME: &'static str = "SimOnlySlots"; type DebugData = SlotDebugData; type LayoutData = DynSimOnly; - type State = Box<[DynSimOnlyValue]>; - type BorrowedState<'a> = &'a mut [DynSimOnlyValue]; + type State = StateAndModified, Box<[bool]>>; + type BorrowedState<'a> = StateAndModified<&'a mut [Self::StateElement], &'a mut [bool]>; + type StateElement = DynSimOnlyValue; fn new_state(layout_data: &[Self::LayoutData]) -> Self::State { - layout_data.iter().map(|ty| ty.default_value()).collect() + let state: Box<[_]> = layout_data.iter().map(|ty| ty.default_value()).collect(); + StateAndModified { + modified: vec![false; state.len()].into_boxed_slice(), + state, + } } fn borrow_state<'a>(state: &'a mut Self::State) -> Self::BorrowedState<'a> { - state + let StateAndModified { state, modified } = state; + StateAndModified { state, modified } } fn part_debug_data( state_layout: &StateLayout, @@ -392,6 +587,50 @@ impl StatePartKind for StatePartKindSimOnlySlots { ) -> fmt::Result { write!(f, "{:?}", state.sim_only_slots[index]) } + fn state_index<'a>( + state: &'a Self::State, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn state_index_mut<'a>( + state: &'a mut Self::State, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn state_index_fetch_and_clear_maybe_modified_flag( + state: &mut Self::State, + part_index: StatePartIndex, + ) -> bool { + std::mem::replace(&mut state.modified[part_index.as_usize()], false) + } + fn borrowed_state_index<'a, 'b>( + state: &'a Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a Self::StateElement { + &state.state[part_index.as_usize()] + } + fn borrowed_state_index_mut<'a, 'b>( + state: &'a mut Self::BorrowedState<'b>, + part_index: StatePartIndex, + ) -> &'a mut Self::StateElement { + state.modified[part_index.as_usize()] = true; + &mut state.state[part_index.as_usize()] + } + fn borrowed_state_get_disjoint_mut<'a, 'b, const N: usize>( + state: &'a mut Self::BorrowedState<'b>, + part_indexes: [StatePartIndex; N], + ) -> [&'a mut Self::StateElement; N] { + for part_index in part_indexes { + state.modified[part_index.as_usize()] = true; + } + state + .state + .get_disjoint_mut(part_indexes.map(StatePartIndex::as_usize)) + .expect("indexes are disjoint") + } } #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)] diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt index 27b040d..2486eaa 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.txt +++ b/crates/fayalite/tests/sim/expected/array_rw.txt @@ -424,8 +424,8 @@ Simulation { }, small_slots: StatePart { value: [ - 16, - 0, + 16 (modified), + 0 (modified), ], }, big_slots: StatePart { @@ -483,7 +483,7 @@ Simulation { 248, 252, 254, - 255, + 255 (modified), ], }, sim_only_slots: StatePart { @@ -1218,6 +1218,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<8>, }, + maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1227,6 +1228,7 @@ Simulation { index: StatePartIndex(1), ty: UInt<8>, }, + maybe_changed: true, state: 0x7f, last_state: 0x7f, }, @@ -1236,6 +1238,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: true, state: 0x3f, last_state: 0x3f, }, @@ -1245,6 +1248,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1254,6 +1258,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, + maybe_changed: true, state: 0x0f, last_state: 0x0f, }, @@ -1263,6 +1268,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x07, last_state: 0x07, }, @@ -1272,6 +1278,7 @@ Simulation { index: StatePartIndex(6), ty: UInt<8>, }, + maybe_changed: true, state: 0x03, last_state: 0x03, }, @@ -1281,6 +1288,7 @@ Simulation { index: StatePartIndex(7), ty: UInt<8>, }, + maybe_changed: true, state: 0x01, last_state: 0x01, }, @@ -1290,6 +1298,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1299,6 +1308,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x80, last_state: 0x80, }, @@ -1308,6 +1318,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<8>, }, + maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1317,6 +1328,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<8>, }, + maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1326,6 +1338,7 @@ Simulation { index: StatePartIndex(12), ty: UInt<8>, }, + maybe_changed: true, state: 0xf0, last_state: 0xf0, }, @@ -1335,6 +1348,7 @@ Simulation { index: StatePartIndex(13), ty: UInt<8>, }, + maybe_changed: true, state: 0xf8, last_state: 0xf8, }, @@ -1344,6 +1358,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0xfc, last_state: 0xfc, }, @@ -1353,6 +1368,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<8>, }, + maybe_changed: true, state: 0xfe, last_state: 0xfe, }, @@ -1362,6 +1378,7 @@ Simulation { index: StatePartIndex(16), ty: UInt<8>, }, + maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1371,6 +1388,7 @@ Simulation { index: StatePartIndex(17), ty: UInt<8>, }, + maybe_changed: true, state: 0x7f, last_state: 0x7f, }, @@ -1380,6 +1398,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x3f, last_state: 0x3f, }, @@ -1389,6 +1408,7 @@ Simulation { index: StatePartIndex(19), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1398,6 +1418,7 @@ Simulation { index: StatePartIndex(20), ty: UInt<8>, }, + maybe_changed: true, state: 0x0f, last_state: 0x0f, }, @@ -1407,6 +1428,7 @@ Simulation { index: StatePartIndex(21), ty: UInt<8>, }, + maybe_changed: true, state: 0x07, last_state: 0x07, }, @@ -1416,6 +1438,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<8>, }, + maybe_changed: true, state: 0x03, last_state: 0x03, }, @@ -1425,6 +1448,7 @@ Simulation { index: StatePartIndex(23), ty: UInt<8>, }, + maybe_changed: true, state: 0x01, last_state: 0x01, }, @@ -1434,6 +1458,7 @@ Simulation { index: StatePartIndex(24), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1443,6 +1468,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<8>, }, + maybe_changed: true, state: 0x80, last_state: 0x80, }, @@ -1452,6 +1478,7 @@ Simulation { index: StatePartIndex(26), ty: UInt<8>, }, + maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1461,6 +1488,7 @@ Simulation { index: StatePartIndex(27), ty: UInt<8>, }, + maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1470,6 +1498,7 @@ Simulation { index: StatePartIndex(28), ty: UInt<8>, }, + maybe_changed: true, state: 0xf0, last_state: 0xf0, }, @@ -1479,6 +1508,7 @@ Simulation { index: StatePartIndex(29), ty: UInt<8>, }, + maybe_changed: true, state: 0xf8, last_state: 0xf8, }, @@ -1488,6 +1518,7 @@ Simulation { index: StatePartIndex(30), ty: UInt<8>, }, + maybe_changed: true, state: 0xfc, last_state: 0xfc, }, @@ -1497,6 +1528,7 @@ Simulation { index: StatePartIndex(31), ty: UInt<8>, }, + maybe_changed: true, state: 0xfe, last_state: 0xe1, }, @@ -1506,6 +1538,7 @@ Simulation { index: StatePartIndex(32), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1515,6 +1548,7 @@ Simulation { index: StatePartIndex(33), ty: UInt<8>, }, + maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1524,6 +1558,7 @@ Simulation { index: StatePartIndex(34), ty: UInt<8>, }, + maybe_changed: true, state: 0x10, last_state: 0x0f, }, @@ -1533,6 +1568,7 @@ Simulation { index: StatePartIndex(35), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0xe1, }, @@ -1541,6 +1577,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1550,6 +1587,7 @@ Simulation { index: StatePartIndex(37), ty: UInt<8>, }, + maybe_changed: true, state: 0xff, last_state: 0xff, }, @@ -1559,6 +1597,7 @@ Simulation { index: StatePartIndex(38), ty: UInt<8>, }, + maybe_changed: true, state: 0x7f, last_state: 0x7f, }, @@ -1568,6 +1607,7 @@ Simulation { index: StatePartIndex(39), ty: UInt<8>, }, + maybe_changed: true, state: 0x3f, last_state: 0x3f, }, @@ -1577,6 +1617,7 @@ Simulation { index: StatePartIndex(40), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1586,6 +1627,7 @@ Simulation { index: StatePartIndex(41), ty: UInt<8>, }, + maybe_changed: true, state: 0x0f, last_state: 0x0f, }, @@ -1595,6 +1637,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x07, last_state: 0x07, }, @@ -1604,6 +1647,7 @@ Simulation { index: StatePartIndex(43), ty: UInt<8>, }, + maybe_changed: true, state: 0x03, last_state: 0x03, }, @@ -1613,6 +1657,7 @@ Simulation { index: StatePartIndex(44), ty: UInt<8>, }, + maybe_changed: true, state: 0x01, last_state: 0x01, }, @@ -1622,6 +1667,7 @@ Simulation { index: StatePartIndex(45), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -1631,6 +1677,7 @@ Simulation { index: StatePartIndex(46), ty: UInt<8>, }, + maybe_changed: true, state: 0x80, last_state: 0x80, }, @@ -1640,6 +1687,7 @@ Simulation { index: StatePartIndex(47), ty: UInt<8>, }, + maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1649,6 +1697,7 @@ Simulation { index: StatePartIndex(48), ty: UInt<8>, }, + maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1658,6 +1707,7 @@ Simulation { index: StatePartIndex(49), ty: UInt<8>, }, + maybe_changed: true, state: 0xf0, last_state: 0xf0, }, @@ -1667,6 +1717,7 @@ Simulation { index: StatePartIndex(50), ty: UInt<8>, }, + maybe_changed: true, state: 0xf8, last_state: 0xf8, }, @@ -1676,6 +1727,7 @@ Simulation { index: StatePartIndex(51), ty: UInt<8>, }, + maybe_changed: true, state: 0xfc, last_state: 0xfc, }, @@ -1685,6 +1737,7 @@ Simulation { index: StatePartIndex(52), ty: UInt<8>, }, + maybe_changed: true, state: 0xfe, last_state: 0xe1, }, diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt index d470792..0df7f20 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt @@ -86,8 +86,8 @@ Simulation { value: [ 1, 0, - 1, - 0, + 1 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -155,6 +155,7 @@ Simulation { kind: BigBool { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -163,6 +164,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt index 56ea4ad..6cf4014 100644 --- a/crates/fayalite/tests/sim/expected/connect_const.txt +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -63,7 +63,7 @@ Simulation { big_slots: StatePart { value: [ 5, - 5, + 5 (modified), ], }, sim_only_slots: StatePart { @@ -124,6 +124,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<8>, }, + maybe_changed: true, state: 0x05, last_state: 0x05, }, diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt index 6b5814a..a75ff8a 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -90,9 +90,9 @@ Simulation { value: [ 1, 1, - 1, - 1, - 1, + 1 (modified), + 1 (modified), + 1 (modified), ], }, sim_only_slots: StatePart { @@ -175,6 +175,7 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -183,6 +184,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index 2bdd665..256e1b7 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -185,10 +185,10 @@ Simulation { }, small_slots: StatePart { value: [ - 0, - 0, - 1, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), ], }, big_slots: StatePart { @@ -197,12 +197,12 @@ Simulation { 0, 3, 3, - 4, - 3, - 0, - 1, - 4, - 4, + 4 (modified), + 3 (modified), + 0 (modified), + 1 (modified), + 4 (modified), + 4 (modified), ], }, sim_only_slots: StatePart { @@ -332,6 +332,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -340,6 +341,7 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -349,6 +351,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<4>, }, + maybe_changed: true, state: 0x3, last_state: 0x2, }, @@ -358,6 +361,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<4>, }, + maybe_changed: true, state: 0x3, last_state: 0x2, }, diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index 87c2098..1448f58 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -167,10 +167,10 @@ Simulation { }, small_slots: StatePart { value: [ - 0, - 0, - 1, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), ], }, big_slots: StatePart { @@ -179,11 +179,11 @@ Simulation { 0, 3, 3, - 4, - 3, - 1, - 4, - 4, + 4 (modified), + 3 (modified), + 1 (modified), + 4 (modified), + 4 (modified), ], }, sim_only_slots: StatePart { @@ -313,6 +313,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -321,6 +322,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -330,6 +332,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<4>, }, + maybe_changed: true, state: 0x3, last_state: 0x2, }, @@ -339,6 +342,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<4>, }, + maybe_changed: true, state: 0x3, last_state: 0x2, }, diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt index 64bbbe6..394cfbb 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.txt +++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt @@ -81,9 +81,9 @@ Simulation { big_slots: StatePart { value: [ 5, - 5, - 6, + 5 (modified), 6, + 6 (modified), ], }, sim_only_slots: StatePart { @@ -137,6 +137,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<8>, }, + maybe_changed: true, state: 0x05, last_state: 0x05, }, @@ -146,6 +147,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: true, state: 0x06, last_state: 0x06, }, diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index a3a52cb..2b00f05 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1191,10 +1191,10 @@ Simulation { value: [ 0, 0, - 0, - 0, - 1, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), 2, ], }, @@ -1207,110 +1207,110 @@ Simulation { 15, 2, 15, + 0 (modified), 0, 0, + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), 0, 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 62, - 62, - 0, - 0, - 1, - 1, - 62, - 3, - 1, + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 62 (modified), + 62 (modified), + 0 (modified), + 0 (modified), 1, 1, + 62 (modified), + 3 (modified), + 1 (modified), + 1 (modified), + 1 (modified), 1, 1, -1, - 1, - 1, - 15, - 3, - 1, - 1, - 3, - -1, - 0, - 0, - 1, - 0, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 2, - 3, - 12, - 13, - 13, - 13, - 2, - 1, - 1, - -1, - 2, - 1, - 1, - -1, - 1, - 1, - 1, - 3, - -1, - 2, - 3, - 3, - 12, - 15, - 60, - 62, - 62, - 62, - 0, - 0, - 0, - 1, - 2, - 3, - 3, - 1, - 1, - 1, - 1, - 1, - 2, - 3, - 6, - 7, - 7, - 7, - 2, - 3, - 3, - 12, - 15, + 1 (modified), + 1 (modified), + 15 (modified), + 3 (modified), + 1 (modified), + 1 (modified), + 3 (modified), + -1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 2 (modified), + 3 (modified), + 12 (modified), + 13 (modified), + 13 (modified), + 13 (modified), + 2 (modified), + 1 (modified), + 1 (modified), + -1 (modified), + 2 (modified), + 1 (modified), + 1 (modified), + -1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 3 (modified), + -1 (modified), + 2 (modified), + 3 (modified), + 3 (modified), + 12 (modified), + 15 (modified), + 60 (modified), + 62 (modified), + 62 (modified), + 62 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 2 (modified), + 3 (modified), + 3 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 2 (modified), + 3 (modified), + 6 (modified), + 7 (modified), + 7 (modified), + 7 (modified), + 2 (modified), + 3 (modified), + 3 (modified), + 12 (modified), + 15 (modified), ], }, sim_only_slots: StatePart { @@ -1746,6 +1746,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -1754,6 +1755,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1762,6 +1764,7 @@ Simulation { kind: BigBool { index: StatePartIndex(2), }, + maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -1771,6 +1774,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<2>, }, + maybe_changed: false, state: 0x2, last_state: 0x2, }, @@ -1780,6 +1784,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<4>, }, + maybe_changed: false, state: 0xf, last_state: 0xf, }, @@ -1789,6 +1794,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1798,6 +1804,7 @@ Simulation { index: StatePartIndex(6), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -1810,6 +1817,7 @@ Simulation { HdlSome(Bundle {0: UInt<1>, 1: Bool}), }, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1819,6 +1827,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1827,6 +1836,7 @@ Simulation { kind: BigBool { index: StatePartIndex(9), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1839,6 +1849,7 @@ Simulation { HdlSome(Bundle {0: UInt<1>, 1: Bool}), }, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1848,6 +1859,7 @@ Simulation { index: StatePartIndex(16), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1856,6 +1868,7 @@ Simulation { kind: BigBool { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1869,6 +1882,7 @@ Simulation { C(Bundle {a: Array, 2>, b: SInt<2>}), }, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1878,6 +1892,7 @@ Simulation { index: StatePartIndex(27), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1886,6 +1901,7 @@ Simulation { kind: BigBool { index: StatePartIndex(28), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1895,6 +1911,7 @@ Simulation { index: StatePartIndex(34), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1904,6 +1921,7 @@ Simulation { index: StatePartIndex(35), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1913,6 +1931,7 @@ Simulation { index: StatePartIndex(36), ty: SInt<2>, }, + maybe_changed: true, state: 0x3, last_state: 0x3, }, diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt index f49106f..48a3af5 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.txt +++ b/crates/fayalite/tests/sim/expected/extern_module.txt @@ -221,6 +221,7 @@ Simulation { kind: BigBool { index: StatePartIndex(0), }, + maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -229,6 +230,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt index 365830f..d488666 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.txt +++ b/crates/fayalite/tests/sim/expected/extern_module2.txt @@ -57,7 +57,7 @@ Simulation { big_slots: StatePart { value: [ 0, - 1, + 1 (modified), 101, ], }, @@ -280,6 +280,7 @@ Simulation { kind: BigBool { index: StatePartIndex(0), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -288,6 +289,7 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -297,6 +299,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: false, state: 0x65, last_state: 0x65, }, diff --git a/crates/fayalite/tests/sim/expected/last_connect.txt b/crates/fayalite/tests/sim/expected/last_connect.txt index 6a43497..297d395 100644 --- a/crates/fayalite/tests/sim/expected/last_connect.txt +++ b/crates/fayalite/tests/sim/expected/last_connect.txt @@ -418,39 +418,39 @@ Simulation { }, big_slots: StatePart { value: [ - 31, + 31 (modified), 1, 1, 1, 1, - 31, - 15, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 1, - 7, - 7, + 31 (modified), + 15 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 7 (modified), + 7 (modified), 3, - 0, - 0, - 3, - 1, - 3, - 1, - 6, - 7, - 7, - 7, - 4, - 0, - 1, - 2, + 0 (modified), + 0 (modified), 3, + 1 (modified), + 3 (modified), + 1 (modified), + 6 (modified), + 7 (modified), + 7 (modified), + 7 (modified), + 4 (modified), + 0 (modified), + 1 (modified), + 2 (modified), + 3 (modified), ], }, sim_only_slots: StatePart { @@ -614,6 +614,7 @@ Simulation { HdlSome(Array), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -622,6 +623,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -630,6 +632,7 @@ Simulation { kind: BigBool { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -638,6 +641,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -646,6 +650,7 @@ Simulation { kind: BigBool { index: StatePartIndex(4), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -658,6 +663,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -667,6 +673,7 @@ Simulation { index: StatePartIndex(17), ty: UInt<8>, }, + maybe_changed: true, state: 0x03, last_state: 0x02, }, @@ -676,6 +683,7 @@ Simulation { index: StatePartIndex(20), ty: UInt<8>, }, + maybe_changed: true, state: 0x03, last_state: 0x02, }, diff --git a/crates/fayalite/tests/sim/expected/many_memories.txt b/crates/fayalite/tests/sim/expected/many_memories.txt index c521d72..84d9162 100644 --- a/crates/fayalite/tests/sim/expected/many_memories.txt +++ b/crates/fayalite/tests/sim/expected/many_memories.txt @@ -2910,102 +2910,102 @@ Simulation { }, small_slots: StatePart { value: [ - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 15, - 1, - 0, - 0, - 0, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 15 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 15 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 15 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 15 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 15 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 15 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 15 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 15 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { @@ -3091,8 +3091,8 @@ Simulation { 0, 0, 1, - 0, - 1, + 0 (modified), + 1 (modified), 15, 1, 0, @@ -3102,8 +3102,8 @@ Simulation { 0, 0, 1, - 0, - 1, + 0 (modified), + 1 (modified), 15, 1, 0, @@ -3113,8 +3113,8 @@ Simulation { 0, 0, 1, - 0, - 1, + 0 (modified), + 1 (modified), 15, 1, 0, @@ -3124,8 +3124,8 @@ Simulation { 0, 0, 1, - 0, - 1, + 0 (modified), + 1 (modified), 15, 1, 0, @@ -3135,8 +3135,8 @@ Simulation { 0, 0, 1, - 0, - 1, + 0 (modified), + 1 (modified), 15, 1, 0, @@ -3146,8 +3146,8 @@ Simulation { 0, 0, 1, - 0, - 1, + 0 (modified), + 1 (modified), 15, 1, 0, @@ -3157,8 +3157,8 @@ Simulation { 0, 0, 1, - 0, - 1, + 0 (modified), + 1 (modified), 15, 1, 0, @@ -3168,8 +3168,8 @@ Simulation { 0, 0, 1, - 0, - 1, + 0 (modified), + 1 (modified), ], }, sim_only_slots: StatePart { @@ -5545,6 +5545,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5553,6 +5554,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5561,6 +5563,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5569,6 +5572,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5578,6 +5582,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5586,6 +5591,7 @@ Simulation { kind: BigBool { index: StatePartIndex(5), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5594,6 +5600,7 @@ Simulation { kind: BigClock { index: StatePartIndex(6), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5602,6 +5609,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5611,6 +5619,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5619,6 +5628,7 @@ Simulation { kind: BigBool { index: StatePartIndex(9), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5627,6 +5637,7 @@ Simulation { kind: BigClock { index: StatePartIndex(10), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5635,6 +5646,7 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5644,6 +5656,7 @@ Simulation { index: StatePartIndex(12), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5652,6 +5665,7 @@ Simulation { kind: BigBool { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5660,6 +5674,7 @@ Simulation { kind: BigClock { index: StatePartIndex(14), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5668,6 +5683,7 @@ Simulation { kind: BigBool { index: StatePartIndex(15), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5677,6 +5693,7 @@ Simulation { index: StatePartIndex(16), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5685,6 +5702,7 @@ Simulation { kind: BigBool { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5693,6 +5711,7 @@ Simulation { kind: BigClock { index: StatePartIndex(18), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5701,6 +5720,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5710,6 +5730,7 @@ Simulation { index: StatePartIndex(20), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5718,6 +5739,7 @@ Simulation { kind: BigBool { index: StatePartIndex(21), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5726,6 +5748,7 @@ Simulation { kind: BigClock { index: StatePartIndex(22), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5734,6 +5757,7 @@ Simulation { kind: BigBool { index: StatePartIndex(23), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5743,6 +5767,7 @@ Simulation { index: StatePartIndex(24), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5751,6 +5776,7 @@ Simulation { kind: BigBool { index: StatePartIndex(25), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5759,6 +5785,7 @@ Simulation { kind: BigClock { index: StatePartIndex(26), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5767,6 +5794,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5776,6 +5804,7 @@ Simulation { index: StatePartIndex(28), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -5784,6 +5813,7 @@ Simulation { kind: BigBool { index: StatePartIndex(29), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5792,6 +5822,7 @@ Simulation { kind: BigClock { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5800,6 +5831,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5809,6 +5841,7 @@ Simulation { index: StatePartIndex(32), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5817,6 +5850,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5825,6 +5859,7 @@ Simulation { kind: BigClock { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5833,6 +5868,7 @@ Simulation { kind: BigBool { index: StatePartIndex(35), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5841,6 +5877,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5850,6 +5887,7 @@ Simulation { index: StatePartIndex(37), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5858,6 +5896,7 @@ Simulation { kind: BigBool { index: StatePartIndex(38), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5866,6 +5905,7 @@ Simulation { kind: BigClock { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5874,6 +5914,7 @@ Simulation { kind: BigBool { index: StatePartIndex(40), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5882,6 +5923,7 @@ Simulation { kind: BigBool { index: StatePartIndex(41), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5891,6 +5933,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5899,6 +5942,7 @@ Simulation { kind: BigBool { index: StatePartIndex(43), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5907,6 +5951,7 @@ Simulation { kind: BigClock { index: StatePartIndex(44), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5915,6 +5960,7 @@ Simulation { kind: BigBool { index: StatePartIndex(45), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5923,6 +5969,7 @@ Simulation { kind: BigBool { index: StatePartIndex(46), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5932,6 +5979,7 @@ Simulation { index: StatePartIndex(47), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5940,6 +5988,7 @@ Simulation { kind: BigBool { index: StatePartIndex(48), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5948,6 +5997,7 @@ Simulation { kind: BigClock { index: StatePartIndex(49), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5956,6 +6006,7 @@ Simulation { kind: BigBool { index: StatePartIndex(50), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5964,6 +6015,7 @@ Simulation { kind: BigBool { index: StatePartIndex(51), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -5973,6 +6025,7 @@ Simulation { index: StatePartIndex(52), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5981,6 +6034,7 @@ Simulation { kind: BigBool { index: StatePartIndex(53), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -5989,6 +6043,7 @@ Simulation { kind: BigClock { index: StatePartIndex(54), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -5997,6 +6052,7 @@ Simulation { kind: BigBool { index: StatePartIndex(55), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6005,6 +6061,7 @@ Simulation { kind: BigBool { index: StatePartIndex(56), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6014,6 +6071,7 @@ Simulation { index: StatePartIndex(57), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6022,6 +6080,7 @@ Simulation { kind: BigBool { index: StatePartIndex(58), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6030,6 +6089,7 @@ Simulation { kind: BigClock { index: StatePartIndex(59), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6038,6 +6098,7 @@ Simulation { kind: BigBool { index: StatePartIndex(60), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6046,6 +6107,7 @@ Simulation { kind: BigBool { index: StatePartIndex(61), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6055,6 +6117,7 @@ Simulation { index: StatePartIndex(62), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6063,6 +6126,7 @@ Simulation { kind: BigBool { index: StatePartIndex(63), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6071,6 +6135,7 @@ Simulation { kind: BigClock { index: StatePartIndex(64), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6079,6 +6144,7 @@ Simulation { kind: BigBool { index: StatePartIndex(65), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6087,6 +6153,7 @@ Simulation { kind: BigBool { index: StatePartIndex(66), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6096,6 +6163,7 @@ Simulation { index: StatePartIndex(67), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6104,6 +6172,7 @@ Simulation { kind: BigBool { index: StatePartIndex(68), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6112,6 +6181,7 @@ Simulation { kind: BigClock { index: StatePartIndex(69), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6120,6 +6190,7 @@ Simulation { kind: BigBool { index: StatePartIndex(70), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6128,6 +6199,7 @@ Simulation { kind: BigBool { index: StatePartIndex(71), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6137,6 +6209,7 @@ Simulation { index: StatePartIndex(72), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6145,6 +6218,7 @@ Simulation { kind: BigBool { index: StatePartIndex(73), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6153,6 +6227,7 @@ Simulation { kind: BigClock { index: StatePartIndex(74), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6161,6 +6236,7 @@ Simulation { kind: BigBool { index: StatePartIndex(75), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6170,6 +6246,7 @@ Simulation { index: StatePartIndex(76), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6178,6 +6255,7 @@ Simulation { kind: BigBool { index: StatePartIndex(77), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6186,6 +6264,7 @@ Simulation { kind: BigClock { index: StatePartIndex(78), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6194,6 +6273,7 @@ Simulation { kind: BigBool { index: StatePartIndex(79), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6202,6 +6282,7 @@ Simulation { kind: BigBool { index: StatePartIndex(80), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6211,6 +6292,7 @@ Simulation { index: StatePartIndex(83), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6219,6 +6301,7 @@ Simulation { kind: BigBool { index: StatePartIndex(84), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6227,6 +6310,7 @@ Simulation { kind: BigClock { index: StatePartIndex(85), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6235,6 +6319,7 @@ Simulation { kind: BigBool { index: StatePartIndex(86), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6244,6 +6329,7 @@ Simulation { index: StatePartIndex(87), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6252,6 +6338,7 @@ Simulation { kind: BigBool { index: StatePartIndex(88), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6260,6 +6347,7 @@ Simulation { kind: BigClock { index: StatePartIndex(89), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6268,6 +6356,7 @@ Simulation { kind: BigBool { index: StatePartIndex(90), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6276,6 +6365,7 @@ Simulation { kind: BigBool { index: StatePartIndex(91), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6285,6 +6375,7 @@ Simulation { index: StatePartIndex(94), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6293,6 +6384,7 @@ Simulation { kind: BigBool { index: StatePartIndex(95), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6301,6 +6393,7 @@ Simulation { kind: BigClock { index: StatePartIndex(96), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6309,6 +6402,7 @@ Simulation { kind: BigBool { index: StatePartIndex(97), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6318,6 +6412,7 @@ Simulation { index: StatePartIndex(98), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6326,6 +6421,7 @@ Simulation { kind: BigBool { index: StatePartIndex(99), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6334,6 +6430,7 @@ Simulation { kind: BigClock { index: StatePartIndex(100), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6342,6 +6439,7 @@ Simulation { kind: BigBool { index: StatePartIndex(101), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6350,6 +6448,7 @@ Simulation { kind: BigBool { index: StatePartIndex(102), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6359,6 +6458,7 @@ Simulation { index: StatePartIndex(105), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6367,6 +6467,7 @@ Simulation { kind: BigBool { index: StatePartIndex(106), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6375,6 +6476,7 @@ Simulation { kind: BigClock { index: StatePartIndex(107), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6383,6 +6485,7 @@ Simulation { kind: BigBool { index: StatePartIndex(108), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6392,6 +6495,7 @@ Simulation { index: StatePartIndex(109), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6400,6 +6504,7 @@ Simulation { kind: BigBool { index: StatePartIndex(110), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6408,6 +6513,7 @@ Simulation { kind: BigClock { index: StatePartIndex(111), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6416,6 +6522,7 @@ Simulation { kind: BigBool { index: StatePartIndex(112), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6424,6 +6531,7 @@ Simulation { kind: BigBool { index: StatePartIndex(113), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6433,6 +6541,7 @@ Simulation { index: StatePartIndex(116), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6441,6 +6550,7 @@ Simulation { kind: BigBool { index: StatePartIndex(117), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6449,6 +6559,7 @@ Simulation { kind: BigClock { index: StatePartIndex(118), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6457,6 +6568,7 @@ Simulation { kind: BigBool { index: StatePartIndex(119), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6466,6 +6578,7 @@ Simulation { index: StatePartIndex(120), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6474,6 +6587,7 @@ Simulation { kind: BigBool { index: StatePartIndex(121), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6482,6 +6596,7 @@ Simulation { kind: BigClock { index: StatePartIndex(122), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6490,6 +6605,7 @@ Simulation { kind: BigBool { index: StatePartIndex(123), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6498,6 +6614,7 @@ Simulation { kind: BigBool { index: StatePartIndex(124), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6507,6 +6624,7 @@ Simulation { index: StatePartIndex(127), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6515,6 +6633,7 @@ Simulation { kind: BigBool { index: StatePartIndex(128), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6523,6 +6642,7 @@ Simulation { kind: BigClock { index: StatePartIndex(129), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6531,6 +6651,7 @@ Simulation { kind: BigBool { index: StatePartIndex(130), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6540,6 +6661,7 @@ Simulation { index: StatePartIndex(131), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6548,6 +6670,7 @@ Simulation { kind: BigBool { index: StatePartIndex(132), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6556,6 +6679,7 @@ Simulation { kind: BigClock { index: StatePartIndex(133), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6564,6 +6688,7 @@ Simulation { kind: BigBool { index: StatePartIndex(134), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6572,6 +6697,7 @@ Simulation { kind: BigBool { index: StatePartIndex(135), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6581,6 +6707,7 @@ Simulation { index: StatePartIndex(138), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6589,6 +6716,7 @@ Simulation { kind: BigBool { index: StatePartIndex(139), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6597,6 +6725,7 @@ Simulation { kind: BigClock { index: StatePartIndex(140), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6605,6 +6734,7 @@ Simulation { kind: BigBool { index: StatePartIndex(141), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6614,6 +6744,7 @@ Simulation { index: StatePartIndex(142), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6622,6 +6753,7 @@ Simulation { kind: BigBool { index: StatePartIndex(143), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6630,6 +6762,7 @@ Simulation { kind: BigClock { index: StatePartIndex(144), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6638,6 +6771,7 @@ Simulation { kind: BigBool { index: StatePartIndex(145), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6646,6 +6780,7 @@ Simulation { kind: BigBool { index: StatePartIndex(146), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6655,6 +6790,7 @@ Simulation { index: StatePartIndex(149), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xf, }, @@ -6663,6 +6799,7 @@ Simulation { kind: BigBool { index: StatePartIndex(150), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -6671,6 +6808,7 @@ Simulation { kind: BigClock { index: StatePartIndex(151), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6679,6 +6817,7 @@ Simulation { kind: BigBool { index: StatePartIndex(152), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6688,6 +6827,7 @@ Simulation { index: StatePartIndex(153), ty: UInt<4>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6696,6 +6836,7 @@ Simulation { kind: BigBool { index: StatePartIndex(154), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6704,6 +6845,7 @@ Simulation { kind: BigClock { index: StatePartIndex(155), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -6712,6 +6854,7 @@ Simulation { kind: BigBool { index: StatePartIndex(156), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -6720,6 +6863,7 @@ Simulation { kind: BigBool { index: StatePartIndex(157), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt index 0358bb3..db5a2f3 100644 --- a/crates/fayalite/tests/sim/expected/memories.txt +++ b/crates/fayalite/tests/sim/expected/memories.txt @@ -522,18 +522,18 @@ Simulation { }, small_slots: StatePart { value: [ - 1, - 0, - 0, - 1, - 2, - 1, - 0, - 0, - 0, - 2, - 2, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 2 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 2 (modified), + 2 (modified), + 0 (modified), ], }, big_slots: StatePart { @@ -562,10 +562,10 @@ Simulation { -32, 1, 1, - 208, - -32, - 1, - 1, + 208 (modified), + -32 (modified), + 1 (modified), + 1 (modified), ], }, sim_only_slots: StatePart { @@ -1168,6 +1168,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<4>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1176,6 +1177,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1184,6 +1186,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1193,6 +1196,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: true, state: 0xb0, last_state: 0xb0, }, @@ -1202,6 +1206,7 @@ Simulation { index: StatePartIndex(4), ty: SInt<8>, }, + maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1211,6 +1216,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<4>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1219,6 +1225,7 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1227,6 +1234,7 @@ Simulation { kind: BigClock { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1236,6 +1244,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<8>, }, + maybe_changed: true, state: 0xd0, last_state: 0xd0, }, @@ -1245,6 +1254,7 @@ Simulation { index: StatePartIndex(9), ty: SInt<8>, }, + maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1253,6 +1263,7 @@ Simulation { kind: BigBool { index: StatePartIndex(10), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1261,6 +1272,7 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1270,6 +1282,7 @@ Simulation { index: StatePartIndex(12), ty: UInt<4>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1278,6 +1291,7 @@ Simulation { kind: BigBool { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1286,6 +1300,7 @@ Simulation { kind: BigClock { index: StatePartIndex(14), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1295,6 +1310,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<8>, }, + maybe_changed: true, state: 0xb0, last_state: 0xb0, }, @@ -1304,6 +1320,7 @@ Simulation { index: StatePartIndex(16), ty: SInt<8>, }, + maybe_changed: true, state: 0xc0, last_state: 0xc0, }, @@ -1313,6 +1330,7 @@ Simulation { index: StatePartIndex(17), ty: UInt<4>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1321,6 +1339,7 @@ Simulation { kind: BigBool { index: StatePartIndex(18), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1329,6 +1348,7 @@ Simulation { kind: BigClock { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1338,6 +1358,7 @@ Simulation { index: StatePartIndex(20), ty: UInt<8>, }, + maybe_changed: true, state: 0xd0, last_state: 0xd0, }, @@ -1347,6 +1368,7 @@ Simulation { index: StatePartIndex(21), ty: SInt<8>, }, + maybe_changed: true, state: 0xe0, last_state: 0xe0, }, @@ -1355,6 +1377,7 @@ Simulation { kind: BigBool { index: StatePartIndex(22), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1363,6 +1386,7 @@ Simulation { kind: BigBool { index: StatePartIndex(23), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt index b4041ba..5a82b91 100644 --- a/crates/fayalite/tests/sim/expected/memories2.txt +++ b/crates/fayalite/tests/sim/expected/memories2.txt @@ -545,15 +545,15 @@ Simulation { value: [ 0, 0, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { @@ -568,32 +568,32 @@ Simulation { 0, 0, 0, + 0 (modified), 0, + 0 (modified), 0, + 0 (modified), + 0 (modified), 0, + 0 (modified), + 0 (modified), 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 1, - 0, - 0, - 0, - 0, - 1, - 1, - 1, + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), ], }, sim_only_slots: StatePart { @@ -943,6 +943,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -951,6 +952,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -959,6 +961,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -968,6 +971,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<2>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -976,6 +980,7 @@ Simulation { kind: BigBool { index: StatePartIndex(4), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -985,6 +990,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<2>, }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -993,6 +999,7 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1002,6 +1009,7 @@ Simulation { index: StatePartIndex(7), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1010,6 +1018,7 @@ Simulation { kind: BigBool { index: StatePartIndex(8), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1018,6 +1027,7 @@ Simulation { kind: BigClock { index: StatePartIndex(9), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1030,6 +1040,7 @@ Simulation { HdlSome(Bool), }, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1038,6 +1049,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1046,6 +1058,7 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1058,6 +1071,7 @@ Simulation { HdlSome(Bool), }, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1066,6 +1080,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1074,6 +1089,7 @@ Simulation { kind: BigBool { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt index 2213912..7522430 100644 --- a/crates/fayalite/tests/sim/expected/memories3.txt +++ b/crates/fayalite/tests/sim/expected/memories3.txt @@ -1356,20 +1356,20 @@ Simulation { }, small_slots: StatePart { value: [ - 1, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { @@ -1415,6 +1415,22 @@ Simulation { 0, 0, 0, + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), 0, 0, 0, @@ -1434,54 +1450,38 @@ Simulation { 0, 0, 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -2391,6 +2391,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2399,6 +2400,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2407,6 +2409,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2416,6 +2419,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2425,6 +2429,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2434,6 +2439,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2443,6 +2449,7 @@ Simulation { index: StatePartIndex(6), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2452,6 +2459,7 @@ Simulation { index: StatePartIndex(7), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2461,6 +2469,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2470,6 +2479,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2479,6 +2489,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2488,6 +2499,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2496,6 +2508,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2504,6 +2517,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2513,6 +2527,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2522,6 +2537,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2531,6 +2547,7 @@ Simulation { index: StatePartIndex(16), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2540,6 +2557,7 @@ Simulation { index: StatePartIndex(17), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2549,6 +2567,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2558,6 +2577,7 @@ Simulation { index: StatePartIndex(19), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2567,6 +2587,7 @@ Simulation { index: StatePartIndex(20), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2576,6 +2597,7 @@ Simulation { index: StatePartIndex(21), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2584,6 +2606,7 @@ Simulation { kind: BigBool { index: StatePartIndex(22), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2592,6 +2615,7 @@ Simulation { kind: BigBool { index: StatePartIndex(23), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2600,6 +2624,7 @@ Simulation { kind: BigBool { index: StatePartIndex(24), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2608,6 +2633,7 @@ Simulation { kind: BigBool { index: StatePartIndex(25), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2616,6 +2642,7 @@ Simulation { kind: BigBool { index: StatePartIndex(26), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2624,6 +2651,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2632,6 +2660,7 @@ Simulation { kind: BigBool { index: StatePartIndex(28), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2640,6 +2669,7 @@ Simulation { kind: BigBool { index: StatePartIndex(29), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2649,6 +2679,7 @@ Simulation { index: StatePartIndex(30), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2657,6 +2688,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2665,6 +2697,7 @@ Simulation { kind: BigClock { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2674,6 +2707,7 @@ Simulation { index: StatePartIndex(33), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2683,6 +2717,7 @@ Simulation { index: StatePartIndex(34), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2692,6 +2727,7 @@ Simulation { index: StatePartIndex(35), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2701,6 +2737,7 @@ Simulation { index: StatePartIndex(36), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2710,6 +2747,7 @@ Simulation { index: StatePartIndex(37), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2719,6 +2757,7 @@ Simulation { index: StatePartIndex(38), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2728,6 +2767,7 @@ Simulation { index: StatePartIndex(39), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2737,6 +2777,7 @@ Simulation { index: StatePartIndex(40), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2746,6 +2787,7 @@ Simulation { index: StatePartIndex(57), ty: UInt<3>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2754,6 +2796,7 @@ Simulation { kind: BigBool { index: StatePartIndex(58), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2762,6 +2805,7 @@ Simulation { kind: BigClock { index: StatePartIndex(59), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -2771,6 +2815,7 @@ Simulation { index: StatePartIndex(60), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2780,6 +2825,7 @@ Simulation { index: StatePartIndex(61), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2789,6 +2835,7 @@ Simulation { index: StatePartIndex(62), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2798,6 +2845,7 @@ Simulation { index: StatePartIndex(63), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2807,6 +2855,7 @@ Simulation { index: StatePartIndex(64), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2816,6 +2865,7 @@ Simulation { index: StatePartIndex(65), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2825,6 +2875,7 @@ Simulation { index: StatePartIndex(66), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2834,6 +2885,7 @@ Simulation { index: StatePartIndex(67), ty: UInt<8>, }, + maybe_changed: true, state: 0x00, last_state: 0x00, }, @@ -2842,6 +2894,7 @@ Simulation { kind: BigBool { index: StatePartIndex(68), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2850,6 +2903,7 @@ Simulation { kind: BigBool { index: StatePartIndex(69), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2858,6 +2912,7 @@ Simulation { kind: BigBool { index: StatePartIndex(70), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2866,6 +2921,7 @@ Simulation { kind: BigBool { index: StatePartIndex(71), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2874,6 +2930,7 @@ Simulation { kind: BigBool { index: StatePartIndex(72), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2882,6 +2939,7 @@ Simulation { kind: BigBool { index: StatePartIndex(73), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2890,6 +2948,7 @@ Simulation { kind: BigBool { index: StatePartIndex(74), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2898,6 +2957,7 @@ Simulation { kind: BigBool { index: StatePartIndex(75), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt index 3f7a55e..7f89a66 100644 --- a/crates/fayalite/tests/sim/expected/mod1.txt +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -207,11 +207,11 @@ Simulation { -2, -2, 15, - -2, - 14, - 5, - 1, - 15, + -2 (modified), + 14 (modified), + 5 (modified), + 1 (modified), + 15 (modified), ], }, sim_only_slots: StatePart { @@ -445,6 +445,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<4>, }, + maybe_changed: true, state: 0xa, last_state: 0x3, }, @@ -454,6 +455,7 @@ Simulation { index: StatePartIndex(1), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x3, }, @@ -463,6 +465,7 @@ Simulation { index: StatePartIndex(2), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -472,6 +475,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xe, }, @@ -481,6 +485,7 @@ Simulation { index: StatePartIndex(8), ty: UInt<4>, }, + maybe_changed: true, state: 0xa, last_state: 0x3, }, @@ -490,6 +495,7 @@ Simulation { index: StatePartIndex(9), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x3, }, @@ -499,6 +505,7 @@ Simulation { index: StatePartIndex(10), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -508,6 +515,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xe, }, @@ -517,6 +525,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<4>, }, + maybe_changed: true, state: 0xa, last_state: 0x3, }, @@ -526,6 +535,7 @@ Simulation { index: StatePartIndex(5), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x3, }, @@ -535,6 +545,7 @@ Simulation { index: StatePartIndex(6), ty: SInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -544,6 +555,7 @@ Simulation { index: StatePartIndex(7), ty: UInt<4>, }, + maybe_changed: true, state: 0xf, last_state: 0xe, }, diff --git a/crates/fayalite/tests/sim/expected/phantom_const.txt b/crates/fayalite/tests/sim/expected/phantom_const.txt index 94072ac..864a4f7 100644 --- a/crates/fayalite/tests/sim/expected/phantom_const.txt +++ b/crates/fayalite/tests/sim/expected/phantom_const.txt @@ -185,11 +185,11 @@ Simulation { }, small_slots: StatePart { value: [ - 1, - 0, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { @@ -197,11 +197,11 @@ Simulation { 0, 0, 0, - 0, - 0, - 0, - 0, - 0, + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -373,6 +373,7 @@ Simulation { ["a","b"], ), }, + maybe_changed: true, state: PhantomConst, last_state: PhantomConst, }, @@ -383,6 +384,7 @@ Simulation { ["a","b"], ), }, + maybe_changed: true, state: PhantomConst, last_state: PhantomConst, }, @@ -392,6 +394,7 @@ Simulation { index: StatePartIndex(0), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -400,6 +403,7 @@ Simulation { kind: BigBool { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -408,6 +412,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -418,6 +423,7 @@ Simulation { "mem_element", ), }, + maybe_changed: true, state: PhantomConst, last_state: PhantomConst, }, diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_false.txt b/crates/fayalite/tests/sim/expected/queue_1_false_false.txt index 570c08d..1ac0403 100644 --- a/crates/fayalite/tests/sim/expected/queue_1_false_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_1_false_false.txt @@ -1098,35 +1098,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 51, + 51 (modified), 0, - 51, + 51 (modified), 25, - 51, + 51 (modified), 0, - 51, + 51 (modified), 25, 1, 0, @@ -1138,56 +1138,56 @@ Simulation { 0, 25, 1, + 25 (modified), + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1, + 1 (modified), + 0 (modified), + 0, + 0, + 0, + 0, + 1, + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 1, + 1 (modified), + 1 (modified), 25, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 1, - 1, - 25, - 0, - 0, - 1, - 1, - 25, - 1, - 50, - 51, - 51, - 51, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 25 (modified), + 1 (modified), + 50 (modified), + 51 (modified), + 51 (modified), + 51 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), 0, + 0 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -1722,6 +1722,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1730,6 +1731,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1742,6 +1744,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1751,6 +1754,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x19, last_state: 0x19, }, @@ -1759,6 +1763,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1771,6 +1776,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1780,6 +1786,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x19, last_state: 0x19, }, @@ -1788,6 +1795,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1797,6 +1805,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1806,6 +1815,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1814,6 +1824,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1822,6 +1833,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1831,6 +1843,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x19, last_state: 0x19, }, @@ -1840,6 +1853,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1848,6 +1862,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1856,6 +1871,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1865,6 +1881,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x19, last_state: 0x19, }, @@ -1873,6 +1890,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1882,6 +1900,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1891,6 +1910,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1899,6 +1919,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1907,6 +1928,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1915,6 +1937,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1923,6 +1946,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1931,6 +1955,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1939,6 +1964,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1947,6 +1973,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1955,6 +1982,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1964,6 +1992,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x19, last_state: 0x19, }, @@ -1973,6 +2002,7 @@ Simulation { index: StatePartIndex(66), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/queue_1_false_true.txt b/crates/fayalite/tests/sim/expected/queue_1_false_true.txt index 5bff275..5b56068 100644 --- a/crates/fayalite/tests/sim/expected/queue_1_false_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_1_false_true.txt @@ -1079,35 +1079,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 63, + 63 (modified), 0, - 63, + 63 (modified), 31, - 63, + 63 (modified), 0, - 63, + 63 (modified), 31, 1, 0, @@ -1119,54 +1119,54 @@ Simulation { 0, 31, 1, + 31 (modified), + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1, + 1 (modified), + 0 (modified), + 0, + 0, + 0, + 0, + 1, + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 1, + 1 (modified), + 1 (modified), 31, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 1, - 1, - 31, - 0, - 0, - 1, - 1, - 31, - 1, - 62, - 63, - 63, - 63, - 0, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 31 (modified), + 1 (modified), + 62 (modified), + 63 (modified), + 63 (modified), + 63 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), 0, + 0 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -1701,6 +1701,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1709,6 +1710,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1721,6 +1723,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1730,6 +1733,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1738,6 +1742,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1750,6 +1755,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1759,6 +1765,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1767,6 +1774,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1776,6 +1784,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1785,6 +1794,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1793,6 +1803,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1801,6 +1812,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1810,6 +1822,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1819,6 +1832,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1827,6 +1841,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1835,6 +1850,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1844,6 +1860,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1852,6 +1869,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1861,6 +1879,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1870,6 +1889,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1878,6 +1898,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1886,6 +1907,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1894,6 +1916,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1902,6 +1925,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1910,6 +1934,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1918,6 +1943,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1926,6 +1952,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1934,6 +1961,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1943,6 +1971,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1952,6 +1981,7 @@ Simulation { index: StatePartIndex(64), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/queue_1_true_false.txt b/crates/fayalite/tests/sim/expected/queue_1_true_false.txt index d9771dc..6076237 100644 --- a/crates/fayalite/tests/sim/expected/queue_1_true_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_1_true_false.txt @@ -1108,35 +1108,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 63, + 63 (modified), 0, - 63, + 63 (modified), 31, - 63, + 63 (modified), 0, - 63, + 63 (modified), 31, 1, 0, @@ -1148,56 +1148,56 @@ Simulation { 0, 31, 1, + 31 (modified), + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1, + 1 (modified), + 0 (modified), + 0, + 0, + 0, + 0, + 1, + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 1, + 1 (modified), + 1 (modified), 31, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 1, - 1, - 31, - 0, - 0, - 1, - 1, - 31, - 1, - 62, - 63, - 63, - 63, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 31 (modified), + 1 (modified), + 62 (modified), + 63 (modified), + 63 (modified), + 63 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), 0, + 0 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -1732,6 +1732,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1740,6 +1741,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1752,6 +1754,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1761,6 +1764,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1769,6 +1773,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1781,6 +1786,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1790,6 +1796,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1798,6 +1805,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1807,6 +1815,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1816,6 +1825,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1824,6 +1834,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1832,6 +1843,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1841,6 +1853,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1850,6 +1863,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1858,6 +1872,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1866,6 +1881,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1875,6 +1891,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1883,6 +1900,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1892,6 +1910,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1901,6 +1920,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1909,6 +1929,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1917,6 +1938,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1925,6 +1947,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1933,6 +1956,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1941,6 +1965,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1949,6 +1974,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1957,6 +1983,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1965,6 +1992,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1974,6 +2002,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x1f, last_state: 0x1f, }, @@ -1983,6 +2012,7 @@ Simulation { index: StatePartIndex(66), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/queue_1_true_true.txt b/crates/fayalite/tests/sim/expected/queue_1_true_true.txt index 0e16d2d..8fe32ad 100644 --- a/crates/fayalite/tests/sim/expected/queue_1_true_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_1_true_true.txt @@ -1089,35 +1089,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 71, + 71 (modified), 0, - 71, + 71 (modified), 35, - 71, + 71 (modified), 0, - 71, + 71 (modified), 35, 1, 0, @@ -1129,54 +1129,54 @@ Simulation { 0, 35, 1, + 35 (modified), + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1, + 1 (modified), + 0 (modified), + 0, + 0, + 0, + 0, + 1, + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 1, + 1 (modified), + 1 (modified), 35, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 1, - 1, - 35, - 0, - 0, - 1, - 1, - 35, - 1, - 70, - 71, - 71, - 71, - 0, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 35 (modified), + 1 (modified), + 70 (modified), + 71 (modified), + 71 (modified), + 71 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), 0, + 0 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -1711,6 +1711,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1719,6 +1720,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1731,6 +1733,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1740,6 +1743,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1748,6 +1752,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1760,6 +1765,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1769,6 +1775,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1777,6 +1784,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1786,6 +1794,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1795,6 +1804,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1803,6 +1813,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1811,6 +1822,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1820,6 +1832,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1829,6 +1842,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1837,6 +1851,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1845,6 +1860,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1854,6 +1870,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1862,6 +1879,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1871,6 +1889,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1880,6 +1899,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1888,6 +1908,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1896,6 +1917,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1904,6 +1926,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1912,6 +1935,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1920,6 +1944,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1928,6 +1953,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1936,6 +1962,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1944,6 +1971,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1953,6 +1981,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1962,6 +1991,7 @@ Simulation { index: StatePartIndex(64), ty: UInt<0>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/queue_2_false_false.txt b/crates/fayalite/tests/sim/expected/queue_2_false_false.txt index 23b0a7b..5a5c47d 100644 --- a/crates/fayalite/tests/sim/expected/queue_2_false_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_2_false_false.txt @@ -1114,35 +1114,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 1, - 1, - 0, - 0, - 1, - 0, - 1, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 71, + 71 (modified), 1, - 71, + 71 (modified), 35, - 71, + 71 (modified), 0, - 71, + 71 (modified), 35, 1, 1, @@ -1154,58 +1154,58 @@ Simulation { 0, 35, 1, + 35 (modified), + 1 (modified), + 0, + 1 (modified), + 0 (modified), + 1, + 1 (modified), + 1, + 1 (modified), + 0 (modified), + 1, + 1, + 0, + 0, + 0, + 0 (modified), + 0, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1 (modified), 35, + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 35 (modified), + 1 (modified), + 70 (modified), + 71 (modified), + 71 (modified), + 71 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 2 (modified), + 0 (modified), + 2 (modified), + 2 (modified), + 0 (modified), 1, - 0, - 1, - 0, - 1, - 1, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 35, - 0, - 1, - 1, - 1, - 35, - 1, - 70, - 71, - 71, - 71, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 1, - 1, - 2, - 0, - 2, - 2, - 0, - 1, - 3, - 1, - 1, + 3 (modified), + 1 (modified), + 1 (modified), ], }, sim_only_slots: StatePart { @@ -1740,6 +1740,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1748,6 +1749,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1760,6 +1762,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1769,6 +1772,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1777,6 +1781,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1789,6 +1794,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1798,6 +1804,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1806,6 +1813,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1815,6 +1823,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1824,6 +1833,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1832,6 +1842,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1840,6 +1851,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1849,6 +1861,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1858,6 +1871,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1866,6 +1880,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1874,6 +1889,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1883,6 +1899,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1891,6 +1908,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1900,6 +1918,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1909,6 +1928,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1917,6 +1937,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1925,6 +1946,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1933,6 +1955,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1941,6 +1964,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1949,6 +1973,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1957,6 +1982,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1965,6 +1991,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1973,6 +2000,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1982,6 +2010,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x23, last_state: 0x23, }, @@ -1991,6 +2020,7 @@ Simulation { index: StatePartIndex(68), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, diff --git a/crates/fayalite/tests/sim/expected/queue_2_false_true.txt b/crates/fayalite/tests/sim/expected/queue_2_false_true.txt index a057fa7..2d9ea3f 100644 --- a/crates/fayalite/tests/sim/expected/queue_2_false_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_2_false_true.txt @@ -1095,35 +1095,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 0, - 1, - 0, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 77, + 77 (modified), 1, - 77, + 77 (modified), 38, - 77, + 77 (modified), 0, - 77, + 77 (modified), 38, 1, 0, @@ -1135,56 +1135,56 @@ Simulation { 0, 38, 1, + 38 (modified), + 1 (modified), + 1, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1, + 1 (modified), + 0 (modified), + 1, + 1, + 0, + 0, + 0, + 0 (modified), + 0, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1 (modified), 38, + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 38 (modified), + 1 (modified), + 76 (modified), + 77 (modified), + 77 (modified), + 77 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 2 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 2 (modified), + 2 (modified), + 0 (modified), 1, - 1, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 38, - 0, - 1, - 1, - 1, - 38, - 1, - 76, - 77, - 77, - 77, - 1, - 1, - 1, - 0, - 0, - 2, - 0, - 0, - 1, - 1, - 2, - 2, - 0, - 1, - 1, - 1, - 1, + 1 (modified), + 1 (modified), + 1 (modified), ], }, sim_only_slots: StatePart { @@ -1719,6 +1719,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1727,6 +1728,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1739,6 +1741,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1748,6 +1751,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1756,6 +1760,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1768,6 +1773,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1777,6 +1783,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1785,6 +1792,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1794,6 +1802,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1803,6 +1812,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1811,6 +1821,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1819,6 +1830,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1828,6 +1840,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1837,6 +1850,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1845,6 +1859,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1853,6 +1868,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1862,6 +1878,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1870,6 +1887,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1879,6 +1897,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1888,6 +1907,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1896,6 +1916,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1904,6 +1925,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1912,6 +1934,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1920,6 +1943,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1928,6 +1952,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1936,6 +1961,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1944,6 +1970,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1952,6 +1979,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1961,6 +1989,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1970,6 +1999,7 @@ Simulation { index: StatePartIndex(66), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, diff --git a/crates/fayalite/tests/sim/expected/queue_2_true_false.txt b/crates/fayalite/tests/sim/expected/queue_2_true_false.txt index 1f6d8ec..3d16da2 100644 --- a/crates/fayalite/tests/sim/expected/queue_2_true_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_2_true_false.txt @@ -1124,35 +1124,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 0, - 1, - 0, - 0, - 0, - 0, - 1, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 79, + 79 (modified), 0, - 79, + 79 (modified), 39, - 77, + 77 (modified), 0, - 77, + 77 (modified), 38, 2, 0, @@ -1164,58 +1164,58 @@ Simulation { 0, 39, 1, + 39 (modified), + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1, + 1 (modified), + 0 (modified), + 0, + 0, + 0, + 0, + 1, + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 1, + 1 (modified), + 1 (modified), 39, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 1, - 1, - 39, - 0, - 0, - 1, - 1, - 38, - 1, - 76, - 77, - 77, - 77, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 1, - 1, - 0, - 1, - 1, - 2, - 2, - 0, - 0, - 0, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 38 (modified), + 1 (modified), + 76 (modified), + 77 (modified), + 77 (modified), + 77 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 2 (modified), + 2 (modified), + 0 (modified), 0, + 0 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -1750,6 +1750,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1758,6 +1759,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1770,6 +1772,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1779,6 +1782,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x27, last_state: 0x27, }, @@ -1787,6 +1791,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1799,6 +1804,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1808,6 +1814,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1816,6 +1823,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1825,6 +1833,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1834,6 +1843,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1842,6 +1852,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1850,6 +1861,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1859,6 +1871,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x26, last_state: 0x26, }, @@ -1868,6 +1881,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1876,6 +1890,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1884,6 +1899,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1893,6 +1909,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x27, last_state: 0x27, }, @@ -1901,6 +1918,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1910,6 +1928,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1919,6 +1938,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1927,6 +1947,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1935,6 +1956,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1943,6 +1965,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1951,6 +1974,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1959,6 +1983,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1967,6 +1992,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1975,6 +2001,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1983,6 +2010,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1992,6 +2020,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x27, last_state: 0x27, }, @@ -2001,6 +2030,7 @@ Simulation { index: StatePartIndex(68), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/queue_2_true_true.txt b/crates/fayalite/tests/sim/expected/queue_2_true_true.txt index 25b08a1..041e62d 100644 --- a/crates/fayalite/tests/sim/expected/queue_2_true_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_2_true_true.txt @@ -1105,35 +1105,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 1, - 1, - 0, - 0, - 0, - 1, - 0, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 85, + 85 (modified), 0, - 85, + 85 (modified), 42, - 83, + 83 (modified), 0, - 83, + 83 (modified), 41, 2, 1, @@ -1145,56 +1145,56 @@ Simulation { 0, 42, 1, + 42 (modified), + 1 (modified), + 1, + 1 (modified), + 0 (modified), + 1, + 1 (modified), + 1, + 1 (modified), + 0 (modified), + 0, + 0, + 0, + 0, + 1, + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 1, + 1 (modified), + 1 (modified), 42, - 1, - 1, - 1, - 0, - 1, - 1, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 1, - 1, - 42, - 0, - 0, - 1, - 1, - 41, - 1, - 82, - 83, - 83, - 83, - 0, - 1, - 1, - 0, - 0, - 2, - 0, - 1, - 2, - 0, - 2, - 2, - 0, - 0, - 0, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 41 (modified), + 1 (modified), + 82 (modified), + 83 (modified), + 83 (modified), + 83 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 2 (modified), + 0 (modified), + 1 (modified), + 2 (modified), + 0 (modified), + 2 (modified), + 2 (modified), + 0 (modified), 0, + 0 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -1729,6 +1729,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1737,6 +1738,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1749,6 +1751,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1758,6 +1761,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x2a, last_state: 0x2a, }, @@ -1766,6 +1770,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1778,6 +1783,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1787,6 +1793,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1795,6 +1802,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1804,6 +1812,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1813,6 +1822,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1821,6 +1831,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1829,6 +1840,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1838,6 +1850,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1847,6 +1860,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1855,6 +1869,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1863,6 +1878,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1872,6 +1888,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x2a, last_state: 0x2a, }, @@ -1880,6 +1897,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1889,6 +1907,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1898,6 +1917,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<1>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1906,6 +1926,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1914,6 +1935,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1922,6 +1944,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1930,6 +1953,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1938,6 +1962,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1946,6 +1971,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1954,6 +1980,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1962,6 +1989,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1971,6 +1999,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x2a, last_state: 0x2a, }, @@ -1980,6 +2009,7 @@ Simulation { index: StatePartIndex(66), ty: UInt<1>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/queue_3_false_false.txt b/crates/fayalite/tests/sim/expected/queue_3_false_false.txt index 6f65006..f9c68cc 100644 --- a/crates/fayalite/tests/sim/expected/queue_3_false_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_3_false_false.txt @@ -1142,35 +1142,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 0, - 1, - 0, - 0, - 1, - 2, - 1, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 2 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 81, + 81 (modified), 1, - 81, + 81 (modified), 40, - 79, + 79 (modified), 0, - 79, + 79 (modified), 39, 2, 0, @@ -1182,59 +1182,59 @@ Simulation { 0, 40, 1, + 40 (modified), + 1 (modified), + 2, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1, + 1 (modified), + 0 (modified), + 1, + 1, + 0, + 0, + 0, + 0 (modified), + 0, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1 (modified), 40, - 1, - 2, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 40, - 0, - 1, - 1, - 1, - 39, - 1, - 78, - 79, - 79, - 79, - 0, - 0, - 1, - 2, - 1, - 0, - 0, - 3, - 3, - 0, - 1, - 1, - 3, - 3, - 0, - 5, - 5, - 1, - 2, - 2, + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 39 (modified), + 1 (modified), + 78 (modified), + 79 (modified), + 79 (modified), + 79 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 2 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 3 (modified), + 3 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 3 (modified), + 3 (modified), + 0 (modified), + 5 (modified), + 5 (modified), + 1 (modified), + 2 (modified), + 2 (modified), ], }, sim_only_slots: StatePart { @@ -1759,6 +1759,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1767,6 +1768,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1779,6 +1781,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1788,6 +1791,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x28, last_state: 0x28, }, @@ -1796,6 +1800,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1808,6 +1813,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1817,6 +1823,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x27, last_state: 0x27, }, @@ -1825,6 +1832,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1834,6 +1842,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1843,6 +1852,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1851,6 +1861,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1859,6 +1870,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1868,6 +1880,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x27, last_state: 0x27, }, @@ -1877,6 +1890,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1885,6 +1899,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1893,6 +1908,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1902,6 +1918,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x28, last_state: 0x28, }, @@ -1910,6 +1927,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1919,6 +1937,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1928,6 +1947,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1936,6 +1956,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1944,6 +1965,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1952,6 +1974,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1960,6 +1983,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1968,6 +1992,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1976,6 +2001,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1984,6 +2010,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1992,6 +2019,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2001,6 +2029,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x28, last_state: 0x28, }, diff --git a/crates/fayalite/tests/sim/expected/queue_3_false_true.txt b/crates/fayalite/tests/sim/expected/queue_3_false_true.txt index 4cffcd6..9b0a7ea 100644 --- a/crates/fayalite/tests/sim/expected/queue_3_false_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_3_false_true.txt @@ -1123,35 +1123,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 2, - 1, - 0, - 0, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 2 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 85, + 85 (modified), 1, - 85, + 85 (modified), 42, - 83, + 83 (modified), 0, - 83, + 83 (modified), 41, 2, 2, @@ -1163,57 +1163,57 @@ Simulation { 0, 42, 1, + 42 (modified), + 1 (modified), + 1, + 2 (modified), + 0 (modified), + 2, + 2 (modified), + 1, + 1 (modified), + 0 (modified), + 1, + 1, + 0, + 0, + 0, + 0 (modified), + 0, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1 (modified), 42, - 1, - 1, - 2, - 0, - 2, - 2, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 42, - 0, - 1, - 1, - 1, - 41, - 1, - 82, - 83, - 83, - 83, - 1, - 2, - 0, - 0, - 0, - 2, - 2, - 1, - 3, - 3, - 3, - 3, - 1, - 4, - 2, - 2, - 7, - 3, + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 41 (modified), + 1 (modified), + 82 (modified), + 83 (modified), + 83 (modified), + 83 (modified), + 1 (modified), + 2 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 2 (modified), + 2 (modified), + 1 (modified), + 3 (modified), + 3 (modified), + 3 (modified), + 3 (modified), + 1 (modified), + 4 (modified), + 2 (modified), + 2 (modified), + 7 (modified), + 3 (modified), ], }, sim_only_slots: StatePart { @@ -1738,6 +1738,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1746,6 +1747,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1758,6 +1760,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1767,6 +1770,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x2a, last_state: 0x2a, }, @@ -1775,6 +1779,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1787,6 +1792,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1796,6 +1802,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1804,6 +1811,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1813,6 +1821,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1822,6 +1831,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1830,6 +1840,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1838,6 +1849,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1847,6 +1859,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1856,6 +1869,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1864,6 +1878,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1872,6 +1887,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1881,6 +1897,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x2a, last_state: 0x2a, }, @@ -1889,6 +1906,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1898,6 +1916,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1907,6 +1926,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1915,6 +1935,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1923,6 +1944,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1931,6 +1953,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1939,6 +1962,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1947,6 +1971,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1955,6 +1980,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1963,6 +1989,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1971,6 +1998,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1980,6 +2008,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x2a, last_state: 0x2a, }, diff --git a/crates/fayalite/tests/sim/expected/queue_3_true_false.txt b/crates/fayalite/tests/sim/expected/queue_3_true_false.txt index 03d3aba..1b486d6 100644 --- a/crates/fayalite/tests/sim/expected/queue_3_true_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_3_true_false.txt @@ -1152,35 +1152,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 2, - 1, - 0, - 0, - 0, - 2, - 1, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 2 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 2 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 87, + 87 (modified), 0, - 87, + 87 (modified), 43, - 83, + 83 (modified), 0, - 83, + 83 (modified), 41, 3, 2, @@ -1192,59 +1192,59 @@ Simulation { 0, 43, 1, + 43 (modified), + 1 (modified), + 2, + 2 (modified), + 0 (modified), + 2, + 2 (modified), + 1, + 1 (modified), + 0 (modified), + 0, + 0, + 0, + 0, + 1, + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 1, + 1 (modified), + 1 (modified), 43, - 1, - 2, - 2, - 0, - 2, - 2, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 1, - 1, - 43, - 0, - 0, - 1, - 1, - 41, - 1, - 82, - 83, - 83, - 83, - 0, - 0, - 0, - 2, - 1, - 0, - 0, - 3, - 3, - 1, - 3, - 3, - 3, - 3, - 0, - 5, - 3, - 3, - 0, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 41 (modified), + 1 (modified), + 82 (modified), + 83 (modified), + 83 (modified), + 83 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 2 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 3 (modified), + 3 (modified), + 1 (modified), + 3 (modified), + 3 (modified), + 3 (modified), + 3 (modified), + 0 (modified), + 5 (modified), + 3 (modified), + 3 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -1769,6 +1769,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1777,6 +1778,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1789,6 +1791,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1798,6 +1801,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1806,6 +1810,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1818,6 +1823,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1827,6 +1833,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1835,6 +1842,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1844,6 +1852,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, + maybe_changed: true, state: 0x3, last_state: 0x3, }, @@ -1853,6 +1862,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1861,6 +1871,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1869,6 +1880,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1878,6 +1890,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1887,6 +1900,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1895,6 +1909,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1903,6 +1918,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1912,6 +1928,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1920,6 +1937,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1929,6 +1947,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1938,6 +1957,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1946,6 +1966,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1954,6 +1975,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1962,6 +1984,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1970,6 +1993,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1978,6 +2002,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1986,6 +2011,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1994,6 +2020,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -2002,6 +2029,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2011,6 +2039,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, diff --git a/crates/fayalite/tests/sim/expected/queue_3_true_true.txt b/crates/fayalite/tests/sim/expected/queue_3_true_true.txt index a663e23..730e7e5 100644 --- a/crates/fayalite/tests/sim/expected/queue_3_true_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_3_true_true.txt @@ -1133,35 +1133,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 2, - 1, - 0, - 0, - 0, - 2, - 1, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 2 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 2 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 87, + 87 (modified), 0, - 87, + 87 (modified), 43, - 83, + 83 (modified), 0, - 83, + 83 (modified), 41, 3, 2, @@ -1173,57 +1173,57 @@ Simulation { 0, 43, 1, + 43 (modified), + 1 (modified), + 2, + 2 (modified), + 0 (modified), + 2, + 2 (modified), + 1, + 1 (modified), + 0 (modified), + 0, + 0, + 0, + 0, + 1, + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 1, + 1 (modified), + 1 (modified), 43, - 1, - 2, - 2, - 0, - 2, - 2, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 1, - 1, - 43, - 0, - 0, - 1, - 1, - 41, - 1, - 82, - 83, - 83, - 83, - 0, - 2, - 1, - 0, - 0, - 3, - 3, - 1, - 3, - 3, - 3, - 3, - 0, - 5, - 3, - 3, - 0, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 41 (modified), + 1 (modified), + 82 (modified), + 83 (modified), + 83 (modified), + 83 (modified), + 0 (modified), + 2 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 3 (modified), + 3 (modified), + 1 (modified), + 3 (modified), + 3 (modified), + 3 (modified), + 3 (modified), + 0 (modified), + 5 (modified), + 3 (modified), + 3 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -1748,6 +1748,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1756,6 +1757,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1768,6 +1770,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1777,6 +1780,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1785,6 +1789,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1797,6 +1802,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1806,6 +1812,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1814,6 +1821,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1823,6 +1831,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<2>, }, + maybe_changed: true, state: 0x3, last_state: 0x3, }, @@ -1832,6 +1841,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1840,6 +1850,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1848,6 +1859,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1857,6 +1869,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1866,6 +1879,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1874,6 +1888,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1882,6 +1897,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1891,6 +1907,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1899,6 +1916,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1908,6 +1926,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1917,6 +1936,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, + maybe_changed: true, state: 0x2, last_state: 0x2, }, @@ -1925,6 +1945,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1933,6 +1954,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1941,6 +1963,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1949,6 +1972,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1957,6 +1981,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1965,6 +1990,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1973,6 +1999,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1981,6 +2008,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1990,6 +2018,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, diff --git a/crates/fayalite/tests/sim/expected/queue_4_false_false.txt b/crates/fayalite/tests/sim/expected/queue_4_false_false.txt index 445d9d0..e549ced 100644 --- a/crates/fayalite/tests/sim/expected/queue_4_false_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_4_false_false.txt @@ -1122,35 +1122,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 1, - 1, - 0, - 0, - 1, - 0, - 3, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 3 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 87, + 87 (modified), 1, - 87, + 87 (modified), 43, - 83, + 83 (modified), 0, - 83, + 83 (modified), 41, 3, 1, @@ -1162,58 +1162,58 @@ Simulation { 0, 43, 1, + 43 (modified), + 1 (modified), + 0, + 1 (modified), + 0 (modified), + 1, + 1 (modified), + 1, + 1 (modified), + 0 (modified), + 1, + 1, + 0, + 0, + 0, + 0 (modified), + 0, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1 (modified), 43, - 1, - 0, - 1, - 0, - 1, - 1, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 43, - 0, - 1, - 1, - 1, - 41, - 1, - 82, - 83, - 83, - 83, - 0, - 0, - 1, - 3, - 0, - 0, - 0, - 1, - 1, - 0, - 2, - 2, - 4, - 4, - 0, - 3, - 7, - 3, + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 41 (modified), + 1 (modified), + 82 (modified), + 83 (modified), + 83 (modified), + 83 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 3 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 2 (modified), + 2 (modified), + 4 (modified), + 4 (modified), + 0 (modified), 3, + 7 (modified), + 3 (modified), + 3 (modified), ], }, sim_only_slots: StatePart { @@ -1748,6 +1748,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1756,6 +1757,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1768,6 +1770,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1777,6 +1780,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1785,6 +1789,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1797,6 +1802,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1806,6 +1812,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1814,6 +1821,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1823,6 +1831,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<3>, }, + maybe_changed: true, state: 0x3, last_state: 0x3, }, @@ -1832,6 +1841,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1840,6 +1850,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1848,6 +1859,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1857,6 +1869,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1866,6 +1879,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1874,6 +1888,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1882,6 +1897,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1891,6 +1907,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1899,6 +1916,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1908,6 +1926,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1917,6 +1936,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1925,6 +1945,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1933,6 +1954,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1941,6 +1963,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1949,6 +1972,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1957,6 +1981,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1965,6 +1990,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1973,6 +1999,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1981,6 +2008,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1990,6 +2018,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1999,6 +2028,7 @@ Simulation { index: StatePartIndex(68), ty: UInt<2>, }, + maybe_changed: true, state: 0x3, last_state: 0x3, }, diff --git a/crates/fayalite/tests/sim/expected/queue_4_false_true.txt b/crates/fayalite/tests/sim/expected/queue_4_false_true.txt index 5e7ada2..9f1d05b 100644 --- a/crates/fayalite/tests/sim/expected/queue_4_false_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_4_false_true.txt @@ -1103,35 +1103,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 1, - 1, - 0, - 0, - 1, - 0, - 3, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 3 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 87, + 87 (modified), 1, - 87, + 87 (modified), 43, - 83, + 83 (modified), 0, - 83, + 83 (modified), 41, 3, 1, @@ -1143,56 +1143,56 @@ Simulation { 0, 43, 1, + 43 (modified), + 1 (modified), + 0, + 1 (modified), + 0 (modified), + 1, + 1 (modified), + 1, + 1 (modified), + 0 (modified), + 1, + 1, + 0, + 0, + 0, + 0 (modified), + 0, + 0 (modified), + 0 (modified), + 0, + 0 (modified), + 1 (modified), 43, - 1, - 0, - 1, - 0, - 1, - 1, - 1, - 1, - 0, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 43, - 0, - 1, - 1, - 1, - 41, - 1, - 82, - 83, - 83, - 83, - 1, - 3, - 0, - 0, - 0, - 1, - 1, - 0, - 2, - 2, - 4, - 4, - 0, - 3, - 7, - 3, + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 41 (modified), + 1 (modified), + 82 (modified), + 83 (modified), + 83 (modified), + 83 (modified), + 1 (modified), + 3 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 2 (modified), + 2 (modified), + 4 (modified), + 4 (modified), + 0 (modified), 3, + 7 (modified), + 3 (modified), + 3 (modified), ], }, sim_only_slots: StatePart { @@ -1727,6 +1727,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1735,6 +1736,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1747,6 +1749,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1756,6 +1759,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1764,6 +1768,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1776,6 +1781,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1785,6 +1791,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1793,6 +1800,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1802,6 +1810,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<3>, }, + maybe_changed: true, state: 0x3, last_state: 0x3, }, @@ -1811,6 +1820,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1819,6 +1829,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1827,6 +1838,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1836,6 +1848,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1845,6 +1858,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1853,6 +1867,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1861,6 +1876,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1870,6 +1886,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1878,6 +1895,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1887,6 +1905,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1896,6 +1915,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1904,6 +1924,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1912,6 +1933,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1920,6 +1942,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1928,6 +1951,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1936,6 +1960,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1944,6 +1969,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1952,6 +1978,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1960,6 +1987,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1969,6 +1997,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x2b, last_state: 0x2b, }, @@ -1978,6 +2007,7 @@ Simulation { index: StatePartIndex(66), ty: UInt<2>, }, + maybe_changed: true, state: 0x3, last_state: 0x3, }, diff --git a/crates/fayalite/tests/sim/expected/queue_4_true_false.txt b/crates/fayalite/tests/sim/expected/queue_4_true_false.txt index 2701c1d..b37a9cd 100644 --- a/crates/fayalite/tests/sim/expected/queue_4_true_false.txt +++ b/crates/fayalite/tests/sim/expected/queue_4_true_false.txt @@ -1132,35 +1132,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 1, - 1, - 0, - 0, - 0, - 1, - 0, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 89, + 89 (modified), 0, - 89, + 89 (modified), 44, - 83, + 83 (modified), 0, - 83, + 83 (modified), 41, 4, 1, @@ -1172,58 +1172,58 @@ Simulation { 0, 44, 1, + 44 (modified), + 1 (modified), + 1, + 1 (modified), + 0 (modified), + 1, + 1 (modified), + 1, + 1 (modified), + 0 (modified), + 0, + 0, + 0, + 0, + 1, + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 1, + 1 (modified), + 1 (modified), 44, - 1, - 1, - 1, - 0, - 1, - 1, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 1, - 1, - 44, - 0, - 0, - 1, - 1, - 41, - 1, - 82, - 83, - 83, - 83, - 0, - 0, - 0, - 3, - 0, - 0, - 0, - 2, - 2, - 0, - 2, - 2, - 4, - 4, - 0, - 0, - 0, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 41 (modified), + 1 (modified), + 82 (modified), + 83 (modified), + 83 (modified), + 83 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 3 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 2 (modified), + 2 (modified), + 0 (modified), + 2 (modified), + 2 (modified), + 4 (modified), + 4 (modified), + 0 (modified), 0, + 0 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -1758,6 +1758,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1766,6 +1767,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1778,6 +1780,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1787,6 +1790,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -1795,6 +1799,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1807,6 +1812,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1816,6 +1822,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1824,6 +1831,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1833,6 +1841,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<3>, }, + maybe_changed: true, state: 0x4, last_state: 0x4, }, @@ -1842,6 +1851,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1850,6 +1860,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1858,6 +1869,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1867,6 +1879,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1876,6 +1889,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1884,6 +1898,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1892,6 +1907,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1901,6 +1917,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -1909,6 +1926,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1918,6 +1936,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1927,6 +1946,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1935,6 +1955,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1943,6 +1964,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1951,6 +1973,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1959,6 +1982,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1967,6 +1991,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1975,6 +2000,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1983,6 +2009,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1991,6 +2018,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -2000,6 +2028,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -2009,6 +2038,7 @@ Simulation { index: StatePartIndex(68), ty: UInt<2>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/queue_4_true_true.txt b/crates/fayalite/tests/sim/expected/queue_4_true_true.txt index a52069d..051b203 100644 --- a/crates/fayalite/tests/sim/expected/queue_4_true_true.txt +++ b/crates/fayalite/tests/sim/expected/queue_4_true_true.txt @@ -1113,35 +1113,35 @@ Simulation { value: [ 1, 1, - 1, - 0, - 0, - 1, - 1, - 1, - 0, - 0, - 0, - 1, - 0, - 1, - 1, - 0, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ 0, 0, - 89, + 89 (modified), 0, - 89, + 89 (modified), 44, - 83, + 83 (modified), 0, - 83, + 83 (modified), 41, 4, 1, @@ -1153,56 +1153,56 @@ Simulation { 0, 44, 1, + 44 (modified), + 1 (modified), + 1, + 1 (modified), + 0 (modified), + 1, + 1 (modified), + 1, + 1 (modified), + 0 (modified), + 0, + 0, + 0, + 0, + 1, + 1 (modified), + 0, + 0 (modified), + 0 (modified), + 1, + 1 (modified), + 1 (modified), 44, - 1, - 1, - 1, - 0, - 1, - 1, - 1, - 1, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 1, - 1, - 44, - 0, - 0, - 1, - 1, - 41, - 1, - 82, - 83, - 83, - 83, - 0, - 3, - 0, - 0, - 0, - 2, - 2, - 0, - 2, - 2, - 4, - 4, - 0, - 0, - 0, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 41 (modified), + 1 (modified), + 82 (modified), + 83 (modified), + 83 (modified), + 83 (modified), + 0 (modified), + 3 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 2 (modified), + 2 (modified), + 0 (modified), + 2 (modified), + 2 (modified), + 4 (modified), + 4 (modified), + 0 (modified), 0, + 0 (modified), + 0 (modified), + 0 (modified), ], }, sim_only_slots: StatePart { @@ -1737,6 +1737,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1745,6 +1746,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1757,6 +1759,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1766,6 +1769,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -1774,6 +1778,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1786,6 +1791,7 @@ Simulation { HdlSome(UInt<8>), }, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1795,6 +1801,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1803,6 +1810,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1812,6 +1820,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<3>, }, + maybe_changed: true, state: 0x4, last_state: 0x4, }, @@ -1821,6 +1830,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1829,6 +1839,7 @@ Simulation { kind: BigBool { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1837,6 +1848,7 @@ Simulation { kind: BigClock { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1846,6 +1858,7 @@ Simulation { index: StatePartIndex(14), ty: UInt<8>, }, + maybe_changed: true, state: 0x29, last_state: 0x29, }, @@ -1855,6 +1868,7 @@ Simulation { index: StatePartIndex(15), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1863,6 +1877,7 @@ Simulation { kind: BigBool { index: StatePartIndex(16), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1871,6 +1886,7 @@ Simulation { kind: BigClock { index: StatePartIndex(17), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -1880,6 +1896,7 @@ Simulation { index: StatePartIndex(18), ty: UInt<8>, }, + maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -1888,6 +1905,7 @@ Simulation { kind: BigBool { index: StatePartIndex(19), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1897,6 +1915,7 @@ Simulation { index: StatePartIndex(22), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1906,6 +1925,7 @@ Simulation { index: StatePartIndex(25), ty: UInt<2>, }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1914,6 +1934,7 @@ Simulation { kind: BigBool { index: StatePartIndex(27), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1922,6 +1943,7 @@ Simulation { kind: BigBool { index: StatePartIndex(30), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1930,6 +1952,7 @@ Simulation { kind: BigBool { index: StatePartIndex(31), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1938,6 +1961,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1946,6 +1970,7 @@ Simulation { kind: BigBool { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1954,6 +1979,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1962,6 +1988,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1970,6 +1997,7 @@ Simulation { kind: BigBool { index: StatePartIndex(39), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1979,6 +2007,7 @@ Simulation { index: StatePartIndex(42), ty: UInt<8>, }, + maybe_changed: true, state: 0x2c, last_state: 0x2c, }, @@ -1988,6 +2017,7 @@ Simulation { index: StatePartIndex(66), ty: UInt<2>, }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt index 1fb5fee..91bbffd 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.txt +++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt @@ -641,15 +641,15 @@ Simulation { }, small_slots: StatePart { value: [ - 0, - 0, - 1, - 1, - 0, - 0, - 1, - 0, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { @@ -662,56 +662,56 @@ Simulation { 0, 0, 0, + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 0, + 1 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), 0, 0, + 0 (modified), + 0, + 0 (modified), + 0, + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), 0, 0, + 0 (modified), + 0, + 0 (modified), + 0, + 1 (modified), + 0 (modified), + 0 (modified), + 0 (modified), + 1 (modified), 0, 0, + 0 (modified), 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 1, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 0, + 0 (modified), ], }, sim_only_slots: StatePart { @@ -1284,6 +1284,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -1293,6 +1294,7 @@ Simulation { index: StatePartIndex(1), ty: UInt<6>, }, + maybe_changed: false, state: 0x00, last_state: 0x00, }, @@ -1301,6 +1303,7 @@ Simulation { kind: BigBool { index: StatePartIndex(2), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1309,6 +1312,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1317,6 +1321,7 @@ Simulation { kind: BigBool { index: StatePartIndex(4), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1325,6 +1330,7 @@ Simulation { kind: BigBool { index: StatePartIndex(5), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1333,6 +1339,7 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1341,6 +1348,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1349,6 +1357,7 @@ Simulation { kind: BigBool { index: StatePartIndex(24), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1357,6 +1366,7 @@ Simulation { kind: BigClock { index: StatePartIndex(33), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1365,6 +1375,7 @@ Simulation { kind: BigBool { index: StatePartIndex(34), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1373,6 +1384,7 @@ Simulation { kind: BigClock { index: StatePartIndex(31), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1381,6 +1393,7 @@ Simulation { kind: BigBool { index: StatePartIndex(32), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1389,6 +1402,7 @@ Simulation { kind: BigBool { index: StatePartIndex(36), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1397,6 +1411,7 @@ Simulation { kind: BigClock { index: StatePartIndex(44), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1405,6 +1420,7 @@ Simulation { kind: BigBool { index: StatePartIndex(45), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1413,6 +1429,7 @@ Simulation { kind: BigClock { index: StatePartIndex(42), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1421,6 +1438,7 @@ Simulation { kind: BigBool { index: StatePartIndex(43), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1429,6 +1447,7 @@ Simulation { kind: BigBool { index: StatePartIndex(47), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1437,6 +1456,7 @@ Simulation { kind: BigClock { index: StatePartIndex(55), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1445,6 +1465,7 @@ Simulation { kind: BigBool { index: StatePartIndex(56), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1453,6 +1474,7 @@ Simulation { kind: BigClock { index: StatePartIndex(53), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -1461,6 +1483,7 @@ Simulation { kind: BigBool { index: StatePartIndex(54), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt index 2e1b176..cc9d95a 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -259,10 +259,10 @@ Simulation { }, small_slots: StatePart { value: [ - 0, - 0, - 1, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), ], }, big_slots: StatePart { @@ -272,14 +272,14 @@ Simulation { 0, 0, 0, + 0 (modified), + 0 (modified), 0, + 0 (modified), 0, + 0 (modified), 0, - 0, - 0, - 0, - 0, - 0, + 0 (modified), ], }, sim_only_slots: StatePart { @@ -458,6 +458,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x0, }, @@ -466,6 +467,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -474,6 +476,7 @@ Simulation { kind: BigBool { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -482,6 +485,7 @@ Simulation { kind: BigBool { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -490,6 +494,7 @@ Simulation { kind: BigBool { index: StatePartIndex(4), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -498,6 +503,7 @@ Simulation { kind: BigBool { index: StatePartIndex(7), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -506,6 +512,7 @@ Simulation { kind: BigBool { index: StatePartIndex(9), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -514,6 +521,7 @@ Simulation { kind: BigBool { index: StatePartIndex(11), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.txt b/crates/fayalite/tests/sim/expected/sim_fork_join.txt index df9c092..c66e77e 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join.txt +++ b/crates/fayalite/tests/sim/expected/sim_fork_join.txt @@ -68,12 +68,12 @@ Simulation { }, big_slots: StatePart { value: [ + 0 (modified), 0, 0, - 0, - 49, - 50, - 50, + 49 (modified), + 50 (modified), + 50 (modified), ], }, sim_only_slots: StatePart { @@ -356,6 +356,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -364,6 +365,7 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -372,6 +374,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -381,6 +384,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -390,6 +394,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -399,6 +404,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt index 917dd5d..ae88960 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt +++ b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt @@ -68,12 +68,12 @@ Simulation { }, big_slots: StatePart { value: [ + 0 (modified), 0, 0, - 0, - 49, - 50, - 50, + 49 (modified), + 50 (modified), + 50 (modified), ], }, sim_only_slots: StatePart { @@ -356,6 +356,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -364,6 +365,7 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -372,6 +374,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -381,6 +384,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -390,6 +394,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -399,6 +404,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.txt b/crates/fayalite/tests/sim/expected/sim_only_connects.txt index 827f3cc..3b90ca8 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.txt +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.txt @@ -380,10 +380,10 @@ Simulation { }, small_slots: StatePart { value: [ - 0, - 0, - 1, - 0, + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), ], }, big_slots: StatePart { @@ -392,15 +392,15 @@ Simulation { 0, 1, 0, + 1 (modified), + 0, + 0, + 0 (modified), + 1 (modified), + 0 (modified), 1, 0, - 0, - 0, - 1, - 0, - 1, - 0, - 1, + 1 (modified), 0, ], }, @@ -443,8 +443,8 @@ Simulation { }, { "extra": "value", - }, - {}, + } (modified), + {} (modified), { "bar": "", "extra": "value", @@ -1252,6 +1252,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1260,6 +1261,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1269,6 +1271,7 @@ Simulation { index: StatePartIndex(0), ty: SimOnly>>, }, + maybe_changed: true, state: { "extra": "value", }, @@ -1282,6 +1285,7 @@ Simulation { index: StatePartIndex(1), ty: SimOnly>>, }, + maybe_changed: true, state: { "extra": "value", }, @@ -1295,6 +1299,7 @@ Simulation { index: StatePartIndex(2), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1312,6 +1317,7 @@ Simulation { index: StatePartIndex(3), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "baz", "extra": "value", @@ -1328,6 +1334,7 @@ Simulation { kind: BigClock { index: StatePartIndex(4), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1336,6 +1343,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(5), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1345,6 +1353,7 @@ Simulation { index: StatePartIndex(6), ty: SimOnly>>, }, + maybe_changed: true, state: { "extra": "value", }, @@ -1358,6 +1367,7 @@ Simulation { index: StatePartIndex(7), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1374,6 +1384,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1382,6 +1393,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(3), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1391,6 +1403,7 @@ Simulation { index: StatePartIndex(4), ty: SimOnly>>, }, + maybe_changed: true, state: { "extra": "value", }, @@ -1404,6 +1417,7 @@ Simulation { index: StatePartIndex(5), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1421,6 +1435,7 @@ Simulation { index: StatePartIndex(8), ty: SimOnly>>, }, + maybe_changed: true, state: { "extra": "value", }, @@ -1433,6 +1448,7 @@ Simulation { kind: BigBool { index: StatePartIndex(6), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1441,6 +1457,7 @@ Simulation { kind: BigClock { index: StatePartIndex(12), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1449,6 +1466,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(13), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1458,6 +1476,7 @@ Simulation { index: StatePartIndex(13), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1475,6 +1494,7 @@ Simulation { index: StatePartIndex(14), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "baz", "extra": "value", @@ -1491,6 +1511,7 @@ Simulation { kind: BigClock { index: StatePartIndex(10), }, + maybe_changed: true, state: 0x1, last_state: 0x1, }, @@ -1499,6 +1520,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(11), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -1508,6 +1530,7 @@ Simulation { index: StatePartIndex(11), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "", "extra": "value", @@ -1525,6 +1548,7 @@ Simulation { index: StatePartIndex(12), ty: SimOnly>>, }, + maybe_changed: true, state: { "bar": "baz", "extra": "value", diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.txt b/crates/fayalite/tests/sim/expected/sim_read_past.txt index 6df4571..17156d0 100644 --- a/crates/fayalite/tests/sim/expected/sim_read_past.txt +++ b/crates/fayalite/tests/sim/expected/sim_read_past.txt @@ -517,67 +517,67 @@ Simulation { }, small_slots: StatePart { value: [ - 1, - 0, - 0, - 1, - 0, - 0, - 1, - 0, - 0, + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 0 (modified), ], }, big_slots: StatePart { value: [ + 0 (modified), 0, 0, - 0, - 49, - 50, - 50, - 0, - 1, - 0, - 49, - 49, - 50, - 1, - 0, - 0, - 48, - 49, - 49, - 0, - 0, - 1, - 48, - 49, - 48, - 0, - 1, - 0, - 49, - 49, - 50, - 0, - 0, - 1, - 49, - 49, - 49, - 0, - 0, - 1, - 49, - 50, - 50, - 0, - 1, - 0, - 49, - 49, - 50, + 49 (modified), + 50 (modified), + 50 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 49 (modified), + 49 (modified), + 50 (modified), + 1 (modified), + 0 (modified), + 0 (modified), + 48 (modified), + 49 (modified), + 49 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 48 (modified), + 49 (modified), + 48 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 49 (modified), + 49 (modified), + 50 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 49 (modified), + 49 (modified), + 49 (modified), + 0 (modified), + 0 (modified), + 1 (modified), + 49 (modified), + 50 (modified), + 50 (modified), + 0 (modified), + 1 (modified), + 0 (modified), + 49 (modified), + 49 (modified), + 50 (modified), ], }, sim_only_slots: StatePart { @@ -9500,6 +9500,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -9508,6 +9509,7 @@ Simulation { kind: BigClock { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -9516,6 +9518,7 @@ Simulation { kind: BigClock { index: StatePartIndex(2), }, + maybe_changed: true, state: 0x0, last_state: 0x1, }, @@ -9525,6 +9528,7 @@ Simulation { index: StatePartIndex(3), ty: UInt<8>, }, + maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -9534,6 +9538,7 @@ Simulation { index: StatePartIndex(4), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -9543,6 +9548,7 @@ Simulation { index: StatePartIndex(5), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, @@ -9551,6 +9557,7 @@ Simulation { kind: BigClock { index: StatePartIndex(6), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -9559,6 +9566,7 @@ Simulation { kind: BigClock { index: StatePartIndex(7), }, + maybe_changed: false, state: 0x1, last_state: 0x1, }, @@ -9567,6 +9575,7 @@ Simulation { kind: BigClock { index: StatePartIndex(8), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -9576,6 +9585,7 @@ Simulation { index: StatePartIndex(9), ty: UInt<8>, }, + maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -9585,6 +9595,7 @@ Simulation { index: StatePartIndex(10), ty: UInt<8>, }, + maybe_changed: false, state: 0x31, last_state: 0x31, }, @@ -9594,6 +9605,7 @@ Simulation { index: StatePartIndex(11), ty: UInt<8>, }, + maybe_changed: false, state: 0x32, last_state: 0x32, }, diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt index 3fea928..5584b73 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt @@ -56,8 +56,8 @@ Simulation { }, big_slots: StatePart { value: [ - 0, - 0, + 0 (modified), + 0 (modified), 3, ], }, @@ -310,6 +310,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -318,6 +319,7 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -327,6 +329,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: false, state: 0x03, last_state: 0x03, }, diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt index 2283ce5..f03c25a 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt @@ -56,8 +56,8 @@ Simulation { }, big_slots: StatePart { value: [ - 0, - 0, + 0 (modified), + 0 (modified), 3, ], }, @@ -310,6 +310,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -318,6 +319,7 @@ Simulation { kind: BigAsyncReset { index: StatePartIndex(1), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -327,6 +329,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: false, state: 0x03, last_state: 0x03, }, diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt index c77046f..c93d6c1 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt @@ -56,7 +56,7 @@ Simulation { }, big_slots: StatePart { value: [ - 0, + 0 (modified), 0, 3, ], @@ -310,6 +310,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -318,6 +319,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -327,6 +329,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: false, state: 0x03, last_state: 0x03, }, diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt index e1c565a..f13af84 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt @@ -56,7 +56,7 @@ Simulation { }, big_slots: StatePart { value: [ - 0, + 0 (modified), 0, 3, ], @@ -310,6 +310,7 @@ Simulation { kind: BigClock { index: StatePartIndex(0), }, + maybe_changed: true, state: 0x0, last_state: 0x0, }, @@ -318,6 +319,7 @@ Simulation { kind: BigSyncReset { index: StatePartIndex(1), }, + maybe_changed: false, state: 0x0, last_state: 0x0, }, @@ -327,6 +329,7 @@ Simulation { index: StatePartIndex(2), ty: UInt<8>, }, + maybe_changed: false, state: 0x03, last_state: 0x03, }, From 8e4eeef72340f1205ed5d2277dab112cdf352b35 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 30 Apr 2026 23:10:49 -0700 Subject: [PATCH 07/10] add support for custom debug/display formatting of #[hdl] structs/enums also cleans up default debug formatting to use the struct/enum name (or MaskType) instead of the implementation detail type name. --- crates/fayalite-proc-macros-impl/src/fold.rs | 1 + .../src/hdl_bundle.rs | 128 ++++++++++--- .../fayalite-proc-macros-impl/src/hdl_enum.rs | 122 ++++++++++++- .../src/hdl_type_alias.rs | 28 ++- .../src/hdl_type_common.rs | 168 +++++++++++++++++- crates/fayalite-proc-macros-impl/src/lib.rs | 5 + crates/fayalite/src/array.rs | 17 +- crates/fayalite/src/bundle.rs | 30 +++- crates/fayalite/src/clock.rs | 14 +- crates/fayalite/src/enum_.rs | 13 +- crates/fayalite/src/int.rs | 31 +++- crates/fayalite/src/int/uint_in_range.rs | 20 ++- crates/fayalite/src/phantom_const.rs | 11 +- crates/fayalite/src/reset.rs | 14 +- crates/fayalite/src/sim/value.rs | 21 ++- crates/fayalite/src/ty.rs | 29 ++- crates/fayalite/tests/hdl_types_fmt.rs | 166 +++++++++++++++++ .../ui/simvalue_is_not_internable.stderr | 18 +- 18 files changed, 773 insertions(+), 63 deletions(-) create mode 100644 crates/fayalite/tests/hdl_types_fmt.rs diff --git a/crates/fayalite-proc-macros-impl/src/fold.rs b/crates/fayalite-proc-macros-impl/src/fold.rs index 22e7b82..50423b5 100644 --- a/crates/fayalite-proc-macros-impl/src/fold.rs +++ b/crates/fayalite-proc-macros-impl/src/fold.rs @@ -257,5 +257,6 @@ no_op_fold!(syn::Token![let]); no_op_fold!(syn::Token![mut]); no_op_fold!(syn::Token![static]); no_op_fold!(syn::Token![struct]); +no_op_fold!(syn::Token![type]); no_op_fold!(syn::Token![where]); no_op_fold!(usize); diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs index 97fa3ff..6847af9 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs @@ -3,8 +3,9 @@ use crate::{ Errors, HdlAttr, PairsIterExt, hdl_type_common::{ - ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedField, ParsedFieldsNamed, ParsedGenerics, - SplitForImpl, TypesParser, WrappedInConst, common_derives, get_target, + CustomDebugOptions, CustomDebugTrait, ItemOptions, MakeHdlTypeExpr, MaybeParsed, + ParsedField, ParsedFieldsNamed, ParsedGenerics, SplitForImpl, TypesParser, WrappedInConst, + common_derives, create_struct_debug_impl, get_target, }, kw, }; @@ -30,6 +31,7 @@ pub(crate) struct ParsedBundle { pub(crate) fields: MaybeParsed, pub(crate) field_flips: Vec>>, pub(crate) mask_type_ident: Ident, + pub(crate) mask_type_name: String, pub(crate) mask_type_match_variant_ident: Ident, pub(crate) mask_type_sim_value_ident: Ident, pub(crate) match_variant_ident: Ident, @@ -88,6 +90,8 @@ impl ParsedBundle { no_runtime_generics: _, cmp_eq: _, ref get, + custom_debug: _, + custom_sim_display: _, } = options.body; if let Some((get, ..)) = get { errors.error(get, "#[hdl(get(...))] is not allowed on structs"); @@ -131,6 +135,7 @@ impl ParsedBundle { fields, field_flips, mask_type_ident: format_ident!("__{}__MaskType", ident), + mask_type_name: format!("MaskType<{}>", ident), mask_type_match_variant_ident: format_ident!("__{}__MaskType__MatchVariant", ident), mask_type_sim_value_ident: format_ident!("__{}__MaskType__SimValue", ident), match_variant_ident: format_ident!("__{}__MatchVariant", ident), @@ -448,6 +453,7 @@ impl ToTokens for ParsedBundle { fields, field_flips, mask_type_ident, + mask_type_name, mask_type_match_variant_ident, mask_type_sim_value_ident, match_variant_ident, @@ -464,11 +470,20 @@ impl ToTokens for ParsedBundle { no_runtime_generics, cmp_eq, get: _, + custom_debug: _, + custom_sim_display, } = &options.body; + let CustomDebugOptions { + type_: custom_debug_type, + sim: custom_debug_sim, + mask_type: custom_debug_mask_type, + mask_sim: custom_debug_mask_sim, + } = options.body.custom_debug(); let target = get_target(target, ident); + let struct_name = ident.to_string(); let mut item_attrs = attrs.clone(); - item_attrs.push(common_derives(span)); - ItemStruct { + item_attrs.push(common_derives(span, false)); + let type_struct = ItemStruct { attrs: item_attrs, vis: vis.clone(), struct_token: *struct_token, @@ -476,8 +491,8 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(fields.clone().into()), semi_token: None, - } - .to_tokens(tokens); + }; + type_struct.to_tokens(tokens); let (impl_generics, type_generics, where_clause) = generics.split_for_impl(); if let (MaybeParsed::Parsed(generics), MaybeParsed::Parsed(fields), None) = (generics, fields, no_runtime_generics) @@ -503,6 +518,9 @@ impl ToTokens for ParsedBundle { } let mut wrapped_in_const = WrappedInConst::new(tokens, span); let tokens = wrapped_in_const.inner(); + if custom_debug_type.is_none() { + create_struct_debug_impl(&type_struct, &struct_name, None).to_tokens(tokens); + } let builder = Builder { vis: vis.clone(), struct_token: *struct_token, @@ -530,9 +548,9 @@ impl ToTokens for ParsedBundle { mask_type_builder.to_tokens(tokens); let unfilled_mask_type_builder_ty = mask_type_builder.builder_struct_ty(|_| BuilderFieldState::Unfilled); - ItemStruct { + let mask_type_struct = ItemStruct { attrs: vec![ - common_derives(span), + common_derives(span, false), parse_quote_spanned! {span=> #[allow(non_camel_case_types, dead_code)] }, @@ -543,17 +561,20 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(mask_type_fields.clone()), semi_token: None, + }; + mask_type_struct.to_tokens(tokens); + if custom_debug_mask_type.is_none() { + create_struct_debug_impl(&mask_type_struct, mask_type_name, None).to_tokens(tokens); } - .to_tokens(tokens); let mut mask_type_match_variant_fields = mask_type_fields.clone(); for Field { ty, .. } in &mut mask_type_match_variant_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::expr::Expr<#ty> }; } - ItemStruct { + let mask_type_match_variant_struct = ItemStruct { attrs: vec![ - common_derives(span), + common_derives(span, false), parse_quote_spanned! {span=> #[allow(non_camel_case_types, dead_code)] }, @@ -564,17 +585,19 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(mask_type_match_variant_fields), semi_token: None, - } - .to_tokens(tokens); + }; + mask_type_match_variant_struct.to_tokens(tokens); + create_struct_debug_impl(&mask_type_match_variant_struct, mask_type_name, None) + .to_tokens(tokens); let mut match_variant_fields = FieldsNamed::from(fields.clone()); for Field { ty, .. } in &mut match_variant_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::expr::Expr<#ty> }; } - ItemStruct { + let match_variant_struct = ItemStruct { attrs: vec![ - common_derives(span), + common_derives(span, false), parse_quote_spanned! {span=> #[allow(non_camel_case_types, dead_code)] }, @@ -585,19 +608,19 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(match_variant_fields), semi_token: None, - } - .to_tokens(tokens); + }; + match_variant_struct.to_tokens(tokens); + create_struct_debug_impl(&match_variant_struct, &struct_name, None).to_tokens(tokens); let mut mask_type_sim_value_fields = mask_type_fields; for Field { ty, .. } in &mut mask_type_sim_value_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::sim::value::SimValue<#ty> }; } - ItemStruct { + let mask_type_sim_value_struct = ItemStruct { attrs: vec![ parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( - ::fayalite::__std::fmt::Debug, ::fayalite::__std::clone::Clone, )] }, @@ -611,19 +634,34 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(mask_type_sim_value_fields), semi_token: None, + }; + mask_type_sim_value_struct.to_tokens(tokens); + if custom_debug_mask_sim.is_none() { + create_struct_debug_impl( + &mask_type_struct, + mask_type_name, + Some(CustomDebugTrait { + trait_path: &parse_quote_spanned! {span=> + ::fayalite::ty::SimValueDebug + }, + fn_name: &format_ident!("sim_value_debug", span = span), + this_arg: &parse_quote_spanned! {span=> + value: &::SimValue + }, + }), + ) + .to_tokens(tokens); } - .to_tokens(tokens); let mut sim_value_fields = FieldsNamed::from(fields.clone()); for Field { ty, .. } in &mut sim_value_fields.named { *ty = parse_quote_spanned! {span=> ::fayalite::sim::value::SimValue<#ty> }; } - ItemStruct { + let sim_value_struct = ItemStruct { attrs: vec![ parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( - ::fayalite::__std::fmt::Debug, ::fayalite::__std::clone::Clone, )] }, @@ -637,8 +675,36 @@ impl ToTokens for ParsedBundle { generics: generics.into(), fields: Fields::Named(sim_value_fields), semi_token: None, + }; + sim_value_struct.to_tokens(tokens); + if custom_debug_sim.is_none() { + create_struct_debug_impl( + &type_struct, + &struct_name, + Some(CustomDebugTrait { + trait_path: &parse_quote_spanned! {span=> + ::fayalite::ty::SimValueDebug + }, + fn_name: &format_ident!("sim_value_debug", span = span), + this_arg: &parse_quote_spanned! {span=> + value: &::SimValue + }, + }), + ) + .to_tokens(tokens); + } + if custom_sim_display.is_some() { + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics ::fayalite::__std::fmt::Display for #sim_value_ident #type_generics + #where_clause + { + fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + <#target #type_generics as ::fayalite::ty::SimValueDisplay>::sim_value_display(self, f) + } + } + }.to_tokens(tokens); } - .to_tokens(tokens); let this_token = Ident::new("__this", span); let fields_token = Ident::new("__fields", span); let self_token = Token![self](span); @@ -820,6 +886,14 @@ impl ToTokens for ParsedBundle { } } #[automatically_derived] + impl #impl_generics ::fayalite::__std::fmt::Debug for #mask_type_sim_value_ident #type_generics + #where_clause + { + fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + <#mask_type_ident #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f) + } + } + #[automatically_derived] impl #impl_generics ::fayalite::expr::ValueType for #mask_type_sim_value_ident #type_generics #where_clause { @@ -980,6 +1054,14 @@ impl ToTokens for ParsedBundle { } } #[automatically_derived] + impl #impl_generics ::fayalite::__std::fmt::Debug for #sim_value_ident #type_generics + #where_clause + { + fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + <#target #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f) + } + } + #[automatically_derived] impl #impl_generics ::fayalite::expr::ValueType for #sim_value_ident #type_generics #where_clause { diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs index ae0f8f4..e2410bc 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs @@ -3,8 +3,9 @@ use crate::{ Errors, HdlAttr, PairsIterExt, hdl_type_common::{ - ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, SplitForImpl, - TypesParser, WrappedInConst, common_derives, get_target, + CustomDebugOptions, ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, + SplitForImpl, TypesParser, WrappedInConst, common_derives, create_struct_debug_impl, + get_target, }, kw, }; @@ -160,6 +161,8 @@ impl ParsedEnum { no_runtime_generics: _, cmp_eq, ref get, + custom_debug: _, + custom_sim_display: _, } = options.body; if let Some((cmp_eq,)) = cmp_eq { errors.error(cmp_eq, "#[hdl(cmp_eq)] is not yet implemented for enums"); @@ -167,6 +170,24 @@ impl ParsedEnum { if let Some((get, ..)) = get { errors.error(get, "#[hdl(get(...))] is not allowed on enums"); } + let CustomDebugOptions { + type_: _, + sim: _, + mask_type, + mask_sim, + } = options.body.custom_debug(); + if let Some((mask_type,)) = mask_type { + errors.error( + mask_type, + "#[hdl(custom_debug(mask_type)] is not allowed on enums", + ); + } + if let Some((mask_sim,)) = mask_sim { + errors.error( + mask_sim, + "#[hdl(custom_debug(mask_sim)] is not allowed on enums", + ); + } attrs.retain(|attr| { if attr.path().is_ident("repr") { errors.error(attr, "#[repr] is not supported on #[hdl] enums"); @@ -230,10 +251,19 @@ impl ToTokens for ParsedEnum { no_runtime_generics, cmp_eq: _, // TODO: implement cmp_eq for enums get: _, + custom_debug: _, + custom_sim_display, } = &options.body; + let CustomDebugOptions { + type_: custom_debug_type, + sim: custom_debug_sim, + mask_type: _, + mask_sim: _, + } = options.body.custom_debug(); let target = get_target(target, ident); + let enum_name = ident.to_string(); let mut struct_attrs = attrs.clone(); - struct_attrs.push(common_derives(span)); + struct_attrs.push(common_derives(span, false)); struct_attrs.push(parse_quote_spanned! {span=> #[allow(non_snake_case)] }); @@ -273,7 +303,7 @@ impl ToTokens for ParsedEnum { } }, )); - ItemStruct { + let type_struct = ItemStruct { attrs: struct_attrs, vis: vis.clone(), struct_token: Token![struct](enum_token.span), @@ -288,8 +318,8 @@ impl ToTokens for ParsedEnum { }) }, semi_token: None, - } - .to_tokens(tokens); + }; + type_struct.to_tokens(tokens); let (impl_generics, type_generics, where_clause) = generics.split_for_impl(); if let (MaybeParsed::Parsed(generics), None) = (generics, no_runtime_generics) { generics.make_runtime_generics(tokens, vis, ident, &target, |context| { @@ -373,6 +403,9 @@ impl ToTokens for ParsedEnum { } .to_tokens(tokens); } + if custom_debug_type.is_none() { + create_struct_debug_impl(&type_struct, &enum_name, None).to_tokens(tokens); + } let mut enum_attrs = attrs.clone(); enum_attrs.push(parse_quote_spanned! {span=> #[allow(dead_code, non_camel_case_types)] @@ -453,7 +486,6 @@ impl ToTokens for ParsedEnum { let mut enum_attrs = attrs.clone(); enum_attrs.push(parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( - ::fayalite::__std::fmt::Debug, ::fayalite::__std::clone::Clone, )] }); @@ -838,6 +870,74 @@ impl ToTokens for ParsedEnum { }, )), ); + if custom_debug_sim.is_none() { + let debug_match_arms = Vec::from_iter( + variants + .iter() + .map( + |ParsedVariant { + attrs: _, + options: _, + ident, + field, + }| { + let variant_name = ident.to_string(); + if let Some(_) = field { + quote_spanned! {span=> + #sim_value_ident::#ident(field, _) => { + f.debug_tuple(#variant_name).field(field).finish() + } + } + } else { + quote_spanned! {span=> + #sim_value_ident::#ident(_) => { + f.write_str(#variant_name) + } + } + } + }, + ) + .chain(sim_value_unknown_variant_name.as_ref().map( + |sim_value_unknown_variant_name| { + let sim_value_unknown_variant_name_str = + sim_value_unknown_variant_name.to_string(); + quote_spanned! {span=> + #sim_value_ident::#sim_value_unknown_variant_name(_) => { + f.write_str(#sim_value_unknown_variant_name_str) + } + } + }, + )), + ); + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics ::fayalite::ty::SimValueDebug for #target #type_generics + #where_clause + { + fn sim_value_debug( + value: &::SimValue, + f: &mut ::fayalite::__std::fmt::Formatter<'_>, + ) -> ::fayalite::__std::fmt::Result { + match value { + #(#debug_match_arms)* + } + } + } + } + .to_tokens(tokens); + } + if custom_sim_display.is_some() { + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics ::fayalite::__std::fmt::Display for #sim_value_ident #type_generics + #where_clause + { + fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + <#target #type_generics as ::fayalite::ty::SimValueDisplay>::sim_value_display(self, f) + } + } + }.to_tokens(tokens); + } let variants_len = variants.len(); quote_spanned! {span=> #[automatically_derived] @@ -934,6 +1034,14 @@ impl ToTokens for ParsedEnum { } } #[automatically_derived] + impl #impl_generics ::fayalite::__std::fmt::Debug for #sim_value_ident #type_generics + #where_clause + { + fn fmt(&self, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + <#target #type_generics as ::fayalite::ty::SimValueDebug>::sim_value_debug(self, f) + } + } + #[automatically_derived] impl #impl_generics ::fayalite::sim::value::ToSimValueWithType<#target #type_generics> for #sim_value_ident #type_generics #where_clause diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs index 0fa2222..556c15b 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs @@ -215,6 +215,8 @@ impl ParsedTypeAlias { no_runtime_generics, cmp_eq, get: _, + ref custom_debug, + custom_sim_display, } = options.body; if let Some((no_static,)) = no_static { errors.error(no_static, "no_static is not valid on type aliases"); @@ -234,6 +236,15 @@ impl ParsedTypeAlias { if let Some((cmp_eq,)) = cmp_eq { errors.error(cmp_eq, "cmp_eq is not valid on type aliases"); } + if let Some((custom_debug, _, _)) = custom_debug { + errors.error(custom_debug, "custom_debug is not valid on type aliases"); + } + if let Some((custom_sim_display,)) = custom_sim_display { + errors.error( + custom_sim_display, + "custom_sim_display is not valid on type aliases", + ); + } if let Some((custom_bounds,)) = custom_bounds { errors.error( custom_bounds, @@ -287,6 +298,8 @@ impl ParsedTypeAlias { no_runtime_generics: _, cmp_eq, ref mut get, + ref custom_debug, + custom_sim_display, } = options.body; if let Some(get) = get.take() { return Self::parse_phantom_const_accessor( @@ -311,6 +324,15 @@ impl ParsedTypeAlias { if let Some((cmp_eq,)) = cmp_eq { errors.error(cmp_eq, "cmp_eq is not valid on type aliases"); } + if let Some((custom_debug, _, _)) = custom_debug { + errors.error(custom_debug, "custom_debug is not valid on type aliases"); + } + if let Some((custom_sim_display,)) = custom_sim_display { + errors.error( + custom_sim_display, + "custom_sim_display is not valid on type aliases", + ); + } let generics = if custom_bounds.is_some() { MaybeParsed::Unrecognized(generics) } else if let Some(generics) = errors.ok(ParsedGenerics::parse(&mut generics)) { @@ -356,6 +378,8 @@ impl ToTokens for ParsedTypeAlias { no_runtime_generics, cmp_eq: _, get: _, + custom_debug: _, + custom_sim_display: _, } = &options.body; let target = get_target(target, ident); let mut type_attrs = attrs.clone(); @@ -402,6 +426,8 @@ impl ToTokens for ParsedTypeAlias { no_runtime_generics: _, cmp_eq: _, get: _, + custom_debug: _, + custom_sim_display: _, } = &options.body; let span = ident.span(); let mut type_attrs = attrs.clone(); @@ -427,7 +453,7 @@ impl ToTokens for ParsedTypeAlias { format_ident!("__{}__GenericsAccumulation", ident); ItemStruct { attrs: vec![ - common_derives(span), + common_derives(span, true), parse_quote_spanned! {span=> #[allow(non_camel_case_types)] }, diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs index 3a0e5e9..18cffc6 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs @@ -7,10 +7,10 @@ use std::{collections::HashMap, fmt, mem}; use syn::{ AngleBracketedGenericArguments, Attribute, Block, ConstParam, Expr, ExprBlock, ExprGroup, ExprIndex, ExprParen, ExprPath, ExprTuple, Field, FieldMutability, Fields, FieldsNamed, - FieldsUnnamed, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index, ItemStruct, - Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound, Turbofish, - Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath, TypeTuple, - Visibility, WhereClause, WherePredicate, + FieldsUnnamed, FnArg, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index, + ItemStruct, Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound, + Turbofish, Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath, + TypeTuple, Visibility, WhereClause, WherePredicate, parse::{Parse, ParseStream}, parse_quote, parse_quote_spanned, punctuated::{Pair, Punctuated}, @@ -18,6 +18,17 @@ use syn::{ token::{Brace, Bracket, Paren}, }; +crate::options! { + #[options = CustomDebugOptions] + #[no_ident_fragment] + pub(crate) enum CustomDebugOption { + Type(type_), + Sim(sim), + MaskType(mask_type), + MaskSim(mask_sim), + } +} + crate::options! { #[options = ItemOptions] pub(crate) enum ItemOption { @@ -28,6 +39,8 @@ crate::options! { NoRuntimeGenerics(no_runtime_generics), CmpEq(cmp_eq), Get(get, Expr), + CustomDebug(custom_debug, CustomDebugOptions), + CustomSimDisplay(custom_sim_display), } } @@ -41,8 +54,36 @@ impl ItemOptions { { self.no_static = Some((kw::no_static(custom_bounds.span),)); } + if let Some((kw, _, custom_debug)) = &mut self.custom_debug { + if let CustomDebugOptions { + type_: None, + sim: None, + mask_type: None, + mask_sim: None, + } = custom_debug + { + *custom_debug = CustomDebugOptions { + type_: Some((kw::type_(kw.span),)), + sim: Some((kw::sim(kw.span),)), + mask_type: None, + mask_sim: None, + }; + } + } Ok(()) } + pub(crate) fn custom_debug(&self) -> &CustomDebugOptions { + self.custom_debug.as_ref().map(|v| &v.2).unwrap_or( + const { + &CustomDebugOptions { + type_: None, + sim: None, + mask_type: None, + mask_sim: None, + } + }, + ) + } } pub(crate) struct WrappedInConst<'a> { @@ -84,10 +125,17 @@ pub(crate) fn get_target(target: &Option<(kw::target, Paren, Path)>, item_ident: } } -pub(crate) fn common_derives(span: Span) -> Attribute { +pub(crate) fn common_derives(span: Span, include_debug: bool) -> Attribute { + let debug = include_debug + .then(|| { + quote_spanned! {span=> + ::fayalite::__std::fmt::Debug + } + }) + .into_iter(); parse_quote_spanned! {span=> #[::fayalite::__std::prelude::v1::derive( - ::fayalite::__std::fmt::Debug, + #(#debug,)* ::fayalite::__std::cmp::Eq, ::fayalite::__std::cmp::PartialEq, ::fayalite::__std::hash::Hash, @@ -2975,7 +3023,7 @@ impl ParsedGenerics { let span = ident.span(); ItemStruct { attrs: vec![ - common_derives(span), + common_derives(span, true), parse_quote_spanned! {span=> #[allow(non_camel_case_types)] }, @@ -4733,3 +4781,109 @@ impl ParsedVisibility { .map(|ord| if ord.is_lt() { self } else { other }) } } + +pub(crate) struct CustomDebugTrait<'a> { + pub(crate) trait_path: &'a Path, + pub(crate) fn_name: &'a Ident, + pub(crate) this_arg: &'a FnArg, +} + +#[must_use] +pub(crate) fn create_struct_debug_impl( + item_struct: &ItemStruct, + debug_struct_name: &str, + custom_debug_trait: Option>, +) -> TokenStream { + let ident = &item_struct.ident; + let span = ident.span(); + let (impl_generics, type_generics, where_clause) = item_struct.generics.split_for_impl(); + let trait_path; + let fn_name; + let this_arg; + let CustomDebugTrait { + trait_path, + fn_name, + this_arg, + } = match custom_debug_trait { + Some(v) => v, + None => { + trait_path = parse_quote_spanned! {span=> + ::fayalite::__std::fmt::Debug + }; + fn_name = parse_quote_spanned! {span=> + fmt + }; + this_arg = parse_quote_spanned! {span=> + &self + }; + CustomDebugTrait { + trait_path: &trait_path, + fn_name: &fn_name, + this_arg: &this_arg, + } + } + }; + let this_arg_name = match this_arg { + FnArg::Receiver(this_arg) => this_arg.self_token.to_token_stream(), + FnArg::Typed(this_arg) => match &*this_arg.pat { + syn::Pat::Ident(pat_ident) => pat_ident.ident.to_token_stream(), + _ => unreachable!(), + }, + }; + match &item_struct.fields { + Fields::Named(fields) => { + let field_idents = fields + .named + .iter() + .map(|v| v.ident.as_ref().expect("known to have field name")); + let field_names = field_idents.clone().map(|v| v.to_string()); + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics #trait_path for #ident #type_generics + #where_clause + { + fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + let _ = #this_arg_name; + f.debug_struct(#debug_struct_name) + #(.field(#field_names, &#this_arg_name.#field_idents))* + .finish() + } + } + } + } + Fields::Unnamed(fields) => { + let field_members = fields + .unnamed + .iter() + .enumerate() + .map(|(index, _)| syn::Index { + index: index as _, + span, + }); + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics #trait_path for #ident #type_generics + #where_clause + { + fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + let _ = #this_arg_name; + f.debug_tuple(#debug_struct_name) + #(.field(&#this_arg_name.#field_members))* + .finish() + } + } + } + } + Fields::Unit => quote_spanned! {ident.span()=> + #[automatically_derived] + impl #impl_generics #trait_path for #ident #type_generics + #where_clause + { + fn #fn_name(#this_arg, f: &mut ::fayalite::__std::fmt::Formatter<'_>) -> ::fayalite::__std::fmt::Result { + let _ = #this_arg_name; + f.write_str(#debug_struct_name) + } + } + }, + } +} diff --git a/crates/fayalite-proc-macros-impl/src/lib.rs b/crates/fayalite-proc-macros-impl/src/lib.rs index 152053c..905cb05 100644 --- a/crates/fayalite-proc-macros-impl/src/lib.rs +++ b/crates/fayalite-proc-macros-impl/src/lib.rs @@ -42,6 +42,7 @@ pub(crate) trait CustomToken: mod kw { pub(crate) use syn::token::Extern as extern_; + pub(crate) use syn::token::Type as type_; macro_rules! custom_keyword { ($kw:ident) => { @@ -75,6 +76,8 @@ mod kw { custom_keyword!(cmp_eq); custom_keyword!(connect_inexact); custom_keyword!(custom_bounds); + custom_keyword!(custom_debug); + custom_keyword!(custom_sim_display); custom_keyword!(flip); custom_keyword!(get); custom_keyword!(hdl); @@ -83,6 +86,8 @@ mod kw { custom_keyword!(input); custom_keyword!(instance); custom_keyword!(m); + custom_keyword!(mask_sim); + custom_keyword!(mask_type); custom_keyword!(memory); custom_keyword!(memory_array); custom_keyword!(memory_with_init); diff --git a/crates/fayalite/src/array.rs b/crates/fayalite/src/array.rs index 6ca6809..fa754fd 100644 --- a/crates/fayalite/src/array.rs +++ b/crates/fayalite/src/array.rs @@ -13,13 +13,13 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, MatchVariantWithoutScope, OpaqueSimValueSlice, OpaqueSimValueWriter, - OpaqueSimValueWritten, StaticType, Type, TypeProperties, TypeWithDeref, + OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties, TypeWithDeref, serde_impls::SerdeCanonicalType, }, util::ConstUsize, }; use serde::{Deserialize, Deserializer, Serialize, Serializer, de::Error}; -use std::{borrow::Cow, iter::FusedIterator, ops::Index}; +use std::{borrow::Cow, fmt, iter::FusedIterator, ops::Index}; #[derive(Copy, Clone, PartialEq, Eq, Hash)] pub struct ArrayType { @@ -28,8 +28,8 @@ pub struct ArrayType { type_properties: TypeProperties, } -impl std::fmt::Debug for ArrayType { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { +impl fmt::Debug for ArrayType { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { write!(f, "Array<{:?}, {}>", self.element, self.len()) } } @@ -182,6 +182,15 @@ impl, Len: Size, State: Visitor + ?Sized> Visit } } +impl SimValueDebug for ArrayType { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl Type for ArrayType { type BaseType = Array; type MaskType = ArrayType; diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs index 1471f3a..5fad35c 100644 --- a/crates/fayalite/src/bundle.rs +++ b/crates/fayalite/src/bundle.rs @@ -14,8 +14,8 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, MatchVariantWithoutScope, OpaqueSimValue, OpaqueSimValueSize, - OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type, - TypeProperties, TypeWithDeref, impl_match_variant_as_self, + OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug, + StaticType, Type, TypeProperties, TypeWithDeref, impl_match_variant_as_self, }, util::HashMap, }; @@ -271,6 +271,15 @@ impl Type for Bundle { } } +impl SimValueDebug for Bundle { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + pub trait BundleType: Type { type Builder: Default; fn fields(&self) -> Interned<[BundleField]>; @@ -471,6 +480,14 @@ macro_rules! impl_tuples { #[var($var)] })*] } + impl<$($T: Type,)*> SimValueDebug for ($($T,)*) { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } + } impl<$($T: Type,)*> Type for ($($T,)*) { type BaseType = Bundle; type MaskType = ($($T::MaskType,)*); @@ -773,6 +790,15 @@ impl_tuples! { ] } +impl SimValueDebug for PhantomData { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl Type for PhantomData { type BaseType = Bundle; type MaskType = (); diff --git a/crates/fayalite/src/clock.rs b/crates/fayalite/src/clock.rs index 168142b..0e6d145 100644 --- a/crates/fayalite/src/clock.rs +++ b/crates/fayalite/src/clock.rs @@ -1,5 +1,6 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information + use crate::{ expr::{Expr, ValueType}, hdl, @@ -9,10 +10,12 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSize, OpaqueSimValueSlice, OpaqueSimValueWriter, - OpaqueSimValueWritten, StaticType, Type, TypeProperties, impl_match_variant_as_self, + OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties, + impl_match_variant_as_self, }, }; use bitvec::{bits, order::Lsb0}; +use std::fmt; #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)] pub struct Clock; @@ -69,6 +72,15 @@ impl Type for Clock { } } +impl SimValueDebug for Clock { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl Clock { pub fn type_properties(self) -> TypeProperties { Self::TYPE_PROPERTIES diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs index a04f67a..d545f93 100644 --- a/crates/fayalite/src/enum_.rs +++ b/crates/fayalite/src/enum_.rs @@ -14,8 +14,8 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, MatchVariantAndInactiveScope, OpaqueSimValue, OpaqueSimValueSize, - OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type, - TypeProperties, + OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug, + StaticType, Type, TypeProperties, }, util::HashMap, }; @@ -410,6 +410,15 @@ impl Type for Enum { } } +impl SimValueDebug for Enum { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + #[derive(Clone, PartialEq, Eq, Hash, Debug, Default)] pub struct EnumPaddingSimValue { bits: Option, diff --git a/crates/fayalite/src/int.rs b/crates/fayalite/src/int.rs index c461306..ff20933 100644 --- a/crates/fayalite/src/int.rs +++ b/crates/fayalite/src/int.rs @@ -15,8 +15,8 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, FillInDefaultedGenerics, OpaqueSimValueSize, OpaqueSimValueSlice, - OpaqueSimValueWriter, OpaqueSimValueWritten, StaticType, Type, TypeProperties, - impl_match_variant_as_self, + OpaqueSimValueWriter, OpaqueSimValueWritten, SimValueDebug, SimValueDisplay, StaticType, + Type, TypeProperties, impl_match_variant_as_self, }, util::{ConstBool, ConstUsize, GenericConstBool, GenericConstUsize, interned_bit, slice_range}, }; @@ -1019,6 +1019,24 @@ macro_rules! impl_int { } } + impl SimValueDebug for $name { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } + } + + impl SimValueDisplay for $name { + fn sim_value_display( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Display::fmt(value, f) + } + } + impl Default for $name { fn default() -> Self { Self::TYPE @@ -1899,6 +1917,15 @@ impl Type for Bool { } } +impl SimValueDebug for Bool { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl StaticType for Bool { const TYPE: Self = Bool; const MASK_TYPE: Self::MaskType = Bool; diff --git a/crates/fayalite/src/int/uint_in_range.rs b/crates/fayalite/src/int/uint_in_range.rs index acf2fec..edf2e25 100644 --- a/crates/fayalite/src/int/uint_in_range.rs +++ b/crates/fayalite/src/int/uint_in_range.rs @@ -14,7 +14,7 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, - StaticType, Type, TypeProperties, impl_match_variant_as_self, + SimValueDebug, StaticType, Type, TypeProperties, impl_match_variant_as_self, }, }; use bitvec::{order::Lsb0, view::BitView}; @@ -94,6 +94,15 @@ impl Type for UIntInRangeMaskType { } } +impl SimValueDebug for UIntInRangeMaskType { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl BundleType for UIntInRangeMaskType { type Builder = NoBuilder; @@ -339,6 +348,15 @@ macro_rules! define_uint_in_range_type { } } + impl SimValueDebug for $UIntInRangeType { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } + } + impl fmt::Debug for $UIntInRangeType { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { value, range } = self; diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs index fb7be6f..ba85817 100644 --- a/crates/fayalite/src/phantom_const.rs +++ b/crates/fayalite/src/phantom_const.rs @@ -9,7 +9,7 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSlice, OpaqueSimValueWriter, OpaqueSimValueWritten, - StaticType, Type, TypeProperties, impl_match_variant_as_self, + SimValueDebug, StaticType, Type, TypeProperties, impl_match_variant_as_self, serde_impls::{SerdeCanonicalType, SerdePhantomConst}, }, }; @@ -327,6 +327,15 @@ impl Type for PhantomConst { } } +impl SimValueDebug for PhantomConst { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl Default for PhantomConst where Interned: Default, diff --git a/crates/fayalite/src/reset.rs b/crates/fayalite/src/reset.rs index 13273ac..ddc3651 100644 --- a/crates/fayalite/src/reset.rs +++ b/crates/fayalite/src/reset.rs @@ -1,5 +1,6 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information + use crate::{ clock::Clock, expr::{CastToImpl, Expr, ValueType}, @@ -8,11 +9,13 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValueSize, OpaqueSimValueSlice, OpaqueSimValueWriter, - OpaqueSimValueWritten, StaticType, Type, TypeProperties, impl_match_variant_as_self, + OpaqueSimValueWritten, SimValueDebug, StaticType, Type, TypeProperties, + impl_match_variant_as_self, }, util::ConstUsize, }; use bitvec::{bits, order::Lsb0}; +use std::fmt; mod sealed { pub trait ResetTypeSealed {} @@ -100,6 +103,15 @@ macro_rules! reset_type { } } + impl SimValueDebug for $name { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } + } + impl $name { pub fn type_properties(self) -> TypeProperties { Self::TYPE_PROPERTIES diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs index b6a4e4b..a127878 100644 --- a/crates/fayalite/src/sim/value.rs +++ b/crates/fayalite/src/sim/value.rs @@ -15,7 +15,8 @@ use crate::{ source_location::SourceLocation, ty::{ CanonicalType, OpaqueSimValue, OpaqueSimValueSize, OpaqueSimValueSlice, - OpaqueSimValueWriter, StaticType, Type, TypeProperties, impl_match_variant_as_self, + OpaqueSimValueWriter, SimValueDebug, StaticType, Type, TypeProperties, + impl_match_variant_as_self, }, util::{ ConstUsize, HashMap, @@ -1394,6 +1395,15 @@ impl Type for DynSimOnly { } } +impl SimValueDebug for DynSimOnly { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl Type for SimOnly { type BaseType = DynSimOnly; type MaskType = Bool; @@ -1459,6 +1469,15 @@ impl Type for SimOnly { } } +impl SimValueDebug for SimOnly { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + impl StaticType for SimOnly { const TYPE: Self = Self::new(); diff --git a/crates/fayalite/src/ty.rs b/crates/fayalite/src/ty.rs index 76c0955..ed0ba03 100644 --- a/crates/fayalite/src/ty.rs +++ b/crates/fayalite/src/ty.rs @@ -367,7 +367,15 @@ impl TypeOrDefault for crate::__ { } pub trait Type: - Copy + Hash + Eq + fmt::Debug + Send + Sync + 'static + FillInDefaultedGenerics + Copy + + Hash + + Eq + + fmt::Debug + + Send + + Sync + + 'static + + FillInDefaultedGenerics + + SimValueDebug { type BaseType: BaseType; type MaskType: Type; @@ -402,6 +410,16 @@ pub trait Type: ) -> OpaqueSimValueWritten<'w>; } +pub trait SimValueDebug { + fn sim_value_debug(value: &::SimValue, f: &mut fmt::Formatter<'_>) -> fmt::Result + where + Self: Type; +} + +pub trait SimValueDisplay: Type { + fn sim_value_display(value: &Self::SimValue, f: &mut fmt::Formatter<'_>) -> fmt::Result; +} + pub trait BaseType: Type< BaseType = Self, @@ -490,6 +508,15 @@ impl Type for CanonicalType { } } +impl SimValueDebug for CanonicalType { + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + fmt::Debug::fmt(value, f) + } +} + #[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize, Default)] #[non_exhaustive] pub struct OpaqueSimValueSizeRange { diff --git a/crates/fayalite/tests/hdl_types_fmt.rs b/crates/fayalite/tests/hdl_types_fmt.rs new file mode 100644 index 0000000..382f64d --- /dev/null +++ b/crates/fayalite/tests/hdl_types_fmt.rs @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information +use fayalite::{prelude::*, ty::SimValueDebug}; +use std::fmt; + +#[hdl(outline_generated)] +struct MyStruct0 { + v: T, + a: ArrayType, S>, +} + +#[hdl] +#[test] +fn check_my_struct0() { + let ty = MyStruct0[UInt[8]][3]; + assert_eq!( + format!("{ty:?}"), + "MyStruct0 { v: UInt<8>, a: Array, 3> }", + ); + assert_eq!( + format!("{:?}", ty.mask_type()), + "MaskType { v: Bool, a: Array }", + ); + let v = #[hdl(sim)] + MyStruct0::<_, _> { + v: 0x23u8, + a: [1u8, 2, 3], + }; + assert_eq!( + format!("{v:?}"), + "MyStruct0 { v: 0x23_u8, a: [0x1_u8, 0x2_u8, 0x3_u8] }", + ); +} + +#[hdl(outline_generated, custom_debug())] +struct MyStruct1 { + v: T, + a: ArrayType, S>, +} + +impl fmt::Debug for MyStruct1 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { v, a } = self; + f.debug_struct("Custom") + .field("v", v) + .field("a", a) + .finish() + } +} + +impl SimValueDebug for MyStruct1 { + #[hdl] + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + #[hdl(sim)] + let Self { v, a } = value; + f.debug_struct("Custom") + .field("v", &v) + .field("a", &a) + .finish() + } +} + +#[hdl] +#[test] +fn check_my_struct1() { + let ty = MyStruct1[UInt[8]][3]; + assert_eq!( + format!("{ty:?}"), + "Custom { v: UInt<8>, a: Array, 3> }", + ); + assert_eq!( + format!("{:?}", ty.mask_type()), + "MaskType { v: Bool, a: Array }", + ); + let v = #[hdl(sim)] + MyStruct1::<_, _> { + v: 0x23u8, + a: [1u8, 2, 3], + }; + assert_eq!( + format!("{v:?}"), + "Custom { v: 0x23_u8, a: [0x1_u8, 0x2_u8, 0x3_u8] }", + ); +} + +#[hdl(outline_generated)] +enum MyEnum0 { + Unit, + V(T), + A(ArrayType, S>), +} + +#[hdl] +#[test] +fn check_my_enum0() { + let ty = MyEnum0[UInt[8]][3]; + assert_eq!( + format!("{ty:?}"), + "MyEnum0 { Unit: (), V: UInt<8>, A: Array, 3> }", + ); + let v = #[hdl(sim)] + ty.Unit(); + assert_eq!(format!("{v:?}"), "Unit"); + let v = #[hdl(sim)] + ty.V(0x23u8); + assert_eq!(format!("{v:?}"), "V(0x23_u8)"); + let v = #[hdl(sim)] + ty.A([1u8, 2, 3]); + assert_eq!(format!("{v:?}"), "A([0x1_u8, 0x2_u8, 0x3_u8])"); +} + +#[hdl(outline_generated, custom_debug())] +enum MyEnum1 { + Unit, + V(T), + A(ArrayType, S>), +} + +impl fmt::Debug for MyEnum1 { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { Unit, V, A } = self; + f.debug_struct("Custom") + .field("Unit", Unit) + .field("V", V) + .field("A", A) + .finish() + } +} + +impl SimValueDebug for MyEnum1 { + #[hdl] + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + type SimValueT = ::SimValue; + match value { + SimValueT::::Unit(_) => f.write_str("MyEnum1::Unit"), + SimValueT::::V(v, _) => f.debug_tuple("MyEnum1::V").field(v).finish(), + SimValueT::::A(a, _) => f.debug_tuple("MyEnum1::A").field(a).finish(), + SimValueT::::Unknown(_) => f.write_str("MyEnum1::Unknown"), + } + } +} + +#[hdl] +#[test] +fn check_my_enum1() { + let ty = MyEnum1[UInt[8]][3]; + assert_eq!( + format!("{ty:?}"), + "Custom { Unit: (), V: UInt<8>, A: Array, 3> }", + ); + let v = #[hdl(sim)] + ty.Unit(); + assert_eq!(format!("{v:?}"), "MyEnum1::Unit"); + let v = #[hdl(sim)] + ty.V(0x23u8); + assert_eq!(format!("{v:?}"), "MyEnum1::V(0x23_u8)"); + let v = #[hdl(sim)] + ty.A([1u8, 2, 3]); + assert_eq!(format!("{v:?}"), "MyEnum1::A([0x1_u8, 0x2_u8, 0x3_u8])"); +} diff --git a/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr b/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr index 6c78637..44aff3f 100644 --- a/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr +++ b/crates/fayalite/tests/ui/simvalue_is_not_internable.stderr @@ -75,12 +75,12 @@ note: required because it appears within the type `Vec` note: required because it appears within the type `OpaqueSimValue` --> src/ty.rs | - 734 | pub struct OpaqueSimValue { + 761 | pub struct OpaqueSimValue { | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` --> src/sim/value.rs | - 51 | struct SimValueInner { + 52 | struct SimValueInner { | ^^^^^^^^^^^^^ note: required because it appears within the type `UnsafeCell>` --> $RUST/core/src/cell.rs @@ -95,7 +95,7 @@ note: required because it appears within the type `util::alternating_cell::Alter note: required because it appears within the type `fayalite::prelude::SimValue<()>` --> src/sim/value.rs | - 160 | pub struct SimValue { + 161 | pub struct SimValue { | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` --> src/intern.rs @@ -214,12 +214,12 @@ note: required because it appears within the type `Vec` note: required because it appears within the type `OpaqueSimValue` --> src/ty.rs | - 734 | pub struct OpaqueSimValue { + 761 | pub struct OpaqueSimValue { | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` --> src/sim/value.rs | - 51 | struct SimValueInner { + 52 | struct SimValueInner { | ^^^^^^^^^^^^^ note: required because it appears within the type `UnsafeCell>` --> $RUST/core/src/cell.rs @@ -234,7 +234,7 @@ note: required because it appears within the type `util::alternating_cell::Alter note: required because it appears within the type `fayalite::prelude::SimValue<()>` --> src/sim/value.rs | - 160 | pub struct SimValue { + 161 | pub struct SimValue { | ^^^^^^^^ note: required by a bound in `intern_sized` --> src/intern.rs @@ -326,12 +326,12 @@ note: required because it appears within the type `Vec` note: required because it appears within the type `OpaqueSimValue` --> src/ty.rs | - 734 | pub struct OpaqueSimValue { + 761 | pub struct OpaqueSimValue { | ^^^^^^^^^^^^^^ note: required because it appears within the type `value::SimValueInner<()>` --> src/sim/value.rs | - 51 | struct SimValueInner { + 52 | struct SimValueInner { | ^^^^^^^^^^^^^ note: required because it appears within the type `UnsafeCell>` --> $RUST/core/src/cell.rs @@ -346,7 +346,7 @@ note: required because it appears within the type `util::alternating_cell::Alter note: required because it appears within the type `fayalite::prelude::SimValue<()>` --> src/sim/value.rs | - 160 | pub struct SimValue { + 161 | pub struct SimValue { | ^^^^^^^^ note: required by a bound in `fayalite::intern::Interned` --> src/intern.rs From 7516ec3c24405e07640db4da52ece6f40acb2bec Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 1 May 2026 18:34:49 -0700 Subject: [PATCH 08/10] implement #[hdl(cmp_eq)] for enums --- .../src/hdl_bundle.rs | 2 +- .../fayalite-proc-macros-impl/src/hdl_enum.rs | 173 ++++++++- crates/fayalite/tests/module.rs | 362 +++++++++++++++++- 3 files changed, 530 insertions(+), 7 deletions(-) diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs index 6847af9..f7ad68d 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs @@ -1223,7 +1223,7 @@ impl ToTokens for ParsedBundle { valueless_eq_body = quote_spanned! {span=> let __lhs = ::fayalite::expr::ValueType::ty(&__lhs); let __rhs = ::fayalite::expr::ValueType::ty(&__rhs); - #(#fields_valueless_eq)|* + #(#fields_valueless_eq)&* }; valueless_ne_body = quote_spanned! {span=> let __lhs = ::fayalite::expr::ValueType::ty(&__lhs); diff --git a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs index e2410bc..e9f013b 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_enum.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_enum.rs @@ -159,14 +159,11 @@ impl ParsedEnum { custom_bounds, no_static: _, no_runtime_generics: _, - cmp_eq, + cmp_eq: _, ref get, custom_debug: _, custom_sim_display: _, } = options.body; - if let Some((cmp_eq,)) = cmp_eq { - errors.error(cmp_eq, "#[hdl(cmp_eq)] is not yet implemented for enums"); - } if let Some((get, ..)) = get { errors.error(get, "#[hdl(get(...))] is not allowed on enums"); } @@ -249,7 +246,7 @@ impl ToTokens for ParsedEnum { custom_bounds: _, no_static, no_runtime_generics, - cmp_eq: _, // TODO: implement cmp_eq for enums + cmp_eq, get: _, custom_debug: _, custom_sim_display, @@ -938,6 +935,172 @@ impl ToTokens for ParsedEnum { } }.to_tokens(tokens); } + if let Some((cmp_eq,)) = cmp_eq { + let mut cmp_eq_where_clause = + Generics::from(generics) + .where_clause + .unwrap_or_else(|| syn::WhereClause { + where_token: Token![where](span), + predicates: Punctuated::new(), + }); + let mut variants_value_eq = vec![]; + let mut variants_expr_eq = vec![]; + let mut fields_valueless_eq = vec![]; + for ( + variant_index, + ParsedVariant { + attrs: _, + options: variant_options, + ident: variant_ident, + field, + }, + ) in variants.iter().enumerate() + { + let VariantOptions {} = variant_options.body; + if let Some(ParsedVariantField { + paren_token: _, + attrs: _, + options: field_options, + ty: field_ty, + comma_token: _, + }) = field + { + let FieldOptions {} = field_options.body; + cmp_eq_where_clause + .predicates + .push(parse_quote_spanned! {cmp_eq.span=> + #field_ty: ::fayalite::expr::HdlPartialEqImpl<#field_ty> + }); + variants_value_eq.push(quote_spanned! {span=> + (#sim_value_ident::#variant_ident(__lhs_field, _), #sim_value_ident::#variant_ident(__rhs_field, _)) => { + ::fayalite::expr::HdlPartialEqImpl::cmp_value_eq( + __lhs.#variant_ident, + ::fayalite::__std::borrow::Cow::Borrowed(__lhs_field), + __rhs.#variant_ident, + ::fayalite::__std::borrow::Cow::Borrowed(__rhs_field), + ) + } + }); + variants_expr_eq.push(quote_spanned! {span=> + { + let (#match_variant_ident::#variant_ident(__lhs), __scope) = + ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( + ::fayalite::__std::iter::Iterator::next(&mut __lhs_match_variant_iter) + .expect("known to have enough variants"), + ) + else { + ::fayalite::__std::unreachable!(); + }; + let (#match_variant_ident::#variant_ident(__rhs), __scope) = + ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( + ::fayalite::__std::iter::Iterator::nth( + &mut ::fayalite::module::match_(__rhs), + #variant_index, + ) + .expect("known to have variant"), + ) + else { + ::fayalite::__std::unreachable!(); + }; + ::fayalite::module::connect(__retval, ::fayalite::expr::HdlPartialEqImpl::cmp_expr_eq(__lhs, __rhs)); + } + }); + fields_valueless_eq.push(quote_spanned! {span=> + ::fayalite::expr::HdlPartialEqImpl::cmp_valueless_eq( + ::fayalite::expr::Valueless::new(__lhs.#variant_ident), + ::fayalite::expr::Valueless::new(__rhs.#variant_ident), + ) + }); + } else { + variants_value_eq.push(quote_spanned! {span=> + (#sim_value_ident::#variant_ident(_), #sim_value_ident::#variant_ident(_)) => true, + }); + variants_expr_eq.push(quote_spanned! {span=> + { + let (#match_variant_ident::#variant_ident, __scope) = + ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( + ::fayalite::__std::iter::Iterator::next(&mut __lhs_match_variant_iter) + .expect("known to have enough variants"), + ) + else { + ::fayalite::__std::unreachable!(); + }; + let (#match_variant_ident::#variant_ident, __scope) = + ::fayalite::ty::MatchVariantAndInactiveScope::match_activate_scope( + ::fayalite::__std::iter::Iterator::nth( + &mut ::fayalite::module::match_(__rhs), + #variant_index, + ) + .expect("known to have variant"), + ) + else { + ::fayalite::__std::unreachable!(); + }; + ::fayalite::module::connect(__retval, true); + } + }); + } + } + if let Some(sim_value_unknown_variant_name) = &sim_value_unknown_variant_name { + variants_value_eq.push(quote_spanned! {span=> + (#sim_value_ident::#sim_value_unknown_variant_name(__lhs_unknown), #sim_value_ident::#sim_value_unknown_variant_name(__rhs_unknown)) => { + __lhs_unknown == __rhs_unknown + } + }); + } + let valueless_eq_body = if fields_valueless_eq.is_empty() { + quote_spanned! {span=> + ::fayalite::expr::Valueless::new(::fayalite::int::Bool) + } + } else { + quote_spanned! {span=> + let __lhs = ::fayalite::expr::ValueType::ty(&__lhs); + let __rhs = ::fayalite::expr::ValueType::ty(&__rhs); + #(#fields_valueless_eq)&* + } + }; + let cmp_expr_eq_wire_name = format!("{ident}_cmp_eq"); + quote_spanned! {span=> + #[automatically_derived] + impl #impl_generics ::fayalite::expr::HdlPartialEqImpl for #target #type_generics + #cmp_eq_where_clause + { + #[track_caller] + fn cmp_value_eq( + __lhs: Self, + __lhs_value: ::fayalite::__std::borrow::Cow<'_, ::SimValue>, + __rhs: Self, + __rhs_value: ::fayalite::__std::borrow::Cow<'_, ::SimValue>, + ) -> ::fayalite::__std::primitive::bool { + match (&*__lhs_value, &*__rhs_value) { + #(#variants_value_eq)* + _ => false, + } + } + + #[track_caller] + fn cmp_expr_eq( + __lhs: ::fayalite::expr::Expr, + __rhs: ::fayalite::expr::Expr, + ) -> ::fayalite::expr::Expr<::fayalite::int::Bool> { + let __retval = ::fayalite::module::wire(::fayalite::module::ImplicitName(#cmp_expr_eq_wire_name), ::fayalite::int::Bool); + ::fayalite::module::connect(__retval, false); + let mut __lhs_match_variant_iter = ::fayalite::module::match_(__lhs); + #(#variants_expr_eq)* + __retval + } + + #[track_caller] + fn cmp_valueless_eq( + __lhs: ::fayalite::expr::Valueless, + __rhs: ::fayalite::expr::Valueless, + ) -> ::fayalite::expr::Valueless<::fayalite::int::Bool> { + #valueless_eq_body + } + } + } + .to_tokens(tokens); + } let variants_len = variants.len(); quote_spanned! {span=> #[automatically_derived] diff --git a/crates/fayalite/tests/module.rs b/crates/fayalite/tests/module.rs index 2761cba..9dc0107 100644 --- a/crates/fayalite/tests/module.rs +++ b/crates/fayalite/tests/module.rs @@ -13,7 +13,7 @@ use fayalite::{ }; use serde_json::json; -#[hdl(outline_generated)] +#[hdl(outline_generated, cmp_eq)] pub enum TestEnum { A, B(UInt<8>), @@ -679,6 +679,366 @@ circuit check_enum_literals: }; } +#[hdl_module(outline_generated)] +pub fn check_enum_cmp_eq() { + #[hdl] + let lhs: TestEnum = m.input(); + #[hdl] + let rhs: TestEnum = m.input(); + #[hdl] + let eq: Bool = m.output(); + connect(eq, lhs.cmp_eq(rhs)); +} + +#[test] +fn test_enum_cmp_eq() { + let _n = SourceLocation::normalize_files_for_tests(); + let m = check_enum_cmp_eq(); + dbg!(m); + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_enums: None, + ..ExportOptions::default() + }, + "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 +circuit check_enum_cmp_eq: + type Ty0 = {|A, B: UInt<8>, C: UInt<1>[3]|} + module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] + input lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1] + input rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1] + output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] + wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] + match lhs: @[module-XXXXXXXXXX.rs 5:1] + A: + match rhs: @[module-XXXXXXXXXX.rs 5:1] + A: + connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] + B(_match_arm_value): + skip + C(_match_arm_value_1): + skip + B(_match_arm_value_2): + match rhs: @[module-XXXXXXXXXX.rs 5:1] + A: + skip + B(_match_arm_value_3): + connect TestEnum_cmp_eq, eq(_match_arm_value_2, _match_arm_value_3) @[module-XXXXXXXXXX.rs 5:1] + C(_match_arm_value_4): + skip + C(_match_arm_value_5): + match rhs: @[module-XXXXXXXXXX.rs 5:1] + A: + skip + B(_match_arm_value_6): + skip + C(_match_arm_value_7): + wire _array_literal_expr: UInt<1>[3] + connect _array_literal_expr[0], eq(_match_arm_value_5[0], _match_arm_value_7[0]) + connect _array_literal_expr[1], eq(_match_arm_value_5[1], _match_arm_value_7[1]) + connect _array_literal_expr[2], eq(_match_arm_value_5[2], _match_arm_value_7[2]) + wire _cast_array_to_bits_expr: UInt<1>[3] + connect _cast_array_to_bits_expr[0], _array_literal_expr[0] + connect _cast_array_to_bits_expr[1], _array_literal_expr[1] + connect _cast_array_to_bits_expr[2], _array_literal_expr[2] + wire _cast_to_bits_expr: UInt<3> + connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) + connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] + connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] +", + }; + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_enums: Some(SimplifyEnumsKind::SimplifyToEnumsWithNoBody), + ..ExportOptions::default() + }, + "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 +circuit check_enum_cmp_eq: + type Ty0 = {|A, B, C|} + type Ty1 = {tag: Ty0, body: UInt<8>} + module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] + input lhs: Ty1 @[module-XXXXXXXXXX.rs 2:1] + input rhs: Ty1 @[module-XXXXXXXXXX.rs 3:1] + output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] + wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] + match lhs.tag: @[module-XXXXXXXXXX.rs 5:1] + A: + match rhs.tag: @[module-XXXXXXXXXX.rs 5:1] + A: + connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] + B: + skip + C: + skip + B: + match rhs.tag: @[module-XXXXXXXXXX.rs 5:1] + A: + skip + B: + connect TestEnum_cmp_eq, eq(bits(lhs.body, 7, 0), bits(rhs.body, 7, 0)) @[module-XXXXXXXXXX.rs 5:1] + C: + skip + C: + match rhs.tag: @[module-XXXXXXXXXX.rs 5:1] + A: + skip + B: + skip + C: + wire _array_literal_expr: UInt<1>[3] + wire _cast_bits_to_array_expr: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0] + connect _cast_bits_to_array_expr_flattened[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1] + connect _cast_bits_to_array_expr_flattened[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2] + wire _cast_bits_to_array_expr_1: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0] + connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1] + connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2] + connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0]) + wire _cast_bits_to_array_expr_2: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0] + connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1] + connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2] + wire _cast_bits_to_array_expr_3: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0] + connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1] + connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2] + connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1]) + wire _cast_bits_to_array_expr_4: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0] + connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1] + connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2] + wire _cast_bits_to_array_expr_5: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0] + connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1] + connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2] + connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2]) + wire _cast_array_to_bits_expr: UInt<1>[3] + connect _cast_array_to_bits_expr[0], _array_literal_expr[0] + connect _cast_array_to_bits_expr[1], _array_literal_expr[1] + connect _cast_array_to_bits_expr[2], _array_literal_expr[2] + wire _cast_to_bits_expr: UInt<3> + connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) + connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] + connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] +", + }; + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_enums: Some(SimplifyEnumsKind::ReplaceWithBundleOfUInts), + ..ExportOptions::default() + }, + "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 +circuit check_enum_cmp_eq: + type Ty0 = {tag: UInt<2>, body: UInt<8>} + module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] + input lhs: Ty0 @[module-XXXXXXXXXX.rs 2:1] + input rhs: Ty0 @[module-XXXXXXXXXX.rs 3:1] + output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] + wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] + when eq(lhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] + else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(lhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, eq(bits(lhs.body, 7, 0), bits(rhs.body, 7, 0)) @[module-XXXXXXXXXX.rs 5:1] + else when eq(rhs.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(rhs.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + skip + else: + wire _array_literal_expr: UInt<1>[3] + wire _cast_bits_to_array_expr: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0] + connect _cast_bits_to_array_expr_flattened[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1] + connect _cast_bits_to_array_expr_flattened[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2] + wire _cast_bits_to_array_expr_1: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0] + connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1] + connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2] + connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0]) + wire _cast_bits_to_array_expr_2: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0] + connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1] + connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2] + wire _cast_bits_to_array_expr_3: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0] + connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1] + connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2] + connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1]) + wire _cast_bits_to_array_expr_4: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(lhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0] + connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(lhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1] + connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(lhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2] + wire _cast_bits_to_array_expr_5: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(rhs.body, 2, 0), 0, 0) + connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0] + connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(rhs.body, 2, 0), 1, 1) + connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1] + connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(rhs.body, 2, 0), 2, 2) + connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2] + connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2]) + wire _cast_array_to_bits_expr: UInt<1>[3] + connect _cast_array_to_bits_expr[0], _array_literal_expr[0] + connect _cast_array_to_bits_expr[1], _array_literal_expr[1] + connect _cast_array_to_bits_expr[2], _array_literal_expr[2] + wire _cast_to_bits_expr: UInt<3> + connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) + connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] + connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] +", + }; + #[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161 + assert_export_firrtl! { + m => + options: ExportOptions { + simplify_enums: Some(SimplifyEnumsKind::ReplaceWithUInt), + ..ExportOptions::default() + }, + "/test/check_enum_cmp_eq.fir": r"FIRRTL version 3.2.0 +circuit check_enum_cmp_eq: + module check_enum_cmp_eq: @[module-XXXXXXXXXX.rs 1:1] + input lhs: UInt<10> @[module-XXXXXXXXXX.rs 2:1] + input rhs: UInt<10> @[module-XXXXXXXXXX.rs 3:1] + output eq: UInt<1> @[module-XXXXXXXXXX.rs 4:1] + wire TestEnum_cmp_eq: UInt<1> @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h0) @[module-XXXXXXXXXX.rs 5:1] + when eq(bits(lhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 5:1] + else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(bits(lhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + connect TestEnum_cmp_eq, eq(bits(bits(lhs, 9, 2), 7, 0), bits(bits(rhs, 9, 2), 7, 0)) @[module-XXXXXXXXXX.rs 5:1] + else when eq(bits(rhs, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 5:1] + skip + else when eq(bits(rhs, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 5:1] + skip + else: + wire _array_literal_expr: UInt<1>[3] + wire _cast_bits_to_array_expr: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr[0], _cast_bits_to_array_expr_flattened[0] + connect _cast_bits_to_array_expr_flattened[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1] + connect _cast_bits_to_array_expr_flattened[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2] + wire _cast_bits_to_array_expr_1: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_1: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_1[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr_1[0], _cast_bits_to_array_expr_flattened_1[0] + connect _cast_bits_to_array_expr_flattened_1[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1] + connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2] + connect _array_literal_expr[0], eq(_cast_bits_to_array_expr[0], _cast_bits_to_array_expr_1[0]) + wire _cast_bits_to_array_expr_2: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_2: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_2[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr_2[0], _cast_bits_to_array_expr_flattened_2[0] + connect _cast_bits_to_array_expr_flattened_2[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_flattened_2[1] + connect _cast_bits_to_array_expr_flattened_2[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr_2[2], _cast_bits_to_array_expr_flattened_2[2] + wire _cast_bits_to_array_expr_3: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_3: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_3[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr_3[0], _cast_bits_to_array_expr_flattened_3[0] + connect _cast_bits_to_array_expr_flattened_3[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr_3[1], _cast_bits_to_array_expr_flattened_3[1] + connect _cast_bits_to_array_expr_flattened_3[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr_3[2], _cast_bits_to_array_expr_flattened_3[2] + connect _array_literal_expr[1], eq(_cast_bits_to_array_expr_2[1], _cast_bits_to_array_expr_3[1]) + wire _cast_bits_to_array_expr_4: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_4: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_4[0], bits(bits(bits(lhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr_4[0], _cast_bits_to_array_expr_flattened_4[0] + connect _cast_bits_to_array_expr_flattened_4[1], bits(bits(bits(lhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr_4[1], _cast_bits_to_array_expr_flattened_4[1] + connect _cast_bits_to_array_expr_flattened_4[2], bits(bits(bits(lhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_flattened_4[2] + wire _cast_bits_to_array_expr_5: UInt<1>[3] + wire _cast_bits_to_array_expr_flattened_5: UInt<1>[3] + connect _cast_bits_to_array_expr_flattened_5[0], bits(bits(bits(rhs, 9, 2), 2, 0), 0, 0) + connect _cast_bits_to_array_expr_5[0], _cast_bits_to_array_expr_flattened_5[0] + connect _cast_bits_to_array_expr_flattened_5[1], bits(bits(bits(rhs, 9, 2), 2, 0), 1, 1) + connect _cast_bits_to_array_expr_5[1], _cast_bits_to_array_expr_flattened_5[1] + connect _cast_bits_to_array_expr_flattened_5[2], bits(bits(bits(rhs, 9, 2), 2, 0), 2, 2) + connect _cast_bits_to_array_expr_5[2], _cast_bits_to_array_expr_flattened_5[2] + connect _array_literal_expr[2], eq(_cast_bits_to_array_expr_4[2], _cast_bits_to_array_expr_5[2]) + wire _cast_array_to_bits_expr: UInt<1>[3] + connect _cast_array_to_bits_expr[0], _array_literal_expr[0] + connect _cast_array_to_bits_expr[1], _array_literal_expr[1] + connect _cast_array_to_bits_expr[2], _array_literal_expr[2] + wire _cast_to_bits_expr: UInt<3> + connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0])) + connect TestEnum_cmp_eq, andr(_cast_to_bits_expr) @[module-XXXXXXXXXX.rs 5:1] + connect eq, TestEnum_cmp_eq @[module-XXXXXXXXXX.rs 6:1] +", + }; +} + #[hdl_module(outline_generated)] pub fn check_struct_enum_match() { #[hdl] From 7e9d7739fba743927392ac9f5466af25ee09515f Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 1 May 2026 18:35:21 -0700 Subject: [PATCH 09/10] use #[hdl(cmp_eq)] for HdlOption and implement conversion <-> Option --- crates/fayalite/src/enum_.rs | 208 ++++++++++++++++++++--------------- 1 file changed, 121 insertions(+), 87 deletions(-) diff --git a/crates/fayalite/src/enum_.rs b/crates/fayalite/src/enum_.rs index d545f93..f6af578 100644 --- a/crates/fayalite/src/enum_.rs +++ b/crates/fayalite/src/enum_.rs @@ -2,7 +2,7 @@ // See Notices.txt for copyright information use crate::{ - expr::{Expr, HdlPartialEq, HdlPartialEqImpl, ToExpr, ValueType, ops::VariantAccess}, + expr::{Expr, ToExpr, ValueType, ops::VariantAccess}, hdl, int::{Bool, UIntValue}, intern::{Intern, Interned}, @@ -10,7 +10,7 @@ use crate::{ EnumMatchVariantAndInactiveScopeImpl, EnumMatchVariantsIterImpl, Scope, connect, enum_match_variants_helper, incomplete_wire, wire, }, - sim::value::SimValue, + sim::value::{SimValue, ToSimValue, ToSimValueWithType}, source_location::SourceLocation, ty::{ CanonicalType, MatchVariantAndInactiveScope, OpaqueSimValue, OpaqueSimValueSize, @@ -21,7 +21,7 @@ use crate::{ }; use bitvec::{order::Lsb0, slice::BitSlice, view::BitView}; use serde::{Deserialize, Serialize}; -use std::{borrow::Cow, convert::Infallible, fmt, iter::FusedIterator, sync::Arc}; +use std::{convert::Infallible, fmt, iter::FusedIterator, sync::Arc}; #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)] pub struct EnumVariant { @@ -732,95 +732,12 @@ pub fn enum_type_to_sim_builder(v: T) -> T::SimBuilder { v.into() } -#[hdl] +#[hdl(cmp_eq)] pub enum HdlOption { HdlNone, HdlSome(T), } -impl, Rhs: Type> HdlPartialEqImpl> - for HdlOption -{ - fn cmp_value_eq( - lhs: Self, - lhs_value: Cow<'_, Self::SimValue>, - rhs: HdlOption, - rhs_value: Cow<'_, as Type>::SimValue>, - ) -> bool { - type SimValueMatch = ::SimValue; - match (&*lhs_value, &*rhs_value) { - (SimValueMatch::::HdlNone(_), SimValueMatch::>::HdlNone(_)) => { - true - } - (SimValueMatch::::HdlSome(..), SimValueMatch::>::HdlNone(_)) - | (SimValueMatch::::HdlNone(_), SimValueMatch::>::HdlSome(..)) => { - false - } - ( - SimValueMatch::::HdlSome(l, _), - SimValueMatch::>::HdlSome(r, _), - ) => HdlPartialEqImpl::cmp_value_eq( - lhs.HdlSome, - Cow::Borrowed(&**l), - rhs.HdlSome, - Cow::Borrowed(&**r), - ), - } - } - - #[hdl] - fn cmp_expr_eq(lhs: Expr, rhs: Expr>) -> Expr { - #[hdl] - let cmp_eq = wire(); - #[hdl] - match lhs { - HdlSome(lhs) => - { - #[hdl] - match rhs { - HdlSome(rhs) => connect(cmp_eq, lhs.cmp_eq(rhs)), - HdlNone => connect(cmp_eq, false), - } - } - HdlNone => - { - #[hdl] - match rhs { - HdlSome(_) => connect(cmp_eq, false), - HdlNone => connect(cmp_eq, true), - } - } - } - cmp_eq - } - - #[hdl] - fn cmp_expr_ne(lhs: Expr, rhs: Expr>) -> Expr { - #[hdl] - let cmp_ne = wire(); - #[hdl] - match lhs { - HdlSome(lhs) => - { - #[hdl] - match rhs { - HdlSome(rhs) => connect(cmp_ne, lhs.cmp_ne(rhs)), - HdlNone => connect(cmp_ne, true), - } - } - HdlNone => - { - #[hdl] - match rhs { - HdlSome(_) => connect(cmp_ne, true), - HdlNone => connect(cmp_ne, false), - } - } - } - cmp_ne - } -} - #[allow(non_snake_case)] pub fn HdlNone() -> Expr> { HdlOption[T::TYPE].HdlNone() @@ -832,6 +749,123 @@ pub fn HdlSome(value: impl ToExpr) -> Expr> { HdlOption[value.ty()].HdlSome(value) } +impl From>> for Option> { + #[hdl] + fn from(value: SimValue>) -> Self { + #[hdl(sim)] + match value { + HdlSome(v) => Some(v), + HdlNone => None, + } + } +} + +impl<'a, T: Type> From<&'a SimValue>> for Option<&'a SimValue> { + #[hdl] + fn from(value: &'a SimValue>) -> Self { + #[hdl(sim)] + match value { + HdlSome(v) => Some(v), + HdlNone => None, + } + } +} + +impl<'a, T: Type> From<&'a mut SimValue>> for Option<&'a mut SimValue> { + #[hdl] + fn from(value: &'a mut SimValue>) -> Self { + #[hdl(sim)] + match value { + HdlSome(v) => Some(v), + HdlNone => None, + } + } +} + +impl>> ValueType for Option { + type Type = HdlOption; + type ValueCategory = T::ValueCategory; + + fn ty(&self) -> Self::Type { + StaticType::TYPE + } +} + +impl> ToSimValueWithType> for Option { + #[hdl] + fn to_sim_value_with_type(&self, ty: HdlOption) -> SimValue> { + match self { + Some(v) => + { + #[hdl(sim)] + ty.HdlSome(v) + } + None => + { + #[hdl(sim)] + ty.HdlNone() + } + } + } + #[hdl] + fn into_sim_value_with_type(self, ty: HdlOption) -> SimValue> { + match self { + Some(v) => + { + #[hdl(sim)] + ty.HdlSome(v) + } + None => + { + #[hdl(sim)] + ty.HdlNone() + } + } + } +} + +impl>> ToSimValue for Option { + #[hdl] + fn to_sim_value(&self) -> SimValue { + match self { + Some(v) => + { + #[hdl(sim)] + HdlSome(v) + } + None => + { + #[hdl(sim)] + HdlNone() + } + } + } + #[hdl] + fn into_sim_value(self) -> SimValue { + match self { + Some(v) => + { + #[hdl(sim)] + HdlSome(v) + } + None => + { + #[hdl(sim)] + HdlNone() + } + } + } +} + +impl>> ToExpr for Option { + fn to_expr(&self) -> Expr { + match self { + Some(v) => HdlSome(v), + None => HdlNone(), + } + } +} + impl HdlOption { #[track_caller] pub fn try_map( From 226631594458f4137739baf98d2a9cd2c257242e Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sun, 3 May 2026 22:35:30 -0700 Subject: [PATCH 10/10] redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue --- .../src/module/transform_body/expand_match.rs | 16 +- .../hdl_let_statements/destructuring.rs | 41 +++- .../module_bodies/hdl_match_statements.rs | 42 +++- crates/fayalite/src/sim/value.rs | 200 +++++++++--------- 4 files changed, 183 insertions(+), 116 deletions(-) diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs index ca06c0b..605f662 100644 --- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs +++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs @@ -1096,11 +1096,9 @@ impl Visitor<'_> { let (#(#bindings,)*) = { type __MatchTy = ::SimValue; let __match_value = #expr; - let __match_value = { - use ::fayalite::sim::value::match_sim_value::*; - // use method syntax to deduce the correct trait to call - ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value() - }; + // use method syntax to deduce what type to convert to + let __match_value = ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value) + .__fayalite_match_sim_value(); #let_token #pat #eq_token __match_value #semi_token (#(#bindings_idents,)*) }; @@ -1172,11 +1170,9 @@ impl Visitor<'_> { { type __MatchTy = ::SimValue; let __match_value = #expr; - let __match_value = { - use ::fayalite::sim::value::match_sim_value::*; - // use method syntax to deduce the correct trait to call - ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value() - }; + // use method syntax to deduce what type to convert to + let __match_value = ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value) + .__fayalite_match_sim_value(); #match_token __match_value { #(#arms)* } diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs index 8d70d21..065e5de 100644 --- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs +++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs @@ -95,7 +95,23 @@ //! } //! //! #[hdl] -//! fn destructure_to_sim_value<'a, T: Type>(v: impl ToSimValue>) { +//! fn destructure_inner(v: as Type>::SimValue) { +//! #[hdl(sim)] +//! let MyStruct:: { +//! a, +//! mut b, +//! c, +//! } = v; +//! +//! // that gives these types: +//! let _: SimValue> = a; +//! let _: SimValue = b; +//! let _: SimValue = c; +//! *b = false; // can modify b since mut was used +//! } +//! +//! #[hdl] +//! fn destructure_inner_ref<'a, T: Type>(v: &'a as Type>::SimValue) { //! #[hdl(sim)] //! let MyStruct:: { //! a, @@ -104,8 +120,25 @@ //! } = v; //! //! // that gives these types: -//! let _: SimValue> = a; -//! let _: SimValue = b; -//! let _: SimValue = c; +//! let _: &'a SimValue> = a; +//! let _: &'a SimValue = b; +//! let _: &'a SimValue = c; +//! } +//! +//! #[hdl] +//! fn destructure_inner_mut<'a, T: Type>(v: &'a mut as Type>::SimValue) { +//! #[hdl(sim)] +//! let MyStruct:: { +//! a, +//! b, +//! c, +//! } = v; +//! +//! **b = true; // you can modify v by modifying b which borrows from it +//! +//! // that gives these types: +//! let _: &'a mut SimValue> = a; +//! let _: &'a mut SimValue = b; +//! let _: &'a mut SimValue = c; //! } //! ``` diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs index accd3d7..9e2d41d 100644 --- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs +++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs @@ -72,15 +72,47 @@ //! } //! //! #[hdl] -//! fn match_to_sim_value<'a, T: Type>(v: impl ToSimValue>) { +//! fn match_inner_move(v: as Type>::SimValue) -> String { //! #[hdl(sim)] //! match v { -//! MyEnum::::A => println!("got A"), -//! MyEnum::::B(b) => { +//! MyEnum::::A => String::from("got A"), +//! MyEnum::::B(mut b) => { //! let _: SimValue = b; // b has this type -//! println!("got B({b})"); +//! let text = format!("got B({b})"); +//! *b = true; // can modify b since mut was used +//! text //! } -//! _ => println!("something else"), +//! _ => String::from("something else"), +//! } +//! } +//! +//! #[hdl] +//! fn match_inner_ref<'a, T: Type>(v: &'a as Type>::SimValue) -> u32 { +//! #[hdl(sim)] +//! match v { +//! MyEnum::::A => 1, +//! MyEnum::::B(b) => { +//! let _: &'a SimValue = b; // b has this type +//! println!("got B({b})"); +//! 5 +//! } +//! _ => 42, +//! } +//! } +//! +//! #[hdl] +//! fn match_inner_mut<'a, T: Type>(v: &'a mut as Type>::SimValue) -> Option<&'a mut SimValue> { +//! #[hdl(sim)] +//! match v { +//! MyEnum::::A => None, +//! MyEnum::::B(b) => { +//! println!("got B({b})"); +//! **b = true; // you can modify v by modifying b which borrows from it +//! let _: &'a mut SimValue = b; // b has this type +//! None +//! } +//! MyEnum::::C(v) => Some(v), // you can return matched values +//! _ => None, // HDL enums can have invalid discriminants, so we need this extra match arm //! } //! } //! ``` diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs index a127878..eaa3f8d 100644 --- a/crates/fayalite/src/sim/value.rs +++ b/crates/fayalite/src/sim/value.rs @@ -552,113 +552,119 @@ impl_sim_value_cmp_as_bool!(AsyncReset); #[doc(hidden)] pub mod match_sim_value { - use crate::{ - sim::value::{SimValue, ToSimValue}, - ty::Type, - }; + use crate::{sim::value::SimValue, ty::Type}; + use std::ops::{Deref, DerefMut}; + + macro_rules! wrapper { + ( + $(pub struct $wrapper:ident<$T:ident>($inner:ty);)* + ) => { + $(#[doc(hidden)] + pub struct $wrapper<$T>($inner); + + impl<$T> $wrapper<$T> { + #[inline(always)] + pub fn new(value: $T) -> Self { + Self(<$inner>::new(value)) + } + } + + impl<$T> Deref for $wrapper<$T> { + type Target = $inner; + + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } + } + + impl<$T> DerefMut for $wrapper<$T> { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } + })* + }; + } + + wrapper! { + pub struct MatchSimValueHelperCheckSimValue(MatchSimValueHelperCheckMutSimValue); + pub struct MatchSimValueHelperCheckMutSimValue(MatchSimValueHelperCheckRefSimValue); + pub struct MatchSimValueHelperCheckRefSimValue(MatchSimValueHelperCheckRefRefSimValue); + pub struct MatchSimValueHelperCheckRefRefSimValue(MatchSimValueHelperCheckRefMutSimValue); + pub struct MatchSimValueHelperCheckRefMutSimValue(MatchSimValueHelperCheckMutRefSimValue); + pub struct MatchSimValueHelperCheckMutRefSimValue(MatchSimValueHelperCheckMutMutSimValue); + pub struct MatchSimValueHelperCheckMutMutSimValue(MatchSimValueHelperIdentity); + } + + impl MatchSimValueHelperCheckSimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> T::SimValue { + SimValue::into_value(self.take()) + } + } + + impl<'a, T: Type> MatchSimValueHelperCheckMutSimValue<&'a mut SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'a mut T::SimValue { + self.take() + } + } + + impl<'a, T: Type> MatchSimValueHelperCheckRefSimValue<&'a SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'a T::SimValue { + self.take() + } + } + + impl<'a, 'b, T: Type> MatchSimValueHelperCheckRefRefSimValue<&'a &'b SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'b T::SimValue { + self.take() + } + } + + impl<'a, 'b, T: Type> MatchSimValueHelperCheckRefMutSimValue<&'a &'b mut SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'a T::SimValue { + self.take() + } + } + + impl<'a, 'b, T: Type> MatchSimValueHelperCheckMutRefSimValue<&'a mut &'b SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'b T::SimValue { + self.take() + } + } + + impl<'a, 'b, T: Type> MatchSimValueHelperCheckMutMutSimValue<&'a mut &'b mut SimValue> { + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> &'a mut T::SimValue { + self.take() + } + } #[doc(hidden)] - pub struct MatchSimValueHelper(Option); + pub struct MatchSimValueHelperIdentity(Option); - impl MatchSimValueHelper { - pub fn new(v: T) -> Self { + impl MatchSimValueHelperIdentity { + fn new(v: T) -> Self { Self(Some(v)) } - } - - #[doc(hidden)] - pub trait MatchSimValue { - type MatchValue; - - /// use `self` so it comes first in the method resolution order - fn __fayalite_match_sim_value(self) -> Self::MatchValue - where - Self: Sized; - } - - impl MatchSimValue for MatchSimValueHelper> { - type MatchValue = T::SimValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - SimValue::into_value(self.0.expect("should be Some")) + #[inline(always)] + fn take(&mut self) -> T { + self.0.take().expect("known to be Some") } - } - - impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a SimValue> { - type MatchValue = &'a T::SimValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - SimValue::value(self.0.expect("should be Some")) - } - } - - impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a mut SimValue> { - type MatchValue = &'a mut T::SimValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - SimValue::value_mut(self.0.expect("should be Some")) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ &'a T> - where - MatchSimValueHelper<&'a T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v))) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ mut &'a T> - where - MatchSimValueHelper<&'a T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v))) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a &'_ mut T> - where - MatchSimValueHelper<&'a T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &**v))) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a mut &'_ mut T> - where - MatchSimValueHelper<&'a mut T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &mut **v))) + #[inline(always)] + pub fn __fayalite_match_sim_value(&mut self) -> T { + self.take() } } #[doc(hidden)] - pub trait MatchSimValueFallback { - type MatchValue; - - /// use `&mut self` so it comes later in the method resolution order than MatchSimValue - fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue; - } - - impl MatchSimValueFallback for MatchSimValueHelper { - type MatchValue = ::SimValue; - - fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue { - SimValue::into_value(self.0.take().expect("should be Some").into_sim_value()) - } - } + pub type MatchSimValueHelper = MatchSimValueHelperCheckSimValue; } pub trait ToSimValue: ToSimValueWithType<::Type> + ValueType {