diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs index f952f42..e8dc51b 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs @@ -224,7 +224,7 @@ impl Builder { .args .push_value(match get_field_state(field_index) { BuilderFieldState::Unfilled => parse_quote_spanned! {self.ident.span()=> - () + ::fayalite::bundle::Unfilled<#ty> }, BuilderFieldState::Generic => { let type_var = type_var_for_field_name(ident); @@ -383,7 +383,7 @@ impl ToTokens for Builder { fn default() -> Self { #ident { #phantom_field_name: ::fayalite::__std::marker::PhantomData, - #(#field_idents: (),)* + #(#field_idents: ::fayalite::__std::default::Default::default(),)* } } } @@ -395,7 +395,7 @@ impl ToTokens for Builder { let type_generics = self.generics.split_for_impl().1; quote_spanned! {self.ident.span()=> #[automatically_derived] - #[allow(non_camel_case_types, dead_code, private_interfaces)] + #[allow(non_camel_case_types, dead_code)] impl #filled_impl_generics ::fayalite::expr::ToExpr for #filled_ty #filled_where_clause { @@ -499,6 +499,7 @@ impl ToTokens for ParsedBundle { }; builder.to_tokens(tokens); let unfilled_builder_ty = builder.builder_struct_ty(|_| BuilderFieldState::Unfilled); + let filled_builder_ty = builder.builder_struct_ty(|_| BuilderFieldState::Filled); let mut mask_type_fields = FieldsNamed::from(fields.clone()); for Field { ty, .. } in &mut mask_type_fields.named { *ty = parse_quote_spanned! {span=> @@ -516,6 +517,8 @@ impl ToTokens for ParsedBundle { mask_type_builder.to_tokens(tokens); let unfilled_mask_type_builder_ty = mask_type_builder.builder_struct_ty(|_| BuilderFieldState::Unfilled); + let filled_mask_type_builder_ty = + mask_type_builder.builder_struct_ty(|_| BuilderFieldState::Filled); ItemStruct { attrs: vec![ common_derives(span), @@ -782,6 +785,7 @@ impl ToTokens for ParsedBundle { #where_clause { type Builder = #unfilled_mask_type_builder_ty; + type FilledBuilder = #filled_mask_type_builder_ty; fn fields(&#self_token) -> ::fayalite::intern::Interned<[::fayalite::bundle::BundleField]> { ::fayalite::intern::Intern::intern(&[#(#fields_body_fields)*][..]) } @@ -931,6 +935,7 @@ impl ToTokens for ParsedBundle { #where_clause { type Builder = #unfilled_builder_ty; + type FilledBuilder = #filled_builder_ty; fn fields(&#self_token) -> ::fayalite::intern::Interned<[::fayalite::bundle::BundleField]> { ::fayalite::intern::Intern::intern(&[#(#fields_body_fields)*][..]) } diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs index 3a0e5e9..f5b353e 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs @@ -4612,124 +4612,3 @@ impl MakeHdlTypeExpr for ParsedTypeTuple { }) } } - -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -pub(crate) enum ParsedSimpleVisibility { - Public(Token![pub]), - PubCrate { - pub_token: Token![pub], - paren_token: Paren, - crate_token: Token![crate], - }, - Inherited, -} - -impl From for Visibility { - fn from(value: ParsedSimpleVisibility) -> Self { - match value { - ParsedSimpleVisibility::Public(v) => Visibility::Public(v), - ParsedSimpleVisibility::PubCrate { - pub_token, - paren_token, - crate_token, - } => Visibility::Restricted(syn::VisRestricted { - pub_token, - paren_token, - in_token: None, - path: Box::new(Ident::new("crate", crate_token.span).into()), - }), - ParsedSimpleVisibility::Inherited => Visibility::Inherited, - } - } -} - -impl PartialOrd for ParsedSimpleVisibility { - fn partial_cmp(&self, other: &Self) -> Option { - Some(self.cmp(other)) - } -} - -impl Ord for ParsedSimpleVisibility { - fn cmp(&self, other: &Self) -> std::cmp::Ordering { - self.visibility_level().cmp(&other.visibility_level()) - } -} - -impl ParsedSimpleVisibility { - const VISIBILITY_LEVEL_INHERITED: u8 = 0; - const VISIBILITY_LEVEL_RESTRICTED: u8 = 1 + Self::VISIBILITY_LEVEL_INHERITED; - const VISIBILITY_LEVEL_PUB_CRATE: u8 = 1 + Self::VISIBILITY_LEVEL_RESTRICTED; - const VISIBILITY_LEVEL_PUB: u8 = 1 + Self::VISIBILITY_LEVEL_PUB_CRATE; - fn visibility_level(self) -> u8 { - match self { - Self::Public(_) => Self::VISIBILITY_LEVEL_PUB, - Self::PubCrate { .. } => Self::VISIBILITY_LEVEL_PUB_CRATE, - Self::Inherited => Self::VISIBILITY_LEVEL_INHERITED, - } - } - pub(crate) fn parse(vis: Visibility) -> Result { - match vis { - Visibility::Public(v) => Ok(Self::Public(v)), - Visibility::Restricted(syn::VisRestricted { - pub_token, - paren_token, - in_token: None, - path, - }) if path.is_ident("crate") => Ok(Self::PubCrate { - pub_token, - paren_token, - crate_token: Token![crate](path.get_ident().expect("just checked").span()), - }), - Visibility::Restricted(v) => Err(v), - Visibility::Inherited => Ok(Self::Inherited), - } - } -} - -#[derive(Clone, Debug, PartialEq, Eq)] -pub(crate) enum ParsedVisibility { - Simple(ParsedSimpleVisibility), - Restricted(syn::VisRestricted), -} - -impl From for Visibility { - fn from(value: ParsedVisibility) -> Self { - match value { - ParsedVisibility::Simple(v) => v.into(), - ParsedVisibility::Restricted(v) => Visibility::Restricted(v), - } - } -} - -impl PartialOrd for ParsedVisibility { - fn partial_cmp(&self, other: &Self) -> Option { - match (self, other) { - (ParsedVisibility::Simple(l), ParsedVisibility::Simple(r)) => Some(l.cmp(r)), - (ParsedVisibility::Simple(l), ParsedVisibility::Restricted(_)) => Some( - l.visibility_level() - .cmp(&ParsedSimpleVisibility::VISIBILITY_LEVEL_RESTRICTED), - ), - (ParsedVisibility::Restricted(_), ParsedVisibility::Simple(r)) => { - Some(ParsedSimpleVisibility::VISIBILITY_LEVEL_RESTRICTED.cmp(&r.visibility_level())) - } - (ParsedVisibility::Restricted(l), ParsedVisibility::Restricted(r)) => { - (l == r).then_some(std::cmp::Ordering::Equal) - } - } - } -} - -impl ParsedVisibility { - #[allow(dead_code)] - pub(crate) fn parse(vis: Visibility) -> Self { - match ParsedSimpleVisibility::parse(vis) { - Ok(simple) => Self::Simple(simple), - Err(restricted) => Self::Restricted(restricted), - } - } - #[allow(dead_code)] - pub(crate) fn min<'a>(&'a self, other: &'a Self) -> Option<&'a Self> { - self.partial_cmp(other) - .map(|ord| if ord.is_lt() { self } else { other }) - } -} diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs index e30eb0f..1aabb19 100644 --- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs +++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_aggregate_literals.rs @@ -88,9 +88,6 @@ impl Visitor<'_> { field.expr = parse_quote_spanned! {field.member.span()=> ::fayalite::sim::value::ToSimValue::to_sim_value(&(#expr)) }; - field - .colon_token - .get_or_insert(Token![:](field.member.span())); } return parse_quote_spanned! {name_span=> { diff --git a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs index ca06c0b..069f00d 100644 --- a/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs +++ b/crates/fayalite-proc-macros-impl/src/module/transform_body/expand_match.rs @@ -10,7 +10,7 @@ use crate::{ }; use proc_macro2::{Span, TokenStream}; use quote::{ToTokens, TokenStreamExt, format_ident, quote_spanned}; -use std::collections::BTreeMap; +use std::collections::BTreeSet; use syn::{ Arm, Attribute, Expr, ExprMatch, FieldPat, Ident, Local, Member, Pat, PatIdent, PatOr, PatParen, PatPath, PatRest, PatStruct, PatTuple, PatTupleStruct, PatWild, Path, PathSegment, @@ -24,65 +24,65 @@ use syn::{ macro_rules! visit_trait { ( - $($vis:vis fn $fn:ident($state:ident: _, $value:ident: &mut $Value:ty) $block:block)* + $($vis:vis fn $fn:ident($state:ident: _, $value:ident: &$Value:ty) $block:block)* ) => { trait VisitMatchPat<'a> { - $(fn $fn(&mut self, $value: &'a mut $Value) { + $(fn $fn(&mut self, $value: &'a $Value) { $fn(self, $value); })* } - $($vis fn $fn<'a>($state: &mut (impl ?Sized + VisitMatchPat<'a>), $value: &'a mut $Value) $block)* + $($vis fn $fn<'a>($state: &mut (impl ?Sized + VisitMatchPat<'a>), $value: &'a $Value) $block)* }; } visit_trait! { - fn visit_match_pat_binding(_state: _, v: &mut MatchPatBinding) { - let MatchPatBinding { mutability: _, ident: _ } = v; + fn visit_match_pat_binding(_state: _, v: &MatchPatBinding) { + let MatchPatBinding { ident: _ } = v; } - fn visit_match_pat_wild(_state: _, v: &mut MatchPatWild) { + fn visit_match_pat_wild(_state: _, v: &MatchPatWild) { let MatchPatWild { underscore_token: _ } = v; } - fn visit_match_pat_rest(_state: _, v: &mut MatchPatRest) { + fn visit_match_pat_rest(_state: _, v: &MatchPatRest) { let MatchPatRest { dot2_token: _ } = v; } - fn visit_match_pat_paren(state: _, v: &mut MatchPatParen) { + fn visit_match_pat_paren(state: _, v: &MatchPatParen) { let MatchPatParen { paren_token: _, pat } = v; state.visit_match_pat(pat); } - fn visit_match_pat_paren_simple(state: _, v: &mut MatchPatParen) { + fn visit_match_pat_paren_simple(state: _, v: &MatchPatParen) { let MatchPatParen { paren_token: _, pat } = v; state.visit_match_pat_simple(pat); } - fn visit_match_pat_or(state: _, v: &mut MatchPatOr) { + fn visit_match_pat_or(state: _, v: &MatchPatOr) { let MatchPatOr { leading_vert: _, cases } = v; for v in cases { state.visit_match_pat(v); } } - fn visit_match_pat_or_simple(state: _, v: &mut MatchPatOr) { + fn visit_match_pat_or_simple(state: _, v: &MatchPatOr) { let MatchPatOr { leading_vert: _, cases } = v; for v in cases { state.visit_match_pat_simple(v); } } - fn visit_match_pat_struct_field(state: _, v: &mut MatchPatStructField) { + fn visit_match_pat_struct_field(state: _, v: &MatchPatStructField) { let MatchPatStructField { field_name: _, colon_token: _, pat } = v; state.visit_match_pat_simple(pat); } - fn visit_match_pat_struct(state: _, v: &mut MatchPatStruct) { + fn visit_match_pat_struct(state: _, v: &MatchPatStruct) { let MatchPatStruct { match_span: _, path: _, brace_token: _, fields, rest: _ } = v; for v in fields { state.visit_match_pat_struct_field(v); } } - fn visit_match_pat_tuple(state: _, v: &mut MatchPatTuple) { + fn visit_match_pat_tuple(state: _, v: &MatchPatTuple) { let MatchPatTuple { paren_token: _, fields } = v; for v in fields { state.visit_match_pat_simple(v); } } - fn visit_match_pat_enum_variant(state: _, v: &mut MatchPatEnumVariant) { + fn visit_match_pat_enum_variant(state: _, v: &MatchPatEnumVariant) { let MatchPatEnumVariant { match_span:_, sim:_, @@ -95,7 +95,7 @@ visit_trait! { state.visit_match_pat_simple(v); } } - fn visit_match_pat_simple(state: _, v: &mut MatchPatSimple) { + fn visit_match_pat_simple(state: _, v: &MatchPatSimple) { match v { MatchPatSimple::Paren(v) => state.visit_match_pat_paren_simple(v), MatchPatSimple::Or(v) => state.visit_match_pat_or_simple(v), @@ -104,7 +104,7 @@ visit_trait! { MatchPatSimple::Rest(v) => state.visit_match_pat_rest(v), } } - fn visit_match_pat(state: _, v: &mut MatchPat) { + fn visit_match_pat(state: _, v: &MatchPat) { match v { MatchPat::Simple(v) => state.visit_match_pat_simple(v), MatchPat::Or(v) => state.visit_match_pat_or(v), @@ -118,15 +118,13 @@ visit_trait! { with_debug_clone_and_fold! { struct MatchPatBinding<> { - mutability: Option, ident: Ident, } } impl ToTokens for MatchPatBinding { fn to_tokens(&self, tokens: &mut TokenStream) { - let Self { mutability, ident } = self; - mutability.to_tokens(tokens); + let Self { ident } = self; ident.to_tokens(tokens); } } @@ -213,20 +211,12 @@ impl ToTokens for MatchPatStructField { colon_token, pat, } = self; - if let ( - None, - MatchPatSimple::Binding(MatchPatBinding { - mutability: _, - ident, - }), - ) = (colon_token, pat) - { + field_name.to_tokens(tokens); + if let (None, MatchPatSimple::Binding(MatchPatBinding { ident })) = (colon_token, pat) { if field_name == ident { - pat.to_tokens(tokens); return; } } - field_name.to_tokens(tokens); colon_token .unwrap_or_else(|| Token![:](field_name.span())) .to_tokens(tokens); @@ -460,7 +450,7 @@ trait ParseMatchPat: Sized { Pat::Ident(PatIdent { attrs: _, by_ref, - mut mutability, + mutability, ident, subpat, }) => { @@ -469,13 +459,10 @@ trait ParseMatchPat: Sized { .errors .error(by_ref, "ref not allowed in #[hdl] patterns"); } - if let Some(mut_token) = mutability { - if state.sim.is_none() { - state - .errors - .error(mut_token, "mut not allowed in #[hdl] patterns"); - mutability = None; // avoid duplicate errors - } + if let Some(mutability) = mutability { + state + .errors + .error(mutability, "mut not allowed in #[hdl] patterns"); } if let Some((at_token, _)) = subpat { state @@ -487,26 +474,18 @@ trait ParseMatchPat: Sized { variant_path, enum_path, variant_name, - }) => { - if let Some(mut_token) = mutability { - state - .errors - .error(mut_token, "mut not allowed on unit variants"); - } - Self::enum_variant( - state, - MatchPatEnumVariant { - match_span: state.match_span, - sim: state.sim, - variant_path, - enum_path, - variant_name, - field: None, - }, - ) - } + }) => Self::enum_variant( + state, + MatchPatEnumVariant { + match_span: state.match_span, + sim: state.sim, + variant_path, + enum_path, + variant_name, + field: None, + }, + ), Err(ident) => Ok(Self::simple(MatchPatSimple::Binding(MatchPatBinding { - mutability, ident, }))), } @@ -1001,16 +980,15 @@ struct HdlMatchParseState<'a> { struct HdlLetPatVisitState<'a> { errors: &'a mut Errors, - bindings: BTreeMap, + bindings: BTreeSet<&'a Ident>, } impl<'a> VisitMatchPat<'a> for HdlLetPatVisitState<'a> { - fn visit_match_pat_binding(&mut self, v: &'a mut MatchPatBinding) { - self.bindings.insert(v.ident.clone(), v.clone()); - v.mutability = None; + fn visit_match_pat_binding(&mut self, v: &'a MatchPatBinding) { + self.bindings.insert(&v.ident); } - fn visit_match_pat_or(&mut self, v: &'a mut MatchPatOr) { + fn visit_match_pat_or(&mut self, v: &'a MatchPatOr) { if let Some(first_inner_vert) = v.first_inner_vert() { self.errors.error( first_inner_vert, @@ -1020,7 +998,7 @@ impl<'a> VisitMatchPat<'a> for HdlLetPatVisitState<'a> { visit_match_pat_or(self, v); } - fn visit_match_pat_or_simple(&mut self, v: &'a mut MatchPatOr) { + fn visit_match_pat_or_simple(&mut self, v: &'a MatchPatOr) { if let Some(first_inner_vert) = v.first_inner_vert() { self.errors.error( first_inner_vert, @@ -1030,7 +1008,7 @@ impl<'a> VisitMatchPat<'a> for HdlLetPatVisitState<'a> { visit_match_pat_or_simple(self, v); } - fn visit_match_pat_enum_variant(&mut self, v: &'a mut MatchPatEnumVariant) { + fn visit_match_pat_enum_variant(&mut self, v: &'a MatchPatEnumVariant) { self.errors.error(v, "refutable pattern in let statement"); } } @@ -1070,7 +1048,7 @@ impl Visitor<'_> { .error(else_, "#[hdl] let ... else { ... } is not implemented"); return empty_let(); } - let Ok(mut pat) = MatchPat::parse( + let Ok(pat) = MatchPat::parse( &mut HdlMatchParseState { sim, match_span: span, @@ -1082,27 +1060,20 @@ impl Visitor<'_> { }; let mut state = HdlLetPatVisitState { errors: &mut self.errors, - bindings: BTreeMap::new(), + bindings: BTreeSet::new(), }; - state.visit_match_pat(&mut pat); + state.visit_match_pat(&pat); let HdlLetPatVisitState { errors: _, bindings, } = state; - let bindings_idents = bindings.keys(); - let bindings = bindings.values(); let retval = if sim.is_some() { parse_quote_spanned! {span=> let (#(#bindings,)*) = { type __MatchTy = ::SimValue; - let __match_value = #expr; - let __match_value = { - use ::fayalite::sim::value::match_sim_value::*; - // use method syntax to deduce the correct trait to call - ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value() - }; - #let_token #pat #eq_token __match_value #semi_token - (#(#bindings_idents,)*) + let __match_value = ::fayalite::sim::value::ToSimValue::to_sim_value(&(#expr)); + #let_token #pat #eq_token ::fayalite::sim::value::SimValue::into_value(__match_value) #semi_token + (#(#bindings,)*) }; } } else { @@ -1134,7 +1105,7 @@ impl Visitor<'_> { __match_variant, ); #let_token #pat #eq_token __match_variant #semi_token - (#(#bindings_idents,)* __scope,) + (#(#bindings,)* __scope,) }; } }; @@ -1171,13 +1142,8 @@ impl Visitor<'_> { quote_spanned! {span=> { type __MatchTy = ::SimValue; - let __match_value = #expr; - let __match_value = { - use ::fayalite::sim::value::match_sim_value::*; - // use method syntax to deduce the correct trait to call - ::fayalite::sim::value::match_sim_value::MatchSimValueHelper::new(__match_value).__fayalite_match_sim_value() - }; - #match_token __match_value { + let __match_expr = ::fayalite::sim::value::ToSimValue::to_sim_value(&(#expr)); + #match_token ::fayalite::sim::value::SimValue::into_value(__match_expr) { #(#arms)* } } diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs index 8d70d21..1fc4705 100644 --- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs +++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/destructuring.rs @@ -31,81 +31,3 @@ //! } //! } //! ``` -//! -//! You can also use `#[hdl(sim)] let` to destructure [`SimValue`]s (or anything that implements [`ToSimValue`]). -//! -//! [`SimValue`]: crate::sim::value::SimValue -//! [`ToSimValue`]: crate::sim::value::ToSimValue -//! -//! ``` -//! # use fayalite::prelude::*; -//! #[hdl] -//! struct MyStruct { -//! a: UInt<8>, -//! b: Bool, -//! c: T, -//! } -//! -//! #[hdl] -//! fn destructure(v: SimValue>) { -//! #[hdl(sim)] -//! let MyStruct:: { -//! a, -//! mut b, -//! c, -//! } = v; -//! -//! // that gives these types: -//! let _: SimValue> = a; -//! let _: SimValue = b; -//! let _: SimValue = c; -//! *b = false; // can modify b since mut was used -//! } -//! -//! #[hdl] -//! fn destructure_ref<'a, T: Type>(v: &'a SimValue>) { -//! #[hdl(sim)] -//! let MyStruct:: { -//! a, -//! b, -//! c, -//! } = v; -//! -//! // that gives these types: -//! let _: &'a SimValue> = a; -//! let _: &'a SimValue = b; -//! let _: &'a SimValue = c; -//! } -//! -//! #[hdl] -//! fn destructure_mut<'a, T: Type>(v: &'a mut SimValue>) { -//! #[hdl(sim)] -//! let MyStruct:: { -//! a, -//! b, -//! c, -//! } = v; -//! -//! **b = true; // you can modify v by modifying b which borrows from it -//! -//! // that gives these types: -//! let _: &'a mut SimValue> = a; -//! let _: &'a mut SimValue = b; -//! let _: &'a mut SimValue = c; -//! } -//! -//! #[hdl] -//! fn destructure_to_sim_value<'a, T: Type>(v: impl ToSimValue>) { -//! #[hdl(sim)] -//! let MyStruct:: { -//! a, -//! b, -//! c, -//! } = v; -//! -//! // that gives these types: -//! let _: SimValue> = a; -//! let _: SimValue = b; -//! let _: SimValue = c; -//! } -//! ``` diff --git a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs index accd3d7..6df70f1 100644 --- a/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs +++ b/crates/fayalite/src/_docs/modules/module_bodies/hdl_match_statements.rs @@ -9,78 +9,3 @@ //! //! `#[hdl] match` statements can only match one level of struct/tuple/enum pattern for now, //! e.g. you can match with the pattern `HdlSome(v)`, but not `HdlSome(HdlSome(_))`. -//! -//! You can also use `#[hdl(sim)] match` to match [`SimValue`]s (or anything that implements [`ToSimValue`]). -//! -//! `#[hdl(sim)] match` statements' bodies may have any type, unlike `#[hdl] match`. -//! -//! [`SimValue`]: crate::sim::value::SimValue -//! [`ToSimValue`]: crate::sim::value::ToSimValue -//! -//! ``` -//! # use fayalite::prelude::*; -//! #[hdl] -//! enum MyEnum { -//! A, -//! B(Bool), -//! C(T), -//! } -//! -//! #[hdl] -//! fn match_move(v: SimValue>) -> String { -//! #[hdl(sim)] -//! match v { -//! MyEnum::::A => String::from("got A"), -//! MyEnum::::B(mut b) => { -//! let _: SimValue = b; // b has this type -//! let text = format!("got B({b})"); -//! *b = true; // can modify b since mut was used -//! text -//! } -//! _ => String::from("something else"), -//! } -//! } -//! -//! #[hdl] -//! fn match_ref<'a, T: Type>(v: &'a SimValue>) -> u32 { -//! #[hdl(sim)] -//! match v { -//! MyEnum::::A => 1, -//! MyEnum::::B(b) => { -//! let _: &'a SimValue = b; // b has this type -//! println!("got B({b})"); -//! 5 -//! } -//! _ => 42, -//! } -//! } -//! -//! #[hdl] -//! fn match_mut<'a, T: Type>(v: &'a mut SimValue>) -> Option<&'a mut SimValue> { -//! #[hdl(sim)] -//! match v { -//! MyEnum::::A => None, -//! MyEnum::::B(b) => { -//! println!("got B({b})"); -//! **b = true; // you can modify v by modifying b which borrows from it -//! let _: &'a mut SimValue = b; // b has this type -//! None -//! } -//! MyEnum::::C(v) => Some(v), // you can return matched values -//! _ => None, // HDL enums can have invalid discriminants, so we need this extra match arm -//! } -//! } -//! -//! #[hdl] -//! fn match_to_sim_value<'a, T: Type>(v: impl ToSimValue>) { -//! #[hdl(sim)] -//! match v { -//! MyEnum::::A => println!("got A"), -//! MyEnum::::B(b) => { -//! let _: SimValue = b; // b has this type -//! println!("got B({b})"); -//! } -//! _ => println!("something else"), -//! } -//! } -//! ``` diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs index 0edf192..a0de189 100644 --- a/crates/fayalite/src/bundle.rs +++ b/crates/fayalite/src/bundle.rs @@ -271,6 +271,7 @@ impl Type for Bundle { pub trait BundleType: Type { type Builder: Default; + type FilledBuilder: ToExpr; fn fields(&self) -> Interned<[BundleField]>; } @@ -373,8 +374,17 @@ impl<'a> BundleSimValueToOpaque<'a> { #[derive(Default)] pub struct NoBuilder; +pub struct Unfilled(PhantomData); + +impl Default for Unfilled { + fn default() -> Self { + Self(PhantomData) + } +} + impl BundleType for Bundle { type Builder = NoBuilder; + type FilledBuilder = Expr; fn fields(&self) -> Interned<[BundleField]> { self.0.fields } @@ -410,14 +420,15 @@ macro_rules! impl_tuple_builder_fields { ) => { impl< $($head_type_var,)* + $cur_type_var: Type, $($tail_type_var,)* > TupleBuilder<( $($head_type_var,)* - (), + Unfilled<$cur_type_var>, $($tail_type_var,)* )> { - pub fn $cur_field<$cur_type_var: Type>(self, $cur_var: impl ToExpr) -> TupleBuilder<( + pub fn $cur_field(self, $cur_var: impl ToExpr) -> TupleBuilder<( $($head_type_var,)* Expr<$cur_type_var>, $($tail_type_var,)* @@ -441,12 +452,6 @@ macro_rules! impl_tuple_builder_fields { ($global:tt []) => {}; } -macro_rules! get_unit_ty { - ($($tt:tt)*) => { - () - }; -} - macro_rules! impl_tuples { ( [$({ @@ -540,7 +545,8 @@ macro_rules! impl_tuples { } } impl<$($T: Type,)*> BundleType for ($($T,)*) { - type Builder = TupleBuilder<($(get_unit_ty!($T),)*)>; + type Builder = TupleBuilder<($(Unfilled<$T>,)*)>; + type FilledBuilder = TupleBuilder<($(Expr<$T>,)*)>; fn fields(&self) -> Interned<[BundleField]> { let ($($var,)*) = self; [$(BundleField { name: stringify!($num).intern(), flipped: false, ty: $var.canonical() }),*].intern_slice() @@ -785,6 +791,7 @@ impl ToExpr for PhantomDataBuilder { impl BundleType for PhantomData { type Builder = PhantomDataBuilder; + type FilledBuilder = PhantomDataBuilder; fn fields(&self) -> Interned<[BundleField]> { Interned::default() } diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs index 59fbec7..cca0d82 100644 --- a/crates/fayalite/src/firrtl.rs +++ b/crates/fayalite/src/firrtl.rs @@ -2326,7 +2326,6 @@ impl<'a> Exporter<'a> { ModuleBody::Extern(ExternModuleBody { verilog_name, parameters, - clocks_for_past: _, simulation: _, }) => { let verilog_name = Ident(verilog_name); diff --git a/crates/fayalite/src/int/uint_in_range.rs b/crates/fayalite/src/int/uint_in_range.rs index 4ed101e..970a439 100644 --- a/crates/fayalite/src/int/uint_in_range.rs +++ b/crates/fayalite/src/int/uint_in_range.rs @@ -96,6 +96,7 @@ impl Type for UIntInRangeMaskType { impl BundleType for UIntInRangeMaskType { type Builder = NoBuilder; + type FilledBuilder = Expr; fn fields(&self) -> Interned<[BundleField]> { let [value_name, range_name] = UINT_IN_RANGE_TYPE_FIELD_NAMES; @@ -299,7 +300,9 @@ macro_rules! define_uint_in_range_type { } } pub fn new(start: Start::SizeType, end: End::SizeType) -> Self { - Self::from_phantom_const_range(PhantomConst::new_sized($SerdeRange { start, end })) + Self::from_phantom_const_range(PhantomConst::new( + $SerdeRange { start, end }.intern_sized(), + )) } pub fn bit_width(self) -> usize { self.value.width() @@ -399,6 +402,7 @@ macro_rules! define_uint_in_range_type { impl BundleType for $UIntInRangeType { type Builder = NoBuilder; + type FilledBuilder = Expr; fn fields(&self) -> Interned<[BundleField]> { let [value_name, range_name] = UINT_IN_RANGE_TYPE_FIELD_NAMES; diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs index 156aeed..96ee1f7 100644 --- a/crates/fayalite/src/lib.rs +++ b/crates/fayalite/src/lib.rs @@ -152,7 +152,7 @@ pub use fayalite_proc_macros::hdl_module; /// This allows you to use some computed property of a [`PhantomConst`] to get a [`Type`] that you can use in other #[hdl] types. /// /// ``` -/// # use fayalite::prelude::*; +/// # use fayalite::{intern::Intern, prelude::*}; /// #[derive(Clone, PartialEq, Eq, Hash, Debug, serde::Serialize, serde::Deserialize)] /// pub struct Config { /// pub foo: usize, @@ -172,7 +172,7 @@ pub use fayalite_proc_macros::hdl_module; /// /// // you can then use Fayalite's standard syntax for creating dynamic types at runtime: /// let bar = Bundle::new(Default::default()); -/// let config = PhantomConst::new_sized(Config { foo: 12, bar }); +/// let config = PhantomConst::new(Config { foo: 12, bar }.intern_sized()); /// let ty = WrapMyArray[config]; /// assert_eq!(ty.my_array, Array[bar][12]); /// ``` @@ -182,7 +182,7 @@ pub use fayalite_proc_macros::hdl_module; /// This allows you to use some computed property of a [`PhantomConst`] to get a [`Size`] that you can use in other #[hdl] types. /// /// ``` -/// # use fayalite::prelude::*; +/// # use fayalite::{intern::Intern, prelude::*}; /// # #[derive(Clone, PartialEq, Eq, Hash, Debug, serde::Serialize, serde::Deserialize)] /// # pub struct ConfigItem {} /// # impl ConfigItem { @@ -207,7 +207,7 @@ pub use fayalite_proc_macros::hdl_module; /// } /// /// // you can then use Fayalite's standard syntax for creating dynamic types at runtime: -/// let config = PhantomConst::new_sized(Config { items: vec![ConfigItem::new(); 5] }); +/// let config = PhantomConst::new(Config { items: vec![ConfigItem::new(); 5] }.intern_sized()); /// let ty = FlagPerItem[config]; /// assert_eq!(ty.flags, Array[Bool][5]); /// ``` diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs index 5ffeaae..6527043 100644 --- a/crates/fayalite/src/module.rs +++ b/crates/fayalite/src/module.rs @@ -41,6 +41,7 @@ use std::{ marker::PhantomData, mem, num::NonZeroU64, + ops::Deref, rc::Rc, sync::atomic::AtomicU64, }; @@ -66,8 +67,6 @@ pub trait ModuleBuildingStatus: type ModuleBody: fmt::Debug; type StmtAnnotations: 'static + Send + Sync + Copy + Eq + Hash + fmt::Debug; type ModuleIOAnnotations; - type ExternModuleParameters: fmt::Debug; - type ExternModuleClocksForPast: fmt::Debug; } #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash, Default)] @@ -80,8 +79,6 @@ impl ModuleBuildingStatus for ModuleBuilt { type ModuleBody = Block; type StmtAnnotations = Interned<[TargetedAnnotation]>; type ModuleIOAnnotations = Interned<[TargetedAnnotation]>; - type ExternModuleParameters = Interned<[ExternModuleParameter]>; - type ExternModuleClocksForPast = Interned<[Target]>; } #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash, Default)] @@ -94,8 +91,6 @@ impl ModuleBuildingStatus for ModuleBuilding { type ModuleBody = BuilderModuleBody; type StmtAnnotations = (); type ModuleIOAnnotations = Vec; - type ExternModuleParameters = Vec; - type ExternModuleClocksForPast = Vec; } #[derive(Debug)] @@ -1085,65 +1080,26 @@ impl From for ModuleBody { } } -#[track_caller] -fn validate_clock_for_past( - clock_for_past: Option, - module_io: &[AnnotatedModuleIO], -) -> Target { - if let Some(clock_for_past) = clock_for_past { - assert_eq!( - clock_for_past.canonical_ty(), - Clock.canonical(), - "clock_for_past: clock is not of type Clock", - ); - if clock_for_past - .base() - .module_io() - .is_some_and(|v| module_io.iter().any(|module_io| module_io.module_io == *v)) - { - let mut target = clock_for_past; - while let Target::Child(child) = target { - match *child.path_element() { - TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {} - TargetPathElement::DynArrayElement(_) => { - panic!( - "clock_for_past: clock must be a static target (you can't use `Expr` array indexes):\n{clock_for_past:?}" - ); - } - } - target = *child.parent(); - } - return clock_for_past; - } - } - panic!("clock_for_past: clock must be some part of this module's I/O:\n{clock_for_past:?}"); -} - #[derive(PartialEq, Eq, Hash, Copy, Clone, Debug)] -pub struct ExternModuleBody { +pub struct ExternModuleBody< + P: Deref = Interned<[ExternModuleParameter]>, +> { pub verilog_name: Interned, - pub parameters: S::ExternModuleParameters, - /// [`Clock`]s that the [`Simulation`] will store the past values of all [`ModuleIO`] for. - /// - /// [`Simulation`]: crate::sim::Simulation - pub clocks_for_past: S::ExternModuleClocksForPast, + pub parameters: P, pub simulation: Option, } -impl From> for ExternModuleBody { - fn from(value: ExternModuleBody) -> Self { +impl From>> for ExternModuleBody { + fn from(value: ExternModuleBody>) -> Self { let ExternModuleBody { verilog_name, parameters, - clocks_for_past, simulation, } = value; let parameters = Intern::intern_owned(parameters); - let clocks_for_past = Intern::intern_owned(clocks_for_past); Self { verilog_name, parameters, - clocks_for_past, simulation, } } @@ -1156,12 +1112,15 @@ impl From for ModuleBody { } #[derive(Debug)] -pub enum ModuleBody { +pub enum ModuleBody< + S: ModuleBuildingStatus = ModuleBuilt, + P: Deref = Interned<[ExternModuleParameter]>, +> { Normal(NormalModuleBody), - Extern(ExternModuleBody), + Extern(ExternModuleBody

), } -pub(crate) type ModuleBodyBuilding = ModuleBody; +pub(crate) type ModuleBodyBuilding = ModuleBody>; impl ModuleBodyBuilding { pub(crate) fn builder_normal_body_opt( @@ -1182,7 +1141,9 @@ impl ModuleBodyBuilding { } } #[track_caller] - pub(crate) fn builder_extern_body(&mut self) -> &mut ExternModuleBody { + pub(crate) fn builder_extern_body( + &mut self, + ) -> &mut ExternModuleBody> { if let Self::Extern(v) = self { v } else { @@ -1336,13 +1297,11 @@ impl fmt::Debug for DebugModuleBody { ModuleBody::Extern(ExternModuleBody { verilog_name, parameters, - clocks_for_past, simulation, }) => { debug_struct .field("verilog_name", verilog_name) .field("parameters", parameters) - .field("clocks_for_past", clocks_for_past) .field("simulation", simulation); } } @@ -1821,13 +1780,8 @@ impl AssertValidityState { ModuleBody::Extern(ExternModuleBody { verilog_name: _, parameters: _, - clocks_for_past, simulation: _, - }) => { - for clock_for_past in clocks_for_past { - validate_clock_for_past(Some(clock_for_past), &self.module.module_io); - } - } + }) => {} ModuleBody::Normal(NormalModuleBody { body }) => { let body = self.make_block_index(body); assert_eq!(body, 0); @@ -1857,17 +1811,9 @@ impl Module { match &mut body { ModuleBody::Normal(_) => {} ModuleBody::Extern(ExternModuleBody { - verilog_name: _, - parameters: _, - clocks_for_past, simulation: Some(simulation), + .. }) => { - let mut clocks_for_past_set = HashSet::default(); - *clocks_for_past = clocks_for_past - .iter() - .copied() - .filter(|clock_for_past| clocks_for_past_set.insert(*clock_for_past)) - .collect(); if module_io.iter().any(|io| { !simulation .sim_io_to_generator_map @@ -2240,7 +2186,6 @@ impl ModuleBuilder { ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody { verilog_name: name.0, parameters: vec![], - clocks_for_past: vec![], simulation: None, }), ModuleKind::Normal => ModuleBody::Normal(NormalModuleBody { @@ -2363,20 +2308,6 @@ impl ModuleBuilder { value: ExternModuleParameterValue::RawVerilog(raw_verilog.intern()), }); } - /// registers a [`Clock`] so you can use it with the [`ExternModuleSimulationState::read_past()`] family of functions. - /// - /// [`ExternModuleSimulationState::read_past()`]: crate::sim::ExternModuleSimulationState::read_past() - #[track_caller] - pub fn register_clock_for_past(&self, clock_for_past: impl ToExpr) { - let clock_for_past = clock_for_past.to_expr().target().as_deref().copied(); - let mut impl_ = self.impl_.borrow_mut(); - let clock_for_past = validate_clock_for_past(clock_for_past, &impl_.io); - impl_ - .body - .builder_extern_body() - .clocks_for_past - .push(clock_for_past); - } #[track_caller] pub fn extern_module_simulation(&self, generator: G) { let mut impl_ = self.impl_.borrow_mut(); diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs index bd4e939..e84d835 100644 --- a/crates/fayalite/src/module/transform/deduce_resets.rs +++ b/crates/fayalite/src/module/transform/deduce_resets.rs @@ -2073,7 +2073,6 @@ impl_run_pass_for_struct! { impl[] RunPass for ExternModuleBody { verilog_name: _, parameters: _, - clocks_for_past: _, simulation: _, } } diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs index eb6a758..9f25166 100644 --- a/crates/fayalite/src/phantom_const.rs +++ b/crates/fayalite/src/phantom_const.rs @@ -131,7 +131,7 @@ impl Index for PhantomConstWithoutGenerics { type Output = PhantomConst; fn index(&self, value: T) -> &Self::Output { - Interned::into_inner(PhantomConst::new(&value).intern_sized()) + Interned::into_inner(PhantomConst::new(value.intern()).intern_sized()) } } @@ -222,26 +222,11 @@ impl Memoize for PhantomConstCanonicalMemoize PhantomConst { - pub fn new_interned(value: Interned) -> Self { + pub fn new(value: Interned) -> Self { Self { value: LazyInterned::Interned(value), } } - pub fn new_sized(value: T) -> Self - where - T: Clone, - { - Self::new_interned(value.intern_sized()) - } - pub fn new(value: &T) -> Self { - Self::new_interned(value.intern()) - } - pub fn new_deref>(value: U) -> Self - where - T: ToOwned, - { - Self::new_interned(value.intern_deref()) - } pub const fn new_lazy(v: &'static dyn LazyInternedTrait) -> Self { Self { value: LazyInterned::new_lazy(v), @@ -260,7 +245,7 @@ impl PhantomConst { if let Some(&retval) = ::downcast_ref::(&self) { return retval; } - ::new_interned( + ::new( PhantomConstCanonicalMemoize::(PhantomData).get_owned(self.get()), ) } @@ -268,7 +253,7 @@ impl PhantomConst { if let Some(&retval) = ::downcast_ref::(&canonical_type) { return retval; } - Self::new_interned( + Self::new( PhantomConstCanonicalMemoize::(PhantomData).get_owned(canonical_type.get()), ) } @@ -361,9 +346,7 @@ impl<'de, T: ?Sized + PhantomConstValue> Deserialize<'de> for PhantomConst { D: Deserializer<'de>, { match SerdeType::::deserialize(deserializer)? { - SerdeCanonicalType::PhantomConst(SerdePhantomConst(value)) => { - Ok(Self::new_interned(value)) - } + SerdeCanonicalType::PhantomConst(SerdePhantomConst(value)) => Ok(Self::new(value)), ty => Err(Error::invalid_value( serde::de::Unexpected::Other(ty.as_serde_unexpected_str()), &"a PhantomConst", diff --git a/crates/fayalite/src/platform/peripherals.rs b/crates/fayalite/src/platform/peripherals.rs index 387142d..90c6640 100644 --- a/crates/fayalite/src/platform/peripherals.rs +++ b/crates/fayalite/src/platform/peripherals.rs @@ -1,7 +1,7 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information -use crate::prelude::*; +use crate::{intern::Intern, prelude::*}; use ordered_float::NotNan; use serde::{Deserialize, Serialize}; @@ -26,9 +26,12 @@ impl ClockInput { ); Self { clk: Clock, - properties: PhantomConst::new_sized(ClockInputProperties { - frequency: NotNan::new(frequency).expect("just checked"), - }), + properties: PhantomConst::new( + ClockInputProperties { + frequency: NotNan::new(frequency).expect("just checked"), + } + .intern_sized(), + ), } } pub fn frequency(self) -> f64 { diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 808ead4..44030c1 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -24,7 +24,7 @@ use crate::{ sim::{ compiler::{ Compiled, CompiledBundleField, CompiledExternModule, CompiledTypeLayoutBody, - CompiledValue, ExternModuleClockForPast, + CompiledValue, }, interpreter::{ BreakAction, BreakpointsSet, RunResult, SmallUInt, State, @@ -48,18 +48,17 @@ use num_traits::{Signed, Zero}; use std::{ any::Any, borrow::Cow, - cell::{Cell, RefCell}, - collections::{BTreeMap, BTreeSet}, + cell::RefCell, + collections::BTreeMap, fmt, future::{Future, IntoFuture}, hash::Hash, mem, - pin::{Pin, pin}, + pin::Pin, ptr, rc::Rc, - sync::{Arc, Mutex, MutexGuard}, + sync::Arc, task::Poll, - usize, }; pub mod compiler; @@ -416,15 +415,6 @@ impl_trace_decl! { name: Interned, flow: Flow, }), - PhantomConst(TracePhantomConst { - fn location(self) -> _ { - self.location - } - location: TraceLocation, - name: Interned, - ty: PhantomConst, - flow: Flow, - }), SimOnly(TraceSimOnly { fn location(self) -> _ { self.location @@ -535,11 +525,6 @@ pub trait TraceWriter: fmt::Debug + 'static { variant_index: usize, ty: Enum, ) -> Result<(), Self::Error>; - fn set_signal_phantom_const( - &mut self, - id: TraceScalarId, - ty: PhantomConst, - ) -> Result<(), Self::Error>; fn set_signal_sim_only_value( &mut self, id: TraceScalarId, @@ -599,11 +584,6 @@ trait TraceWriterDynTrait: fmt::Debug + 'static { variant_index: usize, ty: Enum, ) -> std::io::Result<()>; - fn set_signal_phantom_const_dyn( - &mut self, - id: TraceScalarId, - ty: PhantomConst, - ) -> std::io::Result<()>; fn set_signal_sim_only_value_dyn( &mut self, id: TraceScalarId, @@ -668,13 +648,6 @@ impl TraceWriterDynTrait for T { .map_err(err_into_io)?, ) } - fn set_signal_phantom_const_dyn( - &mut self, - id: TraceScalarId, - ty: PhantomConst, - ) -> std::io::Result<()> { - Ok(TraceWriter::set_signal_phantom_const(self, id, ty).map_err(err_into_io)?) - } fn set_signal_sim_only_value_dyn( &mut self, id: TraceScalarId, @@ -746,13 +719,6 @@ impl TraceWriter for DynTraceWriter { self.0 .set_signal_enum_discriminant_dyn(id, variant_index, ty) } - fn set_signal_phantom_const( - &mut self, - id: TraceScalarId, - ty: PhantomConst, - ) -> Result<(), Self::Error> { - self.0.set_signal_phantom_const_dyn(id, ty) - } fn set_signal_sim_only_value( &mut self, id: TraceScalarId, @@ -928,16 +894,12 @@ pub(crate) enum SimTraceKind { index: StatePartIndex, ty: DynSimOnly, }, - PhantomConst { - ty: PhantomConst, - }, } #[derive(PartialEq, Eq)] pub(crate) enum SimTraceState { Bits(BitVec), SimOnly(DynSimOnlyValue), - PhantomConst, } impl Clone for SimTraceState { @@ -945,7 +907,6 @@ impl Clone for SimTraceState { match self { Self::Bits(v) => Self::Bits(v.clone()), Self::SimOnly(v) => Self::SimOnly(v.clone()), - Self::PhantomConst => Self::PhantomConst, } } fn clone_from(&mut self, source: &Self) { @@ -994,7 +955,6 @@ impl fmt::Debug for SimTraceState { match self { SimTraceState::Bits(v) => BitSliceWriteWithBase(v).fmt(f), SimTraceState::SimOnly(v) => v.fmt(f), - SimTraceState::PhantomConst => f.debug_tuple("PhantomConst").finish(), } } } @@ -1021,7 +981,6 @@ impl SimTraceKind { SimTraceKind::EnumDiscriminant { index: _, ty } => { SimTraceState::Bits(BitVec::repeat(false, ty.discriminant_bit_width())) } - SimTraceKind::PhantomConst { .. } => SimTraceState::PhantomConst, SimTraceKind::SimOnly { index: _, ty } => SimTraceState::SimOnly(ty.default_value()), } } @@ -1040,12 +999,6 @@ impl MaybeNeedsSettle { MaybeNeedsSettle::NoSettleNeeded(v) => MaybeNeedsSettle::NoSettleNeeded(f(v)), } } - fn into_inner(self) -> T { - match self { - MaybeNeedsSettle::NeedsSettle(v) => v, - MaybeNeedsSettle::NoSettleNeeded(v) => v, - } - } } // workaround implementing FnOnce not being stable @@ -1080,7 +1033,6 @@ struct SimulationModuleState { uninitialized_ios: HashMap>, io_targets: HashMap>, did_initial_settle: bool, - clocks_for_past: HashMap, SimulationExternModuleClockForPast>, } impl fmt::Debug for SimulationModuleState { @@ -1090,37 +1042,23 @@ impl fmt::Debug for SimulationModuleState { uninitialized_ios, io_targets, did_initial_settle, - clocks_for_past, } = self; f.debug_struct("SimulationModuleState") .field("base_targets", base_targets) .field("uninitialized_ios", &SortedSetDebug(uninitialized_ios)) .field("io_targets", &SortedSetDebug(io_targets)) .field("did_initial_settle", did_initial_settle) - .field("clocks_for_past", &SortedMapDebug(clocks_for_past)) .finish() } } impl SimulationModuleState { - fn new( - base_targets: impl IntoIterator)>, - clocks_for_past: &[ExternModuleClockForPast], - ) -> Self { + fn new(base_targets: impl IntoIterator)>) -> Self { let mut retval = Self { base_targets: Vec::new(), uninitialized_ios: HashMap::default(), io_targets: HashMap::default(), did_initial_settle: false, - clocks_for_past: clocks_for_past - .iter() - .map(|clock_for_past| { - ( - clock_for_past.clock_for_past, - SimulationExternModuleClockForPast::new(clock_for_past), - ) - }) - .collect(), }; for (base_target, value) in base_targets { retval.base_targets.push(base_target); @@ -1158,7 +1096,6 @@ impl SimulationModuleState { true } } - CompiledTypeLayoutBody::PhantomConst => false, CompiledTypeLayoutBody::Bundle { .. } => { let value = value.map_ty(Bundle::from_canonical); let mut sub_targets = Vec::new(); @@ -1249,34 +1186,7 @@ impl SimulationModuleState { } } #[track_caller] - fn is_reset_async(&self, io: Expr, which_module: WhichModule) -> bool { - let Some(target) = io.target() else { - match which_module { - WhichModule::Main => panic!( - "can't read from an expression that's not a field/element of `Simulation::io()`" - ), - WhichModule::Extern { .. } => panic!( - "can't read from an expression that's not based on one of this module's inputs/outputs" - ), - } - }; - match self.get_io(*target, which_module).layout.ty { - CanonicalType::UInt(_) - | CanonicalType::SInt(_) - | CanonicalType::Bool(_) - | CanonicalType::Array(_) - | CanonicalType::Enum(_) - | CanonicalType::Bundle(_) - | CanonicalType::Reset(_) - | CanonicalType::Clock(_) - | CanonicalType::PhantomConst(_) - | CanonicalType::DynSimOnly(_) => unreachable!(), - CanonicalType::AsyncReset(_) => true, - CanonicalType::SyncReset(_) => false, - } - } - #[track_caller] - fn read_helper_current( + fn read_helper( &self, io: Expr, which_module: WhichModule, @@ -1321,33 +1231,6 @@ impl SimulationModuleState { } } #[track_caller] - fn read_helper( - &self, - io: Expr, - read_time: ReadTime, - which_module: WhichModule, - ) -> MaybeNeedsSettle> { - match read_time { - ReadTime::Current => self.read_helper_current(io, which_module), - ReadTime::Past { clock_for_past } => { - let current = self.read_helper_current(io, which_module); - let clock_for_past_value = self - .read_helper_current(Expr::canonical(clock_for_past), which_module) - .into_inner() - .map_ty(Clock::from_canonical); - let Some(clock_for_past) = self.clocks_for_past.get(&clock_for_past_value) else { - panic!( - "In order to use the `read_past()` family of functions,\n\ - you must call `m.register_clock_for_past(my_io.clk)`\n\ - in the module's body for every clock you use as the\n\ - second argument of the `read_past()` family." - ); - }; - current.map(|current| clock_for_past.current_to_past_map[¤t]) - } - } - } - #[track_caller] fn write_helper( &mut self, io: Expr, @@ -1379,71 +1262,149 @@ impl SimulationModuleState { } } -struct SimulationExternModuleClockForPast { - current_to_past_map: HashMap, CompiledValue>, +#[derive(Copy, Clone, Debug)] +enum WaitTarget { + Settle, + Instant(SimInstant), + Change { key: ChangeKey, value: ChangeValue }, } -impl fmt::Debug for SimulationExternModuleClockForPast { +#[derive(Clone)] +struct EarliestWaitTargets { + settle: bool, + instant: Option, + changes: HashMap, SimValue>, +} + +impl fmt::Debug for EarliestWaitTargets { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - current_to_past_map, - } = self; - f.debug_struct("SimulationExternModuleClockForPast") - .field("current_to_past_map", &SortedMapDebug(current_to_past_map)) - .finish() + f.debug_set().entries(self.iter()).finish() } } -impl SimulationExternModuleClockForPast { - fn new(clock_for_past: &ExternModuleClockForPast) -> Self { - let mut retval = Self { - current_to_past_map: HashMap::default(), - }; - for (current, past) in clock_for_past.current_to_past_map { - retval.add_current_to_past_mapping(current, past); +impl Default for EarliestWaitTargets { + fn default() -> Self { + Self { + settle: false, + instant: None, + changes: HashMap::default(), } + } +} + +impl EarliestWaitTargets { + fn settle() -> Self { + Self { + settle: true, + instant: None, + changes: HashMap::default(), + } + } + fn instant(instant: SimInstant) -> Self { + Self { + settle: false, + instant: Some(instant), + changes: HashMap::default(), + } + } + fn len(&self) -> usize { + self.settle as usize + self.instant.is_some() as usize + self.changes.len() + } + fn is_empty(&self) -> bool { + self.len() == 0 + } + fn clear(&mut self) { + let Self { + settle, + instant, + changes, + } = self; + *settle = false; + *instant = None; + changes.clear(); + } + fn insert( + &mut self, + value: impl std::borrow::Borrow, ChangeValue>>, + ) where + ChangeValue: std::borrow::Borrow>, + { + let value = value.borrow(); + match value { + WaitTarget::Settle => self.settle = true, + WaitTarget::Instant(instant) => { + if self.instant.is_none_or(|v| v > *instant) { + self.instant = Some(*instant); + } + } + WaitTarget::Change { key, value } => { + self.changes + .entry(*key) + .or_insert_with(|| value.borrow().clone()); + } + } + } + fn convert_earlier_instants_to_settle(&mut self, instant: SimInstant) { + if self.instant.is_some_and(|v| v <= instant) { + self.settle = true; + self.instant = None; + } + } + fn iter<'a>( + &'a self, + ) -> impl Clone + + Iterator, &'a SimValue>> + + 'a { + self.settle + .then_some(WaitTarget::Settle) + .into_iter() + .chain(self.instant.map(|instant| WaitTarget::Instant(instant))) + .chain( + self.changes + .iter() + .map(|(&key, value)| WaitTarget::Change { key, value }), + ) + } +} + +impl>> + Extend, ChangeValue>> for EarliestWaitTargets +{ + fn extend, ChangeValue>>>( + &mut self, + iter: T, + ) { + iter.into_iter().for_each(|v| self.insert(v)) + } +} + +impl<'a, ChangeValue: std::borrow::Borrow>> + Extend<&'a WaitTarget, ChangeValue>> for EarliestWaitTargets +{ + fn extend, ChangeValue>>>( + &mut self, + iter: T, + ) { + iter.into_iter().for_each(|v| self.insert(v)) + } +} + +impl FromIterator for EarliestWaitTargets +where + Self: Extend, +{ + fn from_iter>(iter: T) -> Self { + let mut retval = Self::default(); + retval.extend(iter); retval } - fn add_current_to_past_mapping( - &mut self, - current: CompiledValue, - past: CompiledValue, - ) { - self.current_to_past_map.insert(current, past); - match current.layout.body { - CompiledTypeLayoutBody::Scalar | CompiledTypeLayoutBody::PhantomConst => {} - CompiledTypeLayoutBody::Array { .. } => { - let current = current.map_ty(Array::from_canonical); - let past = past.map_ty(Array::from_canonical); - for index in 0..current.layout.ty.len() { - self.add_current_to_past_mapping(current.element(index), past.element(index)); - } - } - CompiledTypeLayoutBody::Bundle { .. } => { - let current = current.map_ty(Bundle::from_canonical); - let past = past.map_ty(Bundle::from_canonical); - for BundleField { name, .. } in current.layout.ty.fields() { - self.add_current_to_past_mapping( - current.field_by_name(name), - past.field_by_name(name), - ); - } - } - } - } -} - -enum ReadTime { - Current, - Past { clock_for_past: Expr }, } struct SimulationExternModuleState { module_state: SimulationModuleState, sim: ExternModuleSimulation, running_generator: Option + 'static>>>, - waker: Arc, - debug_name: Interned, + wait_targets: EarliestWaitTargets, } impl fmt::Debug for SimulationExternModuleState { @@ -1452,8 +1413,7 @@ impl fmt::Debug for SimulationExternModuleState { module_state, sim, running_generator, - waker: _, - debug_name: _, + wait_targets, } = self; f.debug_struct("SimulationExternModuleState") .field("module_state", module_state) @@ -1462,6 +1422,7 @@ impl fmt::Debug for SimulationExternModuleState { "running_generator", &running_generator.as_ref().map(|_| DebugAsDisplay("...")), ) + .field("wait_targets", wait_targets) .finish() } } @@ -1528,350 +1489,28 @@ impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadFn { } } -#[derive(Copy, Clone, PartialEq, Eq, Debug)] -enum EventKind { - State, - ExternModule(usize), -} +struct GeneratorWaker; -impl PartialOrd for EventKind { - fn partial_cmp(&self, other: &Self) -> Option { - Some(self.cmp(other)) - } -} - -impl Ord for EventKind { - fn cmp(&self, other: &Self) -> std::cmp::Ordering { - match (self, other) { - (Self::State, Self::State) => std::cmp::Ordering::Equal, - (Self::State, Self::ExternModule(_)) => std::cmp::Ordering::Less, - (Self::ExternModule(_), Self::State) => std::cmp::Ordering::Greater, - (Self::ExternModule(this), Self::ExternModule(other)) => this.cmp(other), - } - } -} - -#[derive(Copy, Clone, PartialEq, Eq, Debug)] -struct Event { - instant: SimInstant, - kind: EventKind, -} - -impl PartialOrd for Event { - fn partial_cmp(&self, other: &Self) -> Option { - Some(self.cmp(other)) - } -} - -impl Ord for Event { - fn cmp(&self, other: &Self) -> std::cmp::Ordering { - let Self { instant, kind } = other; - self.instant.cmp(instant).then(self.kind.cmp(kind)) - } -} - -struct HashableWaker(std::task::Waker); - -impl Clone for HashableWaker { - fn clone(&self) -> Self { - Self(self.0.clone()) - } - - fn clone_from(&mut self, source: &Self) { - self.0.clone_from(&source.0); - } -} - -impl PartialEq for HashableWaker { - fn eq(&self, other: &Self) -> bool { - self.0.will_wake(&other.0) - } -} - -impl Eq for HashableWaker {} - -impl Hash for HashableWaker { - fn hash(&self, state: &mut H) { - self.0.data().hash(state); - let vtable: *const std::task::RawWakerVTable = self.0.vtable(); - vtable.hash(state); - } -} - -enum EventWakers { - Wakers(HashSet), - CurrentlyWaking, -} - -impl EventWakers { - fn start_waking(&mut self) -> HashSet { - match std::mem::replace(self, Self::CurrentlyWaking) { - Self::Wakers(retval) => retval, - Self::CurrentlyWaking => unreachable!(), - } - } -} - -impl fmt::Debug for EventWakers { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - match self { - Self::Wakers(wakers) => f.debug_tuple("Wakers").field(&wakers.len()).finish(), - Self::CurrentlyWaking => write!(f, "CurrentlyWaking"), - } - } -} - -struct EventQueueData { - instant: SimInstant, - events: BTreeMap, - trace: bool, -} - -impl fmt::Debug for EventQueueData { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - instant, - events, - trace: _, - } = self; - f.debug_struct("EventQueueData") - .field("instant", instant) - .field("events", events) - .finish() - } -} - -struct EventQueueFirstEvent<'a> { - event_queue: Arc, - event_queue_lock: MutexGuard<'a, EventQueueData>, -} - -impl<'a> EventQueueFirstEvent<'a> { - fn event(&self) -> &Event { - self.event_queue_lock - .events - .first_key_value() - .expect("known to be non-empty") - .0 - } - fn remove_and_wake_all_wakers(self) { - let Self { - event_queue, - mut event_queue_lock, - } = self; - let trace = event_queue_lock.trace; - let mut entry = event_queue_lock - .events - .first_entry() - .expect("known to be non-empty"); - let wakers = entry.get_mut().start_waking(); - let event = *entry.key(); - if wakers.is_empty() { - entry.remove(); - if trace { - println!( - "EventQueue first_event remove_and_wake_all_wakers(): event={event:?} no wakers", - ); - } - drop(event_queue_lock); - return; - } - drop(event_queue_lock); - if trace { - println!( - "EventQueue first_event remove_and_wake_all_wakers(): event={event:?} wakers_len={}", - wakers.len() - ); - } - for waker in wakers { - waker.0.wake(); - } - event_queue.lock().events.remove(&event); - if trace { - println!( - "EventQueue first_event remove_and_wake_all_wakers(): event={event:?} finished waking", - ); - } - } - fn into_event_queue_lock(self) -> MutexGuard<'a, EventQueueData> { - self.event_queue_lock - } -} - -impl EventQueueData { - fn new(instant: SimInstant, trace: bool) -> Self { - Self { - instant, - events: BTreeMap::new(), - trace, - } - } - fn instant(&self) -> SimInstant { - self.instant - } - fn set_instant(&mut self, instant: SimInstant) { - if self.trace { - println!("EventQueue set_instant({instant:?})"); - } - self.instant = instant; - } - fn add_event( - &mut self, - mut event: Event, - waker: Option, - ) -> Result<(), std::task::Waker> { - event.instant = event.instant.max(self.instant); - let wakers = self - .events - .entry(event) - .or_insert_with(|| EventWakers::Wakers(HashSet::default())); - let EventWakers::Wakers(wakers) = wakers else { - return match waker { - Some(waker) => Err(waker), - None => Ok(()), - }; - }; - if self.trace { - println!( - "EventQueue add_event({event:?}, {:?})", - waker.is_some().then_some(format_args!("")) - ); - } - wakers.extend(waker.map(HashableWaker)); - Ok(()) - } - fn add_event_for_now(&mut self, kind: EventKind) { - self.add_event( - Event { - instant: self.instant, - kind, - }, - None, - ) - .expect("no waker passed in") - } - fn first_event<'a>( - this: MutexGuard<'a, EventQueueData>, - event_queue: Arc, - ) -> Result, MutexGuard<'a, EventQueueData>> { - if this.events.is_empty() { - Err(this) - } else { - Ok(EventQueueFirstEvent { - event_queue, - event_queue_lock: this, - }) - } - } - fn peek_first_event(&self) -> Option { - Some(*self.events.first_key_value()?.0) - } - fn peek_first_event_for_now(&self) -> Option { - self.peek_first_event() - .filter(|event| event.instant <= self.instant) - } -} - -struct EventQueue(Mutex); - -impl fmt::Debug for EventQueue { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.write_str("EventQueue(")?; - if let Ok(data) = self.0.try_lock() { - (*data).fmt(f)?; - } else { - f.write_str("")?; - } - f.write_str(")") - } -} - -impl EventQueue { - fn new(data: EventQueueData) -> Self { - Self(Mutex::new(data)) - } - fn lock(&self) -> MutexGuard<'_, EventQueueData> { - self.0.lock().expect("not poisoned") - } - fn add_event_for_now(&self, kind: EventKind) { - self.lock().add_event_for_now(kind); - } - fn peek_first_event_for_now(&self) -> Option { - self.lock().peek_first_event_for_now() - } -} - -struct ExternModuleGeneratorWaker { - event_queue: std::sync::Weak, - module_index: usize, -} - -impl std::task::Wake for ExternModuleGeneratorWaker { +impl std::task::Wake for GeneratorWaker { fn wake(self: Arc) { - self.wake_by_ref(); - } - fn wake_by_ref(self: &Arc) { - if let Some(event_queue) = self.event_queue.upgrade() { - event_queue.add_event_for_now(EventKind::ExternModule(self.module_index)); - } + panic!("can't await other kinds of futures in function passed to ExternalModuleSimulation"); } } -struct SensitivitySet { - debug_id: u64, - compiled_values: HashSet>>, - values: Vec<( - Rc>, - Rc>, - )>, - waker: RefCell, - changed: Cell, +#[derive(Default)] +struct ReadyToRunSet { + state_ready_to_run: bool, + extern_modules_ready_to_run: Vec, } -struct SensitivitySetJustId<'a>(&'a SensitivitySet); - -impl fmt::Debug for SensitivitySetJustId<'_> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - self.0.debug_fmt(true, f) - } -} - -impl fmt::Debug for SensitivitySet { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - self.debug_fmt(false, f) - } -} - -impl SensitivitySet { - fn debug_fmt(&self, just_id: bool, f: &mut fmt::Formatter<'_>) -> fmt::Result { +impl ReadyToRunSet { + fn clear(&mut self) { let Self { - debug_id, - compiled_values: _, - values, - waker: _, - changed, + state_ready_to_run, + extern_modules_ready_to_run, } = self; - struct DebugValues<'a>( - &'a [( - Rc>, - Rc>, - )], - ); - impl<'a> fmt::Debug for DebugValues<'a> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_map() - .entries(self.0.iter().map(|(k, v)| (k, v))) - .finish() - } - } - let mut debug_struct = f.debug_struct("SensitivitySet"); - debug_struct.field("id", debug_id); - if !just_id { - debug_struct - .field("values", &DebugValues(values)) - .field("changed", changed); - } - debug_struct.finish_non_exhaustive() + *state_ready_to_run = false; + extern_modules_ready_to_run.clear(); } } @@ -1880,22 +1519,15 @@ struct SimulationImpl { io: Expr, main_module: SimulationModuleState, extern_modules: Box<[SimulationExternModuleState]>, + state_ready_to_run: bool, trace_decls: TraceModule, traces: SimTraces]>>, trace_memories: BTreeMap, TraceMem>, trace_writers: Vec>, + instant: SimInstant, clocks_triggered: Interned<[StatePartIndex]>, breakpoints: Option, - event_queue: Arc, - next_sensitivity_set_debug_id: u64, - waiting_sensitivity_sets_by_compiled_value: HashMap< - Rc>, - ( - Rc>, - HashMap<*const SensitivitySet, Rc>, - ), - >, - waiting_sensitivity_sets_by_address: HashMap<*const SensitivitySet, Rc>, + generator_waker: std::task::Waker, } impl fmt::Debug for SimulationImpl { @@ -1904,70 +1536,6 @@ impl fmt::Debug for SimulationImpl { } } -struct DebugSensitivitySetsByAddress<'a> { - sensitivity_sets: &'a HashMap<*const SensitivitySet, Rc>, - just_id: bool, -} - -impl<'a> fmt::Debug for DebugSensitivitySetsByAddress<'a> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let Self { - sensitivity_sets, - just_id, - } = *self; - let mut values: Vec<_> = sensitivity_sets.values().collect(); - values.sort_by_key(|v| v.debug_id); - if just_id { - f.debug_set() - .entries( - values - .iter() - .map(|sensitivity_set| SensitivitySetJustId(sensitivity_set)), - ) - .finish() - } else { - f.debug_set().entries(values).finish() - } - } -} - -struct DebugSensitivitySetsByCompiledValue<'a>( - &'a HashMap< - Rc>, - ( - Rc>, - HashMap<*const SensitivitySet, Rc>, - ), - >, -); - -impl<'a> fmt::Debug for DebugSensitivitySetsByCompiledValue<'a> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let mut values: Vec<_> = self - .0 - .iter() - .map(|(compiled_value, (sim_value, sensitivity_sets))| { - ( - DebugAsDisplay(if f.alternate() { - format!("{compiled_value:#?}") - } else { - format!("{compiled_value:?}") - }), - ( - sim_value, - DebugSensitivitySetsByAddress { - sensitivity_sets, - just_id: true, - }, - ), - ) - }) - .collect(); - values.sort_by(|l, r| l.0.0.cmp(&r.0.0)); - f.debug_map().entries(values).finish() - } -} - impl SimulationImpl { fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { @@ -1975,75 +1543,48 @@ impl SimulationImpl { io: self_io, main_module, extern_modules, + state_ready_to_run, trace_decls, traces, trace_memories, trace_writers, + instant, clocks_triggered, breakpoints: _, - event_queue, - next_sensitivity_set_debug_id: _, - waiting_sensitivity_sets_by_compiled_value, - waiting_sensitivity_sets_by_address, + generator_waker: _, } = self; f.debug_struct("Simulation") .field("state", state) .field("io", io.unwrap_or(self_io)) .field("main_module", main_module) .field("extern_modules", extern_modules) + .field("state_ready_to_run", state_ready_to_run) .field("trace_decls", trace_decls) .field("traces", traces) .field("trace_memories", trace_memories) .field("trace_writers", trace_writers) + .field("instant", instant) .field("clocks_triggered", clocks_triggered) - .field("event_queue", event_queue) - .field( - "waiting_sensitivity_sets_by_address", - &DebugSensitivitySetsByAddress { - sensitivity_sets: waiting_sensitivity_sets_by_address, - just_id: false, - }, - ) - .field( - "waiting_sensitivity_sets_by_compiled_value", - &DebugSensitivitySetsByCompiledValue(waiting_sensitivity_sets_by_compiled_value), - ) .finish_non_exhaustive() } fn new(compiled: Compiled) -> Self { let io_target = Target::from(compiled.io); - let mut event_queue = EventQueueData::new(SimInstant::START, false); - event_queue.add_event_for_now(EventKind::State); - for module_index in 0..compiled.extern_modules.len() { - event_queue.add_event_for_now(EventKind::ExternModule(module_index)); - } - let event_queue = Arc::new(EventQueue::new(event_queue)); - let extern_modules = Box::from_iter(compiled.extern_modules.iter().enumerate().map( - |( - module_index, - &CompiledExternModule { - module_io_targets, - module_io, - clocks_for_past, - simulation, - debug_name, - }, - )| { + let extern_modules = Box::from_iter(compiled.extern_modules.iter().map( + |&CompiledExternModule { + module_io_targets, + module_io, + simulation, + }| { SimulationExternModuleState { module_state: SimulationModuleState::new( module_io_targets .iter() .copied() .zip(module_io.iter().copied()), - &clocks_for_past, ), sim: simulation, running_generator: None, - waker: Arc::new(ExternModuleGeneratorWaker { - event_queue: Arc::downgrade(&event_queue), - module_index, - }), - debug_name, + wait_targets: EarliestWaitTargets::settle(), } }, )); @@ -2066,9 +1607,9 @@ impl SimulationImpl { value, ) }), - &[], ), extern_modules, + state_ready_to_run: true, trace_decls: compiled.base_module.trace_decls, traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map( |&SimTrace { @@ -2083,12 +1624,10 @@ impl SimulationImpl { ))), trace_memories: BTreeMap::from_iter(compiled.trace_memories.iter().copied()), trace_writers: vec![], + instant: SimInstant::START, clocks_triggered: compiled.clocks_triggered, breakpoints: None, - event_queue, - next_sensitivity_set_debug_id: 0, - waiting_sensitivity_sets_by_compiled_value: HashMap::default(), - waiting_sensitivity_sets_by_address: HashMap::default(), + generator_waker: Arc::new(GeneratorWaker).into(), } } fn write_traces( @@ -2160,9 +1699,6 @@ impl SimulationImpl { ty, )?; } - SimTraceKind::PhantomConst { ty } => { - trace_writer.set_signal_phantom_const(id, ty)? - } SimTraceKind::SimOnly { .. } => { trace_writer.set_signal_sim_only_value(id, state.unwrap_sim_only_ref())? } @@ -2233,7 +1769,6 @@ impl SimulationImpl { .unwrap_bits_mut() .set(0, self.state.small_slots[index] != 0); } - SimTraceKind::PhantomConst { .. } => {} SimTraceKind::SimOnly { index, ty: _ } => { state .unwrap_sim_only_mut() @@ -2247,198 +1782,137 @@ impl SimulationImpl { } #[track_caller] fn advance_time(this_ref: &Rc>, duration: SimDuration) { - Self::run_until(this_ref, &mut |instant| instant.checked_add(duration)); + let run_target = this_ref.borrow().instant + duration; + Self::run_until(this_ref, run_target); } - fn wake_after_change(&mut self, sensitivity_set: Rc) { - let None = self - .waiting_sensitivity_sets_by_address - .insert(Rc::as_ptr(&sensitivity_set), sensitivity_set.clone()) - else { - // already added - return; - }; - if self.breakpoints.as_ref().is_some_and(|v| v.trace) { - println!("SimulationImpl::wake_after_change:\n{sensitivity_set:#?}"); - } - let SensitivitySet { - debug_id: _, - compiled_values: _, - values, - waker: _, - changed: _, - } = &*sensitivity_set; - for (compiled_value, sim_value) in values { - self.waiting_sensitivity_sets_by_compiled_value - .entry(compiled_value.clone()) - .or_insert_with(|| (sim_value.clone(), HashMap::default())) - .1 - .insert(Rc::as_ptr(&sensitivity_set), sensitivity_set.clone()); - } - } - fn cancel_wake_after_change(&mut self, sensitivity_set: &Rc) { - let Some(_) = self - .waiting_sensitivity_sets_by_address - .remove(&Rc::as_ptr(&sensitivity_set)) - else { - return; - }; - if self.breakpoints.as_ref().is_some_and(|v| v.trace) { - println!("SimulationImpl::cancel_wake_after_change:\n{sensitivity_set:#?}"); - } - let SensitivitySet { - debug_id: _, - compiled_values: _, - values, - waker: _, - changed: _, - } = &**sensitivity_set; - for (compiled_value, _) in values { - if let hashbrown::hash_map::Entry::Occupied(mut entry) = self - .waiting_sensitivity_sets_by_compiled_value - .entry(compiled_value.clone()) - { - entry.get_mut().1.remove(&Rc::as_ptr(&sensitivity_set)); - if entry.get().1.is_empty() { - entry.remove(); - } - } - } - } - fn try_wake_at_instant( - &mut self, + /// clears `targets` + #[must_use] + fn yield_wait<'a>( + this: Rc>, module_index: usize, - instant: &mut dyn FnMut(SimInstant) -> Option, - waker: std::task::Waker, - ) -> Result<(), std::task::Waker> { - let mut event_queue = self.event_queue.lock(); - let Some(instant) = instant(event_queue.instant()) else { - return Err(waker); - }; - match event_queue.add_event( - Event { - instant, - kind: EventKind::ExternModule(module_index), - }, - Some(waker), - ) { - Ok(()) => {} - Err(waker) => { - drop(event_queue); - waker.wake(); + targets: &'a mut EarliestWaitTargets, + ) -> impl Future + 'a { + struct MyGenerator<'a> { + sim: Rc>, + yielded_at_all: bool, + module_index: usize, + targets: &'a mut EarliestWaitTargets, + } + impl Future for MyGenerator<'_> { + type Output = (); + + fn poll( + mut self: Pin<&mut Self>, + cx: &mut std::task::Context<'_>, + ) -> Poll { + let this = &mut *self; + let mut sim = this.sim.borrow_mut(); + let sim = &mut *sim; + assert!( + cx.waker().will_wake(&sim.generator_waker), + "can't use ExternModuleSimulationState's methods outside of ExternModuleSimulation" + ); + this.targets.convert_earlier_instants_to_settle(sim.instant); + if this.targets.is_empty() { + this.targets.settle = true; + } + if this.targets.settle { + if this.yielded_at_all { + this.targets.clear(); + return Poll::Ready(()); + } + } + sim.extern_modules[this.module_index] + .wait_targets + .extend(this.targets.iter()); + this.targets.clear(); + this.yielded_at_all = true; + Poll::Pending } } - Ok(()) + MyGenerator { + sim: this, + yielded_at_all: false, + module_index, + targets, + } } async fn yield_advance_time_or_settle( - this: &RefCell, + this: Rc>, module_index: usize, duration: Option, ) { - let mut target_instant = None; - std::future::poll_fn(|cx| { - match this.borrow_mut().try_wake_at_instant( - module_index, - &mut |instant| match target_instant { - Some(target_instant) => { - // already waited at least once - if instant < target_instant { - Some(target_instant) - } else { - None - } - } - None => { - target_instant = instant.checked_add(duration.unwrap_or(SimDuration::ZERO)); - target_instant - } - }, - cx.waker().clone(), - ) { - Ok(()) => Poll::Pending, - Err(_waker) => { - if target_instant.is_none() { - // don't panic in try_wait_at_instant to avoid poisoning the lock - panic!("SimInstant overflow"); - } - Poll::Ready(()) - } - } - }) - .await + let mut targets = duration.map_or(EarliestWaitTargets::settle(), |duration| { + EarliestWaitTargets::instant(this.borrow().instant + duration) + }); + Self::yield_wait(this, module_index, &mut targets).await; } - async fn yield_wait_for_changes( - this: &RefCell, - module_index: usize, - sensitivity_set: SensitivitySet, - timeout: Option, - ) { - if let Some(timeout) = timeout { - if timeout == SimDuration::ZERO { - return Self::yield_advance_time_or_settle(this, module_index, None).await; - } - } - let sensitivity_set = Rc::new(sensitivity_set); - struct CancelOnDrop<'a> { - this: &'a RefCell, - sensitivity_set: &'a Rc, - } - impl Drop for CancelOnDrop<'_> { - fn drop(&mut self) { - let Self { - this, - sensitivity_set, - } = self; - this.borrow_mut().cancel_wake_after_change(&sensitivity_set); - } - } - let _cancel_on_drop = CancelOnDrop { - this, - sensitivity_set: &sensitivity_set, - }; - let mut timeout_instant = None; - std::future::poll_fn(|cx| { - if sensitivity_set.changed.get() { - return Poll::Ready(()); - } - sensitivity_set.waker.borrow_mut().clone_from(cx.waker()); - let mut this = this.borrow_mut(); - this.wake_after_change(sensitivity_set.clone()); - if let Some(timeout) = timeout { - match this.try_wake_at_instant( - module_index, - &mut |instant| match timeout_instant { - Some(timeout_instant) => { - if instant < timeout_instant { - Some(timeout_instant) - } else { - None - } - } - None => { - timeout_instant = instant.checked_add(timeout); - timeout_instant - } - }, - cx.waker().clone(), - ) { - Ok(()) => Poll::Pending, - Err(_waker) => { - if timeout_instant.is_none() { - // don't panic in try_wait_at_instant to avoid poisoning the lock - panic!("SimInstant overflow"); - } - Poll::Ready(()) + fn is_extern_module_ready_to_run(&mut self, module_index: usize) -> Option { + let module = &self.extern_modules[module_index]; + let mut retval = None; + for wait_target in module.wait_targets.iter() { + retval = match (wait_target, retval) { + (WaitTarget::Settle, _) => Some(self.instant), + (WaitTarget::Instant(instant), _) if instant <= self.instant => Some(self.instant), + (WaitTarget::Instant(instant), None) => Some(instant), + (WaitTarget::Instant(instant), Some(retval)) => Some(instant.min(retval)), + (WaitTarget::Change { key, value }, retval) => { + if Self::value_changed(&mut self.state, key, SimValue::opaque(value)) { + Some(self.instant) + } else { + retval } } + }; + if retval == Some(self.instant) { + break; + } + } + retval + } + fn get_ready_to_run_set(&mut self, ready_to_run_set: &mut ReadyToRunSet) -> Option { + ready_to_run_set.clear(); + let mut retval = None; + if self.state_ready_to_run { + ready_to_run_set.state_ready_to_run = true; + retval = Some(self.instant); + } + for module_index in 0..self.extern_modules.len() { + let Some(instant) = self.is_extern_module_ready_to_run(module_index) else { + continue; + }; + if let Some(retval) = &mut retval { + match instant.cmp(retval) { + std::cmp::Ordering::Less => ready_to_run_set.clear(), + std::cmp::Ordering::Equal => {} + std::cmp::Ordering::Greater => continue, + } } else { - Poll::Pending + retval = Some(instant); } - }) - .await; + ready_to_run_set + .extern_modules_ready_to_run + .push(module_index); + } + retval + } + fn set_instant_no_sim(&mut self, instant: SimInstant) { + self.instant = instant; + self.for_each_trace_writer_storing_error(|this, mut trace_writer_state| { + match &mut trace_writer_state { + TraceWriterState::Decls(_) | TraceWriterState::Init(_) => unreachable!(), + TraceWriterState::Running(trace_writer) => { + trace_writer.change_time_to(this.instant)?; + } + TraceWriterState::Errored(_) => {} + } + Ok(trace_writer_state) + }); } #[must_use] #[track_caller] - fn run_state_settle_cycle(&mut self) { + fn run_state_settle_cycle(&mut self) -> bool { + self.state_ready_to_run = false; self.state.setup_call(0); if self.breakpoints.is_some() { loop { @@ -2469,213 +1943,138 @@ impl SimulationImpl { .iter() .any(|i| self.state.small_slots[*i] != 0) { - if self.breakpoints.as_ref().is_some_and(|v| v.trace) { - println!("SimulationImpl clocks triggered"); - } - self.event_queue.add_event_for_now(EventKind::State); + self.state_ready_to_run = true; + true + } else { + false } } #[track_caller] - fn run_extern_module(this_ref: &Rc>, module_index: usize) { - let mut this = this_ref.borrow_mut(); - let trace = this.breakpoints.as_ref().is_some_and(|v| v.trace); - let extern_module = &mut this.extern_modules[module_index]; - let debug_name = extern_module.debug_name; - let waker = std::task::Waker::from(extern_module.waker.clone()); - let mut generator = if !extern_module.module_state.did_initial_settle { - let sim = extern_module.sim; - drop(this); - if trace { - println!("{debug_name}: start"); - } - Box::into_pin(sim.run(ExternModuleSimulationState { - sim_impl: this_ref.clone(), - module_index, - })) - } else if let Some(generator) = extern_module.running_generator.take() { - drop(this); - generator - } else { - return; - }; - if trace { - println!("{debug_name}: poll"); - } - let poll_result = generator - .as_mut() - .poll(&mut std::task::Context::from_waker(&waker)); - let generator = match poll_result { - Poll::Ready(()) => None, - Poll::Pending => Some(generator), - }; - if trace { - println!("{debug_name}: poll returned {poll_result:?}"); - } - this = this_ref.borrow_mut(); - this.extern_modules[module_index] - .module_state - .did_initial_settle = true; - if !this.extern_modules[module_index] - .module_state - .uninitialized_ios - .is_empty() - { - panic!( - "extern module didn't initialize all outputs before \ - waiting, settling, or reading any inputs: {}", - this.extern_modules[module_index].sim.source_location - ); - } - this.extern_modules[module_index].running_generator = generator; - } - fn check_waiting_sensitivity_sets(&mut self) { - if let Some(Event { - instant: _, - kind: EventKind::State, - }) = self.event_queue.peek_first_event_for_now() - { - return; - } - let mut triggered = HashMap::<*const SensitivitySet, Rc>::default(); - for (compiled_value, (sim_value, sensitivity_sets)) in - &self.waiting_sensitivity_sets_by_compiled_value - { - if Self::value_changed( - &mut self.state, - **compiled_value, - SimValue::opaque(sim_value), - ) { - triggered.extend(sensitivity_sets.iter().map(|(&k, v)| (k, v.clone()))); - } - } - for sensitivity_set in triggered.into_values() { - sensitivity_set.changed.set(true); - sensitivity_set.waker.borrow().wake_by_ref(); - self.cancel_wake_after_change(&sensitivity_set); - } - } - fn write_traces_after_event(&mut self) { - if let Some(Event { - instant: _, - kind: EventKind::State, - }) = self.event_queue.peek_first_event_for_now() - { - return; - } - if self.main_module.did_initial_settle { - self.read_traces::(); - } else { - self.read_traces::(); - } - self.state.memory_write_log.sort_unstable(); - self.state.memory_write_log.dedup(); - self.main_module.did_initial_settle = true; - self.for_each_trace_writer_storing_error(|this, trace_writer_state| { - Ok(match trace_writer_state { - TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running( - this.init_trace_writer(trace_writer_decls.write_decls( - this.trace_decls, - this.traces.0.len(), - this.trace_memories.len(), - )?)?, - ), - TraceWriterState::Init(trace_writer) => { - TraceWriterState::Running(this.init_trace_writer(trace_writer)?) - } - TraceWriterState::Running(trace_writer) => { - TraceWriterState::Running(this.update_trace_writer(trace_writer)?) - } - TraceWriterState::Errored(e) => TraceWriterState::Errored(e), - }) - }); - self.state.memory_write_log.clear(); - } - fn write_traces_change_time_to(&mut self, new_instant: SimInstant) { - self.for_each_trace_writer_storing_error(|_this, mut trace_writer_state| { - match &mut trace_writer_state { - TraceWriterState::Decls(_) | TraceWriterState::Init(_) => unreachable!(), - TraceWriterState::Running(trace_writer) => { - trace_writer.change_time_to(new_instant)?; - } - TraceWriterState::Errored(_) => {} - } - Ok(trace_writer_state) - }); - } - #[track_caller] - fn run_until( + fn run_extern_modules_cycle( this_ref: &Rc>, - run_target: &mut dyn FnMut(SimInstant) -> Option, + generator_waker: &std::task::Waker, + extern_modules_ready_to_run: &[usize], ) { let mut this = this_ref.borrow_mut(); + for module_index in extern_modules_ready_to_run.iter().copied() { + let extern_module = &mut this.extern_modules[module_index]; + extern_module.wait_targets.clear(); + let mut generator = if !extern_module.module_state.did_initial_settle { + let sim = extern_module.sim; + drop(this); + Box::into_pin(sim.run(ExternModuleSimulationState { + sim_impl: this_ref.clone(), + module_index, + wait_for_changes_wait_targets: EarliestWaitTargets::default(), + })) + } else if let Some(generator) = extern_module.running_generator.take() { + drop(this); + generator + } else { + continue; + }; + let generator = match generator + .as_mut() + .poll(&mut std::task::Context::from_waker(generator_waker)) + { + Poll::Ready(()) => None, + Poll::Pending => Some(generator), + }; + this = this_ref.borrow_mut(); + this.extern_modules[module_index] + .module_state + .did_initial_settle = true; + if !this.extern_modules[module_index] + .module_state + .uninitialized_ios + .is_empty() + { + panic!( + "extern module didn't initialize all outputs before \ + waiting, settling, or reading any inputs: {}", + this.extern_modules[module_index].sim.source_location + ); + } + this.extern_modules[module_index].running_generator = generator; + } + } + /// clears `targets` + #[track_caller] + fn run_until(this_ref: &Rc>, run_target: SimInstant) { + let mut this = this_ref.borrow_mut(); + let mut ready_to_run_set = ReadyToRunSet::default(); + let generator_waker = this.generator_waker.clone(); assert!( this.main_module.uninitialized_ios.is_empty(), "didn't initialize all inputs", ); - this.check_waiting_sensitivity_sets(); - let arc_event_queue = this.event_queue.clone(); // avoid borrow errors - let mut event_queue = arc_event_queue.lock(); - let Some(run_target) = run_target(event_queue.instant()) else { - drop(event_queue); - panic!("SimInstant overflowed"); - }; - let run_target = run_target.max(event_queue.instant()); + let run_target = run_target.max(this.instant); let mut settle_cycle = 0; + let mut run_extern_modules = true; loop { - if settle_cycle >= 100000 { - drop(event_queue); - panic!("settle(): took too many steps"); - } + assert!(settle_cycle < 100000, "settle(): took too many steps"); settle_cycle += 1; - let event_queue_instant = event_queue.instant(); - let mut changed_time = false; - let first_entry = EventQueueData::first_event(event_queue, arc_event_queue.clone()) - .map_err(|mut event_queue| { - changed_time = event_queue_instant != run_target; - event_queue.set_instant(run_target); - drop(event_queue); - }); - let Ok(first_entry) = first_entry else { - if changed_time { - this.write_traces_change_time_to(run_target); - } - return; + let next_wait_target = match this.get_ready_to_run_set(&mut ready_to_run_set) { + Some(next_wait_target) if next_wait_target <= run_target => next_wait_target, + _ => break, }; - let Event { - instant: event_instant, - kind: event_kind, - } = *first_entry.event(); - if event_instant <= event_queue_instant { - first_entry.remove_and_wake_all_wakers(); - match event_kind { - EventKind::State => this.run_state_settle_cycle(), - EventKind::ExternModule(module_index) => { - drop(this); - Self::run_extern_module(this_ref, module_index); - this = this_ref.borrow_mut(); - } - } - this.write_traces_after_event(); - this.check_waiting_sensitivity_sets(); - } else { - event_queue = first_entry.into_event_queue_lock(); - let new_instant = event_instant.min(run_target); - let changed_time = event_queue_instant != new_instant; - event_queue.set_instant(new_instant); - drop(event_queue); - if changed_time { - this.write_traces_change_time_to(new_instant); - } - if event_instant > run_target { - return; + if next_wait_target > this.instant { + settle_cycle = 0; + this.set_instant_no_sim(next_wait_target); + } + if run_extern_modules { + drop(this); + Self::run_extern_modules_cycle( + this_ref, + &generator_waker, + &ready_to_run_set.extern_modules_ready_to_run, + ); + this = this_ref.borrow_mut(); + } + if ready_to_run_set.state_ready_to_run { + if this.run_state_settle_cycle() { + // wait for clocks to settle before running extern modules again + run_extern_modules = false; + } else { + run_extern_modules = true; } } - event_queue = arc_event_queue.lock(); + if this.main_module.did_initial_settle { + this.read_traces::(); + } else { + this.read_traces::(); + } + this.state.memory_write_log.sort_unstable(); + this.state.memory_write_log.dedup(); + this.main_module.did_initial_settle = true; + this.for_each_trace_writer_storing_error(|this, trace_writer_state| { + Ok(match trace_writer_state { + TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running( + this.init_trace_writer(trace_writer_decls.write_decls( + this.trace_decls, + this.traces.0.len(), + this.trace_memories.len(), + )?)?, + ), + TraceWriterState::Init(trace_writer) => { + TraceWriterState::Running(this.init_trace_writer(trace_writer)?) + } + TraceWriterState::Running(trace_writer) => { + TraceWriterState::Running(this.update_trace_writer(trace_writer)?) + } + TraceWriterState::Errored(e) => TraceWriterState::Errored(e), + }) + }); + this.state.memory_write_log.clear(); + } + if run_target > this.instant { + this.set_instant_no_sim(run_target); } } #[track_caller] fn settle(this_ref: &Rc>) { - Self::run_until(this_ref, &mut Some); + let run_target = this_ref.borrow().instant; + Self::run_until(this_ref, run_target); } fn get_module(&self, which_module: WhichModule) -> &SimulationModuleState { match which_module { @@ -2695,11 +2094,10 @@ impl SimulationImpl { fn read_bit( &mut self, io: Expr, - read_time: ReadTime, which_module: WhichModule, ) -> MaybeNeedsSettle { self.get_module(which_module) - .read_helper(Expr::canonical(io), read_time, which_module) + .read_helper(Expr::canonical(io), which_module) .map(|compiled_value| ReadBitFn { compiled_value }) .apply_no_settle(&mut self.state) } @@ -2708,7 +2106,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(io, which_module); - self.event_queue.add_event_for_now(EventKind::State); + self.state_ready_to_run = true; match compiled_value.range.len().as_single() { Some(TypeLenSingle::SmallSlot) => { self.state.small_slots[compiled_value.range.small_slots.start] = value as _; @@ -2718,17 +2116,15 @@ impl SimulationImpl { } Some(TypeLenSingle::SimOnlySlot) | None => unreachable!(), } - self.debug_write(compiled_value); } #[track_caller] fn read_bool_or_int( &mut self, io: Expr, - read_time: ReadTime, which_module: WhichModule, ) -> MaybeNeedsSettle, I::Value> { self.get_module(which_module) - .read_helper(Expr::canonical(io), read_time, which_module) + .read_helper(Expr::canonical(io), which_module) .map(|compiled_value| ReadBoolOrIntFn { compiled_value, io }) .apply_no_settle(&mut self.state) } @@ -2742,7 +2138,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(Expr::canonical(io), which_module); - self.event_queue.add_event_for_now(EventKind::State); + self.state_ready_to_run = true; let value: BigInt = value.into(); match compiled_value.range.len().as_single() { Some(TypeLenSingle::SmallSlot) => { @@ -2757,7 +2153,6 @@ impl SimulationImpl { } Some(TypeLenSingle::SimOnlySlot) | None => unreachable!(), } - self.debug_write(compiled_value); } #[track_caller] fn read_write_sim_value_helper( @@ -2810,18 +2205,17 @@ impl SimulationImpl { None => unreachable!(), } } - CompiledTypeLayoutBody::Array { elements_non_empty } => { + CompiledTypeLayoutBody::Array { element } => { let ty = ::from_canonical(compiled_value.layout.ty); let element_size = ty.element().size(); for element_index in 0..ty.len() { Self::read_write_sim_value_helper( state, CompiledValue { - layout: elements_non_empty[element_index], - range: compiled_value.range.index_array( - elements_non_empty[element_index].layout.len(), - element_index, - ), + layout: *element, + range: compiled_value + .range + .index_array(element.layout.len(), element_index), write: None, }, start_index + element_index * element_size, @@ -2832,7 +2226,6 @@ impl SimulationImpl { ); } } - CompiledTypeLayoutBody::PhantomConst => {} CompiledTypeLayoutBody::Bundle { fields } => { let ty = Bundle::from_canonical(compiled_value.layout.ty); for ( @@ -2959,23 +2352,15 @@ impl SimulationImpl { any_change.get() } #[track_caller] - fn is_reset_async(&self, io: Expr, which_module: WhichModule) -> bool { - self.get_module(which_module) - .is_reset_async(io, which_module) - } - #[track_caller] fn read( &mut self, io: Expr, - read_time: ReadTime, which_module: WhichModule, ) -> ( CompiledValue, MaybeNeedsSettle>, ) { - let compiled_value = self - .get_module(which_module) - .read_helper(io, read_time, which_module); + let compiled_value = self.get_module(which_module).read_helper(io, which_module); let value = compiled_value .map(|compiled_value| ReadFn { compiled_value, io }) .apply_no_settle(&mut self.state); @@ -2983,18 +2368,6 @@ impl SimulationImpl { | MaybeNeedsSettle::NoSettleNeeded(compiled_value)) = compiled_value; (compiled_value, value) } - fn debug_write(&self, compiled_value: CompiledValue) { - if self.breakpoints.as_ref().is_some_and(|v| v.trace) { - println!( - "wrote: {:#?}", - compiler::DebugCompiledValueStateAsMap { - compiled_value, - state_layout: self.state.insns.state_layout(), - state: &self.state, - }, - ); - } - } #[track_caller] fn write( &mut self, @@ -3005,7 +2378,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(io, which_module); - self.event_queue.add_event_for_now(EventKind::State); + self.state_ready_to_run = true; assert_eq!(Expr::ty(io), SimValue::ty(value)); Self::read_write_sim_value_helper( &mut self.state, @@ -3038,7 +2411,6 @@ impl SimulationImpl { value.clone_from(&opaque.sim_only_values()[index]); }, ); - self.debug_write(compiled_value); } #[track_caller] fn settle_if_needed(this_ref: &Rc>, v: MaybeNeedsSettle) -> O @@ -3054,7 +2426,7 @@ impl SimulationImpl { } } async fn yield_settle_if_needed( - this_ref: &RefCell, + this_ref: &Rc>, module_index: usize, v: MaybeNeedsSettle, ) -> O @@ -3063,7 +2435,7 @@ impl SimulationImpl { { match v { MaybeNeedsSettle::NeedsSettle(v) => { - Self::yield_advance_time_or_settle(this_ref, module_index, None).await; + Self::yield_advance_time_or_settle(this_ref.clone(), module_index, None).await; v.call(&mut this_ref.borrow_mut().state) } MaybeNeedsSettle::NoSettleNeeded(v) => v, @@ -3204,14 +2576,11 @@ impl fmt::Debug for SortedSetDebug<'_, T, V> { } } -struct SortedMapDebug<'a, T>(&'a T); +struct SortedMapDebug<'a, K: 'static + Send + Sync, V>(&'a BTreeMap, V>); -impl<'a, K: fmt::Debug + 'a, V: fmt::Debug + 'a, T> fmt::Debug for SortedMapDebug<'a, T> -where - &'a T: IntoIterator, -{ +impl fmt::Debug for SortedMapDebug<'_, K, V> { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let mut entries = Vec::from_iter(self.0.into_iter().map(|(k, v)| { + let mut entries = Vec::from_iter(self.0.iter().map(|(k, v)| { if f.alternate() { (format!("{k:#?}"), format!("{v:#?}")) } else { @@ -3262,7 +2631,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bool_or_int(io, ReadTime::Current, $which_module); + .read_bool_or_int(io, $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? @@ -3293,7 +2662,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); + .read_bit(Expr::canonical(io), $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? @@ -3307,7 +2676,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); + .read_bit(Expr::canonical(io), $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? @@ -3321,22 +2690,15 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); + .read_bit(Expr::canonical(io), $which_module); $self.settle_if_needed(retval)$(.$await)? } - #[track_caller] - pub fn is_reset_async(&$self, io: Expr) -> bool { - $self - .sim_impl - .borrow_mut() - .is_reset_async(Expr::canonical(io), $which_module) - } $(#[$track_caller])? pub $($async)? fn read(&mut $self, io: Expr) -> SimValue { let retval = $self .sim_impl .borrow_mut() - .read(Expr::canonical(io), ReadTime::Current, $which_module).1; + .read(Expr::canonical(io), $which_module).1; SimValue::from_canonical($self.settle_if_needed(retval)$(.$await)?) } $(#[$track_caller])? @@ -3413,19 +2775,18 @@ impl Simulation { #[doc(hidden)] /// This is explicitly unstable and may be changed/removed at any time pub fn set_breakpoints_unstable(&mut self, pcs: HashSet, trace: bool) { - let mut sim_impl = self.sim_impl.borrow_mut(); - sim_impl.breakpoints = Some(BreakpointsSet { + self.sim_impl.borrow_mut().breakpoints = Some(BreakpointsSet { last_was_break: false, set: pcs, trace, }); - sim_impl.event_queue.lock().trace = trace; } } pub struct ExternModuleSimulationState { sim_impl: Rc>, module_index: usize, + wait_for_changes_wait_targets: EarliestWaitTargets, } impl fmt::Debug for ExternModuleSimulationState { @@ -3433,6 +2794,7 @@ impl fmt::Debug for ExternModuleSimulationState { let Self { sim_impl: _, module_index, + wait_for_changes_wait_targets: _, } = self; f.debug_struct("ExternModuleSimulationState") .field("sim_impl", &DebugAsDisplay("...")) @@ -3443,11 +2805,12 @@ impl fmt::Debug for ExternModuleSimulationState { impl ExternModuleSimulationState { pub async fn settle(&mut self) { - SimulationImpl::yield_advance_time_or_settle(&self.sim_impl, self.module_index, None).await + SimulationImpl::yield_advance_time_or_settle(self.sim_impl.clone(), self.module_index, None) + .await } pub async fn advance_time(&mut self, duration: SimDuration) { SimulationImpl::yield_advance_time_or_settle( - &self.sim_impl, + self.sim_impl.clone(), self.module_index, Some(duration), ) @@ -3458,39 +2821,27 @@ impl ExternModuleSimulationState { iter: I, timeout: Option, ) { - let mut sim_impl = self.sim_impl.borrow_mut(); - let mut sensitivity_set = SensitivitySet { - debug_id: sim_impl.next_sensitivity_set_debug_id, - compiled_values: HashSet::default(), - values: Vec::new(), - waker: RefCell::new(std::task::Waker::noop().clone()), - changed: Cell::new(false), - }; - sim_impl.next_sensitivity_set_debug_id = - sim_impl.next_sensitivity_set_debug_id.wrapping_add(1); - drop(sim_impl); + self.wait_for_changes_wait_targets.clear(); let which_module = WhichModule::Extern { module_index: self.module_index, }; for io in iter { let io = Expr::canonical(io.to_expr()); - let (key, value) = self - .sim_impl - .borrow_mut() - .read(io, ReadTime::Current, which_module); + let (key, value) = self.sim_impl.borrow_mut().read(io, which_module); let value = self.settle_if_needed(value).await; - let key = Rc::new(key); - if sensitivity_set.compiled_values.insert(key.clone()) { - sensitivity_set.values.push((key, Rc::new(value))); - } + self.wait_for_changes_wait_targets + .insert(WaitTarget::Change { key, value }); } - SimulationImpl::yield_wait_for_changes( - &self.sim_impl, + if let Some(timeout) = timeout { + self.wait_for_changes_wait_targets.instant = + Some(self.sim_impl.borrow().instant + timeout); + } + SimulationImpl::yield_wait( + self.sim_impl.clone(), self.module_index, - sensitivity_set, - timeout, + &mut self.wait_for_changes_wait_targets, ) - .await + .await; } pub async fn wait_for_clock_edge(&mut self, clk: impl ToExpr) { let clk = clk.to_expr(); @@ -3507,330 +2858,6 @@ impl ExternModuleSimulationState { { SimulationImpl::yield_settle_if_needed(&self.sim_impl, self.module_index, v).await } - pub async fn fork_join(&mut self, futures: F) -> F::Output { - F::fork_join(futures, self).await - } - async fn resettable_helper( - &mut self, - cancellable: &Cell, - wait_for_reset: impl AsyncFn(Self), - main: impl AsyncFn(Self), - ) -> ! { - let mut wait_for_reset_invocation = pin!(Some(wait_for_reset(self.forked_state()))); - let mut main_invocation = pin!(Some(main(self.forked_state()))); - std::future::poll_fn(|cx: &mut std::task::Context<'_>| { - loop { - if cancellable.get() && wait_for_reset_invocation.is_none() { - cancellable.set(false); - main_invocation.set(Some(main(self.forked_state()))); - wait_for_reset_invocation.set(Some(wait_for_reset(self.forked_state()))) - } - match main_invocation.as_mut().as_pin_mut().map(|f| f.poll(cx)) { - None | Some(Poll::Pending) => {} - Some(Poll::Ready(())) => { - main_invocation.set(None); - continue; - } - } - match wait_for_reset_invocation - .as_mut() - .as_pin_mut() - .map(|f| f.poll(cx)) - { - None | Some(Poll::Pending) => {} - Some(Poll::Ready(())) => { - wait_for_reset_invocation.set(None); - continue; - } - } - return Poll::Pending; - } - }) - .await - } - /// When `cd.rst` is deduced to be an [`AsyncReset`]: - /// * when `cd.rst` is asserted or when first called, `reset` is invoked and any running `run` invocation is cancelled. - /// * when `cd.rst` is de-asserted and when `reset` finishes, `run` is invoked. - /// - /// When `cd.rst` is deduced to be a [`SyncReset`]: - /// * when there's a positive-going clock edge on `cd.clk` and `cd.rst` is asserted or when first called, `reset` is invoked and any running `run` invocation is cancelled. - /// * when `reset` finishes, `run` is invoked. - pub async fn resettable( - &mut self, - cd: impl ToExpr>, - reset: impl AsyncFn(Self) -> T, - run: impl AsyncFn(Self, T), - ) -> ! { - let cd = cd.to_expr(); - let rst = cd.rst; - if self.is_reset_async(rst) { - let cancellable = Cell::new(false); - let wait_for_reset = |mut this: Self| async move { - while this.read_reset(rst).await { - this.wait_for_changes([rst], None).await; - } - while !this.read_reset(rst).await { - this.wait_for_changes([rst], None).await; - } - }; - let main = |mut this: Self| async { - let run_arg = reset(this.forked_state()).await; - cancellable.set(true); - while this.read_reset(rst).await { - this.wait_for_changes([rst], None).await; - } - run(this, run_arg).await - }; - self.resettable_helper(&cancellable, wait_for_reset, main) - .await - } else { - let clk = cd.clk; - let wait_for_reset = |mut this: Self| async move { - loop { - this.wait_for_clock_edge(clk).await; - if this.read_reset(rst).await { - return; - } - } - }; - let cancellable = Cell::new(false); - let main = |this: Self| async { - let run_arg = reset(this.forked_state()).await; - cancellable.set(true); - run(this, run_arg).await - }; - self.resettable_helper(&cancellable, wait_for_reset, main) - .await - } - } - fn forked_state(&self) -> Self { - let Self { - ref sim_impl, - module_index, - } = *self; - Self { - sim_impl: sim_impl.clone(), - module_index, - } - } - pub async fn fork_join_scope<'env, F, Fut>( - &mut self, - in_scope: F, - ) -> ::Output - where - F: FnOnce(ForkJoinScope<'env>, ExternModuleSimulationState) -> Fut, - Fut: IntoFuture>, - { - let scope = ForkJoinScope { - new_tasks: Rc::new(RefCell::new(vec![])), - sim: self.forked_state(), - }; - let join_handle = scope.spawn(in_scope); - #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug)] - struct TaskId(u64); - struct TasksStateInner { - next_task_id: u64, - ready_tasks: BTreeSet, - not_ready_tasks: BTreeSet, - base_waker: std::task::Waker, - } - impl Default for TasksStateInner { - fn default() -> Self { - Self { - next_task_id: Default::default(), - ready_tasks: Default::default(), - not_ready_tasks: Default::default(), - base_waker: std::task::Waker::noop().clone(), - } - } - } - #[derive(Default)] - struct TasksState { - inner: Mutex, - } - #[derive(Clone)] - struct TaskWaker { - state: std::sync::Weak, - task: TaskId, - } - impl std::task::Wake for TaskWaker { - fn wake(self: Arc) { - self.wake_by_ref(); - } - fn wake_by_ref(self: &Arc) { - let Some(state) = self.state.upgrade() else { - return; - }; - let mut inner = state.inner.lock().expect("not poisoned"); - if inner.not_ready_tasks.remove(&self.task) { - inner.ready_tasks.insert(self.task); - inner.base_waker.wake_by_ref(); - } - } - } - struct Task<'env> { - task: Pin + 'env>>, - waker: std::task::Waker, - } - let mut tasks: BTreeMap = BTreeMap::new(); - let tasks_state = Arc::new(TasksState::default()); - std::future::poll_fn(move |cx: &mut std::task::Context<'_>| { - let mut state_inner = tasks_state.inner.lock().expect("not poisoned"); - state_inner.base_waker.clone_from(cx.waker()); - loop { - for new_task in scope.new_tasks.borrow_mut().drain(..) { - let task_id = TaskId(state_inner.next_task_id); - let Some(next_task_id) = state_inner.next_task_id.checked_add(1) else { - drop(state_inner); - panic!("spawned too many tasks"); - }; - state_inner.next_task_id = next_task_id; - state_inner.ready_tasks.insert(task_id); - tasks.insert( - task_id, - Task { - task: new_task, - waker: Arc::new(TaskWaker { - state: Arc::downgrade(&tasks_state), - task: task_id, - }) - .into(), - }, - ); - } - let Some(task_id) = state_inner.ready_tasks.pop_first() else { - if state_inner.not_ready_tasks.is_empty() { - return Poll::Ready(()); - } else { - return Poll::Pending; - }; - }; - state_inner.not_ready_tasks.insert(task_id); // task can be woken while we're running poll - drop(state_inner); - let std::collections::btree_map::Entry::Occupied(mut entry) = tasks.entry(task_id) - else { - unreachable!(); - }; - let Task { task, waker } = entry.get_mut(); - match task.as_mut().poll(&mut std::task::Context::from_waker( - &std::task::Waker::from(waker.clone()), - )) { - Poll::Pending => { - state_inner = tasks_state.inner.lock().expect("not poisoned"); - continue; - } - Poll::Ready(()) => {} - } - drop(entry.remove()); // drop outside lock - state_inner = tasks_state.inner.lock().expect("not poisoned"); - state_inner.not_ready_tasks.remove(&task_id); - state_inner.ready_tasks.remove(&task_id); - } - }) - .await; - match &mut *join_handle.state.borrow_mut() { - JoinHandleState::Running(_) => unreachable!(), - JoinHandleState::Finished(state) => state - .take() - .expect("filled by running all futures to completion"), - } - } - /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. - /// - /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] - /// in the module's body for every clock you use as the second argument of the `read_past()` family. - /// - /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past - pub async fn read_past_bool_or_int( - &mut self, - io: Expr, - clock_for_past: Expr, - ) -> I::Value { - let retval = self.sim_impl.borrow_mut().read_bool_or_int( - io, - ReadTime::Past { clock_for_past }, - WhichModule::Extern { - module_index: self.module_index, - }, - ); - self.settle_if_needed(retval).await - } - /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. - /// - /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] - /// in the module's body for every clock you use as the second argument of the `read_past()` family. - /// - /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past - pub async fn read_past_clock(&mut self, io: Expr, clock_for_past: Expr) -> bool { - let retval = self.sim_impl.borrow_mut().read_bit( - Expr::canonical(io), - ReadTime::Past { clock_for_past }, - WhichModule::Extern { - module_index: self.module_index, - }, - ); - self.settle_if_needed(retval).await - } - /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. - /// - /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] - /// in the module's body for every clock you use as the second argument of the `read_past()` family. - /// - /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past - pub async fn read_past_bool(&mut self, io: Expr, clock_for_past: Expr) -> bool { - let retval = self.sim_impl.borrow_mut().read_bit( - Expr::canonical(io), - ReadTime::Past { clock_for_past }, - WhichModule::Extern { - module_index: self.module_index, - }, - ); - self.settle_if_needed(retval).await - } - /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. - /// - /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] - /// in the module's body for every clock you use as the second argument of the `read_past()` family. - /// - /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past - pub async fn read_past_reset( - &mut self, - io: Expr, - clock_for_past: Expr, - ) -> bool { - let retval = self.sim_impl.borrow_mut().read_bit( - Expr::canonical(io), - ReadTime::Past { clock_for_past }, - WhichModule::Extern { - module_index: self.module_index, - }, - ); - self.settle_if_needed(retval).await - } - /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. - /// - /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] - /// in the module's body for every clock you use as the second argument of the `read_past()` family. - /// - /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past - pub async fn read_past( - &mut self, - io: Expr, - clock_for_past: Expr, - ) -> SimValue { - let retval = self - .sim_impl - .borrow_mut() - .read( - Expr::canonical(io), - ReadTime::Past { clock_for_past }, - WhichModule::Extern { - module_index: self.module_index, - }, - ) - .1; - SimValue::from_canonical(self.settle_if_needed(retval).await) - } impl_simulation_methods!( async_await = (async, await), track_caller = (), @@ -3838,233 +2865,6 @@ impl ExternModuleSimulationState { ); } -pub struct ForkJoinScope<'env> { - new_tasks: Rc + 'env>>>>>, - sim: ExternModuleSimulationState, -} - -impl<'env> Clone for ForkJoinScope<'env> { - fn clone(&self) -> Self { - Self { - new_tasks: self.new_tasks.clone(), - sim: self.sim.forked_state(), - } - } -} - -impl<'env> ForkJoinScope<'env> { - fn spawn_inner(&self, fut: Pin + 'env>>) { - self.new_tasks.borrow_mut().push(fut); - } - pub fn spawn_detached_future( - &self, - fut: impl IntoFuture>, - ) { - self.spawn_inner(Box::pin(fut.into_future())); - } - pub fn spawn_detached(&self, f: F) - where - F: FnOnce(ForkJoinScope<'env>, ExternModuleSimulationState) -> Fut, - Fut: IntoFuture>, - { - self.spawn_detached_future(f(self.clone(), self.sim.forked_state())); - } - pub fn spawn(&self, f: F) -> JoinHandle - where - F: FnOnce(ForkJoinScope<'env>, ExternModuleSimulationState) -> Fut, - Fut: IntoFuture>, - { - let join_handle = JoinHandle { - state: Default::default(), - }; - let state = Rc::downgrade(&join_handle.state); - let fut = f(self.clone(), self.sim.forked_state()).into_future(); - self.spawn_detached_future(async move { - let result = fut.await; - let Some(state) = state.upgrade() else { return }; - let mut state = state.borrow_mut(); - let waker = match &mut *state { - JoinHandleState::Running(waker) => waker.take(), - JoinHandleState::Finished(_) => unreachable!(), - }; - *state = JoinHandleState::Finished(Some(result)); - drop(state); - let Some(waker) = waker else { return }; - waker.wake(); - }); - join_handle - } -} - -enum JoinHandleState { - Running(Option), - Finished(Option), -} - -impl Default for JoinHandleState { - fn default() -> Self { - Self::Running(None) - } -} - -pub struct JoinHandle { - state: Rc>>, -} - -impl JoinHandle { - pub fn is_finished(&self) -> bool { - matches!(*self.state.borrow(), JoinHandleState::Finished(_)) - } - pub fn try_join(self) -> Result { - let mut state = self.state.borrow_mut(); - match &mut *state { - JoinHandleState::Running(_) => { - drop(state); - Err(self) - } - JoinHandleState::Finished(retval) => { - let Some(retval) = retval.take() else { - panic!("already returned the value in poll"); - }; - Ok(retval) - } - } - } - pub async fn join(self) -> T { - self.await - } -} - -impl Future for JoinHandle { - type Output = T; - - fn poll(self: Pin<&mut Self>, cx: &mut std::task::Context<'_>) -> Poll { - match &mut *self.state.borrow_mut() { - JoinHandleState::Running(waker) => { - match waker { - None => *waker = Some(cx.waker().clone()), - Some(waker) => waker.clone_from(cx.waker()), - } - Poll::Pending - } - JoinHandleState::Finished(retval) => { - let Some(retval) = retval.take() else { - panic!("already returned Poll::Ready"); - }; - Poll::Ready(retval) - } - } - } -} - -struct ForkJoinImpl<'a> { - futures: Vec + 'a>>>, -} - -impl Future for ForkJoinImpl<'_> { - type Output = (); - fn poll(self: Pin<&mut Self>, cx: &mut std::task::Context<'_>) -> Poll { - let Self { futures } = self.get_mut(); - futures.retain_mut(|future| future.as_mut().poll(cx).is_pending()); - if futures.is_empty() { - Poll::Ready(()) - } else { - Poll::Pending - } - } -} - -pub trait ForkJoin { - type Output; - #[allow(async_fn_in_trait, reason = "no auto traits needed")] - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output; -} - -impl O, O, const N: usize> ForkJoin for [F; N] { - type Output = [O; N]; - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { - let mut temp = [const { None }; N]; - ForkJoinImpl { - futures: this - .into_iter() - .zip(&mut temp) - .map(|(future, temp)| -> Pin + '_>> { - Box::pin(async { *temp = Some(future(sim_state.forked_state()).await) }) - }) - .collect(), - } - .await; - temp.map(|output| output.expect("set to Some above")) - } -} - -impl O, O> ForkJoin for Vec { - type Output = Vec; - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { - let mut temp = Vec::with_capacity(this.len()); - for _ in 0..this.len() { - temp.push(None); - } - ForkJoinImpl { - futures: this - .into_iter() - .zip(&mut temp) - .map(|(future, temp)| -> Pin + '_>> { - Box::pin(async { *temp = Some(future(sim_state.forked_state()).await) }) - }) - .collect(), - } - .await; - temp.into_iter() - .map(|output| output.expect("set to Some above")) - .collect() - } -} - -impl O, O> ForkJoin for Box<[F]> { - type Output = Box<[O]>; - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { - Vec::fork_join(this.into(), sim_state) - .await - .into_boxed_slice() - } -} - -impl ForkJoin for Box { - type Output = Box; - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { - Box::new(T::fork_join(*this, sim_state).await) - } -} - -macro_rules! impl_fork_join_tuples { - (@impl $(($f:ident: $F:ident => $o:ident: $O:ident)),*) => { - impl<$($F: AsyncFnOnce(ExternModuleSimulationState) -> $O, $O,)*> ForkJoin for ($($F,)*) { - type Output = ($($O,)*); - async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { - #![allow(unused_variables)] - let ($($f,)*) = this; - $(let mut $o = None;)* - ForkJoinImpl { - futures: vec![ - $(Box::pin(async { $o = Some($f(sim_state.forked_state()).await) }),)* - ], - }.await; - ($($o.expect("set to Some above"),)*) - } - } - }; - (($($first:tt)*) $(, $rest:tt)* $(,)?) => { - impl_fork_join_tuples!(@impl ($($first)*) $(, $rest)*); - impl_fork_join_tuples!($($rest),*); - }; - () => { - impl_fork_join_tuples!(@impl); - }; -} - -impl_fork_join_tuples!((f0: F0 => o0: O0), (f1: F1 => o1: O1), (f2: F2 => o2: O2), (f3: F3 => o3: O3), (f4: F4 => o4: O4), (f5: F5 => o5: O5), (f6: F6 => o6: O6), (f7: F7 => o7: O7), (f8: F8 => o8: O8), (f9: F9 => o9: O9), (f10: F10 => o10: O10), (f11: F11 => o11: O11),); - pub trait ExternModuleSimGenerator: Clone + Eq + Hash + Any + Send + Sync + fmt::Debug { fn run<'a>(&'a self, sim: ExternModuleSimulationState) -> impl IntoFuture + 'a; } @@ -4165,7 +2965,7 @@ impl fmt::Debug for ExternModuleSimulation { .field("generator", &self.generator) .field( "sim_io_to_generator_map", - &SortedMapDebug(&*self.sim_io_to_generator_map), + &SortedMapDebug(&self.sim_io_to_generator_map), ) .field("source_location", &self.source_location) .finish() diff --git a/crates/fayalite/src/sim/compiler.rs b/crates/fayalite/src/sim/compiler.rs index 7a0ac0a..fbede7b 100644 --- a/crates/fayalite/src/sim/compiler.rs +++ b/crates/fayalite/src/sim/compiler.rs @@ -28,12 +28,12 @@ use crate::{ ExternModuleSimulation, SimTrace, SimTraceKind, SimTraces, TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl, TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance, TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, - TraceMemoryLocation, TraceModule, TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, - TraceScalarId, TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, + TraceMemoryLocation, TraceModule, TraceModuleIO, TraceReg, TraceSInt, TraceScalarId, + TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, interpreter::{ - self, Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding, - InsnsBuildingDone, InsnsBuildingKind, Label, PrefixLinesWrapper, SmallUInt, - StatePartArrayIndex, StatePartArrayIndexed, + Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding, + InsnsBuildingDone, InsnsBuildingKind, Label, SmallUInt, StatePartArrayIndex, + StatePartArrayIndexed, parts::{ MemoryData, SlotDebugData, StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots, StatePartKindMemories, StatePartKindSimOnlySlots, @@ -82,73 +82,19 @@ pub(crate) struct CompiledBundleField { pub(crate) ty: CompiledTypeLayout, } -impl CompiledBundleField { - fn with_prefixed_debug_names(self, prefix: &str) -> Self { - let Self { offset, ty } = self; - Self { - offset, - ty: ty.with_prefixed_debug_names(prefix), - } - } - fn with_anonymized_debug_info(self) -> Self { - let Self { offset, ty } = self; - Self { - offset, - ty: ty.with_anonymized_debug_info(), - } - } -} - #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)] pub(crate) enum CompiledTypeLayoutBody { Scalar, - PhantomConst, Array { - /// always has at least one element even for zero-sized arrays - elements_non_empty: Interned<[CompiledTypeLayout]>, + /// debug names are ignored, use parent's layout instead + element: Interned>, }, Bundle { + /// debug names are ignored, use parent's layout instead fields: Interned<[CompiledBundleField]>, }, } -impl CompiledTypeLayoutBody { - fn with_prefixed_debug_names(self, prefix: &str) -> Self { - match self { - CompiledTypeLayoutBody::Scalar | CompiledTypeLayoutBody::PhantomConst => self, - CompiledTypeLayoutBody::Array { elements_non_empty } => CompiledTypeLayoutBody::Array { - elements_non_empty: elements_non_empty - .iter() - .map(|element| element.with_prefixed_debug_names(prefix)) - .collect(), - }, - CompiledTypeLayoutBody::Bundle { fields } => CompiledTypeLayoutBody::Bundle { - fields: fields - .iter() - .map(|field| field.with_prefixed_debug_names(prefix)) - .collect(), - }, - } - } - fn with_anonymized_debug_info(self) -> Self { - match self { - CompiledTypeLayoutBody::Scalar | CompiledTypeLayoutBody::PhantomConst => self, - CompiledTypeLayoutBody::Array { elements_non_empty } => CompiledTypeLayoutBody::Array { - elements_non_empty: elements_non_empty - .iter() - .map(|element| element.with_anonymized_debug_info()) - .collect(), - }, - CompiledTypeLayoutBody::Bundle { fields } => CompiledTypeLayoutBody::Bundle { - fields: fields - .iter() - .map(|field| field.with_anonymized_debug_info()) - .collect(), - }, - } - } -} - #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)] pub(crate) struct CompiledTypeLayout { pub(crate) ty: T, @@ -162,7 +108,7 @@ impl CompiledTypeLayout { Self { ty, layout: layout.with_prefixed_debug_names(prefix), - body: body.with_prefixed_debug_names(prefix), + body, } } fn with_anonymized_debug_info(self) -> Self { @@ -170,7 +116,7 @@ impl CompiledTypeLayout { Self { ty, layout: layout.with_anonymized_debug_info(), - body: body.with_anonymized_debug_info(), + body, } } fn get(ty: T) -> Self { @@ -205,29 +151,28 @@ impl CompiledTypeLayout { } CanonicalType::Array(array) => { let mut layout = TypeLayout::empty(); - let element = CompiledTypeLayout::get(array.element()); - let mut elements_non_empty = vec![]; + let element = CompiledTypeLayout::get(array.element()).intern_sized(); for index in 0..array.len() { - let element = element.with_prefixed_debug_names(&format!("[{index}]")); - layout.allocate(&element.layout); - elements_non_empty.push(element); - } - if array.is_empty() { - elements_non_empty.push(element.with_prefixed_debug_names("[]")); + layout.allocate( + &element + .layout + .with_prefixed_debug_names(&format!("[{index}]")), + ); } CompiledTypeLayout { ty: *input, layout: layout.into(), - body: CompiledTypeLayoutBody::Array { - elements_non_empty: elements_non_empty.intern_deref(), - }, + body: CompiledTypeLayoutBody::Array { element }, + } + } + CanonicalType::PhantomConst(_) => { + let unit_layout = CompiledTypeLayout::get(()); + CompiledTypeLayout { + ty: *input, + layout: unit_layout.layout, + body: unit_layout.body, } } - CanonicalType::PhantomConst(_) => CompiledTypeLayout { - ty: *input, - layout: TypeLayout::empty(), - body: CompiledTypeLayoutBody::PhantomConst, - }, CanonicalType::Bundle(bundle) => { let mut layout = TypeLayout::empty(); let fields = bundle @@ -239,9 +184,13 @@ impl CompiledTypeLayout { flipped: _, ty, }| { - let ty = CompiledTypeLayout::get(*ty) - .with_prefixed_debug_names(&format!(".{name}")); - let offset = layout.allocate(&ty.layout).start(); + let ty = CompiledTypeLayout::get(*ty); + let offset = layout + .allocate( + &ty.layout + .with_prefixed_debug_names(&format!(".{name}")), + ) + .start(); CompiledBundleField { offset, ty } }, ) @@ -324,39 +273,6 @@ impl CompiledValue { } } -pub(crate) struct DebugCompiledValueStateAsMap<'a> { - pub(crate) compiled_value: CompiledValue, - pub(crate) state_layout: &'a interpreter::parts::StateLayout, - pub(crate) state: &'a interpreter::State, -} - -impl fmt::Debug for DebugCompiledValueStateAsMap<'_> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - use fmt::Write; - if self.compiled_value.range.is_empty() { - return f.write_str("{}"); - } - writeln!(f, "{{")?; - let mut f = PrefixLinesWrapper::new(f, true, " "); - macro_rules! debug_fmt { - ( - type_plural_fields = [$($type_plural_field:ident,)*]; - ) => { - $(for slot in self.compiled_value.range.$type_plural_field.iter() { - slot.debug_fmt(&mut f, ":", " ", " ", "", Some(self.state_layout), Some(self.state))?; - writeln!(f, ",")?; - })* - }; - } - get_state_part_kinds! { - debug_fmt! { - type_plural_fields; - } - } - write!(f.into_inner(), "}}") - } -} - impl CompiledValue { fn field_by_index(self, field_index: usize) -> CompiledValue { self.map(|layout, range| { @@ -385,13 +301,10 @@ impl CompiledValue { impl CompiledValue { pub(crate) fn element(self, index: usize) -> CompiledValue { self.map(|layout, range| { - let CompiledTypeLayoutBody::Array { elements_non_empty } = layout.body else { + let CompiledTypeLayoutBody::Array { element } = layout.body else { unreachable!(); }; - ( - elements_non_empty[index], - range.index_array(elements_non_empty[index].layout.len(), index), - ) + (*element, range.index_array(element.layout.len(), index)) }) } fn element_dyn( @@ -644,11 +557,10 @@ impl CompiledExpr { self, index_slot: StatePartIndex, ) -> CompiledExpr { - let CompiledTypeLayoutBody::Array { elements_non_empty } = self.static_part.layout.body - else { + let CompiledTypeLayoutBody::Array { element } = self.static_part.layout.body else { unreachable!(); }; - let stride = elements_non_empty[0].layout.len(); + let stride = element.layout.len(); let indexes = self.indexes.join(TypeArrayIndex::from_parts( index_slot, self.static_part.layout.ty.len(), @@ -656,10 +568,10 @@ impl CompiledExpr { )); CompiledExpr { static_part: self.static_part.map(|layout, range| { - let CompiledTypeLayoutBody::Array { elements_non_empty } = layout.body else { + let CompiledTypeLayoutBody::Array { element } = layout.body else { unreachable!(); }; - (elements_non_empty[0], range.index_array(stride, 0)) + (*element, range.index_array(stride, 0)) }), indexes, } @@ -1638,13 +1550,6 @@ struct ClockTrigger { source_location: SourceLocation, } -#[derive(Debug, Clone, Copy, Hash, PartialEq, Eq)] -pub(crate) struct ExternModuleClockForPast { - pub(crate) clock_for_past: CompiledValue, - pub(crate) current_to_past_map: - Interned<[(CompiledValue, CompiledValue)]>, -} - #[derive(Debug)] struct Register { value: CompiledValue, @@ -1732,9 +1637,7 @@ impl fmt::Debug for DebugOpaque { pub(crate) struct CompiledExternModule { pub(crate) module_io_targets: Interned<[Target]>, pub(crate) module_io: Interned<[CompiledValue]>, - pub(crate) clocks_for_past: Interned<[ExternModuleClockForPast]>, pub(crate) simulation: ExternModuleSimulation, - pub(crate) debug_name: Interned, } #[derive(Debug)] @@ -1778,23 +1681,18 @@ macro_rules! impl_compiler { instantiated_module: InstantiatedModule, target: MakeTraceDeclTarget, source_location: SourceLocation, - empty_kind: impl FnOnce() -> SimTraceKind, $($type_singular_field: impl FnOnce(StatePartIndex<$type_kind>) -> SimTraceKind,)* ) -> TraceLocation { match target { MakeTraceDeclTarget::Expr(target) => { let compiled_value = self.compile_expr(instantiated_module, target); let compiled_value = self.compiled_expr_to_value(compiled_value, source_location); - if compiled_value.range.is_empty() { - TraceLocation::Scalar(self.new_sim_trace(empty_kind())) - } else { - TraceLocation::Scalar(self.new_sim_trace(match compiled_value.range.len().as_single() { - $(Some(TypeLenSingle::$type_singular_variant) => { - $type_singular_field(compiled_value.range.$type_plural_field.start) - })* - None => unreachable!(), - })) - } + TraceLocation::Scalar(self.new_sim_trace(match compiled_value.range.len().as_single() { + $(Some(TypeLenSingle::$type_singular_variant) => { + $type_singular_field(compiled_value.range.$type_plural_field.start) + })* + None => unreachable!(), + })) } MakeTraceDeclTarget::Memory { id, @@ -1825,10 +1723,9 @@ macro_rules! impl_compiler { instantiated_module, target, source_location, - || unreachable!(), |index| SimTraceKind::SmallUInt { index, ty }, |index| SimTraceKind::BigUInt { index, ty }, - |_| unreachable!(), + |_| unreachable!(""), ), name, ty, @@ -1840,10 +1737,9 @@ macro_rules! impl_compiler { instantiated_module, target, source_location, - || unreachable!(), |index| SimTraceKind::SmallSInt { index, ty }, |index| SimTraceKind::BigSInt { index, ty }, - |_| unreachable!(), + |_| unreachable!(""), ), name, ty, @@ -1855,10 +1751,9 @@ macro_rules! impl_compiler { instantiated_module, target, source_location, - || unreachable!(), |index| SimTraceKind::SmallBool { index }, |index| SimTraceKind::BigBool { index }, - |_| unreachable!(), + |_| unreachable!(""), ), name, flow, @@ -1903,16 +1798,15 @@ macro_rules! impl_compiler { } .into() } - CanonicalType::Bundle(_) => unreachable!(), + CanonicalType::Bundle(_) | CanonicalType::PhantomConst(_) => unreachable!(), CanonicalType::AsyncReset(_) => TraceAsyncReset { location: self.make_trace_scalar_helper( instantiated_module, target, source_location, - || unreachable!(), |index| SimTraceKind::SmallAsyncReset { index }, |index| SimTraceKind::BigAsyncReset { index }, - |_| unreachable!(), + |_| unreachable!(""), ), name, flow, @@ -1923,10 +1817,9 @@ macro_rules! impl_compiler { instantiated_module, target, source_location, - || unreachable!(), |index| SimTraceKind::SmallSyncReset { index }, |index| SimTraceKind::BigSyncReset { index }, - |_| unreachable!(), + |_| unreachable!(""), ), name, flow, @@ -1938,38 +1831,21 @@ macro_rules! impl_compiler { instantiated_module, target, source_location, - || unreachable!(), |index| SimTraceKind::SmallClock { index }, |index| SimTraceKind::BigClock { index }, - |_| unreachable!(), + |_| unreachable!(""), ), name, flow, } .into(), - CanonicalType::PhantomConst(ty) => TracePhantomConst { - location: self.make_trace_scalar_helper( - instantiated_module, - target, - source_location, - || SimTraceKind::PhantomConst { ty }, - |_| unreachable!(), - |_| unreachable!(), - |_| unreachable!(), - ), - name, - ty, - flow, - } - .into(), CanonicalType::DynSimOnly(ty) => TraceSimOnly { location: self.make_trace_scalar_helper( instantiated_module, target, source_location, - || unreachable!(), - |_| unreachable!(), - |_| unreachable!(), + |_| unreachable!(""), + |_| unreachable!(""), |index| SimTraceKind::SimOnly { index, ty }, ), name, @@ -2419,10 +2295,16 @@ impl Compiler { | CanonicalType::SyncReset(_) | CanonicalType::Reset(_) | CanonicalType::Clock(_) - | CanonicalType::DynSimOnly(_) - | CanonicalType::PhantomConst(_) => { + | CanonicalType::DynSimOnly(_) => { self.make_trace_scalar(instantiated_module, target, name, source_location) } + CanonicalType::PhantomConst(_) => TraceBundle { + name, + fields: Interned::default(), + ty: Bundle::new(Interned::default()), + flow: target.flow(), + } + .into(), } } fn make_trace_decl( @@ -4014,15 +3896,18 @@ impl Compiler { self.enum_discriminants.insert(enum_value, retval); retval } - fn compile_reg( + fn compile_stmt_reg( &mut self, - clk: CompiledValue, - reset_and_init: Option<(Expr, CompiledValue)>, - source_location: SourceLocation, + stmt_reg: StmtReg, instantiated_module: InstantiatedModule, value: CompiledValue, ) { - let clk = self.compile_clock(clk, source_location); + let StmtReg { annotations, reg } = stmt_reg; + let clk = self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().clk)); + let clk = self + .compiled_expr_to_value(clk, reg.source_location()) + .map_ty(Clock::from_canonical); + let clk = self.compile_clock(clk, reg.source_location()); struct Dispatch; impl ResetTypeDispatch for Dispatch { type Input = (); @@ -4041,15 +3926,18 @@ impl Compiler { true } } - let reset = if let Some((rst_expr, init)) = reset_and_init { - let rst = self.compile_expr(instantiated_module, Expr::canonical(rst_expr)); - let rst = self.compiled_expr_to_value(rst, source_location); - let rst = self.compiled_value_bool_dest_is_small(rst, source_location); + let reset = if let Some(init) = reg.init() { + let init = self.compile_expr(instantiated_module, init); + let init = self.compiled_expr_to_value(init, reg.source_location()); + let rst = + self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().rst)); + let rst = self.compiled_expr_to_value(rst, reg.source_location()); + let rst = self.compiled_value_bool_dest_is_small(rst, reg.source_location()); let is_async = R::dispatch((), Dispatch); if is_async { - let cond = Expr::canonical(rst_expr.cast_to(Bool)); + let cond = Expr::canonical(reg.clock_domain().rst.cast_to(Bool)); let cond = self.compile_expr(instantiated_module, cond); - let cond = self.compiled_expr_to_value(cond, source_location); + let cond = self.compiled_expr_to_value(cond, reg.source_location()); let cond = cond.map_ty(Bool::from_canonical); // write to the register's current value since asynchronous reset is combinational let lhs = CompiledValue { @@ -4061,12 +3949,12 @@ impl Compiler { self.compile_simple_connect( [Cond { body: CondBody::IfTrue { cond }, - source_location: source_location, + source_location: reg.source_location(), }] .intern_slice(), lhs, init, - source_location, + reg.source_location(), ); } Some(RegisterReset { @@ -4081,33 +3969,9 @@ impl Compiler { value, clk_triggered: clk.clk_triggered, reset, - source_location, + source_location: reg.source_location(), }); } - fn compile_stmt_reg( - &mut self, - stmt_reg: StmtReg, - instantiated_module: InstantiatedModule, - value: CompiledValue, - ) { - let StmtReg { annotations, reg } = stmt_reg; - let clk = self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().clk)); - let clk = self - .compiled_expr_to_value(clk, reg.source_location()) - .map_ty(Clock::from_canonical); - let reset_and_init = reg.init().map(|init| { - let init = self.compile_expr(instantiated_module, init); - let init = self.compiled_expr_to_value(init, reg.source_location()); - (reg.clock_domain().rst, init) - }); - self.compile_reg( - clk, - reset_and_init, - reg.source_location(), - instantiated_module, - value, - ); - } fn compile_declaration( &mut self, declaration: StmtDeclaration, @@ -4373,24 +4237,24 @@ impl Compiler { insns.push(end_label.into()); } } - CompiledTypeLayoutBody::Array { elements_non_empty } => { + CompiledTypeLayoutBody::Array { element } => { let CompiledTypeLayoutBody::Array { - elements_non_empty: mask_elements_non_empty, + element: mask_element, } = mask_layout.body else { unreachable!(); }; let ty = ::from_canonical(data_layout.ty); let element_bit_width = ty.element().bit_width(); - let element_size = elements_non_empty[0].layout.len(); - let mask_element_size = mask_elements_non_empty[0].layout.len(); + let element_size = element.layout.len(); + let mask_element_size = mask_element.layout.len(); for element_index in 0..ty.len() { self.compile_memory_port_rw_helper( memory, stride, start, - elements_non_empty[element_index], - mask_elements_non_empty[element_index], + *element, + *mask_element, read.as_mut().map( |MemoryPortReadInsns { addr, @@ -4429,7 +4293,6 @@ impl Compiler { start += element_bit_width; } } - CompiledTypeLayoutBody::PhantomConst => {} CompiledTypeLayoutBody::Bundle { fields } => { let CompiledTypeLayoutBody::Bundle { fields: mask_fields, @@ -4997,88 +4860,6 @@ impl Compiler { } } } - fn compile_extern_module_clock_for_past( - &mut self, - instantiated_module: InstantiatedModule, - clock_for_past: Target, - ) -> ExternModuleClockForPast { - let clock_for_past = TargetInInstantiatedModule { - instantiated_module, - target: clock_for_past, - }; - let clock_for_past = self - .compile_value(clock_for_past) - .map_ty(Clock::from_canonical); - let clock_for_past_debug_name = match clock_for_past - .range - .len() - .as_single() - .expect("Clock is a single slot") - { - TypeLenSingle::BigSlot => { - self.insns - .state_layout - .ty - .big_slots - .debug_data(clock_for_past.range.start().big_slots) - .name - } - TypeLenSingle::SmallSlot => { - self.insns - .state_layout - .ty - .small_slots - .debug_data(clock_for_past.range.start().small_slots) - .name - } - TypeLenSingle::SimOnlySlot => { - unreachable!() - } - }; - let module_prefix = format!("{instantiated_module:?}."); - let trimmed_clock_for_past_debug_name = clock_for_past_debug_name - .strip_prefix(&module_prefix) - .unwrap_or(&clock_for_past_debug_name); - let current_to_past_map = instantiated_module - .leaf_module() - .module_io() - .iter() - .map( - |&AnnotatedModuleIO { - annotations: _, - module_io, - }| { - let target_base = TargetBase::from(module_io); - let current = self.compile_value(TargetInInstantiatedModule { - instantiated_module, - target: target_base.into(), - }); - let unprefixed_layout = CompiledTypeLayout::get(module_io.ty()); - let past_layout = unprefixed_layout.with_prefixed_debug_names(&format!( - "{module_prefix}{:?}$past({trimmed_clock_for_past_debug_name})", - target_base.target_name(), - )); - let past = CompiledValue { - range: self.insns.allocate_variable(&past_layout.layout), - layout: past_layout, - write: Some((current.layout, current.range)), - }; - self.compile_reg::( - clock_for_past, - None, - module_io.source_location(), - instantiated_module, - past, - ); - (current, past) - }, - ) - .collect(); - ExternModuleClockForPast { - clock_for_past, - current_to_past_map, - } - } fn compile_module(&mut self, module: Interned) -> &CompiledModule { let mut trace_decls = Vec::new(); let module_io = module @@ -5107,7 +4888,6 @@ impl Compiler { ModuleBody::Extern(ExternModuleBody { verilog_name: _, parameters: _, - clocks_for_past, simulation, }) => { let Some(simulation) = simulation else { @@ -5124,18 +4904,10 @@ impl Compiler { Target::from(*simulation.sim_io_to_generator_map[&v.module_io.intern()]) }) .collect(); - let clocks_for_past = clocks_for_past - .iter() - .map(|clock_for_past| { - self.compile_extern_module_clock_for_past(*module, *clock_for_past) - }) - .collect(); self.extern_modules.push(CompiledExternModule { module_io_targets, module_io, - clocks_for_past, simulation, - debug_name: format!("{module:?}").intern_deref(), }); } } diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs index 391172e..1a6c269 100644 --- a/crates/fayalite/src/sim/interpreter.rs +++ b/crates/fayalite/src/sim/interpreter.rs @@ -196,27 +196,13 @@ impl fmt::Debug for Insn { } } -pub(crate) struct PrefixLinesWrapper<'a, W> { +struct PrefixLinesWrapper<'a, W> { writer: W, at_beginning_of_line: bool, blank_line_prefix: &'a str, line_prefix: &'a str, } -impl<'a, W> PrefixLinesWrapper<'a, W> { - pub(crate) fn new(writer: W, at_beginning_of_line: bool, line_prefix: &'a str) -> Self { - Self { - writer, - at_beginning_of_line, - blank_line_prefix: line_prefix.trim_end(), - line_prefix, - } - } - pub(crate) fn into_inner(self) -> W { - self.writer - } -} - impl fmt::Write for PrefixLinesWrapper<'_, T> { fn write_str(&mut self, input: &str) -> fmt::Result { for part in input.split_inclusive('\n') { @@ -253,7 +239,12 @@ impl Insn { if fields.len() == 0 { return Ok(()); } - let mut f = PrefixLinesWrapper::new(f, false, " "); + let mut f = PrefixLinesWrapper { + writer: f, + at_beginning_of_line: false, + blank_line_prefix: "", + line_prefix: " ", + }; writeln!(f, " {{")?; for (field_name, field) in fields { write!(f, "{field_name}: ")?; @@ -329,7 +320,7 @@ impl Insn { } writeln!(f, ",")?; } - write!(f.into_inner(), "}}") + write!(f.writer, "}}") } } diff --git a/crates/fayalite/src/sim/interpreter/parts.rs b/crates/fayalite/src/sim/interpreter/parts.rs index 75427c9..8732146 100644 --- a/crates/fayalite/src/sim/interpreter/parts.rs +++ b/crates/fayalite/src/sim/interpreter/parts.rs @@ -9,7 +9,7 @@ use crate::{ Insn, InsnsBuilding, InsnsBuildingDone, InsnsBuildingKind, PrefixLinesWrapper, SmallSInt, SmallUInt, State, }, - value::{DynSimOnly, DynSimOnlyValue}, + value::{DynSimOnlyValue, DynSimOnly}, }, ty::CanonicalType, util::{chain, const_str_cmp}, @@ -435,7 +435,12 @@ impl StatePartIndex { if state.is_some() || debug_data.is_some() { f.write_str(comment_start)?; } - let mut f = PrefixLinesWrapper::new(f, false, comment_line_start); + let mut f = PrefixLinesWrapper { + writer: f, + at_beginning_of_line: false, + blank_line_prefix: comment_line_start.trim_end(), + line_prefix: comment_line_start, + }; if let Some(state) = state { f.write_str("(")?; K::debug_fmt_state_value(state, *self, &mut f)?; @@ -448,7 +453,7 @@ impl StatePartIndex { write!(f, "{debug_data:?}")?; } if state.is_some() || debug_data.is_some() { - f.into_inner().write_str(comment_end)?; + f.writer.write_str(comment_end)?; } Ok(()) } diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs index ff836d5..9717417 100644 --- a/crates/fayalite/src/sim/value.rs +++ b/crates/fayalite/src/sim/value.rs @@ -23,10 +23,10 @@ use bitvec::{slice::BitSlice, vec::BitVec}; use hashbrown::hash_map::Entry; use serde::{Deserialize, Deserializer, Serialize, Serializer, de::Error as _, ser::Error as _}; use std::{ - borrow::{Borrow, BorrowMut, Cow}, + borrow::Cow, fmt::{self, Write}, hash::{BuildHasher, Hash, Hasher, RandomState}, - ops::{Deref, DerefMut, Index, IndexMut}, + ops::{Deref, DerefMut}, sync::{Arc, Mutex}, }; @@ -157,13 +157,7 @@ pub struct SimValue { inner: AlternatingCell>, } -impl> fmt::Display for SimValue { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - T::SimValue::fmt(self, f) - } -} - -impl Clone for SimValue { +impl Clone for SimValue { fn clone(&self) -> Self { Self { inner: AlternatingCell::new_unique(self.inner.share().clone()), @@ -370,74 +364,6 @@ impl ToExpr for SimValue { } } -impl Index for SimValue> -where - [SimValue]: Index, -{ - type Output = <[SimValue] as Index>::Output; - - fn index(&self, index: I) -> &Self::Output { - (**self).borrow().index(index) - } -} - -impl IndexMut for SimValue> -where - [SimValue]: IndexMut, -{ - fn index_mut(&mut self, index: I) -> &mut Self::Output { - (**self).borrow_mut().index_mut(index) - } -} - -impl SimValue> { - pub fn iter(&self) -> std::slice::Iter<'_, SimValue> { - (**self).borrow().iter() - } - pub fn iter_mut(&mut self) -> std::slice::IterMut<'_, SimValue> { - (**self).borrow_mut().iter_mut() - } -} - -impl IntoIterator for SimValue> { - type Item = SimValue; - type IntoIter = std::vec::IntoIter>; - - fn into_iter(self) -> Self::IntoIter { - Vec::into_iter(Self::into_value(self).into()) - } -} - -impl<'a, T: Type, Len: Size> IntoIterator for &'a SimValue> { - type Item = &'a SimValue; - type IntoIter = std::slice::Iter<'a, SimValue>; - - fn into_iter(self) -> Self::IntoIter { - self.iter() - } -} - -impl<'a, T: Type, Len: Size> IntoIterator for &'a mut SimValue> { - type Item = &'a mut SimValue; - type IntoIter = std::slice::IterMut<'a, SimValue>; - - fn into_iter(self) -> Self::IntoIter { - self.iter_mut() - } -} - -impl AsRef<[SimValue]> for SimValue> { - fn as_ref(&self) -> &[SimValue] { - (**self).as_ref() - } -} - -impl AsMut<[SimValue]> for SimValue> { - fn as_mut(&mut self) -> &mut [SimValue] { - (**self).as_mut() - } -} - pub trait SimValuePartialEq: Type { #[track_caller] fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool; @@ -468,141 +394,6 @@ impl SimValuePartialEq for Bool { } } -impl SimValuePartialEq for Clock { - fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { - **this == **other - } -} - -impl SimValuePartialEq for Reset { - fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { - **this == **other - } -} - -impl SimValuePartialEq for SyncReset { - fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { - **this == **other - } -} - -impl SimValuePartialEq for AsyncReset { - fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { - **this == **other - } -} - -#[doc(hidden)] -pub mod match_sim_value { - use crate::{ - sim::value::{SimValue, ToSimValue}, - ty::Type, - }; - - #[doc(hidden)] - pub struct MatchSimValueHelper(Option); - - impl MatchSimValueHelper { - pub fn new(v: T) -> Self { - Self(Some(v)) - } - } - - #[doc(hidden)] - pub trait MatchSimValue { - type MatchValue; - - /// use `self` so it comes first in the method resolution order - fn __fayalite_match_sim_value(self) -> Self::MatchValue - where - Self: Sized; - } - - impl MatchSimValue for MatchSimValueHelper> { - type MatchValue = T::SimValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - SimValue::into_value(self.0.expect("should be Some")) - } - } - - impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a SimValue> { - type MatchValue = &'a T::SimValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - SimValue::value(self.0.expect("should be Some")) - } - } - - impl<'a, T: Type> MatchSimValue for MatchSimValueHelper<&'a mut SimValue> { - type MatchValue = &'a mut T::SimValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - SimValue::value_mut(self.0.expect("should be Some")) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ &'a T> - where - MatchSimValueHelper<&'a T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v))) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'_ mut &'a T> - where - MatchSimValueHelper<&'a T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| *v))) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a &'_ mut T> - where - MatchSimValueHelper<&'a T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &**v))) - } - } - - impl<'a, T> MatchSimValue for MatchSimValueHelper<&'a mut &'_ mut T> - where - MatchSimValueHelper<&'a mut T>: MatchSimValue, - { - type MatchValue = as MatchSimValue>::MatchValue; - - fn __fayalite_match_sim_value(self) -> Self::MatchValue { - MatchSimValue::__fayalite_match_sim_value(MatchSimValueHelper(self.0.map(|v| &mut **v))) - } - } - - #[doc(hidden)] - pub trait MatchSimValueFallback { - type MatchValue; - - /// use `&mut self` so it comes later in the method resolution order than MatchSimValue - fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue; - } - - impl MatchSimValueFallback for MatchSimValueHelper { - type MatchValue = ::SimValue; - - fn __fayalite_match_sim_value(&mut self) -> Self::MatchValue { - SimValue::into_value(self.0.take().expect("should be Some").into_sim_value()) - } - } -} - pub trait ToSimValue: ToSimValueWithType<::Type> { type Type: Type; @@ -735,7 +526,7 @@ impl ToSimValueWithType for BitSlice { } } -impl<'a, This: ?Sized + ToSimValue> ToSimValue for &'a This { +impl ToSimValue for &'_ This { type Type = This::Type; fn to_sim_value(&self) -> SimValue { @@ -1511,20 +1302,6 @@ impl ToSimValue for SimOnlyValue { } } -impl SimValuePartialEq for DynSimOnly { - fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { - **this == **other - } -} - -impl, U: SimOnlyValueTrait> SimValuePartialEq> - for SimOnly -{ - fn sim_value_eq(this: &SimValue, other: &SimValue>) -> bool { - ***this == ***other - } -} - #[cfg(test)] mod tests { use super::*; diff --git a/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs b/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs index 3df80a8..98a199c 100644 --- a/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs +++ b/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs @@ -206,25 +206,9 @@ impl Default for SimOnly { } /// a value that can only be used in a Fayalite simulation, it can't be converted to FIRRTL -#[derive(Clone, Eq, Hash, Default, Ord)] +#[derive(Clone, Eq, PartialEq, Hash, Default, PartialOrd, Ord)] pub struct SimOnlyValue(Rc); -impl, U: SimOnlyValueTrait> PartialEq> - for SimOnlyValue -{ - fn eq(&self, other: &SimOnlyValue) -> bool { - >::eq(self, other) - } -} - -impl, U: SimOnlyValueTrait> PartialOrd> - for SimOnlyValue -{ - fn partial_cmp(&self, other: &SimOnlyValue) -> Option { - >::partial_cmp(self, other) - } -} - impl SimOnlyValue { pub fn with_dyn_ref R, R>(&self, f: F) -> R { // Safety: creating a copied `Rc` is safe as long as the copy isn't dropped and isn't changed diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs index 6ba37b3..e66c3ee 100644 --- a/crates/fayalite/src/sim/vcd.rs +++ b/crates/fayalite/src/sim/vcd.rs @@ -6,14 +6,12 @@ use crate::{ expr::Flow, int::UInt, intern::{Intern, Interned}, - prelude::PhantomConst, sim::{ TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl, TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance, TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation, TraceModule, - TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, TraceScalar, TraceScalarId, - TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, TraceWriter, - TraceWriterDecls, + TraceModuleIO, TraceReg, TraceSInt, TraceScalar, TraceScalarId, TraceScope, TraceSimOnly, + TraceSyncReset, TraceUInt, TraceWire, TraceWriter, TraceWriterDecls, time::{SimDuration, SimInstant}, value::DynSimOnlyValue, }, @@ -285,7 +283,6 @@ impl WriteTrace for TraceScalar { Self::Clock(v) => v.write_trace(writer, arg), Self::SyncReset(v) => v.write_trace(writer, arg), Self::AsyncReset(v) => v.write_trace(writer, arg), - Self::PhantomConst(v) => v.write_trace(writer, arg), Self::SimOnly(v) => v.write_trace(writer, arg), } } @@ -552,33 +549,6 @@ impl WriteTrace for TraceAsyncReset { } } -impl WriteTrace for TracePhantomConst { - fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { - let ArgInType { - source_var_type: _, - sink_var_type: _, - duplex_var_type: _, - properties, - scope, - } = arg.in_type(); - let Self { - location, - name, - ty: _, - flow: _, - } = self; - write_vcd_var( - properties, - MemoryElementPartBody::Scalar, - writer, - "string", - 1, - location, - scope.new_identifier(name), - ) - } -} - impl WriteTrace for TraceSimOnly { fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { let ArgInType { @@ -1121,16 +1091,6 @@ impl TraceWriter for VcdWriter { write_enum_discriminant_value_change(&mut self.writer, variant_index, ty, id.as_usize()) } - fn set_signal_phantom_const( - &mut self, - id: TraceScalarId, - ty: PhantomConst, - ) -> Result<(), Self::Error> { - // avoid multi-line strings because GTKWave can't display them properly: - // https://github.com/gtkwave/gtkwave/issues/460 - write_string_value_change(&mut self.writer, format_args!("{ty:?}"), id.as_usize()) - } - fn set_signal_sim_only_value( &mut self, id: TraceScalarId, diff --git a/crates/fayalite/src/ty/serde_impls.rs b/crates/fayalite/src/ty/serde_impls.rs index af324f9..1ca916b 100644 --- a/crates/fayalite/src/ty/serde_impls.rs +++ b/crates/fayalite/src/ty/serde_impls.rs @@ -127,7 +127,7 @@ impl From for CanonicalType { SerdeCanonicalType::Reset => Self::Reset(Reset), SerdeCanonicalType::Clock => Self::Clock(Clock), SerdeCanonicalType::PhantomConst(value) => { - Self::PhantomConst(PhantomConst::new_interned(value.0)) + Self::PhantomConst(PhantomConst::new(value.0)) } SerdeCanonicalType::DynSimOnly(value) => Self::DynSimOnly(value), } diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs index 5030282..148cb64 100644 --- a/crates/fayalite/tests/hdl_types.rs +++ b/crates/fayalite/tests/hdl_types.rs @@ -214,33 +214,3 @@ pub struct MyTypeWithPhantomConstParameter>, pub b: HdlOption>, } - -#[hdl(outline_generated)] -struct MyPrivateType {} - -#[hdl(outline_generated)] -pub(crate) struct MyPubCrateType {} - -#[hdl(outline_generated)] -pub struct MyTypeWithPrivateMembers { - a: MyPrivateType, - pub(crate) b: MyPubCrateType, - pub c: Bool, -} - -#[hdl(outline_generated)] -struct MyPrivateTypeWithArg { - v: T, -} - -#[hdl(outline_generated)] -pub(crate) struct MyPubCrateTypeWithArg { - v: T, -} - -#[hdl(outline_generated)] -pub struct MyTypeWithPrivateMembersWithArg { - a: MyPrivateTypeWithArg, - pub(crate) b: MyPubCrateTypeWithArg, - pub c: T, -} diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index be4e207..873978a 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -506,10 +506,10 @@ fn test_enums() { data_out: _, b_out: _, b2_out: _, - } = &expected; - sim.write(sim.io().en, en); - sim.write(sim.io().which_in, which_in); - sim.write(sim.io().data_in, data_in); + } = expected; + sim.write(sim.io().en, &en); + sim.write(sim.io().which_in, &which_in); + sim.write(sim.io().data_in, &data_in); let io = #[hdl(sim)] IO::<_> { en, @@ -528,7 +528,7 @@ fn test_enums() { ); // make sure matching on SimValue works #[hdl(sim)] - match &io.b_out { + match io.b_out { HdlNone => println!("io.b_out is HdlNone"), HdlSome(v) => println!("io.b_out is HdlSome(({:?}, {:?}))", *v.0, *v.1), } @@ -706,13 +706,13 @@ fn test_memories() { w_en, w_data, w_mask, - } = &expected; - sim.write(sim.io().r.addr, r_addr); - sim.write(sim.io().r.en, r_en); - sim.write(sim.io().w.addr, w_addr); - sim.write(sim.io().w.en, w_en); - sim.write(sim.io().w.data, w_data); - sim.write(sim.io().w.mask, w_mask); + } = expected; + sim.write(sim.io().r.addr, &r_addr); + sim.write(sim.io().r.en, &r_en); + sim.write(sim.io().w.addr, &w_addr); + sim.write(sim.io().w.en, &w_en); + sim.write(sim.io().w.data, &w_data); + sim.write(sim.io().w.mask, &w_mask); let io = #[hdl(sim)] IO { r_addr, @@ -1505,7 +1505,7 @@ fn test_many_memories() { w_en, w_data, w_mask, - } = &expected; + } = expected; for (((r, w), w_data), w_mask) in sim .io() .r @@ -1514,10 +1514,10 @@ fn test_many_memories() { .zip(w_data.iter()) .zip(w_mask.iter()) { - sim.write(r.addr, r_addr); - sim.write(r.en, r_en); - sim.write(w.addr, w_addr); - sim.write(w.en, w_en); + sim.write(r.addr, &r_addr); + sim.write(r.en, &r_en); + sim.write(w.addr, &w_addr); + sim.write(w.en, &w_en); sim.write(w.data, w_data); sim.write(w.mask, w_mask); } @@ -2026,472 +2026,3 @@ fn test_sim_only_connects() { panic!(); } } - -#[hdl_module(outline_generated, extern)] -pub fn sim_fork_join() -where - ConstUsize: KnownSize, -{ - #[hdl] - let clocks: Array = m.input(); - #[hdl] - let outputs: Array, N> = m.output(); - m.extern_module_simulation_fn((clocks, outputs), |(clocks, outputs), mut sim| async move { - sim.write(outputs, [0u8; N]).await; - loop { - sim.fork_join( - clocks - .into_iter() - .zip(outputs) - .map(|(clock, output)| { - move |mut sim: ExternModuleSimulationState| async move { - sim.wait_for_clock_edge(clock).await; - let v = sim - .read_bool_or_int(output) - .await - .to_bigint() - .try_into() - .expect("known to be in range"); - sim.write(output, 1u8.wrapping_add(v)).await; - } - }) - .collect::>(), - ) - .await; - } - }); -} - -#[test] -fn test_sim_fork_join() { - let _n = SourceLocation::normalize_files_for_tests(); - const N: usize = 3; - let mut sim = Simulation::new(sim_fork_join::()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - sim.write(sim.io().clocks, [false; N]); - let mut clocks_triggered = [false; N]; - let mut expected = [0u8; N]; - for i0 in 0..N { - for i1 in 0..N { - for i2 in 0..N { - for i3 in 0..N { - let indexes = [i0, i1, i2, i3]; - for i in indexes { - sim.advance_time(SimDuration::from_micros(1)); - sim.write(sim.io().clocks[i], true); - sim.advance_time(SimDuration::from_micros(1)); - sim.write(sim.io().clocks[i], false); - if !clocks_triggered[i] { - expected[i] = expected[i].wrapping_add(1); - } - clocks_triggered[i] = true; - if clocks_triggered == [true; N] { - clocks_triggered = [false; N]; - } - let output = sim.read(sim.io().outputs); - assert_eq!(output, expected.to_sim_value(), "indexes={indexes:?} i={i}"); - } - } - } - } - } - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/sim_fork_join.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/sim_fork_join.txt") { - panic!(); - } -} - -#[hdl_module(outline_generated, extern)] -pub fn sim_fork_join_scope() -where - ConstUsize: KnownSize, -{ - #[hdl] - let clocks: Array = m.input(); - #[hdl] - let outputs: Array, N> = m.output(); - m.extern_module_simulation_fn((clocks, outputs), |(clocks, outputs), mut sim| async move { - sim.write(outputs, [0u8; N]).await; - loop { - let written = vec![std::cell::Cell::new(false); N]; // test shared scope - let written = &written; // work around move in async move - sim.fork_join_scope(|scope, _| async move { - let mut spawned = vec![]; - for i in 0..N { - let join_handle = - scope.spawn(move |_, mut sim: ExternModuleSimulationState| async move { - sim.wait_for_clock_edge(clocks[i]).await; - let v = sim - .read_bool_or_int(outputs[i]) - .await - .to_bigint() - .try_into() - .expect("known to be in range"); - sim.write(outputs[i], 1u8.wrapping_add(v)).await; - written[i].set(true); - i - }); - if i % 2 == 0 && i < N - 1 { - spawned.push((i, join_handle)); - } - } - for (i, join_handle) in spawned { - assert_eq!(i, join_handle.join().await); - } - }) - .await; - for written in written { - assert!(written.get()); - } - } - }); -} - -#[test] -fn test_sim_fork_join_scope() { - let _n = SourceLocation::normalize_files_for_tests(); - const N: usize = 3; - let mut sim = Simulation::new(sim_fork_join_scope::()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - sim.write(sim.io().clocks, [false; N]); - let mut clocks_triggered = [false; N]; - let mut expected = [0u8; N]; - for i0 in 0..N { - for i1 in 0..N { - for i2 in 0..N { - for i3 in 0..N { - let indexes = [i0, i1, i2, i3]; - for i in indexes { - sim.advance_time(SimDuration::from_micros(1)); - sim.write(sim.io().clocks[i], true); - sim.advance_time(SimDuration::from_micros(1)); - sim.write(sim.io().clocks[i], false); - if !clocks_triggered[i] { - expected[i] = expected[i].wrapping_add(1); - } - clocks_triggered[i] = true; - if clocks_triggered == [true; N] { - clocks_triggered = [false; N]; - } - let output = sim.read(sim.io().outputs); - assert_eq!(output, expected.to_sim_value(), "indexes={indexes:?} i={i}"); - } - } - } - } - } - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/sim_fork_join_scope.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/sim_fork_join_scope.txt") { - panic!(); - } -} - -#[hdl_module(outline_generated, extern)] -pub fn sim_resettable_counter() { - #[hdl] - let cd: ClockDomain = m.input(); - #[hdl] - let out: UInt<8> = m.output(); - m.extern_module_simulation_fn((cd, out), |(cd, out), mut sim| async move { - sim.resettable( - cd, - |mut sim: ExternModuleSimulationState| async move { - sim.write(out, 0u8).await; - }, - |mut sim: ExternModuleSimulationState, ()| async move { - loop { - sim.wait_for_clock_edge(cd.clk).await; - let v: u8 = sim - .read(out) - .await - .to_bigint() - .try_into() - .expect("known to be in range"); - sim.write(out, v.wrapping_add(1)).await; - } - }, - ) - .await - }); -} - -fn test_sim_resettable_counter_helper( - sim: &mut Simulation>, - immediate_reset: bool, -) { - sim.write_clock(sim.io().cd.clk, false); - sim.write_reset(sim.io().cd.rst, immediate_reset); - for _ in 0..2 { - sim.advance_time(SimDuration::from_micros(1)); - sim.write_clock(sim.io().cd.clk, true); - sim.advance_time(SimDuration::from_micros(1)); - sim.write_clock(sim.io().cd.clk, false); - sim.write_reset(sim.io().cd.rst, true); - sim.advance_time(SimDuration::from_micros(1)); - sim.write_clock(sim.io().cd.clk, true); - sim.advance_time(SimDuration::from_micros(1)); - sim.write_clock(sim.io().cd.clk, false); - sim.write_reset(sim.io().cd.rst, false); - for expected in 0..3u8 { - assert_eq!(sim.read(sim.io().out), expected.to_sim_value()); - sim.advance_time(SimDuration::from_micros(1)); - sim.write_clock(sim.io().cd.clk, true); - sim.advance_time(SimDuration::from_micros(1)); - sim.write_clock(sim.io().cd.clk, false); - } - } -} - -#[test] -fn test_sim_resettable_counter_sync() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(sim_resettable_counter::()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - test_sim_resettable_counter_helper(&mut sim, false); - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/sim_resettable_counter_sync.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/sim_resettable_counter_sync.txt") { - panic!(); - } -} - -#[test] -fn test_sim_resettable_counter_sync_immediate_reset() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(sim_resettable_counter::()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - test_sim_resettable_counter_helper(&mut sim, true); - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/sim_resettable_counter_sync_immediate_reset.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/sim_resettable_counter_sync_immediate_reset.txt") { - panic!(); - } -} - -#[test] -fn test_sim_resettable_counter_async() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(sim_resettable_counter::()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - test_sim_resettable_counter_helper(&mut sim, false); - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/sim_resettable_counter_async.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/sim_resettable_counter_async.txt") { - panic!(); - } -} - -#[test] -fn test_sim_resettable_counter_async_immediate_reset() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(sim_resettable_counter::()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - test_sim_resettable_counter_helper(&mut sim, true); - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/sim_resettable_counter_async_immediate_reset.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/sim_resettable_counter_async_immediate_reset.txt") { - panic!(); - } -} - -#[hdl_module(outline_generated)] -pub fn phantom_const() { - #[hdl] - let out: Array>, 2> = - m.output(Array::new_static(PhantomConst::new_sized(vec![ - "a".into(), - "b".into(), - ]))); - let _ = out; - #[hdl] - let mut mem = memory(PhantomConst::new("mem_element")); - mem.depth(1); - let port = mem.new_read_port(); - connect_any(port.addr, 0u8); - connect(port.clk, false.to_clock()); - connect(port.en, false); -} - -#[test] -fn test_phantom_const() { - let _n = SourceLocation::normalize_files_for_tests(); - let mut sim = Simulation::new(phantom_const()); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - sim.advance_time(SimDuration::from_micros(1)); - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/phantom_const.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/phantom_const.txt") { - panic!(); - } -} - -#[hdl_module(outline_generated, extern)] -pub fn sim_read_past() -where - ConstUsize: KnownSize, -{ - #[hdl] - let clocks: Array = m.input(); - #[hdl] - let outputs: Array, N> = m.output(); - #[hdl] - let past_clocks: Array = m.output(); - #[hdl] - let past_outputs: Array, N> = m.output(); - for clock in clocks { - m.register_clock_for_past(clock); - } - m.extern_module_simulation_fn( - (clocks, outputs, past_clocks, past_outputs), - |(clocks, outputs, past_clocks, past_outputs), mut sim| async move { - sim.write(outputs, [0u8; N]).await; - sim.write(past_clocks, [false; N]).await; - sim.write(past_outputs, [0u8; N]).await; - loop { - sim.fork_join_scope(|scope, _| async move { - for (clock, output) in clocks.into_iter().zip(outputs) { - scope.spawn_detached( - move |_, mut sim: ExternModuleSimulationState| async move { - sim.wait_for_clock_edge(clock).await; - dbg!(clock); - let v = sim - .read_bool_or_int(output) - .await - .to_bigint() - .try_into() - .expect("known to be in range"); - sim.write(output, 1u8.wrapping_add(v)).await; - let past_outputs_v = sim.read_past(outputs, clock).await; - dbg!(&past_outputs_v); - sim.write(past_outputs, past_outputs_v).await; - let past_clocks_v = sim.read_past(clocks, clock).await; - dbg!(&past_clocks_v); - sim.write(past_clocks, past_clocks_v).await; - }, - ); - } - }) - .await; - } - }, - ); -} - -#[test] -fn test_sim_read_past() { - let _n = SourceLocation::normalize_files_for_tests(); - const N: usize = 3; - let mut sim = Simulation::new(sim_read_past::()); - // sim.set_breakpoints_unstable(Default::default(), true); - let mut writer = RcWriter::default(); - sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); - sim.write(sim.io().clocks, [false; N]); - let mut clocks_triggered = [false; N]; - let mut expected = [0u8; N]; - let mut past_clocks_expected = [false; N]; - let mut past_expected = expected; - for i0 in 0..N { - for i1 in 0..N { - for i2 in 0..N { - for i3 in 0..N { - let indexes = [i0, i1, i2, i3]; - for i in indexes { - sim.advance_time(SimDuration::from_micros(1)); - sim.write(sim.io().clocks[i], true); - sim.advance_time(SimDuration::from_micros(1)); - sim.write(sim.io().clocks[i], false); - if !clocks_triggered[i] { - past_expected = expected; - expected[i] = expected[i].wrapping_add(1); - past_clocks_expected = [false; N]; - past_clocks_expected[i] = true; - } - dbg!(past_expected); - clocks_triggered[i] = true; - if clocks_triggered == [true; N] { - clocks_triggered = [false; N]; - } - let output = sim.read(sim.io().outputs); - assert_eq!(output, expected.to_sim_value(), "indexes={indexes:?} i={i}"); - let past_clocks = sim.read(sim.io().past_clocks); - assert_eq!( - past_clocks, - past_clocks_expected - .to_sim_value_with_type(Array::::default()), - "indexes={indexes:?} i={i}" - ); - let past_outputs = sim.read(sim.io().past_outputs); - dbg!(&past_outputs); - assert_eq!( - past_outputs, - past_expected.to_sim_value(), - "indexes={indexes:?} i={i}" - ); - } - } - } - } - } - sim.flush_traces().unwrap(); - let vcd = String::from_utf8(writer.take()).unwrap(); - println!("####### VCD:\n{vcd}\n#######"); - if vcd != include_str!("sim/expected/sim_read_past.vcd") { - panic!(); - } - let sim_debug = format!("{sim:#?}"); - println!("#######\n{sim_debug}\n#######"); - if sim_debug != include_str!("sim/expected/sim_read_past.txt") { - panic!(); - } -} diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt index 27b040d..12e86f3 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.txt +++ b/crates/fayalite/tests/sim/expected/array_rw.txt @@ -826,9 +826,9 @@ Simulation { }.write_index, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "array_rw", children: [ @@ -1699,12 +1699,7 @@ Simulation { }, ), ], + instant: 34 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 34 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt index d470792..58b2d20 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt @@ -122,9 +122,9 @@ Simulation { }.i, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "conditional_assignment_last", children: [ @@ -177,12 +177,7 @@ Simulation { }, ), ], + instant: 2 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 2 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt index 56ea4ad..182ed84 100644 --- a/crates/fayalite/tests/sim/expected/connect_const.txt +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -98,9 +98,9 @@ Simulation { }.o, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "connect_const", children: [ @@ -130,12 +130,7 @@ Simulation { ], trace_memories: {}, trace_writers: [], + instant: 0 s, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 0 s, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt index a9c1878..f56a6b4 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -141,9 +141,9 @@ Simulation { }.reset_out, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "connect_const_reset", children: [ @@ -197,12 +197,7 @@ Simulation { }, ), ], + instant: 1 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 1 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index 86bde88..8c8809a 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -100,51 +100,51 @@ Simulation { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, }, - 3: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, - }, - 4: AndSmall { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:1:1 - 5: Const { + 3: Const { dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, value: 0x3, }, // at: module-XXXXXXXXXX.rs:3:1 - 6: BranchIfZero { - target: 8, + 4: BranchIfZero { + target: 6, value: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 7: Copy { + 5: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Add { + 6: Add { dest: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, rhs: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, - 9: CastToUInt { + 7: CastToUInt { dest: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, // at: module-XXXXXXXXXX.rs:4:1 - 10: Copy { + 8: Copy { dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, src: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:6:1 - 11: Copy { + 9: Copy { dest: StatePartIndex(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:3:1 + 10: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, + }, + 11: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, 12: BranchIfSmallNonZero { target: 16, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, @@ -261,9 +261,9 @@ Simulation { }.count, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "counter", children: [ @@ -329,7 +329,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x0, + last_state: 0x1, }, SimTrace { id: TraceScalarId(1), @@ -355,7 +355,7 @@ Simulation { ty: UInt<4>, }, state: 0x3, - last_state: 0x2, + last_state: 0x3, }, ], trace_memories: {}, @@ -368,14 +368,9 @@ Simulation { }, ), ], + instant: 66 μs, clocks_triggered: [ StatePartIndex(1), ], - event_queue: EventQueue(EventQueueData { - instant: 66 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_async.vcd b/crates/fayalite/tests/sim/expected/counter_async.vcd index dab690f..a4b2ee9 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.vcd +++ b/crates/fayalite/tests/sim/expected/counter_async.vcd @@ -26,192 +26,192 @@ b11 $ 0! #3000000 1! -b100 # b100 $ +b100 # #4000000 0! #5000000 1! -b101 # b101 $ +b101 # #6000000 0! #7000000 1! -b110 # b110 $ +b110 # #8000000 0! #9000000 1! -b111 # b111 $ +b111 # #10000000 0! #11000000 1! -b1000 # b1000 $ +b1000 # #12000000 0! #13000000 1! -b1001 # b1001 $ +b1001 # #14000000 0! #15000000 1! -b1010 # b1010 $ +b1010 # #16000000 0! #17000000 1! -b1011 # b1011 $ +b1011 # #18000000 0! #19000000 1! -b1100 # b1100 $ +b1100 # #20000000 0! #21000000 1! -b1101 # b1101 $ +b1101 # #22000000 0! #23000000 1! -b1110 # b1110 $ +b1110 # #24000000 0! #25000000 1! -b1111 # b1111 $ +b1111 # #26000000 0! #27000000 1! -b0 # b0 $ +b0 # #28000000 0! #29000000 1! -b1 # b1 $ +b1 # #30000000 0! #31000000 1! -b10 # b10 $ +b10 # #32000000 0! #33000000 1! -b11 # b11 $ +b11 # #34000000 0! #35000000 1! -b100 # b100 $ +b100 # #36000000 0! #37000000 1! -b101 # b101 $ +b101 # #38000000 0! #39000000 1! -b110 # b110 $ +b110 # #40000000 0! #41000000 1! -b111 # b111 $ +b111 # #42000000 0! #43000000 1! -b1000 # b1000 $ +b1000 # #44000000 0! #45000000 1! -b1001 # b1001 $ +b1001 # #46000000 0! #47000000 1! -b1010 # b1010 $ +b1010 # #48000000 0! #49000000 1! -b1011 # b1011 $ +b1011 # #50000000 0! #51000000 1! -b1100 # b1100 $ +b1100 # #52000000 0! #53000000 1! -b1101 # b1101 $ +b1101 # #54000000 0! #55000000 1! -b1110 # b1110 $ +b1110 # #56000000 0! #57000000 1! -b1111 # b1111 $ +b1111 # #58000000 0! #59000000 1! -b0 # b0 $ +b0 # #60000000 0! #61000000 1! -b1 # b1 $ +b1 # #62000000 0! #63000000 1! -b10 # b10 $ +b10 # #64000000 0! #65000000 1! -b11 # b11 $ +b11 # #66000000 diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index 0a7517e..1d975b3 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -112,21 +112,21 @@ Simulation { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset }, }, - 6: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, - }, - 7: AndSmall { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Const { + 6: Const { dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, value: 0x3, }, // at: module-XXXXXXXXXX.rs:3:1 + 7: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, + }, + 8: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, 9: BranchIfSmallZero { target: 14, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, @@ -242,9 +242,9 @@ Simulation { }.count, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "counter", children: [ @@ -310,7 +310,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x0, + last_state: 0x1, }, SimTrace { id: TraceScalarId(1), @@ -336,7 +336,7 @@ Simulation { ty: UInt<4>, }, state: 0x3, - last_state: 0x2, + last_state: 0x3, }, ], trace_memories: {}, @@ -349,14 +349,9 @@ Simulation { }, ), ], + instant: 66 μs, clocks_triggered: [ StatePartIndex(1), ], - event_queue: EventQueue(EventQueueData { - instant: 66 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_sync.vcd b/crates/fayalite/tests/sim/expected/counter_sync.vcd index 9504a30..bf6249e 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.vcd +++ b/crates/fayalite/tests/sim/expected/counter_sync.vcd @@ -16,199 +16,199 @@ b0 $ $end #1000000 1! -b11 # b11 $ +b11 # 0" #2000000 0! #3000000 1! -b100 # b100 $ +b100 # #4000000 0! #5000000 1! -b101 # b101 $ +b101 # #6000000 0! #7000000 1! -b110 # b110 $ +b110 # #8000000 0! #9000000 1! -b111 # b111 $ +b111 # #10000000 0! #11000000 1! -b1000 # b1000 $ +b1000 # #12000000 0! #13000000 1! -b1001 # b1001 $ +b1001 # #14000000 0! #15000000 1! -b1010 # b1010 $ +b1010 # #16000000 0! #17000000 1! -b1011 # b1011 $ +b1011 # #18000000 0! #19000000 1! -b1100 # b1100 $ +b1100 # #20000000 0! #21000000 1! -b1101 # b1101 $ +b1101 # #22000000 0! #23000000 1! -b1110 # b1110 $ +b1110 # #24000000 0! #25000000 1! -b1111 # b1111 $ +b1111 # #26000000 0! #27000000 1! -b0 # b0 $ +b0 # #28000000 0! #29000000 1! -b1 # b1 $ +b1 # #30000000 0! #31000000 1! -b10 # b10 $ +b10 # #32000000 0! #33000000 1! -b11 # b11 $ +b11 # #34000000 0! #35000000 1! -b100 # b100 $ +b100 # #36000000 0! #37000000 1! -b101 # b101 $ +b101 # #38000000 0! #39000000 1! -b110 # b110 $ +b110 # #40000000 0! #41000000 1! -b111 # b111 $ +b111 # #42000000 0! #43000000 1! -b1000 # b1000 $ +b1000 # #44000000 0! #45000000 1! -b1001 # b1001 $ +b1001 # #46000000 0! #47000000 1! -b1010 # b1010 $ +b1010 # #48000000 0! #49000000 1! -b1011 # b1011 $ +b1011 # #50000000 0! #51000000 1! -b1100 # b1100 $ +b1100 # #52000000 0! #53000000 1! -b1101 # b1101 $ +b1101 # #54000000 0! #55000000 1! -b1110 # b1110 $ +b1110 # #56000000 0! #57000000 1! -b1111 # b1111 $ +b1111 # #58000000 0! #59000000 1! -b0 # b0 $ +b0 # #60000000 0! #61000000 1! -b1 # b1 $ +b1 # #62000000 0! #63000000 1! -b10 # b10 $ +b10 # #64000000 0! #65000000 1! -b11 # b11 $ +b11 # #66000000 diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt index 64bbbe6..4c54aa8 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.txt +++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt @@ -102,9 +102,9 @@ Simulation { uninitialized_ios: {}, io_targets: {}, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "duplicate_names", children: [ @@ -160,12 +160,7 @@ Simulation { }, ), ], + instant: 1 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 1 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index a193e92..4850a21 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1003,64 +1003,65 @@ Simulation { dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset }, }, - 97: IsNonZeroDestIsSmall { - dest: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock }, - }, - 98: AndSmall { - dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:1:1 - 99: Const { + 97: Const { dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, value: 0x0, }, - 100: Copy { + 98: Copy { dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:12:1 - 101: BranchIfZero { - target: 109, + 99: BranchIfZero { + target: 107, value: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:13:1 - 102: BranchIfZero { - target: 104, + 100: BranchIfZero { + target: 102, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:14:1 - 103: Copy { + 101: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:13:1 - 104: BranchIfNonZero { - target: 109, + 102: BranchIfNonZero { + target: 107, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:15:1 - 105: BranchIfZero { - target: 107, + 103: BranchIfZero { + target: 105, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:16:1 - 106: Copy { + 104: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:15:1 - 107: BranchIfNonZero { - target: 109, + 105: BranchIfNonZero { + target: 107, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:17:1 - 108: Copy { + 106: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, + // at: module-XXXXXXXXXX.rs:11:1 + 107: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock }, + }, + 108: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:10:1 109: Copy { dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, @@ -1453,9 +1454,9 @@ Simulation { }.which_out, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "enums", children: [ @@ -1743,7 +1744,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x0, + last_state: 0x1, }, SimTrace { id: TraceScalarId(1), @@ -1923,14 +1924,9 @@ Simulation { }, ), ], + instant: 16 μs, clocks_triggered: [ StatePartIndex(3), ], - event_queue: EventQueue(EventQueueData { - instant: 16 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt index f49106f..e09a767 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.txt +++ b/crates/fayalite/tests/sim/expected/extern_module.txt @@ -102,7 +102,6 @@ Simulation { }.o, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -137,7 +136,6 @@ Simulation { }, }, did_initial_settle: true, - clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -188,8 +186,14 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Instant( + 20.500000000000 μs, + ), + }, }, ], + state_ready_to_run: false, trace_decls: TraceModule { name: "extern_module", children: [ @@ -230,7 +234,7 @@ Simulation { index: StatePartIndex(1), }, state: 0x1, - last_state: 0x0, + last_state: 0x1, }, ], trace_memories: {}, @@ -243,21 +247,7 @@ Simulation { }, ), ], + instant: 20 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 20 μs, - events: { - Event { - instant: 20.500000000000 μs, - kind: ExternModule( - 0, - ), - }: Wakers( - 1, - ), - }, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module.vcd b/crates/fayalite/tests/sim/expected/extern_module.vcd index 5d6a0bc..e026a50 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.vcd +++ b/crates/fayalite/tests/sim/expected/extern_module.vcd @@ -6,9 +6,8 @@ $upscope $end $enddefinitions $end $dumpvars 0! -0" -$end 1" +$end #500000 #1500000 0" diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt index fa6e767..1023b2b 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.txt +++ b/crates/fayalite/tests/sim/expected/extern_module2.txt @@ -121,7 +121,6 @@ Simulation { }.o, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -168,7 +167,6 @@ Simulation { }, }, did_initial_settle: true, - clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -236,8 +234,55 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + }, + }, }, ], + state_ready_to_run: false, trace_decls: TraceModule { name: "extern_module2", children: [ @@ -311,113 +356,7 @@ Simulation { }, ), ], + instant: 60 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 60 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 59, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 59, - .. - }, - }, - ), - }, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module2.vcd b/crates/fayalite/tests/sim/expected/extern_module2.vcd index 4204567..464f4bd 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.vcd +++ b/crates/fayalite/tests/sim/expected/extern_module2.vcd @@ -8,9 +8,8 @@ $enddefinitions $end $dumpvars 1! 0" -b0 # -$end b1001000 # +$end #1000000 1" b1100101 # diff --git a/crates/fayalite/tests/sim/expected/many_memories.txt b/crates/fayalite/tests/sim/expected/many_memories.txt index c521d72..fbbc581 100644 --- a/crates/fayalite/tests/sim/expected/many_memories.txt +++ b/crates/fayalite/tests/sim/expected/many_memories.txt @@ -3834,9 +3834,9 @@ Simulation { }.w[7].mask, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "many_memories", children: [ @@ -7759,6 +7759,7 @@ Simulation { }, ), ], + instant: 38 μs, clocks_triggered: [ StatePartIndex(1), StatePartIndex(6), @@ -7777,11 +7778,5 @@ Simulation { StatePartIndex(85), StatePartIndex(90), ], - event_queue: EventQueue(EventQueueData { - instant: 38 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/many_memories.vcd b/crates/fayalite/tests/sim/expected/many_memories.vcd index 77d1447..cbaeb7b 100644 --- a/crates/fayalite/tests/sim/expected/many_memories.vcd +++ b/crates/fayalite/tests/sim/expected/many_memories.vcd @@ -1052,16 +1052,12 @@ $end 1U# 1e# 1# -1$ 1' 1+ -1, 1/ 13 -14 17 1; -1< 1? 1C 1H @@ -1072,25 +1068,29 @@ $end 1a 1f 1k -1l 1o 1t 1x 1} -1~ 1#" 1(" 1," 11" -12" 15" 1:" 1>" 1C" -1D" 1G" 1L" 1P" +1$ +1, +14 +1< +1l +1~ +12" +1D" #4000000 0# 0' @@ -1150,21 +1150,13 @@ $end 0U# 0e# 1# -0$ 1' -0( 1+ -0, 1/ -00 13 -04 17 -08 1; -0< 1? -0@ 1C 1H 1M @@ -1174,29 +1166,37 @@ $end 1a 1f 1k -0l 1o 1t -0u 1x 1} -0~ 1#" 1(" -0)" 1," 11" -02" 15" 1:" -0;" 1>" 1C" -0D" 1G" 1L" -0M" 1P" +0$ +0( +0, +00 +04 +08 +0< +0@ +0l +0u +0~ +0)" +02" +0;" +0D" +0M" #6000000 0# 0' diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt index 0358bb3..f7f88e3 100644 --- a/crates/fayalite/tests/sim/expected/memories.txt +++ b/crates/fayalite/tests/sim/expected/memories.txt @@ -719,9 +719,9 @@ Simulation { }.w.mask.1, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "memories", children: [ @@ -1616,15 +1616,10 @@ Simulation { }, ), ], + instant: 22 μs, clocks_triggered: [ StatePartIndex(1), StatePartIndex(6), ], - event_queue: EventQueue(EventQueueData { - instant: 22 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories.vcd b/crates/fayalite/tests/sim/expected/memories.vcd index d8f5817..bedc354 100644 --- a/crates/fayalite/tests/sim/expected/memories.vcd +++ b/crates/fayalite/tests/sim/expected/memories.vcd @@ -234,13 +234,13 @@ b100000 6 b10000 9 b100000 I 1# -b10000 $ -b100000 % 1( 1/ +14 +b10000 $ +b100000 % b10000 0 b100000 1 -14 #4000000 0# 0( @@ -256,11 +256,11 @@ b1000000 6 b10000 9 b1000000 I 1# -b1000000 % 1( 1/ -b1000000 1 14 +b1000000 % +b1000000 1 #6000000 0# 0( @@ -278,11 +278,11 @@ b1100000 6 b1010000 9 b1000000 I 1# -b1010000 $ 1( 1/ -b1010000 0 14 +b1010000 $ +b1010000 0 #8000000 0# 0( diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt index b4041ba..c216104 100644 --- a/crates/fayalite/tests/sim/expected/memories2.txt +++ b/crates/fayalite/tests/sim/expected/memories2.txt @@ -677,9 +677,9 @@ Simulation { }.rw.wmode, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "memories2", children: [ @@ -1260,14 +1260,9 @@ Simulation { }, ), ], + instant: 22 μs, clocks_triggered: [ StatePartIndex(3), ], - event_queue: EventQueue(EventQueueData { - instant: 22 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories2.vcd b/crates/fayalite/tests/sim/expected/memories2.vcd index 0ac20f1..4039754 100644 --- a/crates/fayalite/tests/sim/expected/memories2.vcd +++ b/crates/fayalite/tests/sim/expected/memories2.vcd @@ -100,8 +100,8 @@ $end 1) #1250000 1# -b11 $ 1* +b11 $ sHdlSome\x20(1) + 1, #1500000 @@ -113,8 +113,8 @@ sHdlSome\x20(1) + 0) #2250000 1# -b0 $ 1* +b0 $ sHdlNone\x20(0) + 0, #2500000 @@ -303,8 +303,8 @@ b11 ! b11 ( #17250000 1# -b11 $ 1* +b11 $ sHdlSome\x20(1) + 1, #17500000 @@ -316,8 +316,8 @@ b10 ! b10 ( #18250000 1# -b0 $ 1* +b0 $ sHdlNone\x20(0) + 0, #18500000 @@ -339,8 +339,8 @@ b1 ! b1 ( #20250000 1# -b1 $ 1* +b1 $ sHdlSome\x20(1) + #20500000 #20750000 @@ -353,8 +353,8 @@ b0 ( 0) #21250000 1# -b0 $ 1* +b0 $ sHdlNone\x20(0) + #21500000 #21750000 diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt index 2213912..8114c7e 100644 --- a/crates/fayalite/tests/sim/expected/memories3.txt +++ b/crates/fayalite/tests/sim/expected/memories3.txt @@ -1761,9 +1761,9 @@ Simulation { }.w.mask[7], }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "memories3", children: [ @@ -3275,15 +3275,10 @@ Simulation { }, ), ], + instant: 15 μs, clocks_triggered: [ StatePartIndex(1), StatePartIndex(6), ], - event_queue: EventQueue(EventQueueData { - instant: 15 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories3.vcd b/crates/fayalite/tests/sim/expected/memories3.vcd index 32ee75e..5768560 100644 --- a/crates/fayalite/tests/sim/expected/memories3.vcd +++ b/crates/fayalite/tests/sim/expected/memories3.vcd @@ -420,10 +420,6 @@ b10000 T 1\ #3250000 1# -b110100 % -b1111000 ' -b10011010 ( -b11110000 + 1. 1A b110100 C @@ -431,6 +427,10 @@ b1111000 E b10011010 F b11110000 I 1L +b110100 % +b1111000 ' +b10011010 ( +b11110000 + #3500000 #3750000 0# @@ -508,14 +508,6 @@ b1010100 '" b110010 /" b10000 7" 1# -b11111110 $ -b11011100 % -b10111010 & -b10011000 ' -b1110110 ( -b1010100 ) -b110010 * -b10000 + 1. 1A b11111110 B @@ -527,6 +519,14 @@ b1010100 G b110010 H b10000 I 1L +b11111110 $ +b11011100 % +b10111010 & +b10011000 ' +b1110110 ( +b1010100 ) +b110010 * +b10000 + #6500000 #6750000 0# @@ -562,14 +562,6 @@ b1000110 (" b10001010 0" b11001110 8" 1# -b0 $ -b0 % -b0 & -b0 ' -b0 ( -b0 ) -b0 * -b0 + 1. 1A b0 B @@ -581,6 +573,14 @@ b0 G b0 H b0 I 1L +b0 $ +b0 % +b0 & +b0 ' +b0 ( +b0 ) +b0 * +b0 + #7500000 #7750000 0# @@ -688,14 +688,6 @@ b1 ! b1 ? #10250000 1# -b11111110 $ -b11011100 % -b10111010 & -b10011000 ' -b1110110 ( -b1010100 ) -b110010 * -b10000 + 1. 1A b11111110 B @@ -707,6 +699,14 @@ b1010100 G b110010 H b10000 I 1L +b11111110 $ +b11011100 % +b10111010 & +b10011000 ' +b1110110 ( +b1010100 ) +b110010 * +b10000 + #10500000 #10750000 0# @@ -718,14 +718,6 @@ b10 ! b10 ? #11250000 1# -b10011 $ -b1010111 % -b10011011 & -b11011111 ' -b10 ( -b1000110 ) -b10001010 * -b11001110 + 1. 1A b10011 B @@ -737,6 +729,14 @@ b1000110 G b10001010 H b11001110 I 1L +b10011 $ +b1010111 % +b10011011 & +b11011111 ' +b10 ( +b1000110 ) +b10001010 * +b11001110 + #11500000 #11750000 0# @@ -748,14 +748,6 @@ b11 ! b11 ? #12250000 1# -b1110100 $ -b1100101 % -b1110011 & -b1110100 ' -b1101001 ( -b1101110 ) -b1100111 * -b100001 + 1. 1A b1110100 B @@ -767,6 +759,14 @@ b1101110 G b1100111 H b100001 I 1L +b1110100 $ +b1100101 % +b1110011 & +b1110100 ' +b1101001 ( +b1101110 ) +b1100111 * +b100001 + #12500000 #12750000 0# @@ -780,14 +780,6 @@ b0 ? 0@ #13250000 1# -b1101101 $ -b1101111 % -b1110010 & -b1100101 ' -b100000 ( -b1110100 ) -b1110011 * -b1110100 + 1. 1A b1101101 B @@ -799,6 +791,14 @@ b1110100 G b1110011 H b1110100 I 1L +b1101101 $ +b1101111 % +b1110010 & +b1100101 ' +b100000 ( +b1110100 ) +b1110011 * +b1110100 + #13500000 #13750000 0# @@ -808,14 +808,6 @@ b1110100 I #14000000 #14250000 1# -b0 $ -b0 % -b0 & -b0 ' -b0 ( -b0 ) -b0 * -b0 + 1. 1A b0 B @@ -827,6 +819,14 @@ b0 G b0 H b0 I 1L +b0 $ +b0 % +b0 & +b0 ' +b0 ( +b0 ) +b0 * +b0 + #14500000 #14750000 0# diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt index 3f7a55e..4ef02b2 100644 --- a/crates/fayalite/tests/sim/expected/mod1.txt +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -274,9 +274,9 @@ Simulation { }.o.o2, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "mod1", children: [ @@ -558,12 +558,7 @@ Simulation { }, ), ], + instant: 2 μs, clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 2 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/phantom_const.txt b/crates/fayalite/tests/sim/expected/phantom_const.txt deleted file mode 100644 index 8c2237d..0000000 --- a/crates/fayalite/tests/sim/expected/phantom_const.txt +++ /dev/null @@ -1,515 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 5, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: UInt<0>, - }, - ], - .. - }, - big_slots: StatePartLayout { - len: 7, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.addr", - ty: UInt<0>, - }, - SlotDebugData { - name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.clk", - ty: Clock, - }, - SlotDebugData { - name: "", - ty: UInt<8>, - }, - SlotDebugData { - name: "", - ty: UInt<0>, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 1, - debug_data: [ - (), - ], - layout_data: [ - MemoryData { - array_type: Array, - data: [ - // len = 0x1 - [0x0]: 0x0, - ], - }, - ], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - 0: Const { - dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "", ty: Bool }, - value: 0x0, - }, - 1: Copy { - dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Clock }, - src: StatePartIndex(5), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:6:1 - 2: Copy { - dest: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.clk", ty: Clock }, - src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:7:1 - 3: Copy { - dest: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.en", ty: Bool }, - src: StatePartIndex(5), // (0x0) SlotDebugData { name: "", ty: Bool }, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 4: Const { - dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - value: 0x0, - }, - 5: CastToUInt { - dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(3), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, - dest_width: 0, - }, - // at: module-XXXXXXXXXX.rs:5:1 - 6: Copy { - dest: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.addr", ty: UInt<0> }, - src: StatePartIndex(4), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, - }, - // at: module-XXXXXXXXXX.rs:3:1 - 7: CastBigToArrayIndex { - dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, - src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.addr", ty: UInt<0> }, - }, - 8: IsNonZeroDestIsSmall { - dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.en", ty: Bool }, - }, - 9: BranchIfSmallZero { - target: 11, - value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 10: Branch { - target: 11, - }, - 11: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.clk", ty: Clock }, - }, - 12: AndSmall { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 13: BranchIfSmallZero { - target: 14, - value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 14: XorSmallImmediate { - dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 15: Return, - ], - .. - }, - pc: 15, - memory_write_log: [], - memories: StatePart { - value: [ - MemoryData { - array_type: Array, - data: [ - // len = 0x1 - [0x0]: 0x0, - ], - }, - ], - }, - small_slots: StatePart { - value: [ - 1, - 0, - 0, - 0, - 0, - ], - }, - big_slots: StatePart { - value: [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::phantom_const, - instantiated: Module { - name: phantom_const, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::phantom_const, - instantiated: Module { - name: phantom_const, - .. - }, - }.out, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::phantom_const, - instantiated: Module { - name: phantom_const, - .. - }, - }.out, - Instance { - name: ::phantom_const, - instantiated: Module { - name: phantom_const, - .. - }, - }.out[0], - Instance { - name: ::phantom_const, - instantiated: Module { - name: phantom_const, - .. - }, - }.out[1], - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - extern_modules: [], - trace_decls: TraceModule { - name: "phantom_const", - children: [ - TraceModuleIO { - name: "out", - child: TraceArray { - name: "out", - elements: [ - TracePhantomConst { - location: TraceScalarId(0), - name: "[0]", - ty: PhantomConst( - ["a","b"], - ), - flow: Sink, - }, - TracePhantomConst { - location: TraceScalarId(1), - name: "[1]", - ty: PhantomConst( - ["a","b"], - ), - flow: Sink, - }, - ], - ty: Array, - flow: Sink, - }, - ty: Array, - flow: Sink, - }, - TraceMem { - id: TraceMemoryId(0), - name: "mem", - stride: 0, - element_type: TracePhantomConst { - location: TraceMemoryLocation { - id: TraceMemoryId(0), - depth: 1, - stride: 0, - start: 0, - len: 0, - }, - name: "mem", - ty: PhantomConst( - "mem_element", - ), - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(2), - name: "addr", - ty: UInt<0>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(3), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(4), - name: "clk", - flow: Sink, - }, - TracePhantomConst { - location: TraceScalarId(5), - name: "data", - ty: PhantomConst( - "mem_element", - ), - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<0>, - /* offset = 0 */ - en: Bool, - /* offset = 1 */ - clk: Clock, - #[hdl(flip)] /* offset = 2 */ - data: PhantomConst( - "mem_element", - ), - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<0>, - /* offset = 0 */ - en: Bool, - /* offset = 1 */ - clk: Clock, - #[hdl(flip)] /* offset = 2 */ - data: PhantomConst( - "mem_element", - ), - }, - }, - ], - array_type: Array, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: PhantomConst { - ty: PhantomConst( - ["a","b"], - ), - }, - state: PhantomConst, - last_state: PhantomConst, - }, - SimTrace { - id: TraceScalarId(1), - kind: PhantomConst { - ty: PhantomConst( - ["a","b"], - ), - }, - state: PhantomConst, - last_state: PhantomConst, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigUInt { - index: StatePartIndex(0), - ty: UInt<0>, - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigBool { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(4), - kind: BigClock { - index: StatePartIndex(2), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(5), - kind: PhantomConst { - ty: PhantomConst( - "mem_element", - ), - }, - state: PhantomConst, - last_state: PhantomConst, - }, - ], - trace_memories: { - StatePartIndex(0): TraceMem { - id: TraceMemoryId(0), - name: "mem", - stride: 0, - element_type: TracePhantomConst { - location: TraceMemoryLocation { - id: TraceMemoryId(0), - depth: 1, - stride: 0, - start: 0, - len: 0, - }, - name: "mem", - ty: PhantomConst( - "mem_element", - ), - flow: Duplex, - }, - ports: [ - TraceMemPort { - name: "r0", - bundle: TraceBundle { - name: "r0", - fields: [ - TraceUInt { - location: TraceScalarId(2), - name: "addr", - ty: UInt<0>, - flow: Sink, - }, - TraceBool { - location: TraceScalarId(3), - name: "en", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(4), - name: "clk", - flow: Sink, - }, - TracePhantomConst { - location: TraceScalarId(5), - name: "data", - ty: PhantomConst( - "mem_element", - ), - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - addr: UInt<0>, - /* offset = 0 */ - en: Bool, - /* offset = 1 */ - clk: Clock, - #[hdl(flip)] /* offset = 2 */ - data: PhantomConst( - "mem_element", - ), - }, - flow: Sink, - }, - ty: Bundle { - /* offset = 0 */ - addr: UInt<0>, - /* offset = 0 */ - en: Bool, - /* offset = 1 */ - clk: Clock, - #[hdl(flip)] /* offset = 2 */ - data: PhantomConst( - "mem_element", - ), - }, - }, - ], - array_type: Array, - }, - }, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [ - StatePartIndex(1), - ], - event_queue: EventQueue(EventQueueData { - instant: 1 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/phantom_const.vcd b/crates/fayalite/tests/sim/expected/phantom_const.vcd deleted file mode 100644 index ba3869b..0000000 --- a/crates/fayalite/tests/sim/expected/phantom_const.vcd +++ /dev/null @@ -1,31 +0,0 @@ -$timescale 1 ps $end -$scope module phantom_const $end -$scope struct out $end -$var string 1 ! \[0] $end -$var string 1 " \[1] $end -$upscope $end -$scope struct mem $end -$scope struct contents $end -$scope struct \[0] $end -$var string 1 ' mem $end -$upscope $end -$upscope $end -$scope struct r0 $end -$var string 0 # addr $end -$var wire 1 $ en $end -$var wire 1 % clk $end -$var string 1 & data $end -$upscope $end -$upscope $end -$upscope $end -$enddefinitions $end -$dumpvars -s0 ' -sPhantomConst([\"a\",\"b\"]) ! -sPhantomConst([\"a\",\"b\"]) " -s0 # -0$ -0% -sPhantomConst(\"mem_element\") & -$end -#1000000 diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt index 9e46be4..9e4e0d1 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.txt +++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt @@ -743,7 +743,6 @@ Simulation { }.o, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -778,7 +777,6 @@ Simulation { }, }, did_initial_settle: true, - clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -829,6 +827,52 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 3, len: 0 }, + big_slots: StatePartIndexRange { start: 33, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + }, }, SimulationExternModuleState { module_state: SimulationModuleState { @@ -862,7 +906,6 @@ Simulation { }, }, did_initial_settle: true, - clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -913,6 +956,52 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 6, len: 0 }, + big_slots: StatePartIndexRange { start: 44, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + }, }, SimulationExternModuleState { module_state: SimulationModuleState { @@ -946,7 +1035,6 @@ Simulation { }, }, did_initial_settle: true, - clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -997,8 +1085,55 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 55, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + }, }, ], + state_ready_to_run: false, trace_decls: TraceModule { name: "ripple_counter", children: [ @@ -1458,315 +1593,11 @@ Simulation { }, ), ], + instant: 256 μs, clocks_triggered: [ StatePartIndex(1), StatePartIndex(4), StatePartIndex(7), ], - event_queue: EventQueue(EventQueueData { - instant: 256 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 152, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 55, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - SensitivitySet { - id: 167, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 6, len: 0 }, - big_slots: StatePartIndexRange { start: 44, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - SensitivitySet { - id: 170, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 3, len: 0 }, - big_slots: StatePartIndexRange { start: 33, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 3, len: 0 }, - big_slots: StatePartIndexRange { start: 33, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 170, - .. - }, - }, - ), - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 6, len: 0 }, - big_slots: StatePartIndexRange { start: 44, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 167, - .. - }, - }, - ), - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 55, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 152, - .. - }, - }, - ), - }, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.vcd b/crates/fayalite/tests/sim/expected/ripple_counter.vcd index 550205f..6f14a8e 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.vcd +++ b/crates/fayalite/tests/sim/expected/ripple_counter.vcd @@ -66,1648 +66,1688 @@ b0 " $end #1000000 1! +1) b1 " 1# -1) 1* 1, -b111 " -1$ -1% 1+ +b11 " +1$ 1- 1. +b111 " +1% 1/ 11 -b11111 " -1& -1' 10 +b1111 " +1& 12 13 +b11111 " +1' 14 16 +15 b111111 " 1( -15 17 #2000000 0! #3000000 1! +0) b111110 " 0# -0) 0* 0, #4000000 0! #5000000 1! +1) b111111 " 1# -1) 1* 1, +0+ b111101 " 0$ -0+ 0- #6000000 0! #7000000 1! +0) b111100 " 0# -0) 0* 0, #8000000 0! #9000000 1! +1) b111101 " 1# -1) 1* 1, -b111011 " -1$ -0% 1+ +b111111 " +1$ 1- 0. +b111011 " +0% 0/ 01 #10000000 0! #11000000 1! +0) b111010 " 0# -0) 0* 0, #12000000 0! #13000000 1! +1) b111011 " 1# -1) 1* 1, +0+ b111001 " 0$ -0+ 0- #14000000 0! #15000000 1! +0) b111000 " 0# -0) 0* 0, #16000000 0! #17000000 1! +1) b111001 " 1# -1) 1* 1, -b111111 " -1$ -1% 1+ +b111011 " +1$ 1- 1. +b111111 " +1% 1/ 11 +00 b110111 " 0& -00 02 #18000000 0! #19000000 1! +0) b110110 " 0# -0) 0* 0, #20000000 0! #21000000 1! +1) b110111 " 1# -1) 1* 1, +0+ b110101 " 0$ -0+ 0- #22000000 0! #23000000 1! +0) b110100 " 0# -0) 0* 0, #24000000 0! #25000000 1! +1) b110101 " 1# -1) 1* 1, -b110011 " -1$ -0% 1+ +b110111 " +1$ 1- 0. +b110011 " +0% 0/ 01 #26000000 0! #27000000 1! +0) b110010 " 0# -0) 0* 0, #28000000 0! #29000000 1! +1) b110011 " 1# -1) 1* 1, +0+ b110001 " 0$ -0+ 0- #30000000 0! #31000000 1! +0) b110000 " 0# -0) 0* 0, #32000000 0! #33000000 1! +1) b110001 " 1# -1) 1* 1, -b110111 " -1$ -1% 1+ +b110011 " +1$ 1- 1. +b110111 " +1% 1/ 11 -b101111 " -1& -0' 10 +b111111 " +1& 12 03 +b101111 " +0' 04 06 #34000000 0! #35000000 1! +0) b101110 " 0# -0) 0* 0, #36000000 0! #37000000 1! +1) b101111 " 1# -1) 1* 1, +0+ b101101 " 0$ -0+ 0- #38000000 0! #39000000 1! +0) b101100 " 0# -0) 0* 0, #40000000 0! #41000000 1! +1) b101101 " 1# -1) 1* 1, -b101011 " -1$ -0% 1+ +b101111 " +1$ 1- 0. +b101011 " +0% 0/ 01 #42000000 0! #43000000 1! +0) b101010 " 0# -0) 0* 0, #44000000 0! #45000000 1! +1) b101011 " 1# -1) 1* 1, +0+ b101001 " 0$ -0+ 0- #46000000 0! #47000000 1! +0) b101000 " 0# -0) 0* 0, #48000000 0! #49000000 1! +1) b101001 " 1# -1) 1* 1, -b101111 " -1$ -1% 1+ +b101011 " +1$ 1- 1. +b101111 " +1% 1/ 11 +00 b100111 " 0& -00 02 #50000000 0! #51000000 1! +0) b100110 " 0# -0) 0* 0, #52000000 0! #53000000 1! +1) b100111 " 1# -1) 1* 1, +0+ b100101 " 0$ -0+ 0- #54000000 0! #55000000 1! +0) b100100 " 0# -0) 0* 0, #56000000 0! #57000000 1! +1) b100101 " 1# -1) 1* 1, -b100011 " -1$ -0% 1+ +b100111 " +1$ 1- 0. +b100011 " +0% 0/ 01 #58000000 0! #59000000 1! +0) b100010 " 0# -0) 0* 0, #60000000 0! #61000000 1! +1) b100011 " 1# -1) 1* 1, +0+ b100001 " 0$ -0+ 0- #62000000 0! #63000000 1! +0) b100000 " 0# -0) 0* 0, #64000000 0! #65000000 1! +1) b100001 " 1# -1) 1* 1, -b100111 " -1$ -1% 1+ +b100011 " +1$ 1- 1. +b100111 " +1% 1/ 11 -b111111 " -1& -1' 10 +b101111 " +1& 12 13 +b111111 " +1' 14 16 +05 b11111 " 0( -05 07 #66000000 0! #67000000 1! +0) b11110 " 0# -0) 0* 0, #68000000 0! #69000000 1! +1) b11111 " 1# -1) 1* 1, +0+ b11101 " 0$ -0+ 0- #70000000 0! #71000000 1! +0) b11100 " 0# -0) 0* 0, #72000000 0! #73000000 1! +1) b11101 " 1# -1) 1* 1, -b11011 " -1$ -0% 1+ +b11111 " +1$ 1- 0. +b11011 " +0% 0/ 01 #74000000 0! #75000000 1! +0) b11010 " 0# -0) 0* 0, #76000000 0! #77000000 1! +1) b11011 " 1# -1) 1* 1, +0+ b11001 " 0$ -0+ 0- #78000000 0! #79000000 1! +0) b11000 " 0# -0) 0* 0, #80000000 0! #81000000 1! +1) b11001 " 1# -1) 1* 1, -b11111 " -1$ -1% 1+ +b11011 " +1$ 1- 1. +b11111 " +1% 1/ 11 +00 b10111 " 0& -00 02 #82000000 0! #83000000 1! +0) b10110 " 0# -0) 0* 0, #84000000 0! #85000000 1! +1) b10111 " 1# -1) 1* 1, +0+ b10101 " 0$ -0+ 0- #86000000 0! #87000000 1! +0) b10100 " 0# -0) 0* 0, #88000000 0! #89000000 1! +1) b10101 " 1# -1) 1* 1, -b10011 " -1$ -0% 1+ +b10111 " +1$ 1- 0. +b10011 " +0% 0/ 01 #90000000 0! #91000000 1! +0) b10010 " 0# -0) 0* 0, #92000000 0! #93000000 1! +1) b10011 " 1# -1) 1* 1, +0+ b10001 " 0$ -0+ 0- #94000000 0! #95000000 1! +0) b10000 " 0# -0) 0* 0, #96000000 0! #97000000 1! +1) b10001 " 1# -1) 1* 1, -b10111 " -1$ -1% 1+ +b10011 " +1$ 1- 1. +b10111 " +1% 1/ 11 -b1111 " -1& -0' 10 +b11111 " +1& 12 03 +b1111 " +0' 04 06 #98000000 0! #99000000 1! +0) b1110 " 0# -0) 0* 0, #100000000 0! #101000000 1! +1) b1111 " 1# -1) 1* 1, +0+ b1101 " 0$ -0+ 0- #102000000 0! #103000000 1! +0) b1100 " 0# -0) 0* 0, #104000000 0! #105000000 1! +1) b1101 " 1# -1) 1* 1, -b1011 " -1$ -0% 1+ +b1111 " +1$ 1- 0. +b1011 " +0% 0/ 01 #106000000 0! #107000000 1! +0) b1010 " 0# -0) 0* 0, #108000000 0! #109000000 1! +1) b1011 " 1# -1) 1* 1, +0+ b1001 " 0$ -0+ 0- #110000000 0! #111000000 1! +0) b1000 " 0# -0) 0* 0, #112000000 0! #113000000 1! +1) b1001 " 1# -1) 1* 1, -b1111 " -1$ -1% 1+ +b1011 " +1$ 1- 1. +b1111 " +1% 1/ 11 +00 b111 " 0& -00 02 #114000000 0! #115000000 1! +0) b110 " 0# -0) 0* 0, #116000000 0! #117000000 1! +1) b111 " 1# -1) 1* 1, +0+ b101 " 0$ -0+ 0- #118000000 0! #119000000 1! +0) b100 " 0# -0) 0* 0, #120000000 0! #121000000 1! +1) b101 " 1# -1) 1* 1, -b11 " -1$ -0% 1+ +b111 " +1$ 1- 0. +b11 " +0% 0/ 01 #122000000 0! #123000000 1! +0) b10 " 0# -0) 0* 0, #124000000 0! #125000000 1! +1) b11 " 1# -1) 1* 1, +0+ b1 " 0$ -0+ 0- #126000000 0! #127000000 1! +0) b0 " 0# -0) 0* 0, #128000000 0! #129000000 1! +1) b1 " 1# -1) 1* 1, -b111 " -1$ -1% 1+ +b11 " +1$ 1- 1. +b111 " +1% 1/ 11 -b11111 " -1& -1' 10 +b1111 " +1& 12 13 +b11111 " +1' 14 16 +15 b111111 " 1( -15 17 #130000000 0! #131000000 1! +0) b111110 " 0# -0) 0* 0, #132000000 0! #133000000 1! +1) b111111 " 1# -1) 1* 1, +0+ b111101 " 0$ -0+ 0- #134000000 0! #135000000 1! +0) b111100 " 0# -0) 0* 0, #136000000 0! #137000000 1! +1) b111101 " 1# -1) 1* 1, -b111011 " -1$ -0% 1+ +b111111 " +1$ 1- 0. +b111011 " +0% 0/ 01 #138000000 0! #139000000 1! +0) b111010 " 0# -0) 0* 0, #140000000 0! #141000000 1! +1) b111011 " 1# -1) 1* 1, +0+ b111001 " 0$ -0+ 0- #142000000 0! #143000000 1! +0) b111000 " 0# -0) 0* 0, #144000000 0! #145000000 1! +1) b111001 " 1# -1) 1* 1, -b111111 " -1$ -1% 1+ +b111011 " +1$ 1- 1. +b111111 " +1% 1/ 11 +00 b110111 " 0& -00 02 #146000000 0! #147000000 1! +0) b110110 " 0# -0) 0* 0, #148000000 0! #149000000 1! +1) b110111 " 1# -1) 1* 1, +0+ b110101 " 0$ -0+ 0- #150000000 0! #151000000 1! +0) b110100 " 0# -0) 0* 0, #152000000 0! #153000000 1! +1) b110101 " 1# -1) 1* 1, -b110011 " -1$ -0% 1+ +b110111 " +1$ 1- 0. +b110011 " +0% 0/ 01 #154000000 0! #155000000 1! +0) b110010 " 0# -0) 0* 0, #156000000 0! #157000000 1! +1) b110011 " 1# -1) 1* 1, +0+ b110001 " 0$ -0+ 0- #158000000 0! #159000000 1! +0) b110000 " 0# -0) 0* 0, #160000000 0! #161000000 1! +1) b110001 " 1# -1) 1* 1, -b110111 " -1$ -1% 1+ +b110011 " +1$ 1- 1. +b110111 " +1% 1/ 11 -b101111 " -1& -0' 10 +b111111 " +1& 12 03 +b101111 " +0' 04 06 #162000000 0! #163000000 1! +0) b101110 " 0# -0) 0* 0, #164000000 0! #165000000 1! +1) b101111 " 1# -1) 1* 1, +0+ b101101 " 0$ -0+ 0- #166000000 0! #167000000 1! +0) b101100 " 0# -0) 0* 0, #168000000 0! #169000000 1! +1) b101101 " 1# -1) 1* 1, -b101011 " -1$ -0% 1+ +b101111 " +1$ 1- 0. +b101011 " +0% 0/ 01 #170000000 0! #171000000 1! +0) b101010 " 0# -0) 0* 0, #172000000 0! #173000000 1! +1) b101011 " 1# -1) 1* 1, +0+ b101001 " 0$ -0+ 0- #174000000 0! #175000000 1! +0) b101000 " 0# -0) 0* 0, #176000000 0! #177000000 1! +1) b101001 " 1# -1) 1* 1, -b101111 " -1$ -1% 1+ +b101011 " +1$ 1- 1. +b101111 " +1% 1/ 11 +00 b100111 " 0& -00 02 #178000000 0! #179000000 1! +0) b100110 " 0# -0) 0* 0, #180000000 0! #181000000 1! +1) b100111 " 1# -1) 1* 1, +0+ b100101 " 0$ -0+ 0- #182000000 0! #183000000 1! +0) b100100 " 0# -0) 0* 0, #184000000 0! #185000000 1! +1) b100101 " 1# -1) 1* 1, -b100011 " -1$ -0% 1+ +b100111 " +1$ 1- 0. +b100011 " +0% 0/ 01 #186000000 0! #187000000 1! +0) b100010 " 0# -0) 0* 0, #188000000 0! #189000000 1! +1) b100011 " 1# -1) 1* 1, +0+ b100001 " 0$ -0+ 0- #190000000 0! #191000000 1! +0) b100000 " 0# -0) 0* 0, #192000000 0! #193000000 1! +1) b100001 " 1# -1) 1* 1, -b100111 " -1$ -1% 1+ +b100011 " +1$ 1- 1. +b100111 " +1% 1/ 11 -b111111 " -1& -1' 10 +b101111 " +1& 12 13 +b111111 " +1' 14 16 +05 b11111 " 0( -05 07 #194000000 0! #195000000 1! +0) b11110 " 0# -0) 0* 0, #196000000 0! #197000000 1! +1) b11111 " 1# -1) 1* 1, +0+ b11101 " 0$ -0+ 0- #198000000 0! #199000000 1! +0) b11100 " 0# -0) 0* 0, #200000000 0! #201000000 1! +1) b11101 " 1# -1) 1* 1, -b11011 " -1$ -0% 1+ +b11111 " +1$ 1- 0. +b11011 " +0% 0/ 01 #202000000 0! #203000000 1! +0) b11010 " 0# -0) 0* 0, #204000000 0! #205000000 1! +1) b11011 " 1# -1) 1* 1, +0+ b11001 " 0$ -0+ 0- #206000000 0! #207000000 1! +0) b11000 " 0# -0) 0* 0, #208000000 0! #209000000 1! +1) b11001 " 1# -1) 1* 1, -b11111 " -1$ -1% 1+ +b11011 " +1$ 1- 1. +b11111 " +1% 1/ 11 +00 b10111 " 0& -00 02 #210000000 0! #211000000 1! +0) b10110 " 0# -0) 0* 0, #212000000 0! #213000000 1! +1) b10111 " 1# -1) 1* 1, +0+ b10101 " 0$ -0+ 0- #214000000 0! #215000000 1! +0) b10100 " 0# -0) 0* 0, #216000000 0! #217000000 1! +1) b10101 " 1# -1) 1* 1, -b10011 " -1$ -0% 1+ +b10111 " +1$ 1- 0. +b10011 " +0% 0/ 01 #218000000 0! #219000000 1! +0) b10010 " 0# -0) 0* 0, #220000000 0! #221000000 1! +1) b10011 " 1# -1) 1* 1, +0+ b10001 " 0$ -0+ 0- #222000000 0! #223000000 1! +0) b10000 " 0# -0) 0* 0, #224000000 0! #225000000 1! +1) b10001 " 1# -1) 1* 1, -b10111 " -1$ -1% 1+ +b10011 " +1$ 1- 1. +b10111 " +1% 1/ 11 -b1111 " -1& -0' 10 +b11111 " +1& 12 03 +b1111 " +0' 04 06 #226000000 0! #227000000 1! +0) b1110 " 0# -0) 0* 0, #228000000 0! #229000000 1! +1) b1111 " 1# -1) 1* 1, +0+ b1101 " 0$ -0+ 0- #230000000 0! #231000000 1! +0) b1100 " 0# -0) 0* 0, #232000000 0! #233000000 1! +1) b1101 " 1# -1) 1* 1, -b1011 " -1$ -0% 1+ +b1111 " +1$ 1- 0. +b1011 " +0% 0/ 01 #234000000 0! #235000000 1! +0) b1010 " 0# -0) 0* 0, #236000000 0! #237000000 1! +1) b1011 " 1# -1) 1* 1, +0+ b1001 " 0$ -0+ 0- #238000000 0! #239000000 1! +0) b1000 " 0# -0) 0* 0, #240000000 0! #241000000 1! +1) b1001 " 1# -1) 1* 1, -b1111 " -1$ -1% 1+ +b1011 " +1$ 1- 1. +b1111 " +1% 1/ 11 +00 b111 " 0& -00 02 #242000000 0! #243000000 1! +0) b110 " 0# -0) 0* 0, #244000000 0! #245000000 1! +1) b111 " 1# -1) 1* 1, +0+ b101 " 0$ -0+ 0- #246000000 0! #247000000 1! +0) b100 " 0# -0) 0* 0, #248000000 0! #249000000 1! +1) b101 " 1# -1) 1* 1, -b11 " -1$ -0% 1+ +b111 " +1$ 1- 0. +b11 " +0% 0/ 01 #250000000 0! #251000000 1! +0) b10 " 0# -0) 0* 0, #252000000 0! #253000000 1! +1) b11 " 1# -1) 1* 1, +0+ b1 " 0$ -0+ 0- #254000000 0! #255000000 1! +0) b0 " 0# -0) 0* 0, #256000000 diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt index 7dcf26c..9bab424 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -128,21 +128,21 @@ Simulation { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset }, }, - 6: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, - }, - 7: AndSmall { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:1:1 - 8: Const { + 6: Const { dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, value: 0x0, }, // at: module-XXXXXXXXXX.rs:5:1 + 7: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, + }, + 8: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, 9: BranchIfSmallZero { target: 14, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, @@ -337,9 +337,9 @@ Simulation { }.q, }, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [], + state_ready_to_run: false, trace_decls: TraceModule { name: "shift_register", children: [ @@ -440,7 +440,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x0, + last_state: 0x1, }, SimTrace { id: TraceScalarId(1), @@ -509,14 +509,9 @@ Simulation { }, ), ], + instant: 66 μs, clocks_triggered: [ StatePartIndex(1), ], - event_queue: EventQueue(EventQueueData { - instant: 66 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: {}, - waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/shift_register.vcd b/crates/fayalite/tests/sim/expected/shift_register.vcd index 26726eb..0b5f429 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.vcd +++ b/crates/fayalite/tests/sim/expected/shift_register.vcd @@ -52,9 +52,9 @@ $end 0! #11000000 1! -1$ 0& 1( +1$ #12000000 0! 1# @@ -67,10 +67,10 @@ $end 0# #15000000 1! -0$ 0% 1& 0( +0$ #16000000 0! 1# @@ -83,23 +83,23 @@ $end 0! #19000000 1! -1$ 1& 0' 1( +1$ #20000000 0! #21000000 1! -0$ 1' 0( +0$ #22000000 0! #23000000 1! -1$ 1( +1$ #24000000 0! 0# @@ -120,8 +120,8 @@ $end 0! #31000000 1! -0$ 0( +0$ #32000000 0! #33000000 diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.txt b/crates/fayalite/tests/sim/expected/sim_fork_join.txt deleted file mode 100644 index 680fedb..0000000 --- a/crates/fayalite/tests/sim/expected/sim_fork_join.txt +++ /dev/null @@ -1,525 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 6, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[2]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[2]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - 0: Return, - ], - .. - }, - pc: 0, - memory_write_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 0, - 0, - 0, - 49, - 50, - 50, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.clocks, - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.outputs, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.clocks, - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.clocks[0], - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.clocks[1], - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.clocks[2], - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.outputs, - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.outputs[0], - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.outputs[1], - Instance { - name: ::sim_fork_join, - instantiated: Module { - name: sim_fork_join, - .. - }, - }.outputs[2], - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - extern_modules: [ - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }[0], - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }[1], - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }[2], - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }[0], - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }[1], - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }[2], - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ), - f: ..., - }, - sim_io_to_generator_map: { - ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }: ModuleIO { - name: sim_fork_join::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }: ModuleIO { - name: sim_fork_join::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - }, - source_location: SourceLocation( - module-XXXXXXXXXX.rs:4:1, - ), - }, - running_generator: Some( - ..., - ), - }, - ], - trace_decls: TraceModule { - name: "sim_fork_join", - children: [ - TraceModuleIO { - name: "clocks", - child: TraceArray { - name: "clocks", - elements: [ - TraceClock { - location: TraceScalarId(0), - name: "[0]", - flow: Source, - }, - TraceClock { - location: TraceScalarId(1), - name: "[1]", - flow: Source, - }, - TraceClock { - location: TraceScalarId(2), - name: "[2]", - flow: Source, - }, - ], - ty: Array, - flow: Source, - }, - ty: Array, - flow: Source, - }, - TraceModuleIO { - name: "outputs", - child: TraceArray { - name: "outputs", - elements: [ - TraceUInt { - location: TraceScalarId(3), - name: "[0]", - ty: UInt<8>, - flow: Sink, - }, - TraceUInt { - location: TraceScalarId(4), - name: "[1]", - ty: UInt<8>, - flow: Sink, - }, - TraceUInt { - location: TraceScalarId(5), - name: "[2]", - ty: UInt<8>, - flow: Sink, - }, - ], - ty: Array, 3>, - flow: Sink, - }, - ty: Array, 3>, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigClock { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigClock { - index: StatePartIndex(2), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigUInt { - index: StatePartIndex(3), - ty: UInt<8>, - }, - state: 0x31, - last_state: 0x31, - }, - SimTrace { - id: TraceScalarId(4), - kind: BigUInt { - index: StatePartIndex(4), - ty: UInt<8>, - }, - state: 0x32, - last_state: 0x32, - }, - SimTrace { - id: TraceScalarId(5), - kind: BigUInt { - index: StatePartIndex(5), - ty: UInt<8>, - }, - state: 0x32, - last_state: 0x32, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 648 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 198, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[0]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[0]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 198, - .. - }, - }, - ), - }, - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.vcd b/crates/fayalite/tests/sim/expected/sim_fork_join.vcd deleted file mode 100644 index a420c2b..0000000 --- a/crates/fayalite/tests/sim/expected/sim_fork_join.vcd +++ /dev/null @@ -1,1467 +0,0 @@ -$timescale 1 ps $end -$scope module sim_fork_join $end -$scope struct clocks $end -$var wire 1 ! \[0] $end -$var wire 1 " \[1] $end -$var wire 1 # \[2] $end -$upscope $end -$scope struct outputs $end -$var wire 8 $ \[0] $end -$var wire 8 % \[1] $end -$var wire 8 & \[2] $end -$upscope $end -$upscope $end -$enddefinitions $end -$dumpvars -0! -0" -0# -b0 $ -b0 % -b0 & -$end -#1000000 -1! -b1 $ -#2000000 -0! -#3000000 -1! -#4000000 -0! -#5000000 -1! -#6000000 -0! -#7000000 -1! -#8000000 -0! -#9000000 -1! -#10000000 -0! -#11000000 -1! -#12000000 -0! -#13000000 -1! -#14000000 -0! -#15000000 -1" -b1 % -#16000000 -0" -#17000000 -1! -#18000000 -0! -#19000000 -1! -#20000000 -0! -#21000000 -1! -#22000000 -0! -#23000000 -1# -b1 & -#24000000 -0# -#25000000 -1! -b10 $ -#26000000 -0! -#27000000 -1! -#28000000 -0! -#29000000 -1" -b10 % -#30000000 -0" -#31000000 -1! -#32000000 -0! -#33000000 -1! -#34000000 -0! -#35000000 -1! -#36000000 -0! -#37000000 -1" -#38000000 -0" -#39000000 -1" -#40000000 -0" -#41000000 -1! -#42000000 -0! -#43000000 -1! -#44000000 -0! -#45000000 -1" -#46000000 -0" -#47000000 -1# -b10 & -#48000000 -0# -#49000000 -1! -b11 $ -#50000000 -0! -#51000000 -1! -#52000000 -0! -#53000000 -1# -b11 & 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-#115000000 -1" -#116000000 -0" -#117000000 -1" -#118000000 -0" -#119000000 -1# -b110 & -#120000000 -0# -#121000000 -1! -b111 $ -#122000000 -0! -#123000000 -1" -b111 % -#124000000 -0" -#125000000 -1# -b111 & -#126000000 -0# -#127000000 -1! -b1000 $ -#128000000 -0! -#129000000 -1! -#130000000 -0! -#131000000 -1" -b1000 % -#132000000 -0" -#133000000 -1# -b1000 & -#134000000 -0# -#135000000 -1" -b1001 % -#136000000 -0" -#137000000 -1! -b1001 $ -#138000000 -0! -#139000000 -1" -#140000000 -0" -#141000000 -1# -b1001 & -#142000000 -0# -#143000000 -1# -b1010 & -#144000000 -0# -#145000000 -1! -b1010 $ -#146000000 -0! -#147000000 -1# -#148000000 -0# -#149000000 -1! -#150000000 -0! -#151000000 -1! -#152000000 -0! -#153000000 -1! -#154000000 -0! -#155000000 -1# -#156000000 -0# -#157000000 -1! -#158000000 -0! -#159000000 -1" -b1010 % -#160000000 -0" -#161000000 -1! -b1011 $ -#162000000 -0! -#163000000 -1# -b1011 & -#164000000 -0# -#165000000 -1! -#166000000 -0! -#167000000 -1# -#168000000 -0# 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-1! -#222000000 -0! -#223000000 -1! -#224000000 -0! -#225000000 -1" -b10001 % -#226000000 -0" -#227000000 -1! -#228000000 -0! -#229000000 -1! -#230000000 -0! -#231000000 -1" -#232000000 -0" -#233000000 -1" -#234000000 -0" -#235000000 -1! -#236000000 -0! -#237000000 -1! -#238000000 -0! -#239000000 -1# -b10001 & -#240000000 -0# -#241000000 -1" -b10010 % -#242000000 -0" -#243000000 -1! -b10010 $ -#244000000 -0! -#245000000 -1" -#246000000 -0" -#247000000 -1! -#248000000 -0! -#249000000 -1" -#250000000 -0" -#251000000 -1! -#252000000 -0! -#253000000 -1" -#254000000 -0" -#255000000 -1" -#256000000 -0" -#257000000 -1" -#258000000 -0" -#259000000 -1! -#260000000 -0! -#261000000 -1" -#262000000 -0" -#263000000 -1# -b10010 & -#264000000 -0# -#265000000 -1" -b10011 % -#266000000 -0" -#267000000 -1! -b10011 $ -#268000000 -0! -#269000000 -1# -b10011 & -#270000000 -0# -#271000000 -1! -b10100 $ -#272000000 -0! -#273000000 -1" -b10100 % -#274000000 -0" -#275000000 -1! -#276000000 -0! -#277000000 -1# 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b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt deleted file mode 100644 index 40d16a9..0000000 --- a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt +++ /dev/null @@ -1,525 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 6, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[2]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::outputs[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::outputs[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::outputs[2]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - 0: Return, - ], - .. - }, - pc: 0, - memory_write_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 0, - 0, - 0, - 49, - 50, - 50, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::sim_fork_join_scope, - instantiated: Module { - name: sim_fork_join_scope, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::sim_fork_join_scope, - instantiated: Module { - name: sim_fork_join_scope, - .. - }, - }.clocks, - Instance { - name: ::sim_fork_join_scope, - instantiated: Module { - name: sim_fork_join_scope, - .. - }, - }.outputs, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::sim_fork_join_scope, - instantiated: Module { - name: sim_fork_join_scope, - .. - }, - }.clocks, - Instance { - name: ::sim_fork_join_scope, - instantiated: Module { - name: sim_fork_join_scope, - .. - }, - }.clocks[0], - Instance { - name: ::sim_fork_join_scope, - instantiated: Module { - name: sim_fork_join_scope, - .. - }, - }.clocks[1], - Instance { - name: ::sim_fork_join_scope, - instantiated: Module { - name: sim_fork_join_scope, - .. - }, - }.clocks[2], - Instance { - name: ::sim_fork_join_scope, - instantiated: Module { - name: sim_fork_join_scope, - .. - }, - }.outputs, - Instance { - name: ::sim_fork_join_scope, - instantiated: Module { - name: sim_fork_join_scope, - .. - }, - }.outputs[0], - Instance { - name: ::sim_fork_join_scope, - instantiated: Module { - name: sim_fork_join_scope, - .. - }, - }.outputs[1], - Instance { - name: ::sim_fork_join_scope, - instantiated: Module { - name: sim_fork_join_scope, - .. - }, - }.outputs[2], - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - extern_modules: [ - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: sim_fork_join_scope::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join_scope::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: sim_fork_join_scope::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join_scope::clocks, - is_input: true, - ty: Array, - .. - }[0], - ModuleIO { - name: sim_fork_join_scope::clocks, - is_input: true, - ty: Array, - .. - }[1], - ModuleIO { - name: sim_fork_join_scope::clocks, - is_input: true, - ty: Array, - .. - }[2], - ModuleIO { - name: sim_fork_join_scope::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ModuleIO { - name: sim_fork_join_scope::outputs, - is_input: false, - ty: Array, 3>, - .. - }[0], - ModuleIO { - name: sim_fork_join_scope::outputs, - is_input: false, - ty: Array, 3>, - .. - }[1], - ModuleIO { - name: sim_fork_join_scope::outputs, - is_input: false, - ty: Array, 3>, - .. - }[2], - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: sim_fork_join_scope::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join_scope::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ), - f: ..., - }, - sim_io_to_generator_map: { - ModuleIO { - name: sim_fork_join_scope::clocks, - is_input: true, - ty: Array, - .. - }: ModuleIO { - name: sim_fork_join_scope::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_fork_join_scope::outputs, - is_input: false, - ty: Array, 3>, - .. - }: ModuleIO { - name: sim_fork_join_scope::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - }, - source_location: SourceLocation( - module-XXXXXXXXXX.rs:4:1, - ), - }, - running_generator: Some( - ..., - ), - }, - ], - trace_decls: TraceModule { - name: "sim_fork_join_scope", - children: [ - TraceModuleIO { - name: "clocks", - child: TraceArray { - name: "clocks", - elements: [ - TraceClock { - location: TraceScalarId(0), - name: "[0]", - flow: Source, - }, - TraceClock { - location: TraceScalarId(1), - name: "[1]", - flow: Source, - }, - TraceClock { - location: TraceScalarId(2), - name: "[2]", - flow: Source, - }, - ], - ty: Array, - flow: Source, - }, - ty: Array, - flow: Source, - }, - TraceModuleIO { - name: "outputs", - child: TraceArray { - name: "outputs", - elements: [ - TraceUInt { - location: TraceScalarId(3), - name: "[0]", - ty: UInt<8>, - flow: Sink, - }, - TraceUInt { - location: TraceScalarId(4), - name: "[1]", - ty: UInt<8>, - flow: Sink, - }, - TraceUInt { - location: TraceScalarId(5), - name: "[2]", - ty: UInt<8>, - flow: Sink, - }, - ], - ty: Array, 3>, - flow: Sink, - }, - ty: Array, 3>, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigClock { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigClock { - index: StatePartIndex(2), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigUInt { - index: StatePartIndex(3), - ty: UInt<8>, - }, - state: 0x31, - last_state: 0x31, - }, - SimTrace { - id: TraceScalarId(4), - kind: BigUInt { - index: StatePartIndex(4), - ty: UInt<8>, - }, - state: 0x32, - last_state: 0x32, - }, - SimTrace { - id: TraceScalarId(5), - kind: BigUInt { - index: StatePartIndex(5), - ty: UInt<8>, - }, - state: 0x32, - last_state: 0x32, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 648 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 198, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[0]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[0]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { 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}, did_initial_settle: true, - clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -636,7 +635,6 @@ Simulation { }, }, did_initial_settle: true, - clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -719,6 +717,52 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 6, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + }, + }, }, SimulationExternModuleState { module_state: SimulationModuleState { @@ -796,7 +840,6 @@ Simulation { }, }, did_initial_settle: true, - clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -879,8 +922,55 @@ Simulation { running_generator: Some( ..., ), + wait_targets: { + Change { + key: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 4, len: 0 }, + big_slots: StatePartIndexRange { start: 12, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 13, len: 0 }, + }, + write: None, + }, + value: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + }, + }, }, ], + state_ready_to_run: false, trace_decls: TraceModule { name: "sim_only_connects", children: [ @@ -1538,214 +1628,9 @@ Simulation { }, ), ], + instant: 16 μs, clocks_triggered: [ StatePartIndex(1), ], - event_queue: EventQueue(EventQueueData { - instant: 16 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 30, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 6, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - SensitivitySet { - id: 31, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 4, len: 0 }, - big_slots: StatePartIndexRange { start: 12, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 13, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 6, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 30, - .. - }, - }, - ), - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 4, len: 0 }, - big_slots: StatePartIndexRange { start: 12, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 13, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 31, - .. - }, - }, - ), - }, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.vcd b/crates/fayalite/tests/sim/expected/sim_only_connects.vcd index 1e4c249..2f464c0 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.vcd +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.vcd @@ -72,22 +72,22 @@ s{} 8 $end #1000000 1! -s{\"extra\":\x20\"value\"} $ 1' -s{\"extra\":\x20\"value\"} ) 1+ -s{\"extra\":\x20\"value\"} - 10 11 15 -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} % +s{\"extra\":\x20\"value\"} $ +s{\"extra\":\x20\"value\"} ) +s{\"extra\":\x20\"value\"} - s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} * +s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 4 +s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} % +s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} & s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} . s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 3 s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 7 -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} & -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4 -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8 +s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 8 #2000000 0! 0" @@ -107,6 +107,9 @@ s{\"extra\":\x20\"value\"} / 00 11 15 +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4 +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} & +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8 #4000000 0! 0' diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.txt b/crates/fayalite/tests/sim/expected/sim_read_past.txt deleted file mode 100644 index 475943e..0000000 --- a/crates/fayalite/tests/sim/expected/sim_read_past.txt +++ /dev/null @@ -1,9724 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 9, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - big_slots: StatePartLayout { - len: 48, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[2]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[2]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[2]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[2]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[2]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:2:1 - 0: IsNonZeroDestIsSmall { - dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, - }, - 1: AndSmall { - dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 2: IsNonZeroDestIsSmall { - dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, - }, - 3: AndSmall { - dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 4: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, - }, - 5: AndSmall { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - }, - 6: BranchIfSmallZero { - target: 10, - value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 7: Copy { - dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]", ty: Clock }, - src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, - }, - 8: Copy { - dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]", ty: Clock }, - src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, - }, - 9: Copy { - dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]", ty: Clock }, - src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:3:1 - 10: BranchIfSmallZero { - target: 14, - value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 11: Copy { - dest: StatePartIndex(15), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[0]", ty: UInt<8> }, - src: StatePartIndex(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> }, - }, - 12: Copy { - dest: StatePartIndex(16), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[1]", ty: UInt<8> }, - src: StatePartIndex(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> }, - }, - 13: Copy { - dest: StatePartIndex(17), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[2]", ty: UInt<8> }, - src: StatePartIndex(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 14: BranchIfSmallZero { - target: 18, - value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 15: Copy { - dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[0]", ty: Clock }, - src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock }, - }, - 16: Copy { - dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[1]", ty: Clock }, - src: StatePartIndex(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock }, - }, - 17: Copy { - dest: StatePartIndex(20), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[2]", ty: Clock }, - src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:5:1 - 18: BranchIfSmallZero { - target: 22, - value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 19: Copy { - dest: StatePartIndex(21), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[0]", ty: UInt<8> }, - src: StatePartIndex(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> }, - }, - 20: Copy { - dest: StatePartIndex(22), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[1]", ty: UInt<8> }, - src: StatePartIndex(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> }, - }, - 21: Copy { - dest: StatePartIndex(23), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[2]", ty: UInt<8> }, - src: StatePartIndex(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:2:1 - 22: BranchIfSmallZero { - target: 26, - value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 23: Copy { - dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[0]", ty: Clock }, - src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, - }, - 24: Copy { - dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[1]", ty: Clock }, - src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, - }, - 25: Copy { - dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[2]", ty: Clock }, - src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:3:1 - 26: BranchIfSmallZero { - target: 30, - value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 27: Copy { - dest: StatePartIndex(27), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[0]", ty: UInt<8> }, - src: StatePartIndex(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> }, - }, - 28: Copy { - dest: StatePartIndex(28), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[1]", ty: UInt<8> }, - src: StatePartIndex(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> }, - }, - 29: Copy { - dest: StatePartIndex(29), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[2]", ty: UInt<8> }, - src: StatePartIndex(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 30: BranchIfSmallZero { - target: 34, - value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 31: Copy { - dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[0]", ty: Clock }, - src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock }, - }, - 32: Copy { - dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[1]", ty: Clock }, - src: StatePartIndex(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock }, - }, - 33: Copy { - dest: StatePartIndex(32), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[2]", ty: Clock }, - src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:5:1 - 34: BranchIfSmallZero { - target: 38, - value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 35: Copy { - dest: StatePartIndex(33), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[0]", ty: UInt<8> }, - src: StatePartIndex(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> }, - }, - 36: Copy { - dest: StatePartIndex(34), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[1]", ty: UInt<8> }, - src: StatePartIndex(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> }, - }, - 37: Copy { - dest: StatePartIndex(35), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[2]", ty: UInt<8> }, - src: StatePartIndex(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:2:1 - 38: BranchIfSmallZero { - target: 42, - value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 39: Copy { - dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[0]", ty: Clock }, - src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, - }, - 40: Copy { - dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[1]", ty: Clock }, - src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, - }, - 41: Copy { - dest: StatePartIndex(38), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[2]", ty: Clock }, - src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:3:1 - 42: BranchIfSmallZero { - target: 46, - value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 43: Copy { - dest: StatePartIndex(39), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[0]", ty: UInt<8> }, - src: StatePartIndex(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> }, - }, - 44: Copy { - dest: StatePartIndex(40), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[1]", ty: UInt<8> }, - src: StatePartIndex(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> }, - }, - 45: Copy { - dest: StatePartIndex(41), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[2]", ty: UInt<8> }, - src: StatePartIndex(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:4:1 - 46: BranchIfSmallZero { - target: 50, - value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 47: Copy { - dest: StatePartIndex(42), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[0]", ty: Clock }, - src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock }, - }, - 48: Copy { - dest: StatePartIndex(43), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[1]", ty: Clock }, - src: StatePartIndex(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock }, - }, - 49: Copy { - dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[2]", ty: Clock }, - src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock }, - }, - // at: module-XXXXXXXXXX.rs:5:1 - 50: BranchIfSmallZero { - target: 54, - value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, - 51: Copy { - dest: StatePartIndex(45), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[0]", ty: UInt<8> }, - src: StatePartIndex(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> }, - }, - 52: Copy { - dest: StatePartIndex(46), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[1]", ty: UInt<8> }, - src: StatePartIndex(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> }, - }, - 53: Copy { - dest: StatePartIndex(47), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]", ty: UInt<8> }, - src: StatePartIndex(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> }, - }, - // at: module-XXXXXXXXXX.rs:2:1 - 54: XorSmallImmediate { - dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 55: XorSmallImmediate { - dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - 56: XorSmallImmediate { - dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - rhs: 0x1, - }, - // at: module-XXXXXXXXXX.rs:1:1 - 57: Return, - ], - .. - }, - pc: 57, - memory_write_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [ - 1, - 0, - 0, - 1, - 0, - 0, - 1, - 0, - 0, - ], - }, - big_slots: StatePart { - value: [ - 0, - 0, - 0, - 49, - 50, - 50, - 0, - 1, - 0, - 49, - 49, - 50, - 1, - 0, - 0, - 48, - 49, - 49, - 0, - 0, - 1, - 48, - 49, - 48, - 0, - 1, - 0, - 49, - 49, - 50, - 0, - 0, - 1, - 49, - 49, - 49, - 0, - 0, - 1, - 49, - 50, - 50, - 0, - 1, - 0, - 49, - 49, - 50, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.clocks, - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.outputs, - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.past_clocks, - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.past_outputs, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.clocks, - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.clocks[0], - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.clocks[1], - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.clocks[2], - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.outputs, - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.outputs[0], - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.outputs[1], - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.outputs[2], - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.past_clocks, - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.past_clocks[0], - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.past_clocks[1], - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.past_clocks[2], - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.past_outputs, - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.past_outputs[0], - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.past_outputs[1], - Instance { - name: ::sim_read_past, - instantiated: Module { - name: sim_read_past, - .. - }, - }.past_outputs[2], - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - extern_modules: [ - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: sim_read_past::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_read_past::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ModuleIO { - name: sim_read_past::past_clocks, - is_input: false, - ty: Array, - .. - }, - ModuleIO { - name: sim_read_past::past_outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: sim_read_past::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_read_past::clocks, - is_input: true, - ty: Array, - .. - }[0], - ModuleIO { - name: sim_read_past::clocks, - is_input: true, - ty: Array, - .. - }[1], - ModuleIO { - name: sim_read_past::clocks, - is_input: true, - ty: Array, - .. - }[2], - ModuleIO { - name: sim_read_past::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ModuleIO { - name: sim_read_past::outputs, - is_input: false, - ty: Array, 3>, - .. - }[0], - ModuleIO { - name: sim_read_past::outputs, - is_input: false, - ty: Array, 3>, - .. - }[1], - ModuleIO { - name: sim_read_past::outputs, - is_input: false, - ty: Array, 3>, - .. - }[2], - ModuleIO { - name: sim_read_past::past_clocks, - is_input: false, - ty: Array, - .. - }, - ModuleIO { - name: sim_read_past::past_clocks, - is_input: false, - ty: Array, - .. - }[0], - ModuleIO { - name: sim_read_past::past_clocks, - is_input: false, - ty: Array, - .. - }[1], - ModuleIO { - name: sim_read_past::past_clocks, - is_input: false, - ty: Array, - .. - }[2], - ModuleIO { - name: sim_read_past::past_outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ModuleIO { - name: sim_read_past::past_outputs, - is_input: false, - ty: Array, 3>, - .. - }[0], - ModuleIO { - name: sim_read_past::past_outputs, - is_input: false, - ty: Array, 3>, - .. - }[1], - ModuleIO { - name: sim_read_past::past_outputs, - is_input: false, - ty: Array, 3>, - .. - }[2], - }, - did_initial_settle: true, - clocks_for_past: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimulationExternModuleClockForPast { - current_to_past_map: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Array, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 3, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Array { - elements_non_empty: [ - CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 3 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: CompiledValue { - layout: CompiledTypeLayout { - ty: Array, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 3, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Array { - elements_non_empty: [ - CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 12, len: 3 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: Some( - ( - CompiledTypeLayout { - ty: Array, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 3, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", - ty: 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sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[0]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 39, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: Some( - ( - CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - ), - ), - }, - CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[1]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 40, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: Some( - ( - CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - ), - ), - }, - CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 5, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[2]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 41, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: Some( - ( - CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 5, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - ), - ), - }, - CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 9, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[0]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 45, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: Some( - ( - CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 9, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - ), - ), - }, - CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 10, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[1]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 46, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: Some( - ( - CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 10, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - ), - ), - }, - CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 11, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 47, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: Some( - ( - CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 11, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - ), - ), - }, - }, - }, - }, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: sim_read_past::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_read_past::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ModuleIO { - name: sim_read_past::past_clocks, - is_input: false, - ty: Array, - .. - }, - ModuleIO { - name: sim_read_past::past_outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ), - f: ..., - }, - sim_io_to_generator_map: { - ModuleIO { - name: sim_read_past::clocks, - is_input: true, - ty: Array, - .. - }: ModuleIO { - name: sim_read_past::clocks, - is_input: true, - ty: Array, - .. - }, - ModuleIO { - name: sim_read_past::outputs, - is_input: false, - ty: Array, 3>, - .. - }: ModuleIO { - name: sim_read_past::outputs, - is_input: false, - ty: Array, 3>, - .. - }, - ModuleIO { - name: sim_read_past::past_clocks, - is_input: false, - ty: Array, - .. - }: ModuleIO { - name: sim_read_past::past_clocks, - is_input: false, - ty: Array, - .. - }, - ModuleIO { - name: sim_read_past::past_outputs, - is_input: false, - ty: Array, 3>, - .. - }: ModuleIO { - name: sim_read_past::past_outputs, - is_input: false, - ty: Array, 3>, - .. - }, - }, - source_location: SourceLocation( - module-XXXXXXXXXX.rs:6:1, - ), - }, - running_generator: Some( - ..., - ), - }, - ], - trace_decls: TraceModule { - name: "sim_read_past", - children: [ - TraceModuleIO { - name: "clocks", - child: TraceArray { - name: "clocks", - elements: [ - TraceClock { - location: TraceScalarId(0), - name: "[0]", - flow: Source, - }, - TraceClock { - location: TraceScalarId(1), - name: "[1]", - flow: Source, - }, - TraceClock { - location: TraceScalarId(2), - name: "[2]", - flow: Source, - }, - ], - ty: Array, - flow: Source, - }, - ty: Array, - flow: Source, - }, - TraceModuleIO { - name: "outputs", - child: TraceArray { - name: "outputs", - elements: [ - TraceUInt { - location: TraceScalarId(3), - name: "[0]", - ty: UInt<8>, - flow: Sink, - }, - TraceUInt { - location: TraceScalarId(4), - name: "[1]", - ty: UInt<8>, - flow: Sink, - }, - TraceUInt { - location: TraceScalarId(5), - name: "[2]", - ty: UInt<8>, - flow: Sink, - }, - ], - ty: Array, 3>, - flow: Sink, - }, - ty: Array, 3>, - flow: Sink, - }, - TraceModuleIO { - name: "past_clocks", - child: TraceArray { - name: "past_clocks", - elements: [ - TraceClock { - location: TraceScalarId(6), - name: "[0]", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(7), - name: "[1]", - flow: Sink, - }, - TraceClock { - location: TraceScalarId(8), - name: "[2]", - flow: Sink, - }, - ], - ty: Array, - flow: Sink, - }, - ty: Array, - flow: Sink, - }, - TraceModuleIO { - name: "past_outputs", - child: TraceArray { - name: "past_outputs", - elements: [ - TraceUInt { - location: TraceScalarId(9), - name: "[0]", - ty: UInt<8>, - flow: Sink, - }, - TraceUInt { - location: TraceScalarId(10), - name: "[1]", - ty: UInt<8>, - flow: Sink, - }, - TraceUInt { - location: TraceScalarId(11), - name: "[2]", - ty: UInt<8>, - flow: Sink, - }, - ], - ty: Array, 3>, - flow: Sink, - }, - ty: Array, 3>, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigClock { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigClock { - index: StatePartIndex(2), - }, - state: 0x0, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(3), - kind: BigUInt { - index: StatePartIndex(3), - ty: UInt<8>, - }, - state: 0x31, - last_state: 0x31, - }, - SimTrace { - id: TraceScalarId(4), - kind: BigUInt { - index: StatePartIndex(4), - ty: UInt<8>, - }, - state: 0x32, - last_state: 0x32, - }, - SimTrace { - id: TraceScalarId(5), - kind: BigUInt { - index: StatePartIndex(5), - ty: UInt<8>, - }, - state: 0x32, - last_state: 0x32, - }, - SimTrace { - id: TraceScalarId(6), - kind: BigClock { - index: StatePartIndex(6), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(7), - kind: BigClock { - index: StatePartIndex(7), - }, - state: 0x1, - last_state: 0x1, - }, - SimTrace { - id: TraceScalarId(8), - kind: BigClock { - index: StatePartIndex(8), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(9), - kind: BigUInt { - index: StatePartIndex(9), - ty: UInt<8>, - }, - state: 0x31, - last_state: 0x31, - }, - SimTrace { - id: TraceScalarId(10), - kind: BigUInt { - index: StatePartIndex(10), - ty: UInt<8>, - }, - state: 0x31, - last_state: 0x31, - }, - SimTrace { - id: TraceScalarId(11), - kind: BigUInt { - index: StatePartIndex(11), - ty: UInt<8>, - }, - state: 0x32, - last_state: 0x32, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [ - StatePartIndex(1), - StatePartIndex(4), - StatePartIndex(7), - ], - event_queue: EventQueue(EventQueueData { - instant: 648 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 198, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 198, - .. - }, - }, - ), - }, - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.vcd b/crates/fayalite/tests/sim/expected/sim_read_past.vcd deleted file mode 100644 index 5d0a932..0000000 --- a/crates/fayalite/tests/sim/expected/sim_read_past.vcd +++ /dev/null @@ -1,1908 +0,0 @@ -$timescale 1 ps $end -$scope module sim_read_past $end -$scope struct clocks $end -$var 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b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt deleted file mode 100644 index 7b11157..0000000 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt +++ /dev/null @@ -1,552 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 3, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", - ty: AsyncReset, - }, - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::out", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - 0: Return, - ], - .. - }, - pc: 0, - memory_write_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 0, - 0, - 3, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.out, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd.clk, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd.rst, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.out, - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - extern_modules: [ - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }.clk, - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }.rst, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - ), - f: ..., - }, - sim_io_to_generator_map: { - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }: ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }: ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - }, - source_location: SourceLocation( - module-XXXXXXXXXX.rs:4:1, - ), - }, - running_generator: Some( - ..., - ), - }, - ], - trace_decls: TraceModule { - name: "sim_resettable_counter", - children: [ - TraceModuleIO { - name: "cd", - child: TraceBundle { - name: "cd", - fields: [ - TraceClock { - location: TraceScalarId(0), - name: "clk", - flow: Source, - }, - TraceAsyncReset { - location: TraceScalarId(1), - name: "rst", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - flow: Source, - }, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - flow: Source, - }, - TraceModuleIO { - name: "out", - child: TraceUInt { - location: TraceScalarId(2), - name: "out", - ty: UInt<8>, - flow: Sink, - }, - ty: UInt<8>, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigAsyncReset { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigUInt { - index: StatePartIndex(2), - ty: UInt<8>, - }, - state: 0x03, - last_state: 0x03, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 20 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 16, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: AsyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", - ty: AsyncReset, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: AsyncReset, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - SensitivitySet { - id: 23, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: AsyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", - ty: AsyncReset, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: AsyncReset, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 16, - .. - }, - }, - ), - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 23, - .. - }, - }, - ), - }, - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd deleted file mode 100644 index f05658f..0000000 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd +++ /dev/null @@ -1,68 +0,0 @@ -$timescale 1 ps $end -$scope module sim_resettable_counter $end -$scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end -$upscope $end -$var wire 8 # out $end -$upscope $end -$enddefinitions $end -$dumpvars -0! -0" -b0 # -$end -#1000000 -1! -b1 # -#2000000 -0! -1" -b0 # -#3000000 -1! -#4000000 -0! -0" -#5000000 -1! -b1 # -#6000000 -0! -#7000000 -1! -b10 # -#8000000 -0! -#9000000 -1! -b11 # -#10000000 -0! -#11000000 -1! -b100 # -#12000000 -0! -1" -b0 # -#13000000 -1! -#14000000 -0! -0" -#15000000 -1! -b1 # -#16000000 -0! -#17000000 -1! -b10 # -#18000000 -0! -#19000000 -1! -b11 # -#20000000 -0! diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt deleted file mode 100644 index 0ca767a..0000000 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt +++ /dev/null @@ -1,552 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 3, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", - ty: AsyncReset, - }, - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::out", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - 0: Return, - ], - .. - }, - pc: 0, - memory_write_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 0, - 0, - 3, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.out, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd.clk, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd.rst, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.out, - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - extern_modules: [ - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }.clk, - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }.rst, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - ), - f: ..., - }, - sim_io_to_generator_map: { - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }: ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }: ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - }, - source_location: SourceLocation( - module-XXXXXXXXXX.rs:4:1, - ), - }, - running_generator: Some( - ..., - ), - }, - ], - trace_decls: TraceModule { - name: "sim_resettable_counter", - children: [ - TraceModuleIO { - name: "cd", - child: TraceBundle { - name: "cd", - fields: [ - TraceClock { - location: TraceScalarId(0), - name: "clk", - flow: Source, - }, - TraceAsyncReset { - location: TraceScalarId(1), - name: "rst", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - flow: Source, - }, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, - }, - flow: Source, - }, - TraceModuleIO { - name: "out", - child: TraceUInt { - location: TraceScalarId(2), - name: "out", - ty: UInt<8>, - flow: Sink, - }, - ty: UInt<8>, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigAsyncReset { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigUInt { - index: StatePartIndex(2), - ty: UInt<8>, - }, - state: 0x03, - last_state: 0x03, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 20 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 13, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: AsyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", - ty: AsyncReset, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: AsyncReset, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - SensitivitySet { - id: 20, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: AsyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", - ty: AsyncReset, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: AsyncReset, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 13, - .. - }, - }, - ), - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 20, - .. - }, - }, - ), - }, - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd deleted file mode 100644 index 99f7b86..0000000 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd +++ /dev/null @@ -1,65 +0,0 @@ -$timescale 1 ps $end -$scope module sim_resettable_counter $end -$scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end -$upscope $end -$var wire 8 # out $end -$upscope $end -$enddefinitions $end -$dumpvars -0! -1" -b0 # -$end -#1000000 -1! -#2000000 -0! -#3000000 -1! -#4000000 -0! -0" -#5000000 -1! -b1 # -#6000000 -0! -#7000000 -1! -b10 # -#8000000 -0! -#9000000 -1! -b11 # -#10000000 -0! -#11000000 -1! -b100 # -#12000000 -0! -1" -b0 # -#13000000 -1! -#14000000 -0! -0" -#15000000 -1! -b1 # -#16000000 -0! -#17000000 -1! -b10 # -#18000000 -0! -#19000000 -1! -b11 # -#20000000 -0! diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt deleted file mode 100644 index 4af2eb6..0000000 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt +++ /dev/null @@ -1,507 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 3, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", - ty: SyncReset, - }, - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::out", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - 0: Return, - ], - .. - }, - pc: 0, - memory_write_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 0, - 0, - 3, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.out, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd.clk, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd.rst, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.out, - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - extern_modules: [ - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }.clk, - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }.rst, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - ), - f: ..., - }, - sim_io_to_generator_map: { - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }: ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }: ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - }, - source_location: SourceLocation( - module-XXXXXXXXXX.rs:4:1, - ), - }, - running_generator: Some( - ..., - ), - }, - ], - trace_decls: TraceModule { - name: "sim_resettable_counter", - children: [ - TraceModuleIO { - name: "cd", - child: TraceBundle { - name: "cd", - fields: [ - TraceClock { - location: TraceScalarId(0), - name: "clk", - flow: Source, - }, - TraceSyncReset { - location: TraceScalarId(1), - name: "rst", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - flow: Source, - }, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - flow: Source, - }, - TraceModuleIO { - name: "out", - child: TraceUInt { - location: TraceScalarId(2), - name: "out", - ty: UInt<8>, - flow: Sink, - }, - ty: UInt<8>, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigSyncReset { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigUInt { - index: StatePartIndex(2), - ty: UInt<8>, - }, - state: 0x03, - last_state: 0x03, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 20 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 42, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - SensitivitySet { - id: 43, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 42, - .. - }, - SensitivitySet { - id: 43, - .. - }, - }, - ), - }, - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd deleted file mode 100644 index 39c2641..0000000 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd +++ /dev/null @@ -1,70 +0,0 @@ -$timescale 1 ps $end -$scope module sim_resettable_counter $end -$scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end -$upscope $end -$var wire 8 # out $end -$upscope $end -$enddefinitions $end -$dumpvars -0! -0" -b0 # -$end -#1000000 -1! -b1 # -#2000000 -0! -1" -#3000000 -1! -b10 # -b0 # -#4000000 -0! -0" -#5000000 -1! -b1 # -#6000000 -0! -#7000000 -1! -b10 # -#8000000 -0! -#9000000 -1! -b11 # -#10000000 -0! -#11000000 -1! -b100 # -#12000000 -0! -1" -#13000000 -1! -b101 # -b0 # -#14000000 -0! -0" -#15000000 -1! -b1 # -#16000000 -0! -#17000000 -1! -b10 # -#18000000 -0! -#19000000 -1! -b11 # -#20000000 -0! diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt deleted file mode 100644 index 45f09d2..0000000 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt +++ /dev/null @@ -1,507 +0,0 @@ -Simulation { - state: State { - insns: Insns { - state_layout: StateLayout { - ty: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 3, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", - ty: SyncReset, - }, - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::out", - ty: UInt<8>, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - memories: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - insns: [ - // at: module-XXXXXXXXXX.rs:1:1 - 0: Return, - ], - .. - }, - pc: 0, - memory_write_log: [], - memories: StatePart { - value: [], - }, - small_slots: StatePart { - value: [], - }, - big_slots: StatePart { - value: [ - 0, - 0, - 3, - ], - }, - sim_only_slots: StatePart { - value: [], - }, - }, - io: Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }, - main_module: SimulationModuleState { - base_targets: [ - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.out, - ], - uninitialized_ios: {}, - io_targets: { - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd.clk, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.cd.rst, - Instance { - name: ::sim_resettable_counter, - instantiated: Module { - name: sim_resettable_counter, - .. - }, - }.out, - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - extern_modules: [ - SimulationExternModuleState { - module_state: SimulationModuleState { - base_targets: [ - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - ], - uninitialized_ios: {}, - io_targets: { - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }.clk, - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }.rst, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - }, - did_initial_settle: true, - clocks_for_past: {}, - }, - sim: ExternModuleSimulation { - generator: SimGeneratorFn { - args: ( - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - ), - f: ..., - }, - sim_io_to_generator_map: { - ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }: ModuleIO { - name: sim_resettable_counter::cd, - is_input: true, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - .. - }, - ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }: ModuleIO { - name: sim_resettable_counter::out, - is_input: false, - ty: UInt<8>, - .. - }, - }, - source_location: SourceLocation( - module-XXXXXXXXXX.rs:4:1, - ), - }, - running_generator: Some( - ..., - ), - }, - ], - trace_decls: TraceModule { - name: "sim_resettable_counter", - children: [ - TraceModuleIO { - name: "cd", - child: TraceBundle { - name: "cd", - fields: [ - TraceClock { - location: TraceScalarId(0), - name: "clk", - flow: Source, - }, - TraceSyncReset { - location: TraceScalarId(1), - name: "rst", - flow: Source, - }, - ], - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - flow: Source, - }, - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - flow: Source, - }, - TraceModuleIO { - name: "out", - child: TraceUInt { - location: TraceScalarId(2), - name: "out", - ty: UInt<8>, - flow: Sink, - }, - ty: UInt<8>, - flow: Sink, - }, - ], - }, - traces: [ - SimTrace { - id: TraceScalarId(0), - kind: BigClock { - index: StatePartIndex(0), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(1), - kind: BigSyncReset { - index: StatePartIndex(1), - }, - state: 0x0, - last_state: 0x0, - }, - SimTrace { - id: TraceScalarId(2), - kind: BigUInt { - index: StatePartIndex(2), - ty: UInt<8>, - }, - state: 0x03, - last_state: 0x03, - }, - ], - trace_memories: {}, - trace_writers: [ - Running( - VcdWriter { - finished_init: true, - timescale: 1 ps, - .. - }, - ), - ], - clocks_triggered: [], - event_queue: EventQueue(EventQueueData { - instant: 20 μs, - events: {}, - }), - waiting_sensitivity_sets_by_address: { - SensitivitySet { - id: 43, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - SensitivitySet { - id: 44, - values: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - changed: Cell { - value: false, - }, - .. - }, - }, - waiting_sensitivity_sets_by_compiled_value: { - CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }: ( - SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - { - SensitivitySet { - id: 43, - .. - }, - SensitivitySet { - id: 44, - .. - }, - }, - ), - }, - .. -} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd deleted file mode 100644 index 3cb97e2..0000000 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd +++ /dev/null @@ -1,70 +0,0 @@ -$timescale 1 ps $end -$scope module sim_resettable_counter $end -$scope struct cd $end -$var wire 1 ! clk $end -$var wire 1 " rst $end -$upscope $end -$var wire 8 # out $end -$upscope $end -$enddefinitions $end -$dumpvars -0! -1" -b0 # -$end -#1000000 -1! -b1 # -b0 # -#2000000 -0! -#3000000 -1! -b1 # -b0 # -#4000000 -0! -0" -#5000000 -1! -b1 # -#6000000 -0! -#7000000 -1! -b10 # -#8000000 -0! -#9000000 -1! -b11 # -#10000000 -0! -#11000000 -1! -b100 # -#12000000 -0! -1" -#13000000 -1! -b101 # -b0 # -#14000000 -0! -0" -#15000000 -1! -b1 # -#16000000 -0! -#17000000 -1! -b10 # -#18000000 -0! -#19000000 -1! -b11 # -#20000000 -0! diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json index a74cef9..04227ef 100644 --- a/crates/fayalite/visit_types.json +++ b/crates/fayalite/visit_types.json @@ -162,7 +162,6 @@ "$kind": "Struct", "verilog_name": "Visible", "parameters": "Visible", - "clocks_for_past": "Visible", "simulation": "Visible" } },