From 0b821787408e940d30799a525743f25e64d1c6ae Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 27 Oct 2025 20:08:22 -0700 Subject: [PATCH 01/10] add PhantomConstGet to the known Type bounds for #[hdl] struct/enum --- .../src/hdl_type_alias.rs | 106 +------- .../src/hdl_type_common.rs | 256 ++++++++++++++++-- crates/fayalite/src/lib.rs | 4 +- crates/fayalite/tests/hdl_types.rs | 2 +- 4 files changed, 251 insertions(+), 117 deletions(-) diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs index 82353669..0fa2222d 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_alias.rs @@ -3,111 +3,19 @@ use crate::{ Errors, HdlAttr, hdl_type_common::{ - ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, TypesParser, - WrappedInConst, common_derives, get_target, known_items, + ItemOptions, MakeHdlTypeExpr, MaybeParsed, ParsedGenerics, ParsedType, + PhantomConstGetBound, TypesParser, WrappedInConst, common_derives, get_target, known_items, }, kw, }; use proc_macro2::TokenStream; use quote::{ToTokens, format_ident, quote_spanned}; use syn::{ - AngleBracketedGenericArguments, Attribute, Expr, Fields, GenericArgument, GenericParam, - Generics, Ident, ItemStruct, ItemType, Path, PathArguments, Token, TraitBound, - TraitBoundModifier, Type, TypeGroup, TypeParam, TypeParamBound, TypeParen, Visibility, - parse_quote_spanned, punctuated::Pair, token::Paren, + Attribute, Expr, Fields, GenericParam, Generics, Ident, ItemStruct, ItemType, Token, Type, + TypeGroup, TypeParam, TypeParen, Visibility, parse_quote_spanned, punctuated::Pair, + token::Paren, }; -#[derive(Clone, Debug)] -pub(crate) struct PhantomConstGetBound { - pub(crate) phantom_const_get: known_items::PhantomConstGet, - pub(crate) colon2_token: Option, - pub(crate) lt_token: Token![<], - pub(crate) ty: Type, - pub(crate) comma_token: Option, - pub(crate) gt_token: Token![>], -} - -impl From for Path { - fn from(value: PhantomConstGetBound) -> Self { - let PhantomConstGetBound { - phantom_const_get, - colon2_token, - lt_token, - ty, - comma_token, - gt_token, - } = value; - let mut path = phantom_const_get.path; - path.segments.last_mut().expect("known to exist").arguments = - PathArguments::AngleBracketed(AngleBracketedGenericArguments { - colon2_token, - lt_token, - args: FromIterator::from_iter([Pair::new(GenericArgument::Type(ty), comma_token)]), - gt_token, - }); - path - } -} - -impl From for TraitBound { - fn from(value: PhantomConstGetBound) -> Self { - let path = Path::from(value); - TraitBound { - paren_token: None, - modifier: TraitBoundModifier::None, - lifetimes: None, - path, - } - } -} - -impl From for TypeParamBound { - fn from(value: PhantomConstGetBound) -> Self { - TraitBound::from(value).into() - } -} - -impl PhantomConstGetBound { - fn parse_opt(bound: TypeParamBound) -> Option { - let TypeParamBound::Trait(TraitBound { - paren_token: None, - modifier: TraitBoundModifier::None, - lifetimes: None, - path, - }) = bound - else { - return None; - }; - let Ok(( - phantom_const_get, - PathArguments::AngleBracketed(AngleBracketedGenericArguments { - colon2_token, - lt_token, - args, - gt_token, - }), - )) = known_items::PhantomConstGet::parse_path_with_arguments(path) - else { - return None; - }; - let mut args = args.into_pairs(); - let (GenericArgument::Type(ty), comma_token) = args.next()?.into_tuple() else { - return None; - }; - let None = args.next() else { - return None; - }; - Some(Self { - phantom_const_get, - colon2_token, - lt_token, - ty, - comma_token, - gt_token, - }) - } -} - #[derive(Clone, Debug)] pub(crate) struct PhantomConstAccessorTypeParam { attrs: Vec, @@ -162,7 +70,9 @@ impl PhantomConstAccessorTypeParam { let colon_token = colon_token.unwrap_or(Token![:](ident.span())); let mut bounds = bounds.into_pairs(); let (bound, plus_token) = bounds.next()?.into_tuple(); - let phantom_const_get_bound = PhantomConstGetBound::parse_opt(bound)?; + let phantom_const_get_bound = PhantomConstGetBound::parse_type_param_bound(bound) + .ok()? + .ok()?; let None = bounds.next() else { return None; }; diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs index 73acc395..f5b353e0 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs @@ -8,9 +8,9 @@ use syn::{ AngleBracketedGenericArguments, Attribute, Block, ConstParam, Expr, ExprBlock, ExprGroup, ExprIndex, ExprParen, ExprPath, ExprTuple, Field, FieldMutability, Fields, FieldsNamed, FieldsUnnamed, GenericArgument, GenericParam, Generics, Ident, ImplGenerics, Index, ItemStruct, - Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, Turbofish, Type, - TypeGenerics, TypeGroup, TypeParam, TypeParen, TypePath, TypeTuple, Visibility, WhereClause, - WherePredicate, + Path, PathArguments, PathSegment, PredicateType, QSelf, Stmt, Token, TraitBound, Turbofish, + Type, TypeGenerics, TypeGroup, TypeParam, TypeParamBound, TypeParen, TypePath, TypeTuple, + Visibility, WhereClause, WherePredicate, parse::{Parse, ParseStream}, parse_quote, parse_quote_spanned, punctuated::{Pair, Punctuated}, @@ -2065,6 +2065,174 @@ pub(crate) mod known_items { ); } +#[derive(Clone, Debug)] +pub(crate) struct PhantomConstGetBound { + pub(crate) phantom_const_get: known_items::PhantomConstGet, + pub(crate) colon2_token: Option, + pub(crate) lt_token: Token![<], + pub(crate) ty: Type, + pub(crate) comma_token: Option, + pub(crate) gt_token: Token![>], +} + +impl PhantomConstGetBound { + pub(crate) fn parse_path_with_arguments(path: Path) -> syn::Result> { + match known_items::PhantomConstGet::parse_path_with_arguments(path) { + Ok((phantom_const_get, arguments)) => { + Self::parse_path_and_arguments(phantom_const_get, arguments).map(Ok) + } + Err(path) => Ok(Err(path)), + } + } + pub(crate) fn parse_path_and_arguments( + phantom_const_get: known_items::PhantomConstGet, + arguments: PathArguments, + ) -> syn::Result { + let error = |arguments: PathArguments, message: &str| { + let mut path = phantom_const_get.path.clone(); + path.segments.last_mut().expect("known to exist").arguments = arguments; + syn::Error::new_spanned(path, message) + }; + match arguments { + PathArguments::None => Err(error(arguments, "missing generics for PhantomConstGet")), + PathArguments::AngleBracketed(AngleBracketedGenericArguments { + colon2_token, + lt_token, + args, + gt_token, + }) => { + let error = |args: Punctuated, message| { + error( + PathArguments::AngleBracketed(AngleBracketedGenericArguments { + colon2_token, + lt_token, + args, + gt_token, + }), + message, + ) + }; + let mut args = args.into_pairs().peekable(); + let Some((generic_argument, comma_token)) = args.next().map(Pair::into_tuple) + else { + return Err(error( + Default::default(), + "PhantomConstGet takes a type argument but no generic arguments were supplied", + )); + }; + if args.peek().is_some() { + return Err(error( + [Pair::new(generic_argument, comma_token)] + .into_iter() + .chain(args) + .collect(), + "PhantomConstGet takes a single type argument but too many generic arguments were supplied", + )); + }; + let GenericArgument::Type(ty) = generic_argument else { + return Err(error( + Punctuated::from_iter([Pair::new(generic_argument, comma_token)]), + "PhantomConstGet requires a type argument", + )); + }; + Ok(Self { + phantom_const_get, + colon2_token, + lt_token, + ty, + comma_token, + gt_token, + }) + } + PathArguments::Parenthesized(_) => Err(error( + arguments, + "parenthetical generics are not valid for PhantomConstGet", + )), + } + } + pub(crate) fn parse_type_param_bound( + bound: TypeParamBound, + ) -> syn::Result> { + let TypeParamBound::Trait(TraitBound { + paren_token: None, + modifier: syn::TraitBoundModifier::None, + lifetimes: None, + path, + }) = bound + else { + return Ok(Err(bound)); + }; + Ok(match Self::parse_path_with_arguments(path)? { + Ok(v) => Ok(v), + Err(path) => Err(TypeParamBound::Trait(TraitBound { + paren_token: None, + modifier: syn::TraitBoundModifier::None, + lifetimes: None, + path, + })), + }) + } +} + +impl ToTokens for PhantomConstGetBound { + fn to_tokens(&self, tokens: &mut TokenStream) { + let Self { + phantom_const_get, + colon2_token, + lt_token, + ty, + comma_token, + gt_token, + } = self; + phantom_const_get.to_tokens(tokens); + colon2_token.to_tokens(tokens); + lt_token.to_tokens(tokens); + ty.to_tokens(tokens); + comma_token.to_tokens(tokens); + gt_token.to_tokens(tokens); + } +} + +impl From for Path { + fn from(value: PhantomConstGetBound) -> Self { + let PhantomConstGetBound { + phantom_const_get, + colon2_token, + lt_token, + ty, + comma_token, + gt_token, + } = value; + let mut path = phantom_const_get.path; + path.segments.last_mut().expect("known to exist").arguments = + PathArguments::AngleBracketed(AngleBracketedGenericArguments { + colon2_token, + lt_token, + args: FromIterator::from_iter([Pair::new(GenericArgument::Type(ty), comma_token)]), + gt_token, + }); + path + } +} + +impl From for TraitBound { + fn from(value: PhantomConstGetBound) -> Self { + let path = Path::from(value); + TraitBound { + paren_token: None, + modifier: syn::TraitBoundModifier::None, + lifetimes: None, + path, + } + } +} + +impl From for TypeParamBound { + fn from(value: PhantomConstGetBound) -> Self { + TraitBound::from(value).into() + } +} + macro_rules! impl_bounds { ( #[struct = $struct_type:ident] @@ -2072,6 +2240,10 @@ macro_rules! impl_bounds { $( $Variant:ident, )* + $( + #[has_body] + $VariantHasBody:ident($variant_has_body_ty:ty), + )* $( #[unknown] $Unknown:ident, @@ -2081,6 +2253,7 @@ macro_rules! impl_bounds { #[derive(Clone, Debug)] $vis enum $enum_type { $($Variant(known_items::$Variant),)* + $($VariantHasBody($variant_has_body_ty),)* $($Unknown(syn::TypeParamBound),)? } @@ -2090,31 +2263,42 @@ macro_rules! impl_bounds { } })* + $(impl From<$variant_has_body_ty> for $enum_type { + fn from(v: $variant_has_body_ty) -> Self { + Self::$VariantHasBody(v) + } + })* + impl ToTokens for $enum_type { fn to_tokens(&self, tokens: &mut TokenStream) { match self { $(Self::$Variant(v) => v.to_tokens(tokens),)* + $(Self::$VariantHasBody(v) => v.to_tokens(tokens),)* $(Self::$Unknown(v) => v.to_tokens(tokens),)? } } } impl $enum_type { - $vis fn parse_path(path: Path) -> Result { + $vis fn parse_path_with_arguments(path: Path) -> syn::Result> { #![allow(unreachable_code)] $(let path = match known_items::$Variant::parse_path(path) { - Ok(v) => return Ok(Self::$Variant(v)), + Ok(v) => return Ok(Ok(Self::$Variant(v))), Err(path) => path, };)* - $(return Ok(Self::$Unknown(syn::TraitBound { + $(let path = match <$variant_has_body_ty>::parse_path_with_arguments(path)? { + Ok(v) => return Ok(Ok(Self::$VariantHasBody(v))), + Err(path) => path, + };)* + $(return Ok(Ok(Self::$Unknown(syn::TraitBound { paren_token: None, modifier: syn::TraitBoundModifier::None, lifetimes: None, path, - }.into()));)? - Err(path) + }.into())));)? + Ok(Err(path)) } - $vis fn parse_type_param_bound(mut type_param_bound: syn::TypeParamBound) -> Result { + $vis fn parse_type_param_bound(mut type_param_bound: syn::TypeParamBound) -> syn::Result> { #![allow(unreachable_code)] if let syn::TypeParamBound::Trait(mut trait_bound) = type_param_bound { if let syn::TraitBound { @@ -2123,24 +2307,24 @@ macro_rules! impl_bounds { lifetimes: None, path: _, } = trait_bound { - match Self::parse_path(trait_bound.path) { - Ok(retval) => return Ok(retval), + match Self::parse_path_with_arguments(trait_bound.path)? { + Ok(retval) => return Ok(Ok(retval)), Err(path) => trait_bound.path = path, } } type_param_bound = trait_bound.into(); } - $(return Ok(Self::$Unknown(type_param_bound));)? - Err(type_param_bound) + $(return Ok(Ok(Self::$Unknown(type_param_bound)));)? + Ok(Err(type_param_bound)) } } impl Parse for $enum_type { fn parse(input: ParseStream) -> syn::Result { - Self::parse_type_param_bound(input.parse()?) + Self::parse_type_param_bound(input.parse()?)? .map_err(|type_param_bound| syn::Error::new_spanned( type_param_bound, - format_args!("expected one of: {}", [$(stringify!($Variant)),*].join(", ")), + format_args!("expected one of: {}", [$(stringify!($Variant),)* $(stringify!($VariantHasBody)),*].join(", ")), )) } } @@ -2149,6 +2333,7 @@ macro_rules! impl_bounds { #[allow(non_snake_case)] $vis struct $struct_type { $($vis $Variant: Option,)* + $($vis $VariantHasBody: Option<$variant_has_body_ty>,)* $($vis $Unknown: Vec,)? } @@ -2161,6 +2346,11 @@ macro_rules! impl_bounds { separator = Some(::default()); v.to_tokens(tokens); })* + $(if let Some(v) = &self.$VariantHasBody { + separator.to_tokens(tokens); + separator = Some(::default()); + v.to_tokens(tokens); + })* $(for v in &self.$Unknown { separator.to_tokens(tokens); separator = Some(::default()); @@ -2174,6 +2364,7 @@ macro_rules! impl_bounds { #[allow(non_snake_case)] $vis struct Iter { $($Variant: Option,)* + $($VariantHasBody: Option<$variant_has_body_ty>,)* $($Unknown: std::vec::IntoIter,)? } @@ -2184,6 +2375,7 @@ macro_rules! impl_bounds { fn into_iter(self) -> Self::IntoIter { Iter { $($Variant: self.$Variant,)* + $($VariantHasBody: self.$VariantHasBody,)* $($Unknown: self.$Unknown.into_iter(),)? } } @@ -2198,6 +2390,11 @@ macro_rules! impl_bounds { return Some($enum_type::$Variant(value)); } )* + $( + if let Some(value) = self.$VariantHasBody.take() { + return Some($enum_type::$VariantHasBody(value)); + } + )* $( if let Some(value) = self.$Unknown.next() { return Some($enum_type::$Unknown(value)); @@ -2213,6 +2410,11 @@ macro_rules! impl_bounds { init = f(init, $enum_type::$Variant(value)); } )* + $( + if let Some(value) = self.$VariantHasBody.take() { + init = f(init, $enum_type::$VariantHasBody(value)); + } + )* $( if let Some(value) = self.$Unknown.next() { init = f(init, $enum_type::$Unknown(value)); @@ -2229,6 +2431,9 @@ macro_rules! impl_bounds { $($enum_type::$Variant(v) => { self.$Variant = Some(v); })* + $($enum_type::$VariantHasBody(v) => { + self.$VariantHasBody = Some(v); + })* $($enum_type::$Unknown(v) => { self.$Unknown.push(v); })? @@ -2250,6 +2455,9 @@ macro_rules! impl_bounds { $(if let Some(v) = v.$Variant { self.$Variant = Some(v); })* + $(if let Some(v) = v.$VariantHasBody { + self.$VariantHasBody = Some(v); + })* $(self.$Unknown.extend(v.$Unknown);)* }); } @@ -2304,6 +2512,8 @@ impl_bounds! { Size, StaticType, Type, + #[has_body] + PhantomConstGet(PhantomConstGetBound), #[unknown] Unknown, } @@ -2319,6 +2529,8 @@ impl_bounds! { ResetType, StaticType, Type, + #[has_body] + PhantomConstGet(PhantomConstGetBound), #[unknown] Unknown, } @@ -2334,6 +2546,7 @@ impl From for ParsedBound { ParsedTypeBound::ResetType(v) => ParsedBound::ResetType(v), ParsedTypeBound::StaticType(v) => ParsedBound::StaticType(v), ParsedTypeBound::Type(v) => ParsedBound::Type(v), + ParsedTypeBound::PhantomConstGet(v) => ParsedBound::PhantomConstGet(v), ParsedTypeBound::Unknown(v) => ParsedBound::Unknown(v), } } @@ -2349,6 +2562,7 @@ impl From for ParsedBounds { ResetType, StaticType, Type, + PhantomConstGet, Unknown, } = value; Self { @@ -2361,6 +2575,7 @@ impl From for ParsedBounds { Size: None, StaticType, Type, + PhantomConstGet, Unknown, } } @@ -2397,6 +2612,10 @@ impl ParsedTypeBound { ParsedTypeBound::Type(known_items::Type(span)), ]), Self::Type(v) => ParsedTypeBounds::from_iter([ParsedTypeBound::from(v)]), + Self::PhantomConstGet(v) => ParsedTypeBounds::from_iter([ + ParsedTypeBound::from(v), + ParsedTypeBound::Type(known_items::Type(span)), + ]), Self::Unknown(v) => ParsedTypeBounds::from_iter([ParsedTypeBound::Unknown(v)]), } } @@ -2432,6 +2651,7 @@ impl From for ParsedBounds { Size, StaticType: None, Type: None, + PhantomConstGet: None, Unknown: vec![], } } @@ -2534,6 +2754,9 @@ impl ParsedBound { Self::Size(v) => ParsedBoundCategory::SizeType(ParsedSizeTypeBound::Size(v)), Self::StaticType(v) => ParsedBoundCategory::Type(ParsedTypeBound::StaticType(v)), Self::Type(v) => ParsedBoundCategory::Type(ParsedTypeBound::Type(v)), + Self::PhantomConstGet(v) => { + ParsedBoundCategory::Type(ParsedTypeBound::PhantomConstGet(v)) + } Self::Unknown(v) => ParsedBoundCategory::Unknown(v), } } @@ -3419,7 +3642,8 @@ impl ParsedGenerics { | ParsedTypeBound::BundleType(_) | ParsedTypeBound::EnumType(_) | ParsedTypeBound::IntType(_) - | ParsedTypeBound::ResetType(_) => { + | ParsedTypeBound::ResetType(_) + | ParsedTypeBound::PhantomConstGet(_) => { errors.error(bound, "bounds on mask types are not implemented"); } ParsedTypeBound::StaticType(bound) => { diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs index 98849a67..96ee1f71 100644 --- a/crates/fayalite/src/lib.rs +++ b/crates/fayalite/src/lib.rs @@ -166,7 +166,7 @@ pub use fayalite_proc_macros::hdl_module; /// // you can then use it in other types: /// /// #[hdl(no_static)] -/// pub struct WrapMyArray> { +/// pub struct WrapMyArray> { /// pub my_array: GetMyArray

, /// } /// @@ -202,7 +202,7 @@ pub use fayalite_proc_macros::hdl_module; /// // you can then use it in other types: /// /// #[hdl(no_static)] -/// pub struct FlagPerItem> { +/// pub struct FlagPerItem> { /// pub flags: ArrayType>, /// } /// diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs index 8742bb0b..148cb642 100644 --- a/crates/fayalite/tests/hdl_types.rs +++ b/crates/fayalite/tests/hdl_types.rs @@ -210,7 +210,7 @@ pub type GetA> = DynSize; pub type GetB> = UInt; #[hdl(outline_generated, no_static)] -pub struct MyTypeWithPhantomConstParameter> { +pub struct MyTypeWithPhantomConstParameter> { pub a: ArrayType>, pub b: HdlOption>, } From 0be9f9ce2329fd455a40f87e70c51a3ab672cc40 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 27 Oct 2025 22:57:12 -0700 Subject: [PATCH 02/10] fix JobGraph::run to not busy-wait --- crates/fayalite/src/build/graph.rs | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/crates/fayalite/src/build/graph.rs b/crates/fayalite/src/build/graph.rs index d81b282f..bed88295 100644 --- a/crates/fayalite/src/build/graph.rs +++ b/crates/fayalite/src/build/graph.rs @@ -703,8 +703,12 @@ impl JobGraph { } let mut running_jobs = HashMap::default(); let (finished_jobs_sender, finished_jobs_receiver) = mpsc::channel(); + let mut next_finished_job = None; loop { - while let Some(finished_job) = finished_jobs_receiver.try_recv().ok() { + if let Some(finished_job) = next_finished_job + .take() + .or_else(|| finished_jobs_receiver.try_recv().ok()) + { let Some(RunningJob { job, thread }) = running_jobs.remove(&finished_job) else { unreachable!(); @@ -736,6 +740,7 @@ impl JobGraph { } } } + continue; } if let Some(WaitingJobState { job_node_id, @@ -791,12 +796,15 @@ impl JobGraph { .expect("failed to spawn thread for job"), }, ); + continue; } if running_jobs.is_empty() { assert!(item_name_to_waiting_jobs_map.is_empty()); assert!(ready_jobs.is_empty()); return Ok(()); } + // nothing to do yet, block to avoid busy waiting + next_finished_job = finished_jobs_receiver.recv().ok(); } }) } From c11a1743f97b5219725d123d876effe717b633f2 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 30 Oct 2025 21:14:05 -0700 Subject: [PATCH 03/10] add sim.fork_join() and fix Simulator to handle running futures with arbitrary wakers --- crates/fayalite/src/sim.rs | 1245 +++++++++----- crates/fayalite/tests/sim.rs | 82 + .../fayalite/tests/sim/expected/array_rw.txt | 8 +- .../expected/conditional_assignment_last.txt | 8 +- .../tests/sim/expected/connect_const.txt | 8 +- .../sim/expected/connect_const_reset.txt | 8 +- .../tests/sim/expected/counter_async.txt | 12 +- .../tests/sim/expected/counter_async.vcd | 64 +- .../tests/sim/expected/counter_sync.txt | 12 +- .../tests/sim/expected/counter_sync.vcd | 66 +- .../tests/sim/expected/duplicate_names.txt | 8 +- crates/fayalite/tests/sim/expected/enums.txt | 10 +- .../tests/sim/expected/extern_module.txt | 15 +- .../tests/sim/expected/extern_module.vcd | 3 +- .../tests/sim/expected/extern_module2.txt | 155 +- .../tests/sim/expected/extern_module2.vcd | 3 +- .../tests/sim/expected/many_memories.txt | 8 +- .../tests/sim/expected/many_memories.vcd | 48 +- .../fayalite/tests/sim/expected/memories.txt | 8 +- .../fayalite/tests/sim/expected/memories.vcd | 14 +- .../fayalite/tests/sim/expected/memories2.txt | 8 +- .../fayalite/tests/sim/expected/memories2.vcd | 12 +- .../fayalite/tests/sim/expected/memories3.txt | 8 +- .../fayalite/tests/sim/expected/memories3.vcd | 120 +- crates/fayalite/tests/sim/expected/mod1.txt | 8 +- .../tests/sim/expected/ripple_counter.txt | 445 +++-- .../tests/sim/expected/ripple_counter.vcd | 624 ++++--- .../tests/sim/expected/shift_register.txt | 10 +- .../tests/sim/expected/shift_register.vcd | 12 +- .../tests/sim/expected/sim_fork_join.txt | 523 ++++++ .../tests/sim/expected/sim_fork_join.vcd | 1467 +++++++++++++++++ .../tests/sim/expected/sim_only_connects.txt | 300 ++-- .../tests/sim/expected/sim_only_connects.vcd | 17 +- 33 files changed, 4083 insertions(+), 1256 deletions(-) create mode 100644 crates/fayalite/tests/sim/expected/sim_fork_join.txt create mode 100644 crates/fayalite/tests/sim/expected/sim_fork_join.vcd diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 44030c14..35da3367 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -48,7 +48,7 @@ use num_traits::{Signed, Zero}; use std::{ any::Any, borrow::Cow, - cell::RefCell, + cell::{Cell, RefCell}, collections::BTreeMap, fmt, future::{Future, IntoFuture}, @@ -57,8 +57,9 @@ use std::{ pin::Pin, ptr, rc::Rc, - sync::Arc, + sync::{Arc, Mutex}, task::Poll, + usize, }; pub mod compiler; @@ -1262,149 +1263,11 @@ impl SimulationModuleState { } } -#[derive(Copy, Clone, Debug)] -enum WaitTarget { - Settle, - Instant(SimInstant), - Change { key: ChangeKey, value: ChangeValue }, -} - -#[derive(Clone)] -struct EarliestWaitTargets { - settle: bool, - instant: Option, - changes: HashMap, SimValue>, -} - -impl fmt::Debug for EarliestWaitTargets { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.debug_set().entries(self.iter()).finish() - } -} - -impl Default for EarliestWaitTargets { - fn default() -> Self { - Self { - settle: false, - instant: None, - changes: HashMap::default(), - } - } -} - -impl EarliestWaitTargets { - fn settle() -> Self { - Self { - settle: true, - instant: None, - changes: HashMap::default(), - } - } - fn instant(instant: SimInstant) -> Self { - Self { - settle: false, - instant: Some(instant), - changes: HashMap::default(), - } - } - fn len(&self) -> usize { - self.settle as usize + self.instant.is_some() as usize + self.changes.len() - } - fn is_empty(&self) -> bool { - self.len() == 0 - } - fn clear(&mut self) { - let Self { - settle, - instant, - changes, - } = self; - *settle = false; - *instant = None; - changes.clear(); - } - fn insert( - &mut self, - value: impl std::borrow::Borrow, ChangeValue>>, - ) where - ChangeValue: std::borrow::Borrow>, - { - let value = value.borrow(); - match value { - WaitTarget::Settle => self.settle = true, - WaitTarget::Instant(instant) => { - if self.instant.is_none_or(|v| v > *instant) { - self.instant = Some(*instant); - } - } - WaitTarget::Change { key, value } => { - self.changes - .entry(*key) - .or_insert_with(|| value.borrow().clone()); - } - } - } - fn convert_earlier_instants_to_settle(&mut self, instant: SimInstant) { - if self.instant.is_some_and(|v| v <= instant) { - self.settle = true; - self.instant = None; - } - } - fn iter<'a>( - &'a self, - ) -> impl Clone - + Iterator, &'a SimValue>> - + 'a { - self.settle - .then_some(WaitTarget::Settle) - .into_iter() - .chain(self.instant.map(|instant| WaitTarget::Instant(instant))) - .chain( - self.changes - .iter() - .map(|(&key, value)| WaitTarget::Change { key, value }), - ) - } -} - -impl>> - Extend, ChangeValue>> for EarliestWaitTargets -{ - fn extend, ChangeValue>>>( - &mut self, - iter: T, - ) { - iter.into_iter().for_each(|v| self.insert(v)) - } -} - -impl<'a, ChangeValue: std::borrow::Borrow>> - Extend<&'a WaitTarget, ChangeValue>> for EarliestWaitTargets -{ - fn extend, ChangeValue>>>( - &mut self, - iter: T, - ) { - iter.into_iter().for_each(|v| self.insert(v)) - } -} - -impl FromIterator for EarliestWaitTargets -where - Self: Extend, -{ - fn from_iter>(iter: T) -> Self { - let mut retval = Self::default(); - retval.extend(iter); - retval - } -} - struct SimulationExternModuleState { module_state: SimulationModuleState, sim: ExternModuleSimulation, running_generator: Option + 'static>>>, - wait_targets: EarliestWaitTargets, + waker: Arc, } impl fmt::Debug for SimulationExternModuleState { @@ -1413,7 +1276,7 @@ impl fmt::Debug for SimulationExternModuleState { module_state, sim, running_generator, - wait_targets, + waker: _, } = self; f.debug_struct("SimulationExternModuleState") .field("module_state", module_state) @@ -1422,7 +1285,6 @@ impl fmt::Debug for SimulationExternModuleState { "running_generator", &running_generator.as_ref().map(|_| DebugAsDisplay("...")), ) - .field("wait_targets", wait_targets) .finish() } } @@ -1489,28 +1351,255 @@ impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadFn { } } -struct GeneratorWaker; +#[derive(Copy, Clone, PartialEq, Eq, Debug)] +enum EventKind { + State, + ExternModule(usize), +} -impl std::task::Wake for GeneratorWaker { - fn wake(self: Arc) { - panic!("can't await other kinds of futures in function passed to ExternalModuleSimulation"); +impl PartialOrd for EventKind { + fn partial_cmp(&self, other: &Self) -> Option { + Some(self.cmp(other)) } } -#[derive(Default)] -struct ReadyToRunSet { - state_ready_to_run: bool, - extern_modules_ready_to_run: Vec, +impl Ord for EventKind { + fn cmp(&self, other: &Self) -> std::cmp::Ordering { + match (self, other) { + (Self::State, Self::State) => std::cmp::Ordering::Equal, + (Self::State, Self::ExternModule(_)) => std::cmp::Ordering::Less, + (Self::ExternModule(_), Self::State) => std::cmp::Ordering::Greater, + (Self::ExternModule(this), Self::ExternModule(other)) => this.cmp(other), + } + } } -impl ReadyToRunSet { - fn clear(&mut self) { +#[derive(Copy, Clone, PartialEq, Eq, Debug)] +struct Event { + instant: SimInstant, + kind: EventKind, +} + +impl PartialOrd for Event { + fn partial_cmp(&self, other: &Self) -> Option { + Some(self.cmp(other)) + } +} + +impl Ord for Event { + fn cmp(&self, other: &Self) -> std::cmp::Ordering { + let Self { instant, kind } = other; + self.instant.cmp(instant).then(self.kind.cmp(kind)) + } +} + +struct HashableWaker(std::task::Waker); + +impl Clone for HashableWaker { + fn clone(&self) -> Self { + Self(self.0.clone()) + } + + fn clone_from(&mut self, source: &Self) { + self.0.clone_from(&source.0); + } +} + +impl PartialEq for HashableWaker { + fn eq(&self, other: &Self) -> bool { + self.0.will_wake(&other.0) + } +} + +impl Eq for HashableWaker {} + +impl Hash for HashableWaker { + fn hash(&self, state: &mut H) { + self.0.data().hash(state); + let vtable: *const std::task::RawWakerVTable = self.0.vtable(); + vtable.hash(state); + } +} + +struct EventQueueData { + instant: SimInstant, + events: BTreeMap>, +} + +impl fmt::Debug for EventQueueData { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + struct EventsDebug<'a>(&'a BTreeMap>); + impl fmt::Debug for EventsDebug<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let mut debug_map = f.debug_map(); + for (k, v) in self.0 { + debug_map.entry(&format_args!("{k:?}"), &v.len()); + } + debug_map.finish() + } + } + let Self { instant, events } = self; + f.debug_struct("EventQueueData") + .field("instant", instant) + .field("events", &EventsDebug(events)) + .finish() + } +} + +struct EventQueueFirstEntry<'a>( + std::collections::btree_map::OccupiedEntry<'a, Event, HashSet>, +); + +impl<'a> EventQueueFirstEntry<'a> { + fn key(&self) -> &Event { + self.0.key() + } + fn remove(self) -> HashSet { + self.0.remove() + } +} + +impl EventQueueData { + fn new(instant: SimInstant) -> Self { + Self { + instant, + events: BTreeMap::new(), + } + } + fn instant(&self) -> SimInstant { + self.instant + } + fn set_instant(&mut self, instant: SimInstant) { + self.instant = instant; + } + fn add_event(&mut self, mut event: Event, waker: Option) { + event.instant = event.instant.max(self.instant); + self.events + .entry(event) + .or_default() + .extend(waker.map(HashableWaker)); + } + fn add_event_for_now(&mut self, kind: EventKind, waker: Option) { + self.add_event( + Event { + instant: self.instant, + kind, + }, + waker, + ); + } + fn first_entry(&mut self) -> Option> { + self.events.first_entry().map(EventQueueFirstEntry) + } + fn peek_first_event(&self) -> Option { + Some(*self.events.first_key_value()?.0) + } + fn peek_first_event_for_now(&self) -> Option { + self.peek_first_event() + .filter(|event| event.instant <= self.instant) + } +} + +struct EventQueue(Mutex); + +impl fmt::Debug for EventQueue { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.write_str("EventQueue(")?; + if let Ok(data) = self.0.try_lock() { + (*data).fmt(f)?; + } else { + f.write_str("")?; + } + f.write_str(")") + } +} + +impl EventQueue { + fn new(data: EventQueueData) -> Self { + Self(Mutex::new(data)) + } + fn lock(&self) -> std::sync::MutexGuard<'_, EventQueueData> { + self.0.lock().expect("not poisoned") + } + fn add_event_for_now(&self, kind: EventKind, waker: Option) { + self.lock().add_event_for_now(kind, waker); + } + fn peek_first_event_for_now(&self) -> Option { + self.lock().peek_first_event_for_now() + } +} + +struct ExternModuleGeneratorWaker { + event_queue: std::sync::Weak, + module_index: usize, +} + +impl std::task::Wake for ExternModuleGeneratorWaker { + fn wake(self: Arc) { + self.wake_by_ref(); + } + fn wake_by_ref(self: &Arc) { + if let Some(event_queue) = self.event_queue.upgrade() { + event_queue.add_event_for_now(EventKind::ExternModule(self.module_index), None); + } + } +} + +struct SensitivitySet { + debug_id: u64, + compiled_values: HashSet>>, + values: Vec<( + Rc>, + Rc>, + )>, + waker: RefCell, + changed: Cell, +} + +struct SensitivitySetJustId<'a>(&'a SensitivitySet); + +impl fmt::Debug for SensitivitySetJustId<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + self.0.debug_fmt(true, f) + } +} + +impl fmt::Debug for SensitivitySet { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + self.debug_fmt(false, f) + } +} + +impl SensitivitySet { + fn debug_fmt(&self, just_id: bool, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { - state_ready_to_run, - extern_modules_ready_to_run, + debug_id, + compiled_values: _, + values, + waker: _, + changed, } = self; - *state_ready_to_run = false; - extern_modules_ready_to_run.clear(); + struct DebugValues<'a>( + &'a [( + Rc>, + Rc>, + )], + ); + impl<'a> fmt::Debug for DebugValues<'a> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_map() + .entries(self.0.iter().map(|(k, v)| (k, v))) + .finish() + } + } + let mut debug_struct = f.debug_struct("SensitivitySet"); + debug_struct.field("id", debug_id); + if !just_id { + debug_struct + .field("values", &DebugValues(values)) + .field("changed", changed); + } + debug_struct.finish_non_exhaustive() } } @@ -1519,15 +1608,22 @@ struct SimulationImpl { io: Expr, main_module: SimulationModuleState, extern_modules: Box<[SimulationExternModuleState]>, - state_ready_to_run: bool, trace_decls: TraceModule, traces: SimTraces]>>, trace_memories: BTreeMap, TraceMem>, trace_writers: Vec>, - instant: SimInstant, clocks_triggered: Interned<[StatePartIndex]>, breakpoints: Option, - generator_waker: std::task::Waker, + event_queue: Arc, + next_sensitivity_set_debug_id: u64, + waiting_sensitivity_sets_by_compiled_value: HashMap< + Rc>, + ( + Rc>, + HashMap<*const SensitivitySet, Rc>, + ), + >, + waiting_sensitivity_sets_by_address: HashMap<*const SensitivitySet, Rc>, } impl fmt::Debug for SimulationImpl { @@ -1536,6 +1632,70 @@ impl fmt::Debug for SimulationImpl { } } +struct DebugSensitivitySetsByAddress<'a> { + sensitivity_sets: &'a HashMap<*const SensitivitySet, Rc>, + just_id: bool, +} + +impl<'a> fmt::Debug for DebugSensitivitySetsByAddress<'a> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + sensitivity_sets, + just_id, + } = *self; + let mut values: Vec<_> = sensitivity_sets.values().collect(); + values.sort_by_key(|v| v.debug_id); + if just_id { + f.debug_set() + .entries( + values + .iter() + .map(|sensitivity_set| SensitivitySetJustId(sensitivity_set)), + ) + .finish() + } else { + f.debug_set().entries(values).finish() + } + } +} + +struct DebugSensitivitySetsByCompiledValue<'a>( + &'a HashMap< + Rc>, + ( + Rc>, + HashMap<*const SensitivitySet, Rc>, + ), + >, +); + +impl<'a> fmt::Debug for DebugSensitivitySetsByCompiledValue<'a> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let mut values: Vec<_> = self + .0 + .iter() + .map(|(compiled_value, (sim_value, sensitivity_sets))| { + ( + DebugAsDisplay(if f.alternate() { + format!("{compiled_value:#?}") + } else { + format!("{compiled_value:?}") + }), + ( + sim_value, + DebugSensitivitySetsByAddress { + sensitivity_sets, + just_id: true, + }, + ), + ) + }) + .collect(); + values.sort_by(|l, r| l.0.0.cmp(&r.0.0)); + f.debug_map().entries(values).finish() + } +} + impl SimulationImpl { fn debug_fmt(&self, io: Option<&dyn fmt::Debug>, f: &mut fmt::Formatter<'_>) -> fmt::Result { let Self { @@ -1543,38 +1703,58 @@ impl SimulationImpl { io: self_io, main_module, extern_modules, - state_ready_to_run, trace_decls, traces, trace_memories, trace_writers, - instant, clocks_triggered, breakpoints: _, - generator_waker: _, + event_queue, + next_sensitivity_set_debug_id: _, + waiting_sensitivity_sets_by_compiled_value, + waiting_sensitivity_sets_by_address, } = self; f.debug_struct("Simulation") .field("state", state) .field("io", io.unwrap_or(self_io)) .field("main_module", main_module) .field("extern_modules", extern_modules) - .field("state_ready_to_run", state_ready_to_run) .field("trace_decls", trace_decls) .field("traces", traces) .field("trace_memories", trace_memories) .field("trace_writers", trace_writers) - .field("instant", instant) .field("clocks_triggered", clocks_triggered) + .field("event_queue", event_queue) + .field( + "waiting_sensitivity_sets_by_address", + &DebugSensitivitySetsByAddress { + sensitivity_sets: waiting_sensitivity_sets_by_address, + just_id: false, + }, + ) + .field( + "waiting_sensitivity_sets_by_compiled_value", + &DebugSensitivitySetsByCompiledValue(waiting_sensitivity_sets_by_compiled_value), + ) .finish_non_exhaustive() } fn new(compiled: Compiled) -> Self { let io_target = Target::from(compiled.io); - let extern_modules = Box::from_iter(compiled.extern_modules.iter().map( - |&CompiledExternModule { - module_io_targets, - module_io, - simulation, - }| { + let mut event_queue = EventQueueData::new(SimInstant::START); + event_queue.add_event_for_now(EventKind::State, None); + for module_index in 0..compiled.extern_modules.len() { + event_queue.add_event_for_now(EventKind::ExternModule(module_index), None); + } + let event_queue = Arc::new(EventQueue::new(event_queue)); + let extern_modules = Box::from_iter(compiled.extern_modules.iter().enumerate().map( + |( + module_index, + &CompiledExternModule { + module_io_targets, + module_io, + simulation, + }, + )| { SimulationExternModuleState { module_state: SimulationModuleState::new( module_io_targets @@ -1584,7 +1764,10 @@ impl SimulationImpl { ), sim: simulation, running_generator: None, - wait_targets: EarliestWaitTargets::settle(), + waker: Arc::new(ExternModuleGeneratorWaker { + event_queue: Arc::downgrade(&event_queue), + module_index, + }), } }, )); @@ -1609,7 +1792,6 @@ impl SimulationImpl { }), ), extern_modules, - state_ready_to_run: true, trace_decls: compiled.base_module.trace_decls, traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map( |&SimTrace { @@ -1624,10 +1806,12 @@ impl SimulationImpl { ))), trace_memories: BTreeMap::from_iter(compiled.trace_memories.iter().copied()), trace_writers: vec![], - instant: SimInstant::START, clocks_triggered: compiled.clocks_triggered, breakpoints: None, - generator_waker: Arc::new(GeneratorWaker).into(), + event_queue, + next_sensitivity_set_debug_id: 0, + waiting_sensitivity_sets_by_compiled_value: HashMap::default(), + waiting_sensitivity_sets_by_address: HashMap::default(), } } fn write_traces( @@ -1782,137 +1966,170 @@ impl SimulationImpl { } #[track_caller] fn advance_time(this_ref: &Rc>, duration: SimDuration) { - let run_target = this_ref.borrow().instant + duration; - Self::run_until(this_ref, run_target); + Self::run_until(this_ref, &mut |instant| instant.checked_add(duration)); } - /// clears `targets` - #[must_use] - fn yield_wait<'a>( - this: Rc>, - module_index: usize, - targets: &'a mut EarliestWaitTargets, - ) -> impl Future + 'a { - struct MyGenerator<'a> { - sim: Rc>, - yielded_at_all: bool, - module_index: usize, - targets: &'a mut EarliestWaitTargets, + fn wake_after_change(&mut self, sensitivity_set: Rc) { + let None = self + .waiting_sensitivity_sets_by_address + .insert(Rc::as_ptr(&sensitivity_set), sensitivity_set.clone()) + else { + // already added + return; + }; + let SensitivitySet { + debug_id: _, + compiled_values: _, + values, + waker: _, + changed: _, + } = &*sensitivity_set; + for (compiled_value, sim_value) in values { + self.waiting_sensitivity_sets_by_compiled_value + .entry(compiled_value.clone()) + .or_insert_with(|| (sim_value.clone(), HashMap::default())) + .1 + .insert(Rc::as_ptr(&sensitivity_set), sensitivity_set.clone()); } - impl Future for MyGenerator<'_> { - type Output = (); - - fn poll( - mut self: Pin<&mut Self>, - cx: &mut std::task::Context<'_>, - ) -> Poll { - let this = &mut *self; - let mut sim = this.sim.borrow_mut(); - let sim = &mut *sim; - assert!( - cx.waker().will_wake(&sim.generator_waker), - "can't use ExternModuleSimulationState's methods outside of ExternModuleSimulation" - ); - this.targets.convert_earlier_instants_to_settle(sim.instant); - if this.targets.is_empty() { - this.targets.settle = true; + } + fn cancel_wake_after_change(&mut self, sensitivity_set: &Rc) { + let Some(_) = self + .waiting_sensitivity_sets_by_address + .remove(&Rc::as_ptr(&sensitivity_set)) + else { + return; + }; + let SensitivitySet { + debug_id: _, + compiled_values: _, + values, + waker: _, + changed: _, + } = &**sensitivity_set; + for (compiled_value, _) in values { + if let hashbrown::hash_map::Entry::Occupied(mut entry) = self + .waiting_sensitivity_sets_by_compiled_value + .entry(compiled_value.clone()) + { + entry.get_mut().1.remove(&Rc::as_ptr(&sensitivity_set)); + if entry.get().1.is_empty() { + entry.remove(); } - if this.targets.settle { - if this.yielded_at_all { - this.targets.clear(); - return Poll::Ready(()); - } - } - sim.extern_modules[this.module_index] - .wait_targets - .extend(this.targets.iter()); - this.targets.clear(); - this.yielded_at_all = true; - Poll::Pending } } - MyGenerator { - sim: this, - yielded_at_all: false, - module_index, - targets, - } + } + fn try_wake_at_instant( + &mut self, + module_index: usize, + instant: &mut dyn FnMut(SimInstant) -> Option, + waker: std::task::Waker, + ) -> Result<(), std::task::Waker> { + let mut event_queue = self.event_queue.lock(); + let Some(instant) = instant(event_queue.instant()) else { + return Err(waker); + }; + event_queue.add_event( + Event { + instant, + kind: EventKind::ExternModule(module_index), + }, + Some(waker), + ); + Ok(()) } async fn yield_advance_time_or_settle( - this: Rc>, + this: &RefCell, module_index: usize, duration: Option, ) { - let mut targets = duration.map_or(EarliestWaitTargets::settle(), |duration| { - EarliestWaitTargets::instant(this.borrow().instant + duration) - }); - Self::yield_wait(this, module_index, &mut targets).await; + let mut target_instant = None; + std::future::poll_fn(|cx| { + match this.borrow_mut().try_wake_at_instant( + module_index, + &mut |instant| match target_instant { + Some(target_instant) => { + // already waited at least once + if instant < target_instant { + Some(target_instant) + } else { + None + } + } + None => { + target_instant = instant.checked_add(duration.unwrap_or(SimDuration::ZERO)); + target_instant + } + }, + cx.waker().clone(), + ) { + Ok(()) => Poll::Pending, + Err(_waker) => { + if target_instant.is_none() { + // don't panic in try_wait_at_instant to avoid poisoning the lock + panic!("SimInstant overflow"); + } + Poll::Ready(()) + } + } + }) + .await } - fn is_extern_module_ready_to_run(&mut self, module_index: usize) -> Option { - let module = &self.extern_modules[module_index]; - let mut retval = None; - for wait_target in module.wait_targets.iter() { - retval = match (wait_target, retval) { - (WaitTarget::Settle, _) => Some(self.instant), - (WaitTarget::Instant(instant), _) if instant <= self.instant => Some(self.instant), - (WaitTarget::Instant(instant), None) => Some(instant), - (WaitTarget::Instant(instant), Some(retval)) => Some(instant.min(retval)), - (WaitTarget::Change { key, value }, retval) => { - if Self::value_changed(&mut self.state, key, SimValue::opaque(value)) { - Some(self.instant) - } else { - retval + async fn yield_wait_for_changes( + this: &RefCell, + module_index: usize, + sensitivity_set: SensitivitySet, + timeout: Option, + ) { + if let Some(timeout) = timeout { + if timeout == SimDuration::ZERO { + return Self::yield_advance_time_or_settle(this, module_index, None).await; + } + } + let sensitivity_set = Rc::new(sensitivity_set); + let mut timeout_instant = None; + std::future::poll_fn(|cx| { + if sensitivity_set.changed.get() { + return Poll::Ready(()); + } + sensitivity_set.waker.borrow_mut().clone_from(cx.waker()); + let mut this = this.borrow_mut(); + this.wake_after_change(sensitivity_set.clone()); + if let Some(timeout) = timeout { + match this.try_wake_at_instant( + module_index, + &mut |instant| match timeout_instant { + Some(timeout_instant) => { + if instant < timeout_instant { + Some(timeout_instant) + } else { + None + } + } + None => { + timeout_instant = instant.checked_add(timeout); + timeout_instant + } + }, + cx.waker().clone(), + ) { + Ok(()) => Poll::Pending, + Err(_waker) => { + if timeout_instant.is_none() { + // don't panic in try_wait_at_instant to avoid poisoning the lock + panic!("SimInstant overflow"); + } + Poll::Ready(()) } } - }; - if retval == Some(self.instant) { - break; - } - } - retval - } - fn get_ready_to_run_set(&mut self, ready_to_run_set: &mut ReadyToRunSet) -> Option { - ready_to_run_set.clear(); - let mut retval = None; - if self.state_ready_to_run { - ready_to_run_set.state_ready_to_run = true; - retval = Some(self.instant); - } - for module_index in 0..self.extern_modules.len() { - let Some(instant) = self.is_extern_module_ready_to_run(module_index) else { - continue; - }; - if let Some(retval) = &mut retval { - match instant.cmp(retval) { - std::cmp::Ordering::Less => ready_to_run_set.clear(), - std::cmp::Ordering::Equal => {} - std::cmp::Ordering::Greater => continue, - } } else { - retval = Some(instant); + Poll::Pending } - ready_to_run_set - .extern_modules_ready_to_run - .push(module_index); - } - retval - } - fn set_instant_no_sim(&mut self, instant: SimInstant) { - self.instant = instant; - self.for_each_trace_writer_storing_error(|this, mut trace_writer_state| { - match &mut trace_writer_state { - TraceWriterState::Decls(_) | TraceWriterState::Init(_) => unreachable!(), - TraceWriterState::Running(trace_writer) => { - trace_writer.change_time_to(this.instant)?; - } - TraceWriterState::Errored(_) => {} - } - Ok(trace_writer_state) - }); + }) + .await; + this.borrow_mut().cancel_wake_after_change(&sensitivity_set); } #[must_use] #[track_caller] - fn run_state_settle_cycle(&mut self) -> bool { - self.state_ready_to_run = false; + fn run_state_settle_cycle(&mut self) { self.state.setup_call(0); if self.breakpoints.is_some() { loop { @@ -1943,138 +2160,197 @@ impl SimulationImpl { .iter() .any(|i| self.state.small_slots[*i] != 0) { - self.state_ready_to_run = true; - true - } else { - false + self.event_queue.add_event_for_now(EventKind::State, None); } } #[track_caller] - fn run_extern_modules_cycle( + fn run_extern_module(this_ref: &Rc>, module_index: usize) { + let mut this = this_ref.borrow_mut(); + let extern_module = &mut this.extern_modules[module_index]; + let waker = std::task::Waker::from(extern_module.waker.clone()); + let mut generator = if !extern_module.module_state.did_initial_settle { + let sim = extern_module.sim; + drop(this); + Box::into_pin(sim.run(ExternModuleSimulationState { + sim_impl: this_ref.clone(), + module_index, + })) + } else if let Some(generator) = extern_module.running_generator.take() { + drop(this); + generator + } else { + return; + }; + let generator = match generator + .as_mut() + .poll(&mut std::task::Context::from_waker(&waker)) + { + Poll::Ready(()) => None, + Poll::Pending => Some(generator), + }; + this = this_ref.borrow_mut(); + this.extern_modules[module_index] + .module_state + .did_initial_settle = true; + if !this.extern_modules[module_index] + .module_state + .uninitialized_ios + .is_empty() + { + panic!( + "extern module didn't initialize all outputs before \ + waiting, settling, or reading any inputs: {}", + this.extern_modules[module_index].sim.source_location + ); + } + this.extern_modules[module_index].running_generator = generator; + } + fn check_waiting_sensitivity_sets(&mut self) { + if let Some(Event { + instant: _, + kind: EventKind::State, + }) = self.event_queue.peek_first_event_for_now() + { + return; + } + let mut triggered = HashMap::<*const SensitivitySet, Rc>::default(); + for (compiled_value, (sim_value, sensitivity_sets)) in + &self.waiting_sensitivity_sets_by_compiled_value + { + if Self::value_changed( + &mut self.state, + **compiled_value, + SimValue::opaque(sim_value), + ) { + triggered.extend(sensitivity_sets.iter().map(|(&k, v)| (k, v.clone()))); + } + } + for sensitivity_set in triggered.into_values() { + sensitivity_set.changed.set(true); + sensitivity_set.waker.borrow().wake_by_ref(); + self.cancel_wake_after_change(&sensitivity_set); + } + } + fn write_traces_after_event(&mut self) { + if let Some(Event { + instant: _, + kind: EventKind::State, + }) = self.event_queue.peek_first_event_for_now() + { + return; + } + if self.main_module.did_initial_settle { + self.read_traces::(); + } else { + self.read_traces::(); + } + self.state.memory_write_log.sort_unstable(); + self.state.memory_write_log.dedup(); + self.main_module.did_initial_settle = true; + self.for_each_trace_writer_storing_error(|this, trace_writer_state| { + Ok(match trace_writer_state { + TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running( + this.init_trace_writer(trace_writer_decls.write_decls( + this.trace_decls, + this.traces.0.len(), + this.trace_memories.len(), + )?)?, + ), + TraceWriterState::Init(trace_writer) => { + TraceWriterState::Running(this.init_trace_writer(trace_writer)?) + } + TraceWriterState::Running(trace_writer) => { + TraceWriterState::Running(this.update_trace_writer(trace_writer)?) + } + TraceWriterState::Errored(e) => TraceWriterState::Errored(e), + }) + }); + self.state.memory_write_log.clear(); + } + fn write_traces_change_time_to(&mut self, new_instant: SimInstant) { + self.for_each_trace_writer_storing_error(|_this, mut trace_writer_state| { + match &mut trace_writer_state { + TraceWriterState::Decls(_) | TraceWriterState::Init(_) => unreachable!(), + TraceWriterState::Running(trace_writer) => { + trace_writer.change_time_to(new_instant)?; + } + TraceWriterState::Errored(_) => {} + } + Ok(trace_writer_state) + }); + } + #[track_caller] + fn run_until( this_ref: &Rc>, - generator_waker: &std::task::Waker, - extern_modules_ready_to_run: &[usize], + run_target: &mut dyn FnMut(SimInstant) -> Option, ) { let mut this = this_ref.borrow_mut(); - for module_index in extern_modules_ready_to_run.iter().copied() { - let extern_module = &mut this.extern_modules[module_index]; - extern_module.wait_targets.clear(); - let mut generator = if !extern_module.module_state.did_initial_settle { - let sim = extern_module.sim; - drop(this); - Box::into_pin(sim.run(ExternModuleSimulationState { - sim_impl: this_ref.clone(), - module_index, - wait_for_changes_wait_targets: EarliestWaitTargets::default(), - })) - } else if let Some(generator) = extern_module.running_generator.take() { - drop(this); - generator - } else { - continue; - }; - let generator = match generator - .as_mut() - .poll(&mut std::task::Context::from_waker(generator_waker)) - { - Poll::Ready(()) => None, - Poll::Pending => Some(generator), - }; - this = this_ref.borrow_mut(); - this.extern_modules[module_index] - .module_state - .did_initial_settle = true; - if !this.extern_modules[module_index] - .module_state - .uninitialized_ios - .is_empty() - { - panic!( - "extern module didn't initialize all outputs before \ - waiting, settling, or reading any inputs: {}", - this.extern_modules[module_index].sim.source_location - ); - } - this.extern_modules[module_index].running_generator = generator; - } - } - /// clears `targets` - #[track_caller] - fn run_until(this_ref: &Rc>, run_target: SimInstant) { - let mut this = this_ref.borrow_mut(); - let mut ready_to_run_set = ReadyToRunSet::default(); - let generator_waker = this.generator_waker.clone(); assert!( this.main_module.uninitialized_ios.is_empty(), "didn't initialize all inputs", ); - let run_target = run_target.max(this.instant); + this.check_waiting_sensitivity_sets(); + let mut event_queue = this.event_queue.lock(); + let Some(run_target) = run_target(event_queue.instant()) else { + drop(event_queue); + panic!("SimInstant overflowed"); + }; + let run_target = run_target.max(event_queue.instant()); let mut settle_cycle = 0; - let mut run_extern_modules = true; loop { - assert!(settle_cycle < 100000, "settle(): took too many steps"); + if settle_cycle >= 100000 { + drop(event_queue); + panic!("settle(): took too many steps"); + } settle_cycle += 1; - let next_wait_target = match this.get_ready_to_run_set(&mut ready_to_run_set) { - Some(next_wait_target) if next_wait_target <= run_target => next_wait_target, - _ => break, + let event_queue_instant = event_queue.instant(); + let Some(first_entry) = event_queue.first_entry() else { + let changed_time = event_queue_instant != run_target; + event_queue.set_instant(run_target); + drop(event_queue); + if changed_time { + this.write_traces_change_time_to(run_target); + } + return; }; - if next_wait_target > this.instant { - settle_cycle = 0; - this.set_instant_no_sim(next_wait_target); - } - if run_extern_modules { - drop(this); - Self::run_extern_modules_cycle( - this_ref, - &generator_waker, - &ready_to_run_set.extern_modules_ready_to_run, - ); - this = this_ref.borrow_mut(); - } - if ready_to_run_set.state_ready_to_run { - if this.run_state_settle_cycle() { - // wait for clocks to settle before running extern modules again - run_extern_modules = false; - } else { - run_extern_modules = true; + let Event { + instant: event_instant, + kind: event_kind, + } = *first_entry.key(); + if event_instant <= event_queue_instant { + let wakers = first_entry.remove(); + drop(event_queue); + for HashableWaker(waker) in wakers { + waker.wake(); + } + match event_kind { + EventKind::State => this.run_state_settle_cycle(), + EventKind::ExternModule(module_index) => { + drop(this); + Self::run_extern_module(this_ref, module_index); + this = this_ref.borrow_mut(); + } + } + this.write_traces_after_event(); + this.check_waiting_sensitivity_sets(); + } else { + let new_instant = event_instant.min(run_target); + let changed_time = event_queue_instant != new_instant; + event_queue.set_instant(new_instant); + drop(event_queue); + if changed_time { + this.write_traces_change_time_to(new_instant); + } + if event_instant > run_target { + return; } } - if this.main_module.did_initial_settle { - this.read_traces::(); - } else { - this.read_traces::(); - } - this.state.memory_write_log.sort_unstable(); - this.state.memory_write_log.dedup(); - this.main_module.did_initial_settle = true; - this.for_each_trace_writer_storing_error(|this, trace_writer_state| { - Ok(match trace_writer_state { - TraceWriterState::Decls(trace_writer_decls) => TraceWriterState::Running( - this.init_trace_writer(trace_writer_decls.write_decls( - this.trace_decls, - this.traces.0.len(), - this.trace_memories.len(), - )?)?, - ), - TraceWriterState::Init(trace_writer) => { - TraceWriterState::Running(this.init_trace_writer(trace_writer)?) - } - TraceWriterState::Running(trace_writer) => { - TraceWriterState::Running(this.update_trace_writer(trace_writer)?) - } - TraceWriterState::Errored(e) => TraceWriterState::Errored(e), - }) - }); - this.state.memory_write_log.clear(); - } - if run_target > this.instant { - this.set_instant_no_sim(run_target); + event_queue = this.event_queue.lock(); } } #[track_caller] fn settle(this_ref: &Rc>) { - let run_target = this_ref.borrow().instant; - Self::run_until(this_ref, run_target); + Self::run_until(this_ref, &mut Some); } fn get_module(&self, which_module: WhichModule) -> &SimulationModuleState { match which_module { @@ -2106,7 +2382,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(io, which_module); - self.state_ready_to_run = true; + self.event_queue.add_event_for_now(EventKind::State, None); match compiled_value.range.len().as_single() { Some(TypeLenSingle::SmallSlot) => { self.state.small_slots[compiled_value.range.small_slots.start] = value as _; @@ -2138,7 +2414,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(Expr::canonical(io), which_module); - self.state_ready_to_run = true; + self.event_queue.add_event_for_now(EventKind::State, None); let value: BigInt = value.into(); match compiled_value.range.len().as_single() { Some(TypeLenSingle::SmallSlot) => { @@ -2378,7 +2654,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(io, which_module); - self.state_ready_to_run = true; + self.event_queue.add_event_for_now(EventKind::State, None); assert_eq!(Expr::ty(io), SimValue::ty(value)); Self::read_write_sim_value_helper( &mut self.state, @@ -2426,7 +2702,7 @@ impl SimulationImpl { } } async fn yield_settle_if_needed( - this_ref: &Rc>, + this_ref: &RefCell, module_index: usize, v: MaybeNeedsSettle, ) -> O @@ -2435,7 +2711,7 @@ impl SimulationImpl { { match v { MaybeNeedsSettle::NeedsSettle(v) => { - Self::yield_advance_time_or_settle(this_ref.clone(), module_index, None).await; + Self::yield_advance_time_or_settle(this_ref, module_index, None).await; v.call(&mut this_ref.borrow_mut().state) } MaybeNeedsSettle::NoSettleNeeded(v) => v, @@ -2786,7 +3062,6 @@ impl Simulation { pub struct ExternModuleSimulationState { sim_impl: Rc>, module_index: usize, - wait_for_changes_wait_targets: EarliestWaitTargets, } impl fmt::Debug for ExternModuleSimulationState { @@ -2794,7 +3069,6 @@ impl fmt::Debug for ExternModuleSimulationState { let Self { sim_impl: _, module_index, - wait_for_changes_wait_targets: _, } = self; f.debug_struct("ExternModuleSimulationState") .field("sim_impl", &DebugAsDisplay("...")) @@ -2805,12 +3079,11 @@ impl fmt::Debug for ExternModuleSimulationState { impl ExternModuleSimulationState { pub async fn settle(&mut self) { - SimulationImpl::yield_advance_time_or_settle(self.sim_impl.clone(), self.module_index, None) - .await + SimulationImpl::yield_advance_time_or_settle(&self.sim_impl, self.module_index, None).await } pub async fn advance_time(&mut self, duration: SimDuration) { SimulationImpl::yield_advance_time_or_settle( - self.sim_impl.clone(), + &self.sim_impl, self.module_index, Some(duration), ) @@ -2821,7 +3094,17 @@ impl ExternModuleSimulationState { iter: I, timeout: Option, ) { - self.wait_for_changes_wait_targets.clear(); + let mut sim_impl = self.sim_impl.borrow_mut(); + let mut sensitivity_set = SensitivitySet { + debug_id: sim_impl.next_sensitivity_set_debug_id, + compiled_values: HashSet::default(), + values: Vec::new(), + waker: RefCell::new(std::task::Waker::noop().clone()), + changed: Cell::new(false), + }; + sim_impl.next_sensitivity_set_debug_id = + sim_impl.next_sensitivity_set_debug_id.wrapping_add(1); + drop(sim_impl); let which_module = WhichModule::Extern { module_index: self.module_index, }; @@ -2829,19 +3112,18 @@ impl ExternModuleSimulationState { let io = Expr::canonical(io.to_expr()); let (key, value) = self.sim_impl.borrow_mut().read(io, which_module); let value = self.settle_if_needed(value).await; - self.wait_for_changes_wait_targets - .insert(WaitTarget::Change { key, value }); + let key = Rc::new(key); + if sensitivity_set.compiled_values.insert(key.clone()) { + sensitivity_set.values.push((key, Rc::new(value))); + } } - if let Some(timeout) = timeout { - self.wait_for_changes_wait_targets.instant = - Some(self.sim_impl.borrow().instant + timeout); - } - SimulationImpl::yield_wait( - self.sim_impl.clone(), + SimulationImpl::yield_wait_for_changes( + &self.sim_impl, self.module_index, - &mut self.wait_for_changes_wait_targets, + sensitivity_set, + timeout, ) - .await; + .await } pub async fn wait_for_clock_edge(&mut self, clk: impl ToExpr) { let clk = clk.to_expr(); @@ -2858,6 +3140,19 @@ impl ExternModuleSimulationState { { SimulationImpl::yield_settle_if_needed(&self.sim_impl, self.module_index, v).await } + pub async fn fork_join(&mut self, futures: F) -> F::Output { + F::fork_join(futures, self).await + } + fn forked_state(&self) -> Self { + let Self { + ref sim_impl, + module_index, + } = *self; + Self { + sim_impl: sim_impl.clone(), + module_index, + } + } impl_simulation_methods!( async_await = (async, await), track_caller = (), @@ -2865,6 +3160,114 @@ impl ExternModuleSimulationState { ); } +struct ForkJoinImpl<'a> { + futures: Vec + 'a>>>, +} + +impl Future for ForkJoinImpl<'_> { + type Output = (); + fn poll(self: Pin<&mut Self>, cx: &mut std::task::Context<'_>) -> Poll { + let Self { futures } = self.get_mut(); + futures.retain_mut(|future| future.as_mut().poll(cx).is_pending()); + if futures.is_empty() { + Poll::Ready(()) + } else { + Poll::Pending + } + } +} + +pub trait ForkJoin { + type Output; + #[allow(async_fn_in_trait, reason = "no auto traits needed")] + async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output; +} + +impl O, O, const N: usize> ForkJoin for [F; N] { + type Output = [O; N]; + async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { + let mut temp = [const { None }; N]; + ForkJoinImpl { + futures: this + .into_iter() + .zip(&mut temp) + .map(|(future, temp)| -> Pin + '_>> { + Box::pin(async { *temp = Some(future(sim_state.forked_state()).await) }) + }) + .collect(), + } + .await; + temp.map(|output| output.expect("set to Some above")) + } +} + +impl O, O> ForkJoin for Vec { + type Output = Vec; + async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { + let mut temp = Vec::with_capacity(this.len()); + for _ in 0..this.len() { + temp.push(None); + } + ForkJoinImpl { + futures: this + .into_iter() + .zip(&mut temp) + .map(|(future, temp)| -> Pin + '_>> { + Box::pin(async { *temp = Some(future(sim_state.forked_state()).await) }) + }) + .collect(), + } + .await; + temp.into_iter() + .map(|output| output.expect("set to Some above")) + .collect() + } +} + +impl O, O> ForkJoin for Box<[F]> { + type Output = Box<[O]>; + async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { + Vec::fork_join(this.into(), sim_state) + .await + .into_boxed_slice() + } +} + +impl ForkJoin for Box { + type Output = Box; + async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { + Box::new(T::fork_join(*this, sim_state).await) + } +} + +macro_rules! impl_fork_join_tuples { + (@impl $(($f:ident: $F:ident => $o:ident: $O:ident)),*) => { + impl<$($F: AsyncFnOnce(ExternModuleSimulationState) -> $O, $O,)*> ForkJoin for ($($F,)*) { + type Output = ($($O,)*); + async fn fork_join(this: Self, sim_state: &mut ExternModuleSimulationState) -> Self::Output { + #![allow(unused_variables)] + let ($($f,)*) = this; + $(let mut $o = None;)* + ForkJoinImpl { + futures: vec![ + $(Box::pin(async { $o = Some($f(sim_state.forked_state()).await) }),)* + ], + }.await; + ($($o.expect("set to Some above"),)*) + } + } + }; + (($($first:tt)*) $(, $rest:tt)* $(,)?) => { + impl_fork_join_tuples!(@impl ($($first)*) $(, $rest)*); + impl_fork_join_tuples!($($rest),*); + }; + () => { + impl_fork_join_tuples!(@impl); + }; +} + +impl_fork_join_tuples!((f0: F0 => o0: O0), (f1: F1 => o1: O1), (f2: F2 => o2: O2), (f3: F3 => o3: O3), (f4: F4 => o4: O4), (f5: F5 => o5: O5), (f6: F6 => o6: O6), (f7: F7 => o7: O7), (f8: F8 => o8: O8), (f9: F9 => o9: O9), (f10: F10 => o10: O10), (f11: F11 => o11: O11),); + pub trait ExternModuleSimGenerator: Clone + Eq + Hash + Any + Send + Sync + fmt::Debug { fn run<'a>(&'a self, sim: ExternModuleSimulationState) -> impl IntoFuture + 'a; } diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index 873978a9..b055ffa0 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -2026,3 +2026,85 @@ fn test_sim_only_connects() { panic!(); } } + +#[hdl_module(outline_generated, extern)] +pub fn sim_fork_join() +where + ConstUsize: KnownSize, +{ + #[hdl] + let clocks: Array = m.input(); + #[hdl] + let outputs: Array, N> = m.output(); + m.extern_module_simulation_fn((clocks, outputs), |(clocks, outputs), mut sim| async move { + sim.write(outputs, [0u8; N]).await; + loop { + sim.fork_join( + clocks + .into_iter() + .zip(outputs) + .map(|(clock, output)| { + move |mut sim: ExternModuleSimulationState| async move { + sim.wait_for_clock_edge(clock).await; + let v = sim + .read_bool_or_int(output) + .await + .to_bigint() + .try_into() + .expect("known to be in range"); + sim.write(output, 1u8.wrapping_add(v)).await; + } + }) + .collect::>(), + ) + .await; + } + }); +} + +#[test] +fn test_sim_fork_join() { + let _n = SourceLocation::normalize_files_for_tests(); + const N: usize = 3; + let mut sim = Simulation::new(sim_fork_join::()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + sim.write(sim.io().clocks, [false; N]); + let mut clocks_triggered = [false; N]; + let mut expected = [0u8; N]; + for i0 in 0..N { + for i1 in 0..N { + for i2 in 0..N { + for i3 in 0..N { + let indexes = [i0, i1, i2, i3]; + for i in indexes { + sim.advance_time(SimDuration::from_micros(1)); + sim.write(sim.io().clocks[i], true); + sim.advance_time(SimDuration::from_micros(1)); + sim.write(sim.io().clocks[i], false); + if !clocks_triggered[i] { + expected[i] = expected[i].wrapping_add(1); + } + clocks_triggered[i] = true; + if clocks_triggered == [true; N] { + clocks_triggered = [false; N]; + } + let output = sim.read(sim.io().outputs); + assert_eq!(output, expected.to_sim_value(), "indexes={indexes:?} i={i}"); + } + } + } + } + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/sim_fork_join.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/sim_fork_join.txt") { + panic!(); + } +} diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt index 12e86f30..2f25f359 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.txt +++ b/crates/fayalite/tests/sim/expected/array_rw.txt @@ -828,7 +828,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "array_rw", children: [ @@ -1699,7 +1698,12 @@ Simulation { }, ), ], - instant: 34 μs, clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 34 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt index 58b2d20f..47997e5b 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt @@ -124,7 +124,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "conditional_assignment_last", children: [ @@ -177,7 +176,12 @@ Simulation { }, ), ], - instant: 2 μs, clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 2 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt index 182ed84f..ac6c052b 100644 --- a/crates/fayalite/tests/sim/expected/connect_const.txt +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -100,7 +100,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "connect_const", children: [ @@ -130,7 +129,12 @@ Simulation { ], trace_memories: {}, trace_writers: [], - instant: 0 s, clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 0 s, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt index f56a6b4e..999f414c 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -143,7 +143,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "connect_const_reset", children: [ @@ -197,7 +196,12 @@ Simulation { }, ), ], - instant: 1 μs, clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 1 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index 8c8809ab..7a43720e 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -263,7 +263,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "counter", children: [ @@ -329,7 +328,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x1, + last_state: 0x0, }, SimTrace { id: TraceScalarId(1), @@ -355,7 +354,7 @@ Simulation { ty: UInt<4>, }, state: 0x3, - last_state: 0x3, + last_state: 0x2, }, ], trace_memories: {}, @@ -368,9 +367,14 @@ Simulation { }, ), ], - instant: 66 μs, clocks_triggered: [ StatePartIndex(1), ], + event_queue: EventQueue(EventQueueData { + instant: 66 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_async.vcd b/crates/fayalite/tests/sim/expected/counter_async.vcd index a4b2ee91..dab690f5 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.vcd +++ b/crates/fayalite/tests/sim/expected/counter_async.vcd @@ -26,192 +26,192 @@ b11 $ 0! #3000000 1! -b100 $ b100 # +b100 $ #4000000 0! #5000000 1! -b101 $ b101 # +b101 $ #6000000 0! #7000000 1! -b110 $ b110 # +b110 $ #8000000 0! #9000000 1! -b111 $ b111 # +b111 $ #10000000 0! #11000000 1! -b1000 $ b1000 # +b1000 $ #12000000 0! #13000000 1! -b1001 $ b1001 # +b1001 $ #14000000 0! #15000000 1! -b1010 $ b1010 # +b1010 $ #16000000 0! #17000000 1! -b1011 $ b1011 # +b1011 $ #18000000 0! #19000000 1! -b1100 $ b1100 # +b1100 $ #20000000 0! #21000000 1! -b1101 $ b1101 # +b1101 $ #22000000 0! #23000000 1! -b1110 $ b1110 # +b1110 $ #24000000 0! #25000000 1! -b1111 $ b1111 # +b1111 $ #26000000 0! #27000000 1! -b0 $ b0 # +b0 $ #28000000 0! #29000000 1! -b1 $ b1 # +b1 $ #30000000 0! #31000000 1! -b10 $ b10 # +b10 $ #32000000 0! #33000000 1! -b11 $ b11 # +b11 $ #34000000 0! #35000000 1! -b100 $ b100 # +b100 $ #36000000 0! #37000000 1! -b101 $ b101 # +b101 $ #38000000 0! #39000000 1! -b110 $ b110 # +b110 $ #40000000 0! #41000000 1! -b111 $ b111 # +b111 $ #42000000 0! #43000000 1! -b1000 $ b1000 # +b1000 $ #44000000 0! #45000000 1! -b1001 $ b1001 # +b1001 $ #46000000 0! #47000000 1! -b1010 $ b1010 # +b1010 $ #48000000 0! #49000000 1! -b1011 $ b1011 # +b1011 $ #50000000 0! #51000000 1! -b1100 $ b1100 # +b1100 $ #52000000 0! #53000000 1! -b1101 $ b1101 # +b1101 $ #54000000 0! #55000000 1! -b1110 $ b1110 # +b1110 $ #56000000 0! #57000000 1! -b1111 $ b1111 # +b1111 $ #58000000 0! #59000000 1! -b0 $ b0 # +b0 $ #60000000 0! #61000000 1! -b1 $ b1 # +b1 $ #62000000 0! #63000000 1! -b10 $ b10 # +b10 $ #64000000 0! #65000000 1! -b11 $ b11 # +b11 $ #66000000 diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index 1d975b3d..b96ce5fd 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -244,7 +244,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "counter", children: [ @@ -310,7 +309,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x1, + last_state: 0x0, }, SimTrace { id: TraceScalarId(1), @@ -336,7 +335,7 @@ Simulation { ty: UInt<4>, }, state: 0x3, - last_state: 0x3, + last_state: 0x2, }, ], trace_memories: {}, @@ -349,9 +348,14 @@ Simulation { }, ), ], - instant: 66 μs, clocks_triggered: [ StatePartIndex(1), ], + event_queue: EventQueue(EventQueueData { + instant: 66 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/counter_sync.vcd b/crates/fayalite/tests/sim/expected/counter_sync.vcd index bf6249e4..9504a30a 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.vcd +++ b/crates/fayalite/tests/sim/expected/counter_sync.vcd @@ -16,199 +16,199 @@ b0 $ $end #1000000 1! -b11 $ b11 # +b11 $ 0" #2000000 0! #3000000 1! -b100 $ b100 # +b100 $ #4000000 0! #5000000 1! -b101 $ b101 # +b101 $ #6000000 0! #7000000 1! -b110 $ b110 # +b110 $ #8000000 0! #9000000 1! -b111 $ b111 # +b111 $ #10000000 0! #11000000 1! -b1000 $ b1000 # +b1000 $ #12000000 0! #13000000 1! -b1001 $ b1001 # +b1001 $ #14000000 0! #15000000 1! -b1010 $ b1010 # +b1010 $ #16000000 0! #17000000 1! -b1011 $ b1011 # +b1011 $ #18000000 0! #19000000 1! -b1100 $ b1100 # +b1100 $ #20000000 0! #21000000 1! -b1101 $ b1101 # +b1101 $ #22000000 0! #23000000 1! -b1110 $ b1110 # +b1110 $ #24000000 0! #25000000 1! -b1111 $ b1111 # +b1111 $ #26000000 0! #27000000 1! -b0 $ b0 # +b0 $ #28000000 0! #29000000 1! -b1 $ b1 # +b1 $ #30000000 0! #31000000 1! -b10 $ b10 # +b10 $ #32000000 0! #33000000 1! -b11 $ b11 # +b11 $ #34000000 0! #35000000 1! -b100 $ b100 # +b100 $ #36000000 0! #37000000 1! -b101 $ b101 # +b101 $ #38000000 0! #39000000 1! -b110 $ b110 # +b110 $ #40000000 0! #41000000 1! -b111 $ b111 # +b111 $ #42000000 0! #43000000 1! -b1000 $ b1000 # +b1000 $ #44000000 0! #45000000 1! -b1001 $ b1001 # +b1001 $ #46000000 0! #47000000 1! -b1010 $ b1010 # +b1010 $ #48000000 0! #49000000 1! -b1011 $ b1011 # +b1011 $ #50000000 0! #51000000 1! -b1100 $ b1100 # +b1100 $ #52000000 0! #53000000 1! -b1101 $ b1101 # +b1101 $ #54000000 0! #55000000 1! -b1110 $ b1110 # +b1110 $ #56000000 0! #57000000 1! -b1111 $ b1111 # +b1111 $ #58000000 0! #59000000 1! -b0 $ b0 # +b0 $ #60000000 0! #61000000 1! -b1 $ b1 # +b1 $ #62000000 0! #63000000 1! -b10 $ b10 # +b10 $ #64000000 0! #65000000 1! -b11 $ b11 # +b11 $ #66000000 diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt index 4c54aa85..e127210b 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.txt +++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt @@ -104,7 +104,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "duplicate_names", children: [ @@ -160,7 +159,12 @@ Simulation { }, ), ], - instant: 1 μs, clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 1 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index 4850a215..eeef867d 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1456,7 +1456,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "enums", children: [ @@ -1744,7 +1743,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x1, + last_state: 0x0, }, SimTrace { id: TraceScalarId(1), @@ -1924,9 +1923,14 @@ Simulation { }, ), ], - instant: 16 μs, clocks_triggered: [ StatePartIndex(3), ], + event_queue: EventQueue(EventQueueData { + instant: 16 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt index e09a7671..03349409 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.txt +++ b/crates/fayalite/tests/sim/expected/extern_module.txt @@ -186,14 +186,8 @@ Simulation { running_generator: Some( ..., ), - wait_targets: { - Instant( - 20.500000000000 μs, - ), - }, }, ], - state_ready_to_run: false, trace_decls: TraceModule { name: "extern_module", children: [ @@ -247,7 +241,14 @@ Simulation { }, ), ], - instant: 20 μs, clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 20 μs, + events: { + Event { instant: 20.500000000000 μs, kind: ExternModule(0) }: 1, + }, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module.vcd b/crates/fayalite/tests/sim/expected/extern_module.vcd index e026a50c..5d6a0bc9 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.vcd +++ b/crates/fayalite/tests/sim/expected/extern_module.vcd @@ -6,8 +6,9 @@ $upscope $end $enddefinitions $end $dumpvars 0! -1" +0" $end +1" #500000 #1500000 0" diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt index 1023b2ba..3d7cfaef 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.txt +++ b/crates/fayalite/tests/sim/expected/extern_module2.txt @@ -234,55 +234,8 @@ Simulation { running_generator: Some( ..., ), - wait_targets: { - Change { - key: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }, - value: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - }, - }, }, ], - state_ready_to_run: false, trace_decls: TraceModule { name: "extern_module2", children: [ @@ -356,7 +309,113 @@ Simulation { }, ), ], - instant: 60 μs, clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 60 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: { + SensitivitySet { + id: 59, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + }, + waiting_sensitivity_sets_by_compiled_value: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 59, + .. + }, + }, + ), + }, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/extern_module2.vcd b/crates/fayalite/tests/sim/expected/extern_module2.vcd index 464f4bd4..42045679 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.vcd +++ b/crates/fayalite/tests/sim/expected/extern_module2.vcd @@ -8,8 +8,9 @@ $enddefinitions $end $dumpvars 1! 0" -b1001000 # +b0 # $end +b1001000 # #1000000 1" b1100101 # diff --git a/crates/fayalite/tests/sim/expected/many_memories.txt b/crates/fayalite/tests/sim/expected/many_memories.txt index fbbc5819..f311cf7e 100644 --- a/crates/fayalite/tests/sim/expected/many_memories.txt +++ b/crates/fayalite/tests/sim/expected/many_memories.txt @@ -3836,7 +3836,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "many_memories", children: [ @@ -7759,7 +7758,6 @@ Simulation { }, ), ], - instant: 38 μs, clocks_triggered: [ StatePartIndex(1), StatePartIndex(6), @@ -7778,5 +7776,11 @@ Simulation { StatePartIndex(85), StatePartIndex(90), ], + event_queue: EventQueue(EventQueueData { + instant: 38 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/many_memories.vcd b/crates/fayalite/tests/sim/expected/many_memories.vcd index cbaeb7b1..77d1447a 100644 --- a/crates/fayalite/tests/sim/expected/many_memories.vcd +++ b/crates/fayalite/tests/sim/expected/many_memories.vcd @@ -1052,12 +1052,16 @@ $end 1U# 1e# 1# +1$ 1' 1+ +1, 1/ 13 +14 17 1; +1< 1? 1C 1H @@ -1068,29 +1072,25 @@ $end 1a 1f 1k +1l 1o 1t 1x 1} +1~ 1#" 1(" 1," 11" +12" 15" 1:" 1>" 1C" +1D" 1G" 1L" 1P" -1$ -1, -14 -1< -1l -1~ -12" -1D" #4000000 0# 0' @@ -1150,13 +1150,21 @@ $end 0U# 0e# 1# +0$ 1' +0( 1+ +0, 1/ +00 13 +04 17 +08 1; +0< 1? +0@ 1C 1H 1M @@ -1166,37 +1174,29 @@ $end 1a 1f 1k +0l 1o 1t +0u 1x 1} +0~ 1#" 1(" +0)" 1," 11" +02" 15" 1:" +0;" 1>" 1C" +0D" 1G" 1L" -1P" -0$ -0( -0, -00 -04 -08 -0< -0@ -0l -0u -0~ -0)" -02" -0;" -0D" 0M" +1P" #6000000 0# 0' diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt index f7f88e3b..03c5ee37 100644 --- a/crates/fayalite/tests/sim/expected/memories.txt +++ b/crates/fayalite/tests/sim/expected/memories.txt @@ -721,7 +721,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "memories", children: [ @@ -1616,10 +1615,15 @@ Simulation { }, ), ], - instant: 22 μs, clocks_triggered: [ StatePartIndex(1), StatePartIndex(6), ], + event_queue: EventQueue(EventQueueData { + instant: 22 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories.vcd b/crates/fayalite/tests/sim/expected/memories.vcd index bedc354b..d8f58172 100644 --- a/crates/fayalite/tests/sim/expected/memories.vcd +++ b/crates/fayalite/tests/sim/expected/memories.vcd @@ -234,13 +234,13 @@ b100000 6 b10000 9 b100000 I 1# -1( -1/ -14 b10000 $ b100000 % +1( +1/ b10000 0 b100000 1 +14 #4000000 0# 0( @@ -256,11 +256,11 @@ b1000000 6 b10000 9 b1000000 I 1# +b1000000 % 1( 1/ -14 -b1000000 % b1000000 1 +14 #6000000 0# 0( @@ -278,11 +278,11 @@ b1100000 6 b1010000 9 b1000000 I 1# +b1010000 $ 1( 1/ -14 -b1010000 $ b1010000 0 +14 #8000000 0# 0( diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt index c216104c..f1cb72b6 100644 --- a/crates/fayalite/tests/sim/expected/memories2.txt +++ b/crates/fayalite/tests/sim/expected/memories2.txt @@ -679,7 +679,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "memories2", children: [ @@ -1260,9 +1259,14 @@ Simulation { }, ), ], - instant: 22 μs, clocks_triggered: [ StatePartIndex(3), ], + event_queue: EventQueue(EventQueueData { + instant: 22 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories2.vcd b/crates/fayalite/tests/sim/expected/memories2.vcd index 4039754f..0ac20f19 100644 --- a/crates/fayalite/tests/sim/expected/memories2.vcd +++ b/crates/fayalite/tests/sim/expected/memories2.vcd @@ -100,8 +100,8 @@ $end 1) #1250000 1# -1* b11 $ +1* sHdlSome\x20(1) + 1, #1500000 @@ -113,8 +113,8 @@ sHdlSome\x20(1) + 0) #2250000 1# -1* b0 $ +1* sHdlNone\x20(0) + 0, #2500000 @@ -303,8 +303,8 @@ b11 ! b11 ( #17250000 1# -1* b11 $ +1* sHdlSome\x20(1) + 1, #17500000 @@ -316,8 +316,8 @@ b10 ! b10 ( #18250000 1# -1* b0 $ +1* sHdlNone\x20(0) + 0, #18500000 @@ -339,8 +339,8 @@ b1 ! b1 ( #20250000 1# -1* b1 $ +1* sHdlSome\x20(1) + #20500000 #20750000 @@ -353,8 +353,8 @@ b0 ( 0) #21250000 1# -1* b0 $ +1* sHdlNone\x20(0) + #21500000 #21750000 diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt index 8114c7e4..3166e17b 100644 --- a/crates/fayalite/tests/sim/expected/memories3.txt +++ b/crates/fayalite/tests/sim/expected/memories3.txt @@ -1763,7 +1763,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "memories3", children: [ @@ -3275,10 +3274,15 @@ Simulation { }, ), ], - instant: 15 μs, clocks_triggered: [ StatePartIndex(1), StatePartIndex(6), ], + event_queue: EventQueue(EventQueueData { + instant: 15 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/memories3.vcd b/crates/fayalite/tests/sim/expected/memories3.vcd index 5768560e..32ee75e6 100644 --- a/crates/fayalite/tests/sim/expected/memories3.vcd +++ b/crates/fayalite/tests/sim/expected/memories3.vcd @@ -420,6 +420,10 @@ b10000 T 1\ #3250000 1# +b110100 % +b1111000 ' +b10011010 ( +b11110000 + 1. 1A b110100 C @@ -427,10 +431,6 @@ b1111000 E b10011010 F b11110000 I 1L -b110100 % -b1111000 ' -b10011010 ( -b11110000 + #3500000 #3750000 0# @@ -508,6 +508,14 @@ b1010100 '" b110010 /" b10000 7" 1# +b11111110 $ +b11011100 % +b10111010 & +b10011000 ' +b1110110 ( +b1010100 ) +b110010 * +b10000 + 1. 1A b11111110 B @@ -519,14 +527,6 @@ b1010100 G b110010 H b10000 I 1L -b11111110 $ -b11011100 % -b10111010 & -b10011000 ' -b1110110 ( -b1010100 ) -b110010 * -b10000 + #6500000 #6750000 0# @@ -562,6 +562,14 @@ b1000110 (" b10001010 0" b11001110 8" 1# +b0 $ +b0 % +b0 & +b0 ' +b0 ( +b0 ) +b0 * +b0 + 1. 1A b0 B @@ -573,14 +581,6 @@ b0 G b0 H b0 I 1L -b0 $ -b0 % -b0 & -b0 ' -b0 ( -b0 ) -b0 * -b0 + #7500000 #7750000 0# @@ -688,6 +688,14 @@ b1 ! b1 ? #10250000 1# +b11111110 $ +b11011100 % +b10111010 & +b10011000 ' +b1110110 ( +b1010100 ) +b110010 * +b10000 + 1. 1A b11111110 B @@ -699,14 +707,6 @@ b1010100 G b110010 H b10000 I 1L -b11111110 $ -b11011100 % -b10111010 & -b10011000 ' -b1110110 ( -b1010100 ) -b110010 * -b10000 + #10500000 #10750000 0# @@ -718,6 +718,14 @@ b10 ! b10 ? #11250000 1# +b10011 $ +b1010111 % +b10011011 & +b11011111 ' +b10 ( +b1000110 ) +b10001010 * +b11001110 + 1. 1A b10011 B @@ -729,14 +737,6 @@ b1000110 G b10001010 H b11001110 I 1L -b10011 $ -b1010111 % -b10011011 & -b11011111 ' -b10 ( -b1000110 ) -b10001010 * -b11001110 + #11500000 #11750000 0# @@ -748,6 +748,14 @@ b11 ! b11 ? #12250000 1# +b1110100 $ +b1100101 % +b1110011 & +b1110100 ' +b1101001 ( +b1101110 ) +b1100111 * +b100001 + 1. 1A b1110100 B @@ -759,14 +767,6 @@ b1101110 G b1100111 H b100001 I 1L -b1110100 $ -b1100101 % -b1110011 & -b1110100 ' -b1101001 ( -b1101110 ) -b1100111 * -b100001 + #12500000 #12750000 0# @@ -780,6 +780,14 @@ b0 ? 0@ #13250000 1# +b1101101 $ +b1101111 % +b1110010 & +b1100101 ' +b100000 ( +b1110100 ) +b1110011 * +b1110100 + 1. 1A b1101101 B @@ -791,14 +799,6 @@ b1110100 G b1110011 H b1110100 I 1L -b1101101 $ -b1101111 % -b1110010 & -b1100101 ' -b100000 ( -b1110100 ) -b1110011 * -b1110100 + #13500000 #13750000 0# @@ -808,6 +808,14 @@ b1110100 + #14000000 #14250000 1# +b0 $ +b0 % +b0 & +b0 ' +b0 ( +b0 ) +b0 * +b0 + 1. 1A b0 B @@ -819,14 +827,6 @@ b0 G b0 H b0 I 1L -b0 $ -b0 % -b0 & -b0 ' -b0 ( -b0 ) -b0 * -b0 + #14500000 #14750000 0# diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt index 4ef02b2e..355b6ee0 100644 --- a/crates/fayalite/tests/sim/expected/mod1.txt +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -276,7 +276,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "mod1", children: [ @@ -558,7 +557,12 @@ Simulation { }, ), ], - instant: 2 μs, clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 2 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt index 9e4e0d1b..58189754 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.txt +++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt @@ -827,52 +827,6 @@ Simulation { running_generator: Some( ..., ), - wait_targets: { - Change { - key: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 3, len: 0 }, - big_slots: StatePartIndexRange { start: 33, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }, - value: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - }, }, SimulationExternModuleState { module_state: SimulationModuleState { @@ -956,52 +910,6 @@ Simulation { running_generator: Some( ..., ), - wait_targets: { - Change { - key: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 6, len: 0 }, - big_slots: StatePartIndexRange { start: 44, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }, - value: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - }, }, SimulationExternModuleState { module_state: SimulationModuleState { @@ -1085,55 +993,8 @@ Simulation { running_generator: Some( ..., ), - wait_targets: { - Change { - key: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 9, len: 0 }, - big_slots: StatePartIndexRange { start: 55, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, - }, - write: None, - }, - value: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x0_u1, - sim_only_values: [], - }, - }, - }, - }, }, ], - state_ready_to_run: false, trace_decls: TraceModule { name: "ripple_counter", children: [ @@ -1593,11 +1454,315 @@ Simulation { }, ), ], - instant: 256 μs, clocks_triggered: [ StatePartIndex(1), StatePartIndex(4), StatePartIndex(7), ], + event_queue: EventQueue(EventQueueData { + instant: 256 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: { + SensitivitySet { + id: 152, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 55, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + SensitivitySet { + id: 167, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 6, len: 0 }, + big_slots: StatePartIndexRange { start: 44, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + SensitivitySet { + id: 170, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 3, len: 0 }, + big_slots: StatePartIndexRange { start: 33, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + }, + waiting_sensitivity_sets_by_compiled_value: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 3, len: 0 }, + big_slots: StatePartIndexRange { start: 33, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 170, + .. + }, + }, + ), + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 6, len: 0 }, + big_slots: StatePartIndexRange { start: 44, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 167, + .. + }, + }, + ), + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 55, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 152, + .. + }, + }, + ), + }, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.vcd b/crates/fayalite/tests/sim/expected/ripple_counter.vcd index 6f14a8e8..550205f8 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.vcd +++ b/crates/fayalite/tests/sim/expected/ripple_counter.vcd @@ -66,1688 +66,1648 @@ b0 " $end #1000000 1! -1) b1 " 1# +1) 1* 1, -1+ -b11 " +b111 " 1$ +1% +1+ 1- 1. -b111 " -1% 1/ 11 -10 -b1111 " +b11111 " 1& +1' +10 12 13 -b11111 " -1' 14 16 -15 b111111 " 1( +15 17 #2000000 0! #3000000 1! -0) b111110 " 0# +0) 0* 0, #4000000 0! #5000000 1! -1) b111111 " 1# +1) 1* 1, -0+ b111101 " 0$ +0+ 0- #6000000 0! #7000000 1! -0) b111100 " 0# +0) 0* 0, #8000000 0! #9000000 1! -1) b111101 " 1# +1) 1* 1, -1+ -b111111 " +b111011 " 1$ +0% +1+ 1- 0. -b111011 " -0% 0/ 01 #10000000 0! #11000000 1! -0) b111010 " 0# +0) 0* 0, #12000000 0! #13000000 1! -1) b111011 " 1# +1) 1* 1, -0+ b111001 " 0$ +0+ 0- #14000000 0! #15000000 1! -0) b111000 " 0# +0) 0* 0, #16000000 0! #17000000 1! -1) b111001 " 1# +1) 1* 1, -1+ -b111011 " +b111111 " 1$ +1% +1+ 1- 1. -b111111 " -1% 1/ 11 -00 b110111 " 0& +00 02 #18000000 0! #19000000 1! -0) b110110 " 0# +0) 0* 0, #20000000 0! #21000000 1! -1) b110111 " 1# +1) 1* 1, -0+ b110101 " 0$ +0+ 0- #22000000 0! #23000000 1! -0) b110100 " 0# +0) 0* 0, #24000000 0! #25000000 1! -1) b110101 " 1# +1) 1* 1, -1+ -b110111 " +b110011 " 1$ +0% +1+ 1- 0. -b110011 " -0% 0/ 01 #26000000 0! #27000000 1! -0) b110010 " 0# +0) 0* 0, #28000000 0! #29000000 1! -1) b110011 " 1# +1) 1* 1, -0+ b110001 " 0$ +0+ 0- #30000000 0! #31000000 1! -0) b110000 " 0# +0) 0* 0, #32000000 0! #33000000 1! -1) b110001 " 1# +1) 1* 1, -1+ -b110011 " +b110111 " 1$ +1% +1+ 1- 1. -b110111 " -1% 1/ 11 -10 -b111111 " +b101111 " 1& +0' +10 12 03 -b101111 " -0' 04 06 #34000000 0! #35000000 1! -0) b101110 " 0# +0) 0* 0, #36000000 0! #37000000 1! -1) b101111 " 1# +1) 1* 1, -0+ b101101 " 0$ +0+ 0- #38000000 0! #39000000 1! -0) b101100 " 0# +0) 0* 0, #40000000 0! #41000000 1! -1) b101101 " 1# +1) 1* 1, -1+ -b101111 " +b101011 " 1$ +0% +1+ 1- 0. -b101011 " -0% 0/ 01 #42000000 0! #43000000 1! -0) b101010 " 0# +0) 0* 0, #44000000 0! #45000000 1! -1) b101011 " 1# +1) 1* 1, -0+ b101001 " 0$ +0+ 0- #46000000 0! #47000000 1! -0) b101000 " 0# +0) 0* 0, #48000000 0! #49000000 1! -1) b101001 " 1# +1) 1* 1, -1+ -b101011 " +b101111 " 1$ +1% +1+ 1- 1. -b101111 " -1% 1/ 11 -00 b100111 " 0& +00 02 #50000000 0! #51000000 1! -0) b100110 " 0# +0) 0* 0, #52000000 0! #53000000 1! -1) b100111 " 1# +1) 1* 1, -0+ b100101 " 0$ +0+ 0- #54000000 0! #55000000 1! -0) b100100 " 0# +0) 0* 0, #56000000 0! #57000000 1! -1) b100101 " 1# +1) 1* 1, -1+ -b100111 " +b100011 " 1$ +0% +1+ 1- 0. -b100011 " -0% 0/ 01 #58000000 0! #59000000 1! -0) b100010 " 0# +0) 0* 0, #60000000 0! #61000000 1! -1) b100011 " 1# +1) 1* 1, -0+ b100001 " 0$ +0+ 0- #62000000 0! #63000000 1! -0) b100000 " 0# +0) 0* 0, #64000000 0! #65000000 1! -1) b100001 " 1# +1) 1* 1, -1+ -b100011 " +b100111 " 1$ +1% +1+ 1- 1. -b100111 " -1% 1/ 11 -10 -b101111 " +b111111 " 1& +1' +10 12 13 -b111111 " -1' 14 16 -05 b11111 " 0( +05 07 #66000000 0! #67000000 1! -0) b11110 " 0# +0) 0* 0, #68000000 0! #69000000 1! -1) b11111 " 1# +1) 1* 1, -0+ b11101 " 0$ +0+ 0- #70000000 0! #71000000 1! -0) b11100 " 0# +0) 0* 0, #72000000 0! #73000000 1! -1) b11101 " 1# +1) 1* 1, -1+ -b11111 " +b11011 " 1$ +0% +1+ 1- 0. -b11011 " -0% 0/ 01 #74000000 0! #75000000 1! -0) b11010 " 0# +0) 0* 0, #76000000 0! #77000000 1! -1) b11011 " 1# +1) 1* 1, -0+ b11001 " 0$ +0+ 0- #78000000 0! #79000000 1! -0) b11000 " 0# +0) 0* 0, #80000000 0! #81000000 1! -1) b11001 " 1# +1) 1* 1, -1+ -b11011 " +b11111 " 1$ +1% +1+ 1- 1. -b11111 " -1% 1/ 11 -00 b10111 " 0& +00 02 #82000000 0! #83000000 1! -0) b10110 " 0# +0) 0* 0, #84000000 0! #85000000 1! -1) b10111 " 1# +1) 1* 1, -0+ b10101 " 0$ +0+ 0- #86000000 0! #87000000 1! -0) b10100 " 0# +0) 0* 0, #88000000 0! #89000000 1! -1) b10101 " 1# +1) 1* 1, -1+ -b10111 " +b10011 " 1$ +0% +1+ 1- 0. -b10011 " -0% 0/ 01 #90000000 0! #91000000 1! -0) b10010 " 0# +0) 0* 0, #92000000 0! #93000000 1! -1) b10011 " 1# +1) 1* 1, -0+ b10001 " 0$ +0+ 0- #94000000 0! #95000000 1! -0) b10000 " 0# +0) 0* 0, #96000000 0! #97000000 1! -1) b10001 " 1# +1) 1* 1, -1+ -b10011 " +b10111 " 1$ +1% +1+ 1- 1. -b10111 " -1% 1/ 11 -10 -b11111 " +b1111 " 1& +0' +10 12 03 -b1111 " -0' 04 06 #98000000 0! #99000000 1! -0) b1110 " 0# +0) 0* 0, #100000000 0! #101000000 1! -1) b1111 " 1# +1) 1* 1, -0+ b1101 " 0$ +0+ 0- #102000000 0! #103000000 1! -0) b1100 " 0# +0) 0* 0, #104000000 0! #105000000 1! -1) b1101 " 1# +1) 1* 1, -1+ -b1111 " +b1011 " 1$ +0% +1+ 1- 0. -b1011 " -0% 0/ 01 #106000000 0! #107000000 1! -0) b1010 " 0# +0) 0* 0, #108000000 0! #109000000 1! -1) b1011 " 1# +1) 1* 1, -0+ b1001 " 0$ +0+ 0- #110000000 0! #111000000 1! -0) b1000 " 0# +0) 0* 0, #112000000 0! #113000000 1! -1) b1001 " 1# +1) 1* 1, -1+ -b1011 " +b1111 " 1$ +1% +1+ 1- 1. -b1111 " -1% 1/ 11 -00 b111 " 0& +00 02 #114000000 0! #115000000 1! -0) b110 " 0# +0) 0* 0, #116000000 0! #117000000 1! -1) b111 " 1# +1) 1* 1, -0+ b101 " 0$ +0+ 0- #118000000 0! #119000000 1! -0) b100 " 0# +0) 0* 0, #120000000 0! #121000000 1! -1) b101 " 1# +1) 1* 1, -1+ -b111 " +b11 " 1$ +0% +1+ 1- 0. -b11 " -0% 0/ 01 #122000000 0! #123000000 1! -0) b10 " 0# +0) 0* 0, #124000000 0! #125000000 1! -1) b11 " 1# +1) 1* 1, -0+ b1 " 0$ +0+ 0- #126000000 0! #127000000 1! -0) b0 " 0# +0) 0* 0, #128000000 0! #129000000 1! -1) b1 " 1# +1) 1* 1, -1+ -b11 " +b111 " 1$ +1% +1+ 1- 1. -b111 " -1% 1/ 11 -10 -b1111 " +b11111 " 1& +1' +10 12 13 -b11111 " -1' 14 16 -15 b111111 " 1( +15 17 #130000000 0! #131000000 1! -0) b111110 " 0# +0) 0* 0, #132000000 0! #133000000 1! -1) b111111 " 1# +1) 1* 1, -0+ b111101 " 0$ +0+ 0- #134000000 0! #135000000 1! -0) b111100 " 0# +0) 0* 0, #136000000 0! #137000000 1! -1) b111101 " 1# +1) 1* 1, -1+ -b111111 " +b111011 " 1$ +0% +1+ 1- 0. -b111011 " -0% 0/ 01 #138000000 0! #139000000 1! -0) b111010 " 0# +0) 0* 0, #140000000 0! #141000000 1! -1) b111011 " 1# +1) 1* 1, -0+ b111001 " 0$ +0+ 0- #142000000 0! #143000000 1! -0) b111000 " 0# +0) 0* 0, #144000000 0! #145000000 1! -1) b111001 " 1# +1) 1* 1, -1+ -b111011 " +b111111 " 1$ +1% +1+ 1- 1. -b111111 " -1% 1/ 11 -00 b110111 " 0& +00 02 #146000000 0! #147000000 1! -0) b110110 " 0# +0) 0* 0, #148000000 0! #149000000 1! -1) b110111 " 1# +1) 1* 1, -0+ b110101 " 0$ +0+ 0- #150000000 0! #151000000 1! -0) b110100 " 0# +0) 0* 0, #152000000 0! #153000000 1! -1) b110101 " 1# +1) 1* 1, -1+ -b110111 " +b110011 " 1$ +0% +1+ 1- 0. -b110011 " -0% 0/ 01 #154000000 0! #155000000 1! -0) b110010 " 0# +0) 0* 0, #156000000 0! #157000000 1! -1) b110011 " 1# +1) 1* 1, -0+ b110001 " 0$ +0+ 0- #158000000 0! #159000000 1! -0) b110000 " 0# +0) 0* 0, #160000000 0! #161000000 1! -1) b110001 " 1# +1) 1* 1, -1+ -b110011 " +b110111 " 1$ +1% +1+ 1- 1. -b110111 " -1% 1/ 11 -10 -b111111 " +b101111 " 1& +0' +10 12 03 -b101111 " -0' 04 06 #162000000 0! #163000000 1! -0) b101110 " 0# +0) 0* 0, #164000000 0! #165000000 1! -1) b101111 " 1# +1) 1* 1, -0+ b101101 " 0$ +0+ 0- #166000000 0! #167000000 1! -0) b101100 " 0# +0) 0* 0, #168000000 0! #169000000 1! -1) b101101 " 1# +1) 1* 1, -1+ -b101111 " +b101011 " 1$ +0% +1+ 1- 0. -b101011 " -0% 0/ 01 #170000000 0! #171000000 1! -0) b101010 " 0# +0) 0* 0, #172000000 0! #173000000 1! -1) b101011 " 1# +1) 1* 1, -0+ b101001 " 0$ +0+ 0- #174000000 0! #175000000 1! -0) b101000 " 0# +0) 0* 0, #176000000 0! #177000000 1! -1) b101001 " 1# +1) 1* 1, -1+ -b101011 " +b101111 " 1$ +1% +1+ 1- 1. -b101111 " -1% 1/ 11 -00 b100111 " 0& +00 02 #178000000 0! #179000000 1! -0) b100110 " 0# +0) 0* 0, #180000000 0! #181000000 1! -1) b100111 " 1# +1) 1* 1, -0+ b100101 " 0$ +0+ 0- #182000000 0! #183000000 1! -0) b100100 " 0# +0) 0* 0, #184000000 0! #185000000 1! -1) b100101 " 1# +1) 1* 1, -1+ -b100111 " +b100011 " 1$ +0% +1+ 1- 0. -b100011 " -0% 0/ 01 #186000000 0! #187000000 1! -0) b100010 " 0# +0) 0* 0, #188000000 0! #189000000 1! -1) b100011 " 1# +1) 1* 1, -0+ b100001 " 0$ +0+ 0- #190000000 0! #191000000 1! -0) b100000 " 0# +0) 0* 0, #192000000 0! #193000000 1! -1) b100001 " 1# +1) 1* 1, -1+ -b100011 " +b100111 " 1$ +1% +1+ 1- 1. -b100111 " -1% 1/ 11 -10 -b101111 " +b111111 " 1& +1' +10 12 13 -b111111 " -1' 14 16 -05 b11111 " 0( +05 07 #194000000 0! #195000000 1! -0) b11110 " 0# +0) 0* 0, #196000000 0! #197000000 1! -1) b11111 " 1# +1) 1* 1, -0+ b11101 " 0$ +0+ 0- #198000000 0! #199000000 1! -0) b11100 " 0# +0) 0* 0, #200000000 0! #201000000 1! -1) b11101 " 1# +1) 1* 1, -1+ -b11111 " +b11011 " 1$ +0% +1+ 1- 0. -b11011 " -0% 0/ 01 #202000000 0! #203000000 1! -0) b11010 " 0# +0) 0* 0, #204000000 0! #205000000 1! -1) b11011 " 1# +1) 1* 1, -0+ b11001 " 0$ +0+ 0- #206000000 0! #207000000 1! -0) b11000 " 0# +0) 0* 0, #208000000 0! #209000000 1! -1) b11001 " 1# +1) 1* 1, -1+ -b11011 " +b11111 " 1$ +1% +1+ 1- 1. -b11111 " -1% 1/ 11 -00 b10111 " 0& +00 02 #210000000 0! #211000000 1! -0) b10110 " 0# +0) 0* 0, #212000000 0! #213000000 1! -1) b10111 " 1# +1) 1* 1, -0+ b10101 " 0$ +0+ 0- #214000000 0! #215000000 1! -0) b10100 " 0# +0) 0* 0, #216000000 0! #217000000 1! -1) b10101 " 1# +1) 1* 1, -1+ -b10111 " +b10011 " 1$ +0% +1+ 1- 0. -b10011 " -0% 0/ 01 #218000000 0! #219000000 1! -0) b10010 " 0# +0) 0* 0, #220000000 0! #221000000 1! -1) b10011 " 1# +1) 1* 1, -0+ b10001 " 0$ +0+ 0- #222000000 0! #223000000 1! -0) b10000 " 0# +0) 0* 0, #224000000 0! #225000000 1! -1) b10001 " 1# +1) 1* 1, -1+ -b10011 " +b10111 " 1$ +1% +1+ 1- 1. -b10111 " -1% 1/ 11 -10 -b11111 " +b1111 " 1& +0' +10 12 03 -b1111 " -0' 04 06 #226000000 0! #227000000 1! -0) b1110 " 0# +0) 0* 0, #228000000 0! #229000000 1! -1) b1111 " 1# +1) 1* 1, -0+ b1101 " 0$ +0+ 0- #230000000 0! #231000000 1! -0) b1100 " 0# +0) 0* 0, #232000000 0! #233000000 1! -1) b1101 " 1# +1) 1* 1, -1+ -b1111 " +b1011 " 1$ +0% +1+ 1- 0. -b1011 " -0% 0/ 01 #234000000 0! #235000000 1! -0) b1010 " 0# +0) 0* 0, #236000000 0! #237000000 1! -1) b1011 " 1# +1) 1* 1, -0+ b1001 " 0$ +0+ 0- #238000000 0! #239000000 1! -0) b1000 " 0# +0) 0* 0, #240000000 0! #241000000 1! -1) b1001 " 1# +1) 1* 1, -1+ -b1011 " +b1111 " 1$ +1% +1+ 1- 1. -b1111 " -1% 1/ 11 -00 b111 " 0& +00 02 #242000000 0! #243000000 1! -0) b110 " 0# +0) 0* 0, #244000000 0! #245000000 1! -1) b111 " 1# +1) 1* 1, -0+ b101 " 0$ +0+ 0- #246000000 0! #247000000 1! -0) b100 " 0# +0) 0* 0, #248000000 0! #249000000 1! -1) b101 " 1# +1) 1* 1, -1+ -b111 " +b11 " 1$ +0% +1+ 1- 0. -b11 " -0% 0/ 01 #250000000 0! #251000000 1! -0) b10 " 0# +0) 0* 0, #252000000 0! #253000000 1! -1) b11 " 1# +1) 1* 1, -0+ b1 " 0$ +0+ 0- #254000000 0! #255000000 1! -0) b0 " 0# +0) 0* 0, #256000000 diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt index 9bab4248..2ca06d2d 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -339,7 +339,6 @@ Simulation { did_initial_settle: true, }, extern_modules: [], - state_ready_to_run: false, trace_decls: TraceModule { name: "shift_register", children: [ @@ -440,7 +439,7 @@ Simulation { index: StatePartIndex(0), }, state: 0x1, - last_state: 0x1, + last_state: 0x0, }, SimTrace { id: TraceScalarId(1), @@ -509,9 +508,14 @@ Simulation { }, ), ], - instant: 66 μs, clocks_triggered: [ StatePartIndex(1), ], + event_queue: EventQueue(EventQueueData { + instant: 66 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/shift_register.vcd b/crates/fayalite/tests/sim/expected/shift_register.vcd index 0b5f4290..26726eb0 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.vcd +++ b/crates/fayalite/tests/sim/expected/shift_register.vcd @@ -52,9 +52,9 @@ $end 0! #11000000 1! +1$ 0& 1( -1$ #12000000 0! 1# @@ -67,10 +67,10 @@ $end 0# #15000000 1! +0$ 0% 1& 0( -0$ #16000000 0! 1# @@ -83,23 +83,23 @@ $end 0! #19000000 1! +1$ 1& 0' 1( -1$ #20000000 0! #21000000 1! +0$ 1' 0( -0$ #22000000 0! #23000000 1! -1( 1$ +1( #24000000 0! 0# @@ -120,8 +120,8 @@ $end 0! #31000000 1! -0( 0$ +0( #32000000 0! #33000000 diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.txt b/crates/fayalite/tests/sim/expected/sim_fork_join.txt new file mode 100644 index 00000000..4ad3e620 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_fork_join.txt @@ -0,0 +1,523 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 6, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + 0: Return, + ], + .. + }, + pc: 0, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 0, + 49, + 50, + 50, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::sim_fork_join, + instantiated: Module { + name: sim_fork_join, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::sim_fork_join, + instantiated: Module { + name: sim_fork_join, + .. + }, + }.clocks, + Instance { + name: ::sim_fork_join, + instantiated: Module { + name: sim_fork_join, + .. + }, + }.outputs, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::sim_fork_join, + instantiated: Module { + name: sim_fork_join, + .. + }, + }.clocks, + Instance { + name: ::sim_fork_join, + instantiated: Module { + name: sim_fork_join, + .. + }, + }.clocks[0], + Instance { + name: ::sim_fork_join, + instantiated: Module { + name: sim_fork_join, + .. + }, + }.clocks[1], + Instance { + name: ::sim_fork_join, + instantiated: Module { + name: sim_fork_join, + .. + }, + }.clocks[2], + Instance { + name: ::sim_fork_join, + instantiated: Module { + name: sim_fork_join, + .. + }, + }.outputs, + Instance { + name: ::sim_fork_join, + instantiated: Module { + name: sim_fork_join, + .. + }, + }.outputs[0], + Instance { + name: ::sim_fork_join, + instantiated: Module { + name: sim_fork_join, + .. + }, + }.outputs[1], + Instance { + name: ::sim_fork_join, + instantiated: Module { + name: sim_fork_join, + .. + }, + }.outputs[2], + }, + did_initial_settle: true, + }, + extern_modules: [ + SimulationExternModuleState { + module_state: SimulationModuleState { + base_targets: [ + ModuleIO { + name: sim_fork_join::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_fork_join::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ], + uninitialized_ios: {}, + io_targets: { + ModuleIO { + name: sim_fork_join::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_fork_join::clocks, + is_input: true, + ty: Array, + .. + }[0], + ModuleIO { + name: sim_fork_join::clocks, + is_input: true, + ty: Array, + .. + }[1], + ModuleIO { + name: sim_fork_join::clocks, + is_input: true, + ty: Array, + .. + }[2], + ModuleIO { + name: sim_fork_join::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_fork_join::outputs, + is_input: false, + ty: Array, 3>, + .. + }[0], + ModuleIO { + name: sim_fork_join::outputs, + is_input: false, + ty: Array, 3>, + .. + }[1], + ModuleIO { + name: sim_fork_join::outputs, + is_input: false, + ty: Array, 3>, + .. + }[2], + }, + did_initial_settle: true, + }, + sim: ExternModuleSimulation { + generator: SimGeneratorFn { + args: ( + ModuleIO { + name: sim_fork_join::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_fork_join::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ), + f: ..., + }, + sim_io_to_generator_map: { + ModuleIO { + name: sim_fork_join::clocks, + is_input: true, + ty: Array, + .. + }: ModuleIO { + name: sim_fork_join::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_fork_join::outputs, + is_input: false, + ty: Array, 3>, + .. + }: ModuleIO { + name: sim_fork_join::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + }, + source_location: SourceLocation( + module-XXXXXXXXXX.rs:4:1, + ), + }, + running_generator: Some( + ..., + ), + }, + ], + trace_decls: TraceModule { + name: "sim_fork_join", + children: [ + TraceModuleIO { + name: "clocks", + child: TraceArray { + name: "clocks", + elements: [ + TraceClock { + location: TraceScalarId(0), + name: "[0]", + flow: Source, + }, + TraceClock { + location: TraceScalarId(1), + name: "[1]", + flow: Source, + }, + TraceClock { + location: TraceScalarId(2), + name: "[2]", + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ty: Array, + flow: Source, + }, + TraceModuleIO { + name: "outputs", + child: TraceArray { + name: "outputs", + elements: [ + TraceUInt { + location: TraceScalarId(3), + name: "[0]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(4), + name: "[1]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(5), + name: "[2]", + ty: UInt<8>, + flow: Sink, + }, + ], + ty: Array, 3>, + flow: Sink, + }, + ty: Array, 3>, + flow: Sink, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigClock { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigClock { + index: StatePartIndex(2), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(3), + ty: UInt<8>, + }, + state: 0x31, + last_state: 0x31, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigUInt { + index: StatePartIndex(4), + ty: UInt<8>, + }, + state: 0x32, + last_state: 0x32, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x32, + last_state: 0x32, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 648 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: { + SensitivitySet { + id: 198, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + }, + waiting_sensitivity_sets_by_compiled_value: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 198, + .. + }, + }, + ), + }, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.vcd b/crates/fayalite/tests/sim/expected/sim_fork_join.vcd new file mode 100644 index 00000000..a420c2b7 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_fork_join.vcd @@ -0,0 +1,1467 @@ +$timescale 1 ps $end +$scope module sim_fork_join $end +$scope struct clocks $end +$var wire 1 ! \[0] $end +$var wire 1 " \[1] $end +$var wire 1 # \[2] $end +$upscope $end +$scope struct outputs $end +$var wire 8 $ \[0] $end +$var wire 8 % \[1] $end +$var wire 8 & \[2] $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +0" +0# +b0 $ +b0 % +b0 & +$end +#1000000 +1! +b1 $ +#2000000 +0! +#3000000 +1! +#4000000 +0! +#5000000 +1! +#6000000 +0! +#7000000 +1! +#8000000 +0! +#9000000 +1! +#10000000 +0! +#11000000 +1! +#12000000 +0! +#13000000 +1! +#14000000 +0! +#15000000 +1" +b1 % +#16000000 +0" +#17000000 +1! +#18000000 +0! +#19000000 +1! +#20000000 +0! +#21000000 +1! +#22000000 +0! +#23000000 +1# +b1 & +#24000000 +0# +#25000000 +1! +b10 $ +#26000000 +0! +#27000000 +1! +#28000000 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+#631000000 +1! +b110001 $ +#632000000 +0! +#633000000 +1# +b110010 & +#634000000 +0# +#635000000 +1# +#636000000 +0# +#637000000 +1# +#638000000 +0# +#639000000 +1" +b110010 % +#640000000 +0" +#641000000 +1# +#642000000 +0# +#643000000 +1# +#644000000 +0# +#645000000 +1# +#646000000 +0# +#647000000 +1# +#648000000 +0# diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.txt b/crates/fayalite/tests/sim/expected/sim_only_connects.txt index 114b3138..3c1605d1 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.txt +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.txt @@ -717,52 +717,6 @@ Simulation { running_generator: Some( ..., ), - wait_targets: { - Change { - key: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 6, len: 0 }, - }, - write: None, - }, - value: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - }, - }, }, SimulationExternModuleState { module_state: SimulationModuleState { @@ -922,55 +876,8 @@ Simulation { running_generator: Some( ..., ), - wait_targets: { - Change { - key: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - sim_only_slots: StatePartLayout { - len: 0, - debug_data: [], - layout_data: [], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 4, len: 0 }, - big_slots: StatePartIndexRange { start: 12, len: 1 }, - sim_only_slots: StatePartIndexRange { start: 13, len: 0 }, - }, - write: None, - }, - value: SimValue { - ty: Clock, - value: OpaqueSimValue { - bits: 0x1_u1, - sim_only_values: [], - }, - }, - }, - }, }, ], - state_ready_to_run: false, trace_decls: TraceModule { name: "sim_only_connects", children: [ @@ -1628,9 +1535,214 @@ Simulation { }, ), ], - instant: 16 μs, clocks_triggered: [ StatePartIndex(1), ], + event_queue: EventQueue(EventQueueData { + instant: 16 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: { + SensitivitySet { + id: 30, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 6, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + SensitivitySet { + id: 31, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 4, len: 0 }, + big_slots: StatePartIndexRange { start: 12, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 13, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + }, + waiting_sensitivity_sets_by_compiled_value: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 6, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 30, + .. + }, + }, + ), + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 4, len: 0 }, + big_slots: StatePartIndexRange { start: 12, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 13, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x1_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 31, + .. + }, + }, + ), + }, .. } \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.vcd b/crates/fayalite/tests/sim/expected/sim_only_connects.vcd index 2f464c0e..1e4c2497 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.vcd +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.vcd @@ -72,22 +72,22 @@ s{} 8 $end #1000000 1! +s{\"extra\":\x20\"value\"} $ 1' +s{\"extra\":\x20\"value\"} ) 1+ +s{\"extra\":\x20\"value\"} - 10 11 15 -s{\"extra\":\x20\"value\"} $ -s{\"extra\":\x20\"value\"} ) -s{\"extra\":\x20\"value\"} - -s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} * -s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 4 s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} % -s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} & +s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} * s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} . s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 3 s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 7 -s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 8 +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} & +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4 +s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8 #2000000 0! 0" @@ -107,9 +107,6 @@ s{\"extra\":\x20\"value\"} / 00 11 15 -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4 -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} & -s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8 #4000000 0! 0' From 840c5e1895b7cdad3eaa2c009558de9196fe477b Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 3 Nov 2025 23:59:36 -0800 Subject: [PATCH 04/10] add ExternModuleSimulationState::resettable helper for procedural simulations that have a reset input. --- crates/fayalite/src/sim.rs | 152 ++++- crates/fayalite/tests/sim.rs | 136 +++++ .../expected/sim_resettable_counter_async.txt | 550 ++++++++++++++++++ .../expected/sim_resettable_counter_async.vcd | 68 +++ ...settable_counter_async_immediate_reset.txt | 550 ++++++++++++++++++ ...settable_counter_async_immediate_reset.vcd | 65 +++ .../expected/sim_resettable_counter_sync.txt | 505 ++++++++++++++++ .../expected/sim_resettable_counter_sync.vcd | 70 +++ ...esettable_counter_sync_immediate_reset.txt | 505 ++++++++++++++++ ...esettable_counter_sync_immediate_reset.vcd | 70 +++ 10 files changed, 2669 insertions(+), 2 deletions(-) create mode 100644 crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt create mode 100644 crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd create mode 100644 crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt create mode 100644 crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd create mode 100644 crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt create mode 100644 crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd create mode 100644 crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt create mode 100644 crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 35da3367..5887dee3 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -54,7 +54,7 @@ use std::{ future::{Future, IntoFuture}, hash::Hash, mem, - pin::Pin, + pin::{Pin, pin}, ptr, rc::Rc, sync::{Arc, Mutex}, @@ -1187,6 +1187,33 @@ impl SimulationModuleState { } } #[track_caller] + fn is_reset_async(&self, io: Expr, which_module: WhichModule) -> bool { + let Some(target) = io.target() else { + match which_module { + WhichModule::Main => panic!( + "can't read from an expression that's not a field/element of `Simulation::io()`" + ), + WhichModule::Extern { .. } => panic!( + "can't read from an expression that's not based on one of this module's inputs/outputs" + ), + } + }; + match self.get_io(*target, which_module).layout.ty { + CanonicalType::UInt(_) + | CanonicalType::SInt(_) + | CanonicalType::Bool(_) + | CanonicalType::Array(_) + | CanonicalType::Enum(_) + | CanonicalType::Bundle(_) + | CanonicalType::Reset(_) + | CanonicalType::Clock(_) + | CanonicalType::PhantomConst(_) + | CanonicalType::DynSimOnly(_) => unreachable!(), + CanonicalType::AsyncReset(_) => true, + CanonicalType::SyncReset(_) => false, + } + } + #[track_caller] fn read_helper( &self, io: Expr, @@ -2085,6 +2112,23 @@ impl SimulationImpl { } } let sensitivity_set = Rc::new(sensitivity_set); + struct CancelOnDrop<'a> { + this: &'a RefCell, + sensitivity_set: &'a Rc, + } + impl Drop for CancelOnDrop<'_> { + fn drop(&mut self) { + let Self { + this, + sensitivity_set, + } = self; + this.borrow_mut().cancel_wake_after_change(&sensitivity_set); + } + } + let _cancel_on_drop = CancelOnDrop { + this, + sensitivity_set: &sensitivity_set, + }; let mut timeout_instant = None; std::future::poll_fn(|cx| { if sensitivity_set.changed.get() { @@ -2125,7 +2169,6 @@ impl SimulationImpl { } }) .await; - this.borrow_mut().cancel_wake_after_change(&sensitivity_set); } #[must_use] #[track_caller] @@ -2628,6 +2671,11 @@ impl SimulationImpl { any_change.get() } #[track_caller] + fn is_reset_async(&self, io: Expr, which_module: WhichModule) -> bool { + self.get_module(which_module) + .is_reset_async(io, which_module) + } + #[track_caller] fn read( &mut self, io: Expr, @@ -2969,6 +3017,13 @@ macro_rules! impl_simulation_methods { .read_bit(Expr::canonical(io), $which_module); $self.settle_if_needed(retval)$(.$await)? } + #[track_caller] + pub fn is_reset_async(&$self, io: Expr) -> bool { + $self + .sim_impl + .borrow_mut() + .is_reset_async(Expr::canonical(io), $which_module) + } $(#[$track_caller])? pub $($async)? fn read(&mut $self, io: Expr) -> SimValue { let retval = $self @@ -3143,6 +3198,99 @@ impl ExternModuleSimulationState { pub async fn fork_join(&mut self, futures: F) -> F::Output { F::fork_join(futures, self).await } + async fn resettable_helper( + &mut self, + cancellable: &Cell, + wait_for_reset: impl AsyncFn(Self), + main: impl AsyncFn(Self), + ) -> ! { + let mut wait_for_reset_invocation = pin!(Some(wait_for_reset(self.forked_state()))); + let mut main_invocation = pin!(Some(main(self.forked_state()))); + std::future::poll_fn(|cx: &mut std::task::Context<'_>| { + loop { + if cancellable.get() && wait_for_reset_invocation.is_none() { + cancellable.set(false); + main_invocation.set(Some(main(self.forked_state()))); + wait_for_reset_invocation.set(Some(wait_for_reset(self.forked_state()))) + } + match main_invocation.as_mut().as_pin_mut().map(|f| f.poll(cx)) { + None | Some(Poll::Pending) => {} + Some(Poll::Ready(())) => { + main_invocation.set(None); + continue; + } + } + match wait_for_reset_invocation + .as_mut() + .as_pin_mut() + .map(|f| f.poll(cx)) + { + None | Some(Poll::Pending) => {} + Some(Poll::Ready(())) => { + wait_for_reset_invocation.set(None); + continue; + } + } + return Poll::Pending; + } + }) + .await + } + /// When `cd.rst` is deduced to be an [`AsyncReset`]: + /// * when `cd.rst` is asserted or when first called, `reset` is invoked and any running `run` invocation is cancelled. + /// * when `cd.rst` is de-asserted and when `reset` finishes, `run` is invoked. + /// + /// When `cd.rst` is deduced to be a [`SyncReset`]: + /// * when there's a positive-going clock edge on `cd.clk` and `cd.rst` is asserted or when first called, `reset` is invoked and any running `run` invocation is cancelled. + /// * when `reset` finishes, `run` is invoked. + pub async fn resettable( + &mut self, + cd: impl ToExpr>, + reset: impl AsyncFn(Self) -> T, + run: impl AsyncFn(Self, T), + ) -> ! { + let cd = cd.to_expr(); + let rst = cd.rst; + if self.is_reset_async(rst) { + let cancellable = Cell::new(false); + let wait_for_reset = |mut this: Self| async move { + while this.read_reset(rst).await { + this.wait_for_changes([rst], None).await; + } + while !this.read_reset(rst).await { + this.wait_for_changes([rst], None).await; + } + }; + let main = |mut this: Self| async { + let run_arg = reset(this.forked_state()).await; + cancellable.set(true); + while this.read_reset(rst).await { + this.wait_for_changes([rst], None).await; + } + run(this, run_arg).await + }; + self.resettable_helper(&cancellable, wait_for_reset, main) + .await + } else { + let clk = cd.clk; + let wait_for_reset = |mut this: Self| async move { + loop { + this.wait_for_clock_edge(clk).await; + if this.read_reset(rst).await { + return; + } + } + }; + let cancellable = Cell::new(false); + let main = |this: Self| async { + let run_arg = reset(this.forked_state()).await; + cancellable.set(true); + run(this, run_arg).await + }; + self.resettable_helper(&cancellable, wait_for_reset, main) + .await + } + } fn forked_state(&self) -> Self { let Self { ref sim_impl, diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index b055ffa0..1f452c92 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -2108,3 +2108,139 @@ fn test_sim_fork_join() { panic!(); } } + +#[hdl_module(outline_generated, extern)] +pub fn sim_resettable_counter() { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let out: UInt<8> = m.output(); + m.extern_module_simulation_fn((cd, out), |(cd, out), mut sim| async move { + sim.resettable( + cd, + |mut sim: ExternModuleSimulationState| async move { + sim.write(out, 0u8).await; + }, + |mut sim: ExternModuleSimulationState, ()| async move { + loop { + sim.wait_for_clock_edge(cd.clk).await; + let v: u8 = sim + .read(out) + .await + .to_bigint() + .try_into() + .expect("known to be in range"); + sim.write(out, v.wrapping_add(1)).await; + } + }, + ) + .await + }); +} + +fn test_sim_resettable_counter_helper( + sim: &mut Simulation>, + immediate_reset: bool, +) { + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, immediate_reset); + for _ in 0..2 { + sim.advance_time(SimDuration::from_micros(1)); + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_micros(1)); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, true); + sim.advance_time(SimDuration::from_micros(1)); + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_micros(1)); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, false); + for expected in 0..3u8 { + assert_eq!(sim.read(sim.io().out), expected.to_sim_value()); + sim.advance_time(SimDuration::from_micros(1)); + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_micros(1)); + sim.write_clock(sim.io().cd.clk, false); + } + } +} + +#[test] +fn test_sim_resettable_counter_sync() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(sim_resettable_counter::()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + test_sim_resettable_counter_helper(&mut sim, false); + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/sim_resettable_counter_sync.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/sim_resettable_counter_sync.txt") { + panic!(); + } +} + +#[test] +fn test_sim_resettable_counter_sync_immediate_reset() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(sim_resettable_counter::()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + test_sim_resettable_counter_helper(&mut sim, true); + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/sim_resettable_counter_sync_immediate_reset.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/sim_resettable_counter_sync_immediate_reset.txt") { + panic!(); + } +} + +#[test] +fn test_sim_resettable_counter_async() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(sim_resettable_counter::()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + test_sim_resettable_counter_helper(&mut sim, false); + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/sim_resettable_counter_async.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/sim_resettable_counter_async.txt") { + panic!(); + } +} + +#[test] +fn test_sim_resettable_counter_async_immediate_reset() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(sim_resettable_counter::()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + test_sim_resettable_counter_helper(&mut sim, true); + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/sim_resettable_counter_async_immediate_reset.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/sim_resettable_counter_async_immediate_reset.txt") { + panic!(); + } +} diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt new file mode 100644 index 00000000..351f944c --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt @@ -0,0 +1,550 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 3, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", + ty: AsyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::out", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + 0: Return, + ], + .. + }, + pc: 0, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.out, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd.clk, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd.rst, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.out, + }, + did_initial_settle: true, + }, + extern_modules: [ + SimulationExternModuleState { + module_state: SimulationModuleState { + base_targets: [ + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + ], + uninitialized_ios: {}, + io_targets: { + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }.clk, + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }.rst, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + }, + did_initial_settle: true, + }, + sim: ExternModuleSimulation { + generator: SimGeneratorFn { + args: ( + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + ), + f: ..., + }, + sim_io_to_generator_map: { + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }: ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }: ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + }, + source_location: SourceLocation( + module-XXXXXXXXXX.rs:4:1, + ), + }, + running_generator: Some( + ..., + ), + }, + ], + trace_decls: TraceModule { + name: "sim_resettable_counter", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceAsyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceUInt { + location: TraceScalarId(2), + name: "out", + ty: UInt<8>, + flow: Sink, + }, + ty: UInt<8>, + flow: Sink, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigAsyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigUInt { + index: StatePartIndex(2), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 20 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: { + SensitivitySet { + id: 16, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: AsyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: AsyncReset, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: AsyncReset, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + SensitivitySet { + id: 23, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + }, + waiting_sensitivity_sets_by_compiled_value: { + CompiledValue { + layout: CompiledTypeLayout { + ty: AsyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: AsyncReset, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: AsyncReset, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 16, + .. + }, + }, + ), + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 23, + .. + }, + }, + ), + }, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd new file mode 100644 index 00000000..f05658f4 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.vcd @@ -0,0 +1,68 @@ +$timescale 1 ps $end +$scope module sim_resettable_counter $end +$scope struct cd $end +$var wire 1 ! clk $end +$var wire 1 " rst $end +$upscope $end +$var wire 8 # out $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +0" +b0 # +$end +#1000000 +1! +b1 # +#2000000 +0! +1" +b0 # +#3000000 +1! +#4000000 +0! +0" +#5000000 +1! +b1 # +#6000000 +0! +#7000000 +1! +b10 # +#8000000 +0! +#9000000 +1! +b11 # +#10000000 +0! +#11000000 +1! +b100 # +#12000000 +0! +1" +b0 # +#13000000 +1! +#14000000 +0! +0" +#15000000 +1! +b1 # +#16000000 +0! +#17000000 +1! +b10 # +#18000000 +0! +#19000000 +1! +b11 # +#20000000 +0! diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt new file mode 100644 index 00000000..abd7cf65 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt @@ -0,0 +1,550 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 3, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", + ty: AsyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::out", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + 0: Return, + ], + .. + }, + pc: 0, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.out, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd.clk, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd.rst, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.out, + }, + did_initial_settle: true, + }, + extern_modules: [ + SimulationExternModuleState { + module_state: SimulationModuleState { + base_targets: [ + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + ], + uninitialized_ios: {}, + io_targets: { + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }.clk, + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }.rst, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + }, + did_initial_settle: true, + }, + sim: ExternModuleSimulation { + generator: SimGeneratorFn { + args: ( + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + ), + f: ..., + }, + sim_io_to_generator_map: { + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }: ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }: ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + }, + source_location: SourceLocation( + module-XXXXXXXXXX.rs:4:1, + ), + }, + running_generator: Some( + ..., + ), + }, + ], + trace_decls: TraceModule { + name: "sim_resettable_counter", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceAsyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: AsyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceUInt { + location: TraceScalarId(2), + name: "out", + ty: UInt<8>, + flow: Sink, + }, + ty: UInt<8>, + flow: Sink, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigAsyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigUInt { + index: StatePartIndex(2), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 20 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: { + SensitivitySet { + id: 13, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: AsyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: AsyncReset, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: AsyncReset, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + SensitivitySet { + id: 20, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + }, + waiting_sensitivity_sets_by_compiled_value: { + CompiledValue { + layout: CompiledTypeLayout { + ty: AsyncReset, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: AsyncReset, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 1, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: AsyncReset, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 13, + .. + }, + }, + ), + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 20, + .. + }, + }, + ), + }, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd new file mode 100644 index 00000000..99f7b867 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.vcd @@ -0,0 +1,65 @@ +$timescale 1 ps $end +$scope module sim_resettable_counter $end +$scope struct cd $end +$var wire 1 ! clk $end +$var wire 1 " rst $end +$upscope $end +$var wire 8 # out $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +1" +b0 # +$end +#1000000 +1! +#2000000 +0! +#3000000 +1! +#4000000 +0! +0" +#5000000 +1! +b1 # +#6000000 +0! +#7000000 +1! +b10 # +#8000000 +0! +#9000000 +1! +b11 # +#10000000 +0! +#11000000 +1! +b100 # +#12000000 +0! +1" +b0 # +#13000000 +1! +#14000000 +0! +0" +#15000000 +1! +b1 # +#16000000 +0! +#17000000 +1! +b10 # +#18000000 +0! +#19000000 +1! +b11 # +#20000000 +0! diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt new file mode 100644 index 00000000..8ff0c2fd --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt @@ -0,0 +1,505 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 3, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::out", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + 0: Return, + ], + .. + }, + pc: 0, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.out, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd.clk, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd.rst, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.out, + }, + did_initial_settle: true, + }, + extern_modules: [ + SimulationExternModuleState { + module_state: SimulationModuleState { + base_targets: [ + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + ], + uninitialized_ios: {}, + io_targets: { + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }.clk, + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }.rst, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + }, + did_initial_settle: true, + }, + sim: ExternModuleSimulation { + generator: SimGeneratorFn { + args: ( + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + ), + f: ..., + }, + sim_io_to_generator_map: { + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }: ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }: ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + }, + source_location: SourceLocation( + module-XXXXXXXXXX.rs:4:1, + ), + }, + running_generator: Some( + ..., + ), + }, + ], + trace_decls: TraceModule { + name: "sim_resettable_counter", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceUInt { + location: TraceScalarId(2), + name: "out", + ty: UInt<8>, + flow: Sink, + }, + ty: UInt<8>, + flow: Sink, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigUInt { + index: StatePartIndex(2), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 20 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: { + SensitivitySet { + id: 42, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + SensitivitySet { + id: 43, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + }, + waiting_sensitivity_sets_by_compiled_value: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 42, + .. + }, + SensitivitySet { + id: 43, + .. + }, + }, + ), + }, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd new file mode 100644 index 00000000..39c2641d --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.vcd @@ -0,0 +1,70 @@ +$timescale 1 ps $end +$scope module sim_resettable_counter $end +$scope struct cd $end +$var wire 1 ! clk $end +$var wire 1 " rst $end +$upscope $end +$var wire 8 # out $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +0" +b0 # +$end +#1000000 +1! +b1 # +#2000000 +0! +1" +#3000000 +1! +b10 # +b0 # +#4000000 +0! +0" +#5000000 +1! +b1 # +#6000000 +0! +#7000000 +1! +b10 # +#8000000 +0! +#9000000 +1! +b11 # +#10000000 +0! +#11000000 +1! +b100 # +#12000000 +0! +1" +#13000000 +1! +b101 # +b0 # +#14000000 +0! +0" +#15000000 +1! +b1 # +#16000000 +0! +#17000000 +1! +b10 # +#18000000 +0! +#19000000 +1! +b11 # +#20000000 +0! diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt new file mode 100644 index 00000000..e6819475 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt @@ -0,0 +1,505 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 3, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", + ty: SyncReset, + }, + SlotDebugData { + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::out", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + 0: Return, + ], + .. + }, + pc: 0, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 3, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.out, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd.clk, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.cd.rst, + Instance { + name: ::sim_resettable_counter, + instantiated: Module { + name: sim_resettable_counter, + .. + }, + }.out, + }, + did_initial_settle: true, + }, + extern_modules: [ + SimulationExternModuleState { + module_state: SimulationModuleState { + base_targets: [ + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + ], + uninitialized_ios: {}, + io_targets: { + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }.clk, + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }.rst, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + }, + did_initial_settle: true, + }, + sim: ExternModuleSimulation { + generator: SimGeneratorFn { + args: ( + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + ), + f: ..., + }, + sim_io_to_generator_map: { + ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }: ModuleIO { + name: sim_resettable_counter::cd, + is_input: true, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + .. + }, + ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }: ModuleIO { + name: sim_resettable_counter::out, + is_input: false, + ty: UInt<8>, + .. + }, + }, + source_location: SourceLocation( + module-XXXXXXXXXX.rs:4:1, + ), + }, + running_generator: Some( + ..., + ), + }, + ], + trace_decls: TraceModule { + name: "sim_resettable_counter", + children: [ + TraceModuleIO { + name: "cd", + child: TraceBundle { + name: "cd", + fields: [ + TraceClock { + location: TraceScalarId(0), + name: "clk", + flow: Source, + }, + TraceSyncReset { + location: TraceScalarId(1), + name: "rst", + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + ty: Bundle { + /* offset = 0 */ + clk: Clock, + /* offset = 1 */ + rst: SyncReset, + }, + flow: Source, + }, + TraceModuleIO { + name: "out", + child: TraceUInt { + location: TraceScalarId(2), + name: "out", + ty: UInt<8>, + flow: Sink, + }, + ty: UInt<8>, + flow: Sink, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigSyncReset { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigUInt { + index: StatePartIndex(2), + ty: UInt<8>, + }, + state: 0x03, + last_state: 0x03, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 20 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: { + SensitivitySet { + id: 43, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + SensitivitySet { + id: 44, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + }, + waiting_sensitivity_sets_by_compiled_value: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 43, + .. + }, + SensitivitySet { + id: 44, + .. + }, + }, + ), + }, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd new file mode 100644 index 00000000..3cb97e24 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.vcd @@ -0,0 +1,70 @@ +$timescale 1 ps $end +$scope module sim_resettable_counter $end +$scope struct cd $end +$var wire 1 ! clk $end +$var wire 1 " rst $end +$upscope $end +$var wire 8 # out $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +1" +b0 # +$end +#1000000 +1! +b1 # +b0 # +#2000000 +0! +#3000000 +1! +b1 # +b0 # +#4000000 +0! +0" +#5000000 +1! +b1 # +#6000000 +0! +#7000000 +1! +b10 # +#8000000 +0! +#9000000 +1! +b11 # +#10000000 +0! +#11000000 +1! +b100 # +#12000000 +0! +1" +#13000000 +1! +b101 # +b0 # +#14000000 +0! +0" +#15000000 +1! +b1 # +#16000000 +0! +#17000000 +1! +b10 # +#18000000 +0! +#19000000 +1! +b11 # +#20000000 +0! From 0b77d1bea0af932a40fd221daf65d5a9b7d62bc5 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 5 Nov 2025 22:44:43 -0800 Subject: [PATCH 05/10] fix Simulator panicking when you use PhantomConst --- crates/fayalite/src/int/uint_in_range.rs | 4 +- crates/fayalite/src/lib.rs | 8 +- crates/fayalite/src/phantom_const.rs | 27 +- crates/fayalite/src/platform/peripherals.rs | 11 +- crates/fayalite/src/sim.rs | 46 ++ crates/fayalite/src/sim/compiler.rs | 86 +-- crates/fayalite/src/sim/vcd.rs | 44 +- crates/fayalite/src/ty/serde_impls.rs | 2 +- crates/fayalite/tests/sim.rs | 38 ++ .../tests/sim/expected/phantom_const.txt | 514 ++++++++++++++++++ .../tests/sim/expected/phantom_const.vcd | 31 ++ 11 files changed, 756 insertions(+), 55 deletions(-) create mode 100644 crates/fayalite/tests/sim/expected/phantom_const.txt create mode 100644 crates/fayalite/tests/sim/expected/phantom_const.vcd diff --git a/crates/fayalite/src/int/uint_in_range.rs b/crates/fayalite/src/int/uint_in_range.rs index 970a439c..65d30927 100644 --- a/crates/fayalite/src/int/uint_in_range.rs +++ b/crates/fayalite/src/int/uint_in_range.rs @@ -300,9 +300,7 @@ macro_rules! define_uint_in_range_type { } } pub fn new(start: Start::SizeType, end: End::SizeType) -> Self { - Self::from_phantom_const_range(PhantomConst::new( - $SerdeRange { start, end }.intern_sized(), - )) + Self::from_phantom_const_range(PhantomConst::new_sized($SerdeRange { start, end })) } pub fn bit_width(self) -> usize { self.value.width() diff --git a/crates/fayalite/src/lib.rs b/crates/fayalite/src/lib.rs index 96ee1f71..156aeed2 100644 --- a/crates/fayalite/src/lib.rs +++ b/crates/fayalite/src/lib.rs @@ -152,7 +152,7 @@ pub use fayalite_proc_macros::hdl_module; /// This allows you to use some computed property of a [`PhantomConst`] to get a [`Type`] that you can use in other #[hdl] types. /// /// ``` -/// # use fayalite::{intern::Intern, prelude::*}; +/// # use fayalite::prelude::*; /// #[derive(Clone, PartialEq, Eq, Hash, Debug, serde::Serialize, serde::Deserialize)] /// pub struct Config { /// pub foo: usize, @@ -172,7 +172,7 @@ pub use fayalite_proc_macros::hdl_module; /// /// // you can then use Fayalite's standard syntax for creating dynamic types at runtime: /// let bar = Bundle::new(Default::default()); -/// let config = PhantomConst::new(Config { foo: 12, bar }.intern_sized()); +/// let config = PhantomConst::new_sized(Config { foo: 12, bar }); /// let ty = WrapMyArray[config]; /// assert_eq!(ty.my_array, Array[bar][12]); /// ``` @@ -182,7 +182,7 @@ pub use fayalite_proc_macros::hdl_module; /// This allows you to use some computed property of a [`PhantomConst`] to get a [`Size`] that you can use in other #[hdl] types. /// /// ``` -/// # use fayalite::{intern::Intern, prelude::*}; +/// # use fayalite::prelude::*; /// # #[derive(Clone, PartialEq, Eq, Hash, Debug, serde::Serialize, serde::Deserialize)] /// # pub struct ConfigItem {} /// # impl ConfigItem { @@ -207,7 +207,7 @@ pub use fayalite_proc_macros::hdl_module; /// } /// /// // you can then use Fayalite's standard syntax for creating dynamic types at runtime: -/// let config = PhantomConst::new(Config { items: vec![ConfigItem::new(); 5] }.intern_sized()); +/// let config = PhantomConst::new_sized(Config { items: vec![ConfigItem::new(); 5] }); /// let ty = FlagPerItem[config]; /// assert_eq!(ty.flags, Array[Bool][5]); /// ``` diff --git a/crates/fayalite/src/phantom_const.rs b/crates/fayalite/src/phantom_const.rs index 9f251665..eb6a7584 100644 --- a/crates/fayalite/src/phantom_const.rs +++ b/crates/fayalite/src/phantom_const.rs @@ -131,7 +131,7 @@ impl Index for PhantomConstWithoutGenerics { type Output = PhantomConst; fn index(&self, value: T) -> &Self::Output { - Interned::into_inner(PhantomConst::new(value.intern()).intern_sized()) + Interned::into_inner(PhantomConst::new(&value).intern_sized()) } } @@ -222,11 +222,26 @@ impl Memoize for PhantomConstCanonicalMemoize PhantomConst { - pub fn new(value: Interned) -> Self { + pub fn new_interned(value: Interned) -> Self { Self { value: LazyInterned::Interned(value), } } + pub fn new_sized(value: T) -> Self + where + T: Clone, + { + Self::new_interned(value.intern_sized()) + } + pub fn new(value: &T) -> Self { + Self::new_interned(value.intern()) + } + pub fn new_deref>(value: U) -> Self + where + T: ToOwned, + { + Self::new_interned(value.intern_deref()) + } pub const fn new_lazy(v: &'static dyn LazyInternedTrait) -> Self { Self { value: LazyInterned::new_lazy(v), @@ -245,7 +260,7 @@ impl PhantomConst { if let Some(&retval) = ::downcast_ref::(&self) { return retval; } - ::new( + ::new_interned( PhantomConstCanonicalMemoize::(PhantomData).get_owned(self.get()), ) } @@ -253,7 +268,7 @@ impl PhantomConst { if let Some(&retval) = ::downcast_ref::(&canonical_type) { return retval; } - Self::new( + Self::new_interned( PhantomConstCanonicalMemoize::(PhantomData).get_owned(canonical_type.get()), ) } @@ -346,7 +361,9 @@ impl<'de, T: ?Sized + PhantomConstValue> Deserialize<'de> for PhantomConst { D: Deserializer<'de>, { match SerdeType::::deserialize(deserializer)? { - SerdeCanonicalType::PhantomConst(SerdePhantomConst(value)) => Ok(Self::new(value)), + SerdeCanonicalType::PhantomConst(SerdePhantomConst(value)) => { + Ok(Self::new_interned(value)) + } ty => Err(Error::invalid_value( serde::de::Unexpected::Other(ty.as_serde_unexpected_str()), &"a PhantomConst", diff --git a/crates/fayalite/src/platform/peripherals.rs b/crates/fayalite/src/platform/peripherals.rs index 90c66402..387142de 100644 --- a/crates/fayalite/src/platform/peripherals.rs +++ b/crates/fayalite/src/platform/peripherals.rs @@ -1,7 +1,7 @@ // SPDX-License-Identifier: LGPL-3.0-or-later // See Notices.txt for copyright information -use crate::{intern::Intern, prelude::*}; +use crate::prelude::*; use ordered_float::NotNan; use serde::{Deserialize, Serialize}; @@ -26,12 +26,9 @@ impl ClockInput { ); Self { clk: Clock, - properties: PhantomConst::new( - ClockInputProperties { - frequency: NotNan::new(frequency).expect("just checked"), - } - .intern_sized(), - ), + properties: PhantomConst::new_sized(ClockInputProperties { + frequency: NotNan::new(frequency).expect("just checked"), + }), } } pub fn frequency(self) -> f64 { diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 5887dee3..b19eeb04 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -416,6 +416,15 @@ impl_trace_decl! { name: Interned, flow: Flow, }), + PhantomConst(TracePhantomConst { + fn location(self) -> _ { + self.location + } + location: TraceLocation, + name: Interned, + ty: PhantomConst, + flow: Flow, + }), SimOnly(TraceSimOnly { fn location(self) -> _ { self.location @@ -526,6 +535,11 @@ pub trait TraceWriter: fmt::Debug + 'static { variant_index: usize, ty: Enum, ) -> Result<(), Self::Error>; + fn set_signal_phantom_const( + &mut self, + id: TraceScalarId, + ty: PhantomConst, + ) -> Result<(), Self::Error>; fn set_signal_sim_only_value( &mut self, id: TraceScalarId, @@ -585,6 +599,11 @@ trait TraceWriterDynTrait: fmt::Debug + 'static { variant_index: usize, ty: Enum, ) -> std::io::Result<()>; + fn set_signal_phantom_const_dyn( + &mut self, + id: TraceScalarId, + ty: PhantomConst, + ) -> std::io::Result<()>; fn set_signal_sim_only_value_dyn( &mut self, id: TraceScalarId, @@ -649,6 +668,13 @@ impl TraceWriterDynTrait for T { .map_err(err_into_io)?, ) } + fn set_signal_phantom_const_dyn( + &mut self, + id: TraceScalarId, + ty: PhantomConst, + ) -> std::io::Result<()> { + Ok(TraceWriter::set_signal_phantom_const(self, id, ty).map_err(err_into_io)?) + } fn set_signal_sim_only_value_dyn( &mut self, id: TraceScalarId, @@ -720,6 +746,13 @@ impl TraceWriter for DynTraceWriter { self.0 .set_signal_enum_discriminant_dyn(id, variant_index, ty) } + fn set_signal_phantom_const( + &mut self, + id: TraceScalarId, + ty: PhantomConst, + ) -> Result<(), Self::Error> { + self.0.set_signal_phantom_const_dyn(id, ty) + } fn set_signal_sim_only_value( &mut self, id: TraceScalarId, @@ -895,12 +928,16 @@ pub(crate) enum SimTraceKind { index: StatePartIndex, ty: DynSimOnly, }, + PhantomConst { + ty: PhantomConst, + }, } #[derive(PartialEq, Eq)] pub(crate) enum SimTraceState { Bits(BitVec), SimOnly(DynSimOnlyValue), + PhantomConst, } impl Clone for SimTraceState { @@ -908,6 +945,7 @@ impl Clone for SimTraceState { match self { Self::Bits(v) => Self::Bits(v.clone()), Self::SimOnly(v) => Self::SimOnly(v.clone()), + Self::PhantomConst => Self::PhantomConst, } } fn clone_from(&mut self, source: &Self) { @@ -956,6 +994,7 @@ impl fmt::Debug for SimTraceState { match self { SimTraceState::Bits(v) => BitSliceWriteWithBase(v).fmt(f), SimTraceState::SimOnly(v) => v.fmt(f), + SimTraceState::PhantomConst => f.debug_tuple("PhantomConst").finish(), } } } @@ -982,6 +1021,7 @@ impl SimTraceKind { SimTraceKind::EnumDiscriminant { index: _, ty } => { SimTraceState::Bits(BitVec::repeat(false, ty.discriminant_bit_width())) } + SimTraceKind::PhantomConst { .. } => SimTraceState::PhantomConst, SimTraceKind::SimOnly { index: _, ty } => SimTraceState::SimOnly(ty.default_value()), } } @@ -1097,6 +1137,7 @@ impl SimulationModuleState { true } } + CompiledTypeLayoutBody::PhantomConst => false, CompiledTypeLayoutBody::Bundle { .. } => { let value = value.map_ty(Bundle::from_canonical); let mut sub_targets = Vec::new(); @@ -1910,6 +1951,9 @@ impl SimulationImpl { ty, )?; } + SimTraceKind::PhantomConst { ty } => { + trace_writer.set_signal_phantom_const(id, ty)? + } SimTraceKind::SimOnly { .. } => { trace_writer.set_signal_sim_only_value(id, state.unwrap_sim_only_ref())? } @@ -1980,6 +2024,7 @@ impl SimulationImpl { .unwrap_bits_mut() .set(0, self.state.small_slots[index] != 0); } + SimTraceKind::PhantomConst { .. } => {} SimTraceKind::SimOnly { index, ty: _ } => { state .unwrap_sim_only_mut() @@ -2545,6 +2590,7 @@ impl SimulationImpl { ); } } + CompiledTypeLayoutBody::PhantomConst => {} CompiledTypeLayoutBody::Bundle { fields } => { let ty = Bundle::from_canonical(compiled_value.layout.ty); for ( diff --git a/crates/fayalite/src/sim/compiler.rs b/crates/fayalite/src/sim/compiler.rs index fbede7b4..98e5abfb 100644 --- a/crates/fayalite/src/sim/compiler.rs +++ b/crates/fayalite/src/sim/compiler.rs @@ -28,8 +28,8 @@ use crate::{ ExternModuleSimulation, SimTrace, SimTraceKind, SimTraces, TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl, TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance, TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, - TraceMemoryLocation, TraceModule, TraceModuleIO, TraceReg, TraceSInt, TraceScalarId, - TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, + TraceMemoryLocation, TraceModule, TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, + TraceScalarId, TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, interpreter::{ Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding, InsnsBuildingDone, InsnsBuildingKind, Label, SmallUInt, StatePartArrayIndex, @@ -85,6 +85,7 @@ pub(crate) struct CompiledBundleField { #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)] pub(crate) enum CompiledTypeLayoutBody { Scalar, + PhantomConst, Array { /// debug names are ignored, use parent's layout instead element: Interned>, @@ -165,14 +166,11 @@ impl CompiledTypeLayout { body: CompiledTypeLayoutBody::Array { element }, } } - CanonicalType::PhantomConst(_) => { - let unit_layout = CompiledTypeLayout::get(()); - CompiledTypeLayout { - ty: *input, - layout: unit_layout.layout, - body: unit_layout.body, - } - } + CanonicalType::PhantomConst(_) => CompiledTypeLayout { + ty: *input, + layout: TypeLayout::empty(), + body: CompiledTypeLayoutBody::PhantomConst, + }, CanonicalType::Bundle(bundle) => { let mut layout = TypeLayout::empty(); let fields = bundle @@ -1681,18 +1679,23 @@ macro_rules! impl_compiler { instantiated_module: InstantiatedModule, target: MakeTraceDeclTarget, source_location: SourceLocation, + empty_kind: impl FnOnce() -> SimTraceKind, $($type_singular_field: impl FnOnce(StatePartIndex<$type_kind>) -> SimTraceKind,)* ) -> TraceLocation { match target { MakeTraceDeclTarget::Expr(target) => { let compiled_value = self.compile_expr(instantiated_module, target); let compiled_value = self.compiled_expr_to_value(compiled_value, source_location); - TraceLocation::Scalar(self.new_sim_trace(match compiled_value.range.len().as_single() { - $(Some(TypeLenSingle::$type_singular_variant) => { - $type_singular_field(compiled_value.range.$type_plural_field.start) - })* - None => unreachable!(), - })) + if compiled_value.range.is_empty() { + TraceLocation::Scalar(self.new_sim_trace(empty_kind())) + } else { + TraceLocation::Scalar(self.new_sim_trace(match compiled_value.range.len().as_single() { + $(Some(TypeLenSingle::$type_singular_variant) => { + $type_singular_field(compiled_value.range.$type_plural_field.start) + })* + None => unreachable!(), + })) + } } MakeTraceDeclTarget::Memory { id, @@ -1723,9 +1726,10 @@ macro_rules! impl_compiler { instantiated_module, target, source_location, + || unreachable!(), |index| SimTraceKind::SmallUInt { index, ty }, |index| SimTraceKind::BigUInt { index, ty }, - |_| unreachable!(""), + |_| unreachable!(), ), name, ty, @@ -1737,9 +1741,10 @@ macro_rules! impl_compiler { instantiated_module, target, source_location, + || unreachable!(), |index| SimTraceKind::SmallSInt { index, ty }, |index| SimTraceKind::BigSInt { index, ty }, - |_| unreachable!(""), + |_| unreachable!(), ), name, ty, @@ -1751,9 +1756,10 @@ macro_rules! impl_compiler { instantiated_module, target, source_location, + || unreachable!(), |index| SimTraceKind::SmallBool { index }, |index| SimTraceKind::BigBool { index }, - |_| unreachable!(""), + |_| unreachable!(), ), name, flow, @@ -1798,15 +1804,16 @@ macro_rules! impl_compiler { } .into() } - CanonicalType::Bundle(_) | CanonicalType::PhantomConst(_) => unreachable!(), + CanonicalType::Bundle(_) => unreachable!(), CanonicalType::AsyncReset(_) => TraceAsyncReset { location: self.make_trace_scalar_helper( instantiated_module, target, source_location, + || unreachable!(), |index| SimTraceKind::SmallAsyncReset { index }, |index| SimTraceKind::BigAsyncReset { index }, - |_| unreachable!(""), + |_| unreachable!(), ), name, flow, @@ -1817,9 +1824,10 @@ macro_rules! impl_compiler { instantiated_module, target, source_location, + || unreachable!(), |index| SimTraceKind::SmallSyncReset { index }, |index| SimTraceKind::BigSyncReset { index }, - |_| unreachable!(""), + |_| unreachable!(), ), name, flow, @@ -1831,21 +1839,38 @@ macro_rules! impl_compiler { instantiated_module, target, source_location, + || unreachable!(), |index| SimTraceKind::SmallClock { index }, |index| SimTraceKind::BigClock { index }, - |_| unreachable!(""), + |_| unreachable!(), ), name, flow, } .into(), + CanonicalType::PhantomConst(ty) => TracePhantomConst { + location: self.make_trace_scalar_helper( + instantiated_module, + target, + source_location, + || SimTraceKind::PhantomConst { ty }, + |_| unreachable!(), + |_| unreachable!(), + |_| unreachable!(), + ), + name, + ty, + flow, + } + .into(), CanonicalType::DynSimOnly(ty) => TraceSimOnly { location: self.make_trace_scalar_helper( instantiated_module, target, source_location, - |_| unreachable!(""), - |_| unreachable!(""), + || unreachable!(), + |_| unreachable!(), + |_| unreachable!(), |index| SimTraceKind::SimOnly { index, ty }, ), name, @@ -2295,16 +2320,10 @@ impl Compiler { | CanonicalType::SyncReset(_) | CanonicalType::Reset(_) | CanonicalType::Clock(_) - | CanonicalType::DynSimOnly(_) => { + | CanonicalType::DynSimOnly(_) + | CanonicalType::PhantomConst(_) => { self.make_trace_scalar(instantiated_module, target, name, source_location) } - CanonicalType::PhantomConst(_) => TraceBundle { - name, - fields: Interned::default(), - ty: Bundle::new(Interned::default()), - flow: target.flow(), - } - .into(), } } fn make_trace_decl( @@ -4293,6 +4312,7 @@ impl Compiler { start += element_bit_width; } } + CompiledTypeLayoutBody::PhantomConst => {} CompiledTypeLayoutBody::Bundle { fields } => { let CompiledTypeLayoutBody::Bundle { fields: mask_fields, diff --git a/crates/fayalite/src/sim/vcd.rs b/crates/fayalite/src/sim/vcd.rs index e66c3ee2..6ba37b31 100644 --- a/crates/fayalite/src/sim/vcd.rs +++ b/crates/fayalite/src/sim/vcd.rs @@ -6,12 +6,14 @@ use crate::{ expr::Flow, int::UInt, intern::{Intern, Interned}, + prelude::PhantomConst, sim::{ TraceArray, TraceAsyncReset, TraceBool, TraceBundle, TraceClock, TraceDecl, TraceEnumDiscriminant, TraceEnumWithFields, TraceFieldlessEnum, TraceInstance, TraceLocation, TraceMem, TraceMemPort, TraceMemoryId, TraceMemoryLocation, TraceModule, - TraceModuleIO, TraceReg, TraceSInt, TraceScalar, TraceScalarId, TraceScope, TraceSimOnly, - TraceSyncReset, TraceUInt, TraceWire, TraceWriter, TraceWriterDecls, + TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, TraceScalar, TraceScalarId, + TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, TraceWriter, + TraceWriterDecls, time::{SimDuration, SimInstant}, value::DynSimOnlyValue, }, @@ -283,6 +285,7 @@ impl WriteTrace for TraceScalar { Self::Clock(v) => v.write_trace(writer, arg), Self::SyncReset(v) => v.write_trace(writer, arg), Self::AsyncReset(v) => v.write_trace(writer, arg), + Self::PhantomConst(v) => v.write_trace(writer, arg), Self::SimOnly(v) => v.write_trace(writer, arg), } } @@ -549,6 +552,33 @@ impl WriteTrace for TraceAsyncReset { } } +impl WriteTrace for TracePhantomConst { + fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { + let ArgInType { + source_var_type: _, + sink_var_type: _, + duplex_var_type: _, + properties, + scope, + } = arg.in_type(); + let Self { + location, + name, + ty: _, + flow: _, + } = self; + write_vcd_var( + properties, + MemoryElementPartBody::Scalar, + writer, + "string", + 1, + location, + scope.new_identifier(name), + ) + } +} + impl WriteTrace for TraceSimOnly { fn write_trace(self, writer: &mut W, mut arg: A) -> io::Result<()> { let ArgInType { @@ -1091,6 +1121,16 @@ impl TraceWriter for VcdWriter { write_enum_discriminant_value_change(&mut self.writer, variant_index, ty, id.as_usize()) } + fn set_signal_phantom_const( + &mut self, + id: TraceScalarId, + ty: PhantomConst, + ) -> Result<(), Self::Error> { + // avoid multi-line strings because GTKWave can't display them properly: + // https://github.com/gtkwave/gtkwave/issues/460 + write_string_value_change(&mut self.writer, format_args!("{ty:?}"), id.as_usize()) + } + fn set_signal_sim_only_value( &mut self, id: TraceScalarId, diff --git a/crates/fayalite/src/ty/serde_impls.rs b/crates/fayalite/src/ty/serde_impls.rs index 1ca916b7..af324f9f 100644 --- a/crates/fayalite/src/ty/serde_impls.rs +++ b/crates/fayalite/src/ty/serde_impls.rs @@ -127,7 +127,7 @@ impl From for CanonicalType { SerdeCanonicalType::Reset => Self::Reset(Reset), SerdeCanonicalType::Clock => Self::Clock(Clock), SerdeCanonicalType::PhantomConst(value) => { - Self::PhantomConst(PhantomConst::new(value.0)) + Self::PhantomConst(PhantomConst::new_interned(value.0)) } SerdeCanonicalType::DynSimOnly(value) => Self::DynSimOnly(value), } diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index 1f452c92..75f7cef4 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -2244,3 +2244,41 @@ fn test_sim_resettable_counter_async_immediate_reset() { panic!(); } } + +#[hdl_module(outline_generated)] +pub fn phantom_const() { + #[hdl] + let out: Array>, 2> = + m.output(Array::new_static(PhantomConst::new_sized(vec![ + "a".into(), + "b".into(), + ]))); + let _ = out; + #[hdl] + let mut mem = memory(PhantomConst::new("mem_element")); + mem.depth(1); + let port = mem.new_read_port(); + connect_any(port.addr, 0u8); + connect(port.clk, false.to_clock()); + connect(port.en, false); +} + +#[test] +fn test_phantom_const() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut sim = Simulation::new(phantom_const()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + sim.advance_time(SimDuration::from_micros(1)); + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/phantom_const.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/phantom_const.txt") { + panic!(); + } +} diff --git a/crates/fayalite/tests/sim/expected/phantom_const.txt b/crates/fayalite/tests/sim/expected/phantom_const.txt new file mode 100644 index 00000000..dbc8f129 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/phantom_const.txt @@ -0,0 +1,514 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 5, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 7, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.addr", + ty: UInt<0>, + }, + SlotDebugData { + name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.en", + ty: Bool, + }, + SlotDebugData { + name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.clk", + ty: Clock, + }, + SlotDebugData { + name: "", + ty: UInt<8>, + }, + SlotDebugData { + name: "", + ty: UInt<0>, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 1, + debug_data: [ + (), + ], + layout_data: [ + MemoryData { + array_type: Array, + data: [ + // len = 0x1 + [0x0]: 0x0, + ], + }, + ], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + 0: Const { + dest: StatePartIndex(5), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + 1: Copy { + dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Clock }, + src: StatePartIndex(5), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:6:1 + 2: Copy { + dest: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.clk", ty: Clock }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:7:1 + 3: Copy { + dest: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.en", ty: Bool }, + src: StatePartIndex(5), // (0x0) SlotDebugData { name: "", ty: Bool }, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 4: Const { + dest: StatePartIndex(3), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + value: 0x0, + }, + 5: CastToUInt { + dest: StatePartIndex(4), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(3), // (0x0) SlotDebugData { name: "", ty: UInt<8> }, + dest_width: 0, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 6: Copy { + dest: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.addr", ty: UInt<0> }, + src: StatePartIndex(4), // (0x0) SlotDebugData { name: "", ty: UInt<0> }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 7: CastBigToArrayIndex { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: UInt<0> }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.addr", ty: UInt<0> }, + }, + 8: IsNonZeroDestIsSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.en", ty: Bool }, + }, + 9: BranchIfSmallZero { + target: 11, + value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 10: Branch { + target: 11, + }, + 11: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(phantom_const: phantom_const).phantom_const::mem::r0.clk", ty: Clock }, + }, + 12: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 13: BranchIfSmallZero { + target: 14, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 14: XorSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 15: Return, + ], + .. + }, + pc: 15, + memory_write_log: [], + memories: StatePart { + value: [ + MemoryData { + array_type: Array, + data: [ + // len = 0x1 + [0x0]: 0x0, + ], + }, + ], + }, + small_slots: StatePart { + value: [ + 1, + 0, + 0, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::phantom_const, + instantiated: Module { + name: phantom_const, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::phantom_const, + instantiated: Module { + name: phantom_const, + .. + }, + }.out, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::phantom_const, + instantiated: Module { + name: phantom_const, + .. + }, + }.out, + Instance { + name: ::phantom_const, + instantiated: Module { + name: phantom_const, + .. + }, + }.out[0], + Instance { + name: ::phantom_const, + instantiated: Module { + name: phantom_const, + .. + }, + }.out[1], + }, + did_initial_settle: true, + }, + extern_modules: [], + trace_decls: TraceModule { + name: "phantom_const", + children: [ + TraceModuleIO { + name: "out", + child: TraceArray { + name: "out", + elements: [ + TracePhantomConst { + location: TraceScalarId(0), + name: "[0]", + ty: PhantomConst( + ["a","b"], + ), + flow: Sink, + }, + TracePhantomConst { + location: TraceScalarId(1), + name: "[1]", + ty: PhantomConst( + ["a","b"], + ), + flow: Sink, + }, + ], + ty: Array, + flow: Sink, + }, + ty: Array, + flow: Sink, + }, + TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 0, + element_type: TracePhantomConst { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 0, + start: 0, + len: 0, + }, + name: "mem", + ty: PhantomConst( + "mem_element", + ), + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(2), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(3), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(4), + name: "clk", + flow: Sink, + }, + TracePhantomConst { + location: TraceScalarId(5), + name: "data", + ty: PhantomConst( + "mem_element", + ), + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: PhantomConst( + "mem_element", + ), + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: PhantomConst( + "mem_element", + ), + }, + }, + ], + array_type: Array, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: PhantomConst { + ty: PhantomConst( + ["a","b"], + ), + }, + state: PhantomConst, + last_state: PhantomConst, + }, + SimTrace { + id: TraceScalarId(1), + kind: PhantomConst { + ty: PhantomConst( + ["a","b"], + ), + }, + state: PhantomConst, + last_state: PhantomConst, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigUInt { + index: StatePartIndex(0), + ty: UInt<0>, + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigBool { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigClock { + index: StatePartIndex(2), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(5), + kind: PhantomConst { + ty: PhantomConst( + "mem_element", + ), + }, + state: PhantomConst, + last_state: PhantomConst, + }, + ], + trace_memories: { + StatePartIndex(0): TraceMem { + id: TraceMemoryId(0), + name: "mem", + stride: 0, + element_type: TracePhantomConst { + location: TraceMemoryLocation { + id: TraceMemoryId(0), + depth: 1, + stride: 0, + start: 0, + len: 0, + }, + name: "mem", + ty: PhantomConst( + "mem_element", + ), + flow: Duplex, + }, + ports: [ + TraceMemPort { + name: "r0", + bundle: TraceBundle { + name: "r0", + fields: [ + TraceUInt { + location: TraceScalarId(2), + name: "addr", + ty: UInt<0>, + flow: Sink, + }, + TraceBool { + location: TraceScalarId(3), + name: "en", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(4), + name: "clk", + flow: Sink, + }, + TracePhantomConst { + location: TraceScalarId(5), + name: "data", + ty: PhantomConst( + "mem_element", + ), + flow: Source, + }, + ], + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: PhantomConst( + "mem_element", + ), + }, + flow: Sink, + }, + ty: Bundle { + /* offset = 0 */ + addr: UInt<0>, + /* offset = 0 */ + en: Bool, + /* offset = 1 */ + clk: Clock, + #[hdl(flip)] /* offset = 2 */ + data: PhantomConst( + "mem_element", + ), + }, + }, + ], + array_type: Array, + }, + }, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(1), + ], + event_queue: EventQueue(EventQueueData { + instant: 1 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: {}, + waiting_sensitivity_sets_by_compiled_value: {}, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/phantom_const.vcd b/crates/fayalite/tests/sim/expected/phantom_const.vcd new file mode 100644 index 00000000..ba3869b8 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/phantom_const.vcd @@ -0,0 +1,31 @@ +$timescale 1 ps $end +$scope module phantom_const $end +$scope struct out $end +$var string 1 ! \[0] $end +$var string 1 " \[1] $end +$upscope $end +$scope struct mem $end +$scope struct contents $end +$scope struct \[0] $end +$var string 1 ' mem $end +$upscope $end +$upscope $end +$scope struct r0 $end +$var string 0 # addr $end +$var wire 1 $ en $end +$var wire 1 % clk $end +$var string 1 & data $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +s0 ' +sPhantomConst([\"a\",\"b\"]) ! +sPhantomConst([\"a\",\"b\"]) " +s0 # +0$ +0% +sPhantomConst(\"mem_element\") & +$end +#1000000 From 26a709017873c47d2d7d81efb8d2159fd04fd928 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 6 Nov 2025 20:22:53 -0800 Subject: [PATCH 06/10] add ParsedVisibility --- .../src/hdl_type_common.rs | 121 ++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs index f5b353e0..3a0e5e9e 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_type_common.rs @@ -4612,3 +4612,124 @@ impl MakeHdlTypeExpr for ParsedTypeTuple { }) } } + +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +pub(crate) enum ParsedSimpleVisibility { + Public(Token![pub]), + PubCrate { + pub_token: Token![pub], + paren_token: Paren, + crate_token: Token![crate], + }, + Inherited, +} + +impl From for Visibility { + fn from(value: ParsedSimpleVisibility) -> Self { + match value { + ParsedSimpleVisibility::Public(v) => Visibility::Public(v), + ParsedSimpleVisibility::PubCrate { + pub_token, + paren_token, + crate_token, + } => Visibility::Restricted(syn::VisRestricted { + pub_token, + paren_token, + in_token: None, + path: Box::new(Ident::new("crate", crate_token.span).into()), + }), + ParsedSimpleVisibility::Inherited => Visibility::Inherited, + } + } +} + +impl PartialOrd for ParsedSimpleVisibility { + fn partial_cmp(&self, other: &Self) -> Option { + Some(self.cmp(other)) + } +} + +impl Ord for ParsedSimpleVisibility { + fn cmp(&self, other: &Self) -> std::cmp::Ordering { + self.visibility_level().cmp(&other.visibility_level()) + } +} + +impl ParsedSimpleVisibility { + const VISIBILITY_LEVEL_INHERITED: u8 = 0; + const VISIBILITY_LEVEL_RESTRICTED: u8 = 1 + Self::VISIBILITY_LEVEL_INHERITED; + const VISIBILITY_LEVEL_PUB_CRATE: u8 = 1 + Self::VISIBILITY_LEVEL_RESTRICTED; + const VISIBILITY_LEVEL_PUB: u8 = 1 + Self::VISIBILITY_LEVEL_PUB_CRATE; + fn visibility_level(self) -> u8 { + match self { + Self::Public(_) => Self::VISIBILITY_LEVEL_PUB, + Self::PubCrate { .. } => Self::VISIBILITY_LEVEL_PUB_CRATE, + Self::Inherited => Self::VISIBILITY_LEVEL_INHERITED, + } + } + pub(crate) fn parse(vis: Visibility) -> Result { + match vis { + Visibility::Public(v) => Ok(Self::Public(v)), + Visibility::Restricted(syn::VisRestricted { + pub_token, + paren_token, + in_token: None, + path, + }) if path.is_ident("crate") => Ok(Self::PubCrate { + pub_token, + paren_token, + crate_token: Token![crate](path.get_ident().expect("just checked").span()), + }), + Visibility::Restricted(v) => Err(v), + Visibility::Inherited => Ok(Self::Inherited), + } + } +} + +#[derive(Clone, Debug, PartialEq, Eq)] +pub(crate) enum ParsedVisibility { + Simple(ParsedSimpleVisibility), + Restricted(syn::VisRestricted), +} + +impl From for Visibility { + fn from(value: ParsedVisibility) -> Self { + match value { + ParsedVisibility::Simple(v) => v.into(), + ParsedVisibility::Restricted(v) => Visibility::Restricted(v), + } + } +} + +impl PartialOrd for ParsedVisibility { + fn partial_cmp(&self, other: &Self) -> Option { + match (self, other) { + (ParsedVisibility::Simple(l), ParsedVisibility::Simple(r)) => Some(l.cmp(r)), + (ParsedVisibility::Simple(l), ParsedVisibility::Restricted(_)) => Some( + l.visibility_level() + .cmp(&ParsedSimpleVisibility::VISIBILITY_LEVEL_RESTRICTED), + ), + (ParsedVisibility::Restricted(_), ParsedVisibility::Simple(r)) => { + Some(ParsedSimpleVisibility::VISIBILITY_LEVEL_RESTRICTED.cmp(&r.visibility_level())) + } + (ParsedVisibility::Restricted(l), ParsedVisibility::Restricted(r)) => { + (l == r).then_some(std::cmp::Ordering::Equal) + } + } + } +} + +impl ParsedVisibility { + #[allow(dead_code)] + pub(crate) fn parse(vis: Visibility) -> Self { + match ParsedSimpleVisibility::parse(vis) { + Ok(simple) => Self::Simple(simple), + Err(restricted) => Self::Restricted(restricted), + } + } + #[allow(dead_code)] + pub(crate) fn min<'a>(&'a self, other: &'a Self) -> Option<&'a Self> { + self.partial_cmp(other) + .map(|ord| if ord.is_lt() { self } else { other }) + } +} From fbc8ffa5aea6cc76d643880cd21a34993fb1ec4f Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 6 Nov 2025 20:23:16 -0800 Subject: [PATCH 07/10] fix private fields in #[hdl] pub struct --- .../src/hdl_bundle.rs | 11 ++----- crates/fayalite/src/bundle.rs | 25 ++++++---------- crates/fayalite/src/int/uint_in_range.rs | 2 -- crates/fayalite/tests/hdl_types.rs | 30 +++++++++++++++++++ 4 files changed, 42 insertions(+), 26 deletions(-) diff --git a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs index e8dc51bf..f952f426 100644 --- a/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs +++ b/crates/fayalite-proc-macros-impl/src/hdl_bundle.rs @@ -224,7 +224,7 @@ impl Builder { .args .push_value(match get_field_state(field_index) { BuilderFieldState::Unfilled => parse_quote_spanned! {self.ident.span()=> - ::fayalite::bundle::Unfilled<#ty> + () }, BuilderFieldState::Generic => { let type_var = type_var_for_field_name(ident); @@ -383,7 +383,7 @@ impl ToTokens for Builder { fn default() -> Self { #ident { #phantom_field_name: ::fayalite::__std::marker::PhantomData, - #(#field_idents: ::fayalite::__std::default::Default::default(),)* + #(#field_idents: (),)* } } } @@ -395,7 +395,7 @@ impl ToTokens for Builder { let type_generics = self.generics.split_for_impl().1; quote_spanned! {self.ident.span()=> #[automatically_derived] - #[allow(non_camel_case_types, dead_code)] + #[allow(non_camel_case_types, dead_code, private_interfaces)] impl #filled_impl_generics ::fayalite::expr::ToExpr for #filled_ty #filled_where_clause { @@ -499,7 +499,6 @@ impl ToTokens for ParsedBundle { }; builder.to_tokens(tokens); let unfilled_builder_ty = builder.builder_struct_ty(|_| BuilderFieldState::Unfilled); - let filled_builder_ty = builder.builder_struct_ty(|_| BuilderFieldState::Filled); let mut mask_type_fields = FieldsNamed::from(fields.clone()); for Field { ty, .. } in &mut mask_type_fields.named { *ty = parse_quote_spanned! {span=> @@ -517,8 +516,6 @@ impl ToTokens for ParsedBundle { mask_type_builder.to_tokens(tokens); let unfilled_mask_type_builder_ty = mask_type_builder.builder_struct_ty(|_| BuilderFieldState::Unfilled); - let filled_mask_type_builder_ty = - mask_type_builder.builder_struct_ty(|_| BuilderFieldState::Filled); ItemStruct { attrs: vec![ common_derives(span), @@ -785,7 +782,6 @@ impl ToTokens for ParsedBundle { #where_clause { type Builder = #unfilled_mask_type_builder_ty; - type FilledBuilder = #filled_mask_type_builder_ty; fn fields(&#self_token) -> ::fayalite::intern::Interned<[::fayalite::bundle::BundleField]> { ::fayalite::intern::Intern::intern(&[#(#fields_body_fields)*][..]) } @@ -935,7 +931,6 @@ impl ToTokens for ParsedBundle { #where_clause { type Builder = #unfilled_builder_ty; - type FilledBuilder = #filled_builder_ty; fn fields(&#self_token) -> ::fayalite::intern::Interned<[::fayalite::bundle::BundleField]> { ::fayalite::intern::Intern::intern(&[#(#fields_body_fields)*][..]) } diff --git a/crates/fayalite/src/bundle.rs b/crates/fayalite/src/bundle.rs index a0de189f..0edf1928 100644 --- a/crates/fayalite/src/bundle.rs +++ b/crates/fayalite/src/bundle.rs @@ -271,7 +271,6 @@ impl Type for Bundle { pub trait BundleType: Type { type Builder: Default; - type FilledBuilder: ToExpr; fn fields(&self) -> Interned<[BundleField]>; } @@ -374,17 +373,8 @@ impl<'a> BundleSimValueToOpaque<'a> { #[derive(Default)] pub struct NoBuilder; -pub struct Unfilled(PhantomData); - -impl Default for Unfilled { - fn default() -> Self { - Self(PhantomData) - } -} - impl BundleType for Bundle { type Builder = NoBuilder; - type FilledBuilder = Expr; fn fields(&self) -> Interned<[BundleField]> { self.0.fields } @@ -420,15 +410,14 @@ macro_rules! impl_tuple_builder_fields { ) => { impl< $($head_type_var,)* - $cur_type_var: Type, $($tail_type_var,)* > TupleBuilder<( $($head_type_var,)* - Unfilled<$cur_type_var>, + (), $($tail_type_var,)* )> { - pub fn $cur_field(self, $cur_var: impl ToExpr) -> TupleBuilder<( + pub fn $cur_field<$cur_type_var: Type>(self, $cur_var: impl ToExpr) -> TupleBuilder<( $($head_type_var,)* Expr<$cur_type_var>, $($tail_type_var,)* @@ -452,6 +441,12 @@ macro_rules! impl_tuple_builder_fields { ($global:tt []) => {}; } +macro_rules! get_unit_ty { + ($($tt:tt)*) => { + () + }; +} + macro_rules! impl_tuples { ( [$({ @@ -545,8 +540,7 @@ macro_rules! impl_tuples { } } impl<$($T: Type,)*> BundleType for ($($T,)*) { - type Builder = TupleBuilder<($(Unfilled<$T>,)*)>; - type FilledBuilder = TupleBuilder<($(Expr<$T>,)*)>; + type Builder = TupleBuilder<($(get_unit_ty!($T),)*)>; fn fields(&self) -> Interned<[BundleField]> { let ($($var,)*) = self; [$(BundleField { name: stringify!($num).intern(), flipped: false, ty: $var.canonical() }),*].intern_slice() @@ -791,7 +785,6 @@ impl ToExpr for PhantomDataBuilder { impl BundleType for PhantomData { type Builder = PhantomDataBuilder; - type FilledBuilder = PhantomDataBuilder; fn fields(&self) -> Interned<[BundleField]> { Interned::default() } diff --git a/crates/fayalite/src/int/uint_in_range.rs b/crates/fayalite/src/int/uint_in_range.rs index 65d30927..4ed101ec 100644 --- a/crates/fayalite/src/int/uint_in_range.rs +++ b/crates/fayalite/src/int/uint_in_range.rs @@ -96,7 +96,6 @@ impl Type for UIntInRangeMaskType { impl BundleType for UIntInRangeMaskType { type Builder = NoBuilder; - type FilledBuilder = Expr; fn fields(&self) -> Interned<[BundleField]> { let [value_name, range_name] = UINT_IN_RANGE_TYPE_FIELD_NAMES; @@ -400,7 +399,6 @@ macro_rules! define_uint_in_range_type { impl BundleType for $UIntInRangeType { type Builder = NoBuilder; - type FilledBuilder = Expr; fn fields(&self) -> Interned<[BundleField]> { let [value_name, range_name] = UINT_IN_RANGE_TYPE_FIELD_NAMES; diff --git a/crates/fayalite/tests/hdl_types.rs b/crates/fayalite/tests/hdl_types.rs index 148cb642..50302827 100644 --- a/crates/fayalite/tests/hdl_types.rs +++ b/crates/fayalite/tests/hdl_types.rs @@ -214,3 +214,33 @@ pub struct MyTypeWithPhantomConstParameter>, pub b: HdlOption>, } + +#[hdl(outline_generated)] +struct MyPrivateType {} + +#[hdl(outline_generated)] +pub(crate) struct MyPubCrateType {} + +#[hdl(outline_generated)] +pub struct MyTypeWithPrivateMembers { + a: MyPrivateType, + pub(crate) b: MyPubCrateType, + pub c: Bool, +} + +#[hdl(outline_generated)] +struct MyPrivateTypeWithArg { + v: T, +} + +#[hdl(outline_generated)] +pub(crate) struct MyPubCrateTypeWithArg { + v: T, +} + +#[hdl(outline_generated)] +pub struct MyTypeWithPrivateMembersWithArg { + a: MyPrivateTypeWithArg, + pub(crate) b: MyPubCrateTypeWithArg, + pub c: T, +} From 45fea70c1841aedbb32377d88c0280c7a83e6208 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 7 Nov 2025 02:18:43 -0800 Subject: [PATCH 08/10] add ExternModuleSimulationState::fork_join_scope --- crates/fayalite/src/sim.rs | 243 ++- crates/fayalite/tests/sim.rs | 93 ++ .../sim/expected/sim_fork_join_scope.txt | 523 ++++++ .../sim/expected/sim_fork_join_scope.vcd | 1467 +++++++++++++++++ 4 files changed, 2325 insertions(+), 1 deletion(-) create mode 100644 crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt create mode 100644 crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index b19eeb04..01233cb2 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -49,7 +49,7 @@ use std::{ any::Any, borrow::Cow, cell::{Cell, RefCell}, - collections::BTreeMap, + collections::{BTreeMap, BTreeSet}, fmt, future::{Future, IntoFuture}, hash::Hash, @@ -3347,6 +3347,128 @@ impl ExternModuleSimulationState { module_index, } } + pub async fn fork_join_scope<'env, F, Fut>( + &mut self, + in_scope: F, + ) -> ::Output + where + F: FnOnce(ForkJoinScope<'env>, ExternModuleSimulationState) -> Fut, + Fut: IntoFuture>, + { + let scope = ForkJoinScope { + new_tasks: Rc::new(RefCell::new(vec![])), + sim: self.forked_state(), + }; + let join_handle = scope.spawn(in_scope); + #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug)] + struct TaskId(u64); + struct TasksStateInner { + next_task_id: u64, + ready_tasks: BTreeSet, + not_ready_tasks: BTreeSet, + base_waker: std::task::Waker, + } + impl Default for TasksStateInner { + fn default() -> Self { + Self { + next_task_id: Default::default(), + ready_tasks: Default::default(), + not_ready_tasks: Default::default(), + base_waker: std::task::Waker::noop().clone(), + } + } + } + #[derive(Default)] + struct TasksState { + inner: Mutex, + } + #[derive(Clone)] + struct TaskWaker { + state: std::sync::Weak, + task: TaskId, + } + impl std::task::Wake for TaskWaker { + fn wake(self: Arc) { + self.wake_by_ref(); + } + fn wake_by_ref(self: &Arc) { + let Some(state) = self.state.upgrade() else { + return; + }; + let mut inner = state.inner.lock().expect("not poisoned"); + if inner.not_ready_tasks.remove(&self.task) { + inner.ready_tasks.insert(self.task); + inner.base_waker.wake_by_ref(); + } + } + } + struct Task<'env> { + task: Pin + 'env>>, + waker: std::task::Waker, + } + let mut tasks: BTreeMap = BTreeMap::new(); + let tasks_state = Arc::new(TasksState::default()); + std::future::poll_fn(move |cx: &mut std::task::Context<'_>| { + let mut state_inner = tasks_state.inner.lock().expect("not poisoned"); + state_inner.base_waker.clone_from(cx.waker()); + loop { + for new_task in scope.new_tasks.borrow_mut().drain(..) { + let task_id = TaskId(state_inner.next_task_id); + let Some(next_task_id) = state_inner.next_task_id.checked_add(1) else { + drop(state_inner); + panic!("spawned too many tasks"); + }; + state_inner.next_task_id = next_task_id; + state_inner.ready_tasks.insert(task_id); + tasks.insert( + task_id, + Task { + task: new_task, + waker: Arc::new(TaskWaker { + state: Arc::downgrade(&tasks_state), + task: task_id, + }) + .into(), + }, + ); + } + let Some(task_id) = state_inner.ready_tasks.pop_first() else { + if state_inner.not_ready_tasks.is_empty() { + return Poll::Ready(()); + } else { + return Poll::Pending; + }; + }; + state_inner.not_ready_tasks.insert(task_id); // task can be woken while we're running poll + drop(state_inner); + let std::collections::btree_map::Entry::Occupied(mut entry) = tasks.entry(task_id) + else { + unreachable!(); + }; + let Task { task, waker } = entry.get_mut(); + match task.as_mut().poll(&mut std::task::Context::from_waker( + &std::task::Waker::from(waker.clone()), + )) { + Poll::Pending => { + state_inner = tasks_state.inner.lock().expect("not poisoned"); + continue; + } + Poll::Ready(()) => {} + } + drop(entry.remove()); // drop outside lock + state_inner = tasks_state.inner.lock().expect("not poisoned"); + state_inner.not_ready_tasks.remove(&task_id); + state_inner.ready_tasks.remove(&task_id); + } + }) + .await; + match &mut *join_handle.state.borrow_mut() { + JoinHandleState::Running(_) => unreachable!(), + JoinHandleState::Finished(state) => state + .take() + .expect("filled by running all futures to completion"), + } + } impl_simulation_methods!( async_await = (async, await), track_caller = (), @@ -3354,6 +3476,125 @@ impl ExternModuleSimulationState { ); } +pub struct ForkJoinScope<'env> { + new_tasks: Rc + 'env>>>>>, + sim: ExternModuleSimulationState, +} + +impl<'env> Clone for ForkJoinScope<'env> { + fn clone(&self) -> Self { + Self { + new_tasks: self.new_tasks.clone(), + sim: self.sim.forked_state(), + } + } +} + +impl<'env> ForkJoinScope<'env> { + fn spawn_inner(&self, fut: Pin + 'env>>) { + self.new_tasks.borrow_mut().push(fut); + } + pub fn spawn_detached_future( + &self, + fut: impl IntoFuture>, + ) { + self.spawn_inner(Box::pin(fut.into_future())); + } + pub fn spawn_detached(&self, f: F) + where + F: FnOnce(ForkJoinScope<'env>, ExternModuleSimulationState) -> Fut, + Fut: IntoFuture>, + { + self.spawn_detached_future(f(self.clone(), self.sim.forked_state())); + } + pub fn spawn(&self, f: F) -> JoinHandle + where + F: FnOnce(ForkJoinScope<'env>, ExternModuleSimulationState) -> Fut, + Fut: IntoFuture>, + { + let join_handle = JoinHandle { + state: Default::default(), + }; + let state = Rc::downgrade(&join_handle.state); + let fut = f(self.clone(), self.sim.forked_state()).into_future(); + self.spawn_detached_future(async move { + let result = fut.await; + let Some(state) = state.upgrade() else { return }; + let mut state = state.borrow_mut(); + let waker = match &mut *state { + JoinHandleState::Running(waker) => waker.take(), + JoinHandleState::Finished(_) => unreachable!(), + }; + *state = JoinHandleState::Finished(Some(result)); + drop(state); + let Some(waker) = waker else { return }; + waker.wake(); + }); + join_handle + } +} + +enum JoinHandleState { + Running(Option), + Finished(Option), +} + +impl Default for JoinHandleState { + fn default() -> Self { + Self::Running(None) + } +} + +pub struct JoinHandle { + state: Rc>>, +} + +impl JoinHandle { + pub fn is_finished(&self) -> bool { + matches!(*self.state.borrow(), JoinHandleState::Finished(_)) + } + pub fn try_join(self) -> Result { + let mut state = self.state.borrow_mut(); + match &mut *state { + JoinHandleState::Running(_) => { + drop(state); + Err(self) + } + JoinHandleState::Finished(retval) => { + let Some(retval) = retval.take() else { + panic!("already returned the value in poll"); + }; + Ok(retval) + } + } + } + pub async fn join(self) -> T { + self.await + } +} + +impl Future for JoinHandle { + type Output = T; + + fn poll(self: Pin<&mut Self>, cx: &mut std::task::Context<'_>) -> Poll { + match &mut *self.state.borrow_mut() { + JoinHandleState::Running(waker) => { + match waker { + None => *waker = Some(cx.waker().clone()), + Some(waker) => waker.clone_from(cx.waker()), + } + Poll::Pending + } + JoinHandleState::Finished(retval) => { + let Some(retval) = retval.take() else { + panic!("already returned Poll::Ready"); + }; + Poll::Ready(retval) + } + } + } +} + struct ForkJoinImpl<'a> { futures: Vec + 'a>>>, } diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index 75f7cef4..6d0380ba 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -2109,6 +2109,99 @@ fn test_sim_fork_join() { } } +#[hdl_module(outline_generated, extern)] +pub fn sim_fork_join_scope() +where + ConstUsize: KnownSize, +{ + #[hdl] + let clocks: Array = m.input(); + #[hdl] + let outputs: Array, N> = m.output(); + m.extern_module_simulation_fn((clocks, outputs), |(clocks, outputs), mut sim| async move { + sim.write(outputs, [0u8; N]).await; + loop { + let written = vec![std::cell::Cell::new(false); N]; // test shared scope + let written = &written; // work around move in async move + sim.fork_join_scope(|scope, _| async move { + let mut spawned = vec![]; + for i in 0..N { + let join_handle = + scope.spawn(move |_, mut sim: ExternModuleSimulationState| async move { + sim.wait_for_clock_edge(clocks[i]).await; + let v = sim + .read_bool_or_int(outputs[i]) + .await + .to_bigint() + .try_into() + .expect("known to be in range"); + sim.write(outputs[i], 1u8.wrapping_add(v)).await; + written[i].set(true); + i + }); + if i % 2 == 0 && i < N - 1 { + spawned.push((i, join_handle)); + } + } + for (i, join_handle) in spawned { + assert_eq!(i, join_handle.join().await); + } + }) + .await; + for written in written { + assert!(written.get()); + } + } + }); +} + +#[test] +fn test_sim_fork_join_scope() { + let _n = SourceLocation::normalize_files_for_tests(); + const N: usize = 3; + let mut sim = Simulation::new(sim_fork_join_scope::()); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + sim.write(sim.io().clocks, [false; N]); + let mut clocks_triggered = [false; N]; + let mut expected = [0u8; N]; + for i0 in 0..N { + for i1 in 0..N { + for i2 in 0..N { + for i3 in 0..N { + let indexes = [i0, i1, i2, i3]; + for i in indexes { + sim.advance_time(SimDuration::from_micros(1)); + sim.write(sim.io().clocks[i], true); + sim.advance_time(SimDuration::from_micros(1)); + sim.write(sim.io().clocks[i], false); + if !clocks_triggered[i] { + expected[i] = expected[i].wrapping_add(1); + } + clocks_triggered[i] = true; + if clocks_triggered == [true; N] { + clocks_triggered = [false; N]; + } + let output = sim.read(sim.io().outputs); + assert_eq!(output, expected.to_sim_value(), "indexes={indexes:?} i={i}"); + } + } + } + } + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/sim_fork_join_scope.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/sim_fork_join_scope.txt") { + panic!(); + } +} + #[hdl_module(outline_generated, extern)] pub fn sim_resettable_counter() { #[hdl] diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt new file mode 100644 index 00000000..ba5577d4 --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt @@ -0,0 +1,523 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 6, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::outputs[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::outputs[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::outputs[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:1:1 + 0: Return, + ], + .. + }, + pc: 0, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 0, + 49, + 50, + 50, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::sim_fork_join_scope, + instantiated: Module { + name: sim_fork_join_scope, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::sim_fork_join_scope, + instantiated: Module { + name: sim_fork_join_scope, + .. + }, + }.clocks, + Instance { + name: ::sim_fork_join_scope, + instantiated: Module { + name: sim_fork_join_scope, + .. + }, + }.outputs, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::sim_fork_join_scope, + instantiated: Module { + name: sim_fork_join_scope, + .. + }, + }.clocks, + Instance { + name: ::sim_fork_join_scope, + instantiated: Module { + name: sim_fork_join_scope, + .. + }, + }.clocks[0], + Instance { + name: ::sim_fork_join_scope, + instantiated: Module { + name: sim_fork_join_scope, + .. + }, + }.clocks[1], + Instance { + name: ::sim_fork_join_scope, + instantiated: Module { + name: sim_fork_join_scope, + .. + }, + }.clocks[2], + Instance { + name: ::sim_fork_join_scope, + instantiated: Module { + name: sim_fork_join_scope, + .. + }, + }.outputs, + Instance { + name: ::sim_fork_join_scope, + instantiated: Module { + name: sim_fork_join_scope, + .. + }, + }.outputs[0], + Instance { + name: ::sim_fork_join_scope, + instantiated: Module { + name: sim_fork_join_scope, + .. + }, + }.outputs[1], + Instance { + name: ::sim_fork_join_scope, + instantiated: Module { + name: sim_fork_join_scope, + .. + }, + }.outputs[2], + }, + did_initial_settle: true, + }, + extern_modules: [ + SimulationExternModuleState { + module_state: SimulationModuleState { + base_targets: [ + ModuleIO { + name: sim_fork_join_scope::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_fork_join_scope::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ], + uninitialized_ios: {}, + io_targets: { + ModuleIO { + name: sim_fork_join_scope::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_fork_join_scope::clocks, + is_input: true, + ty: Array, + .. + }[0], + ModuleIO { + name: sim_fork_join_scope::clocks, + is_input: true, + ty: Array, + .. + }[1], + ModuleIO { + name: sim_fork_join_scope::clocks, + is_input: true, + ty: Array, + .. + }[2], + ModuleIO { + name: sim_fork_join_scope::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_fork_join_scope::outputs, + is_input: false, + ty: Array, 3>, + .. + }[0], + ModuleIO { + name: sim_fork_join_scope::outputs, + is_input: false, + ty: Array, 3>, + .. + }[1], + ModuleIO { + name: sim_fork_join_scope::outputs, + is_input: false, + ty: Array, 3>, + .. + }[2], + }, + did_initial_settle: true, + }, + sim: ExternModuleSimulation { + generator: SimGeneratorFn { + args: ( + ModuleIO { + name: sim_fork_join_scope::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_fork_join_scope::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ), + f: ..., + }, + sim_io_to_generator_map: { + ModuleIO { + name: sim_fork_join_scope::clocks, + is_input: true, + ty: Array, + .. + }: ModuleIO { + name: sim_fork_join_scope::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_fork_join_scope::outputs, + is_input: false, + ty: Array, 3>, + .. + }: ModuleIO { + name: sim_fork_join_scope::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + }, + source_location: SourceLocation( + module-XXXXXXXXXX.rs:4:1, + ), + }, + running_generator: Some( + ..., + ), + }, + ], + trace_decls: TraceModule { + name: "sim_fork_join_scope", + children: [ + TraceModuleIO { + name: "clocks", + child: TraceArray { + name: "clocks", + elements: [ + TraceClock { + location: TraceScalarId(0), + name: "[0]", + flow: Source, + }, + TraceClock { + location: TraceScalarId(1), + name: "[1]", + flow: Source, + }, + TraceClock { + location: TraceScalarId(2), + name: "[2]", + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ty: Array, + flow: Source, + }, + TraceModuleIO { + name: "outputs", + child: TraceArray { + name: "outputs", + elements: [ + TraceUInt { + location: TraceScalarId(3), + name: "[0]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(4), + name: "[1]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(5), + name: "[2]", + ty: UInt<8>, + flow: Sink, + }, + ], + ty: Array, 3>, + flow: Sink, + }, + ty: Array, 3>, + flow: Sink, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigClock { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigClock { + index: StatePartIndex(2), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(3), + ty: UInt<8>, + }, + state: 0x31, + last_state: 0x31, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigUInt { + index: StatePartIndex(4), + ty: UInt<8>, + }, + state: 0x32, + last_state: 0x32, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x32, + last_state: 0x32, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [], + event_queue: EventQueue(EventQueueData { + instant: 648 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: { + SensitivitySet { + id: 198, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + }, + waiting_sensitivity_sets_by_compiled_value: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 198, + .. + }, + }, + ), + }, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd new file mode 100644 index 00000000..555e83ed --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.vcd @@ -0,0 +1,1467 @@ +$timescale 1 ps $end +$scope module sim_fork_join_scope $end +$scope struct clocks $end +$var wire 1 ! \[0] $end +$var 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+#648000000 +0# From df020e9c9bb2daecd224cd55cd385ad42341827e Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 12 Nov 2025 03:36:40 -0800 Subject: [PATCH 09/10] add ExternModuleSimulatorState::read_past() and more output when simulator trace is enabled --- crates/fayalite/src/firrtl.rs | 1 + crates/fayalite/src/module.rs | 105 +- .../src/module/transform/deduce_resets.rs | 1 + crates/fayalite/src/sim.rs | 526 +- crates/fayalite/src/sim/compiler.rs | 316 +- crates/fayalite/src/sim/interpreter.rs | 25 +- crates/fayalite/src/sim/interpreter/parts.rs | 11 +- crates/fayalite/src/sim/value.rs | 38 + .../src/sim/value/sim_only_value_unsafe.rs | 18 +- crates/fayalite/tests/sim.rs | 120 + .../fayalite/tests/sim/expected/array_rw.txt | 1 + .../expected/conditional_assignment_last.txt | 1 + .../tests/sim/expected/connect_const.txt | 1 + .../sim/expected/connect_const_reset.txt | 1 + .../tests/sim/expected/counter_async.txt | 35 +- .../tests/sim/expected/counter_sync.txt | 17 +- .../tests/sim/expected/duplicate_names.txt | 1 + crates/fayalite/tests/sim/expected/enums.txt | 50 +- .../tests/sim/expected/extern_module.txt | 13 +- .../tests/sim/expected/extern_module2.txt | 2 + .../tests/sim/expected/many_memories.txt | 1 + .../fayalite/tests/sim/expected/memories.txt | 1 + .../fayalite/tests/sim/expected/memories2.txt | 1 + .../fayalite/tests/sim/expected/memories3.txt | 1 + crates/fayalite/tests/sim/expected/mod1.txt | 1 + .../tests/sim/expected/phantom_const.txt | 1 + .../tests/sim/expected/ripple_counter.txt | 4 + .../tests/sim/expected/shift_register.txt | 17 +- .../tests/sim/expected/sim_fork_join.txt | 6 +- .../sim/expected/sim_fork_join_scope.txt | 6 +- .../tests/sim/expected/sim_only_connects.txt | 11 +- .../tests/sim/expected/sim_read_past.txt | 9724 +++++++++++++++++ .../tests/sim/expected/sim_read_past.vcd | 1908 ++++ .../expected/sim_resettable_counter_async.txt | 10 +- ...settable_counter_async_immediate_reset.txt | 10 +- .../expected/sim_resettable_counter_sync.txt | 8 +- ...esettable_counter_sync_immediate_reset.txt | 8 +- crates/fayalite/visit_types.json | 1 + 38 files changed, 12749 insertions(+), 253 deletions(-) create mode 100644 crates/fayalite/tests/sim/expected/sim_read_past.txt create mode 100644 crates/fayalite/tests/sim/expected/sim_read_past.vcd diff --git a/crates/fayalite/src/firrtl.rs b/crates/fayalite/src/firrtl.rs index cca0d823..59fbec7f 100644 --- a/crates/fayalite/src/firrtl.rs +++ b/crates/fayalite/src/firrtl.rs @@ -2326,6 +2326,7 @@ impl<'a> Exporter<'a> { ModuleBody::Extern(ExternModuleBody { verilog_name, parameters, + clocks_for_past: _, simulation: _, }) => { let verilog_name = Ident(verilog_name); diff --git a/crates/fayalite/src/module.rs b/crates/fayalite/src/module.rs index 6527043c..5ffeaae2 100644 --- a/crates/fayalite/src/module.rs +++ b/crates/fayalite/src/module.rs @@ -41,7 +41,6 @@ use std::{ marker::PhantomData, mem, num::NonZeroU64, - ops::Deref, rc::Rc, sync::atomic::AtomicU64, }; @@ -67,6 +66,8 @@ pub trait ModuleBuildingStatus: type ModuleBody: fmt::Debug; type StmtAnnotations: 'static + Send + Sync + Copy + Eq + Hash + fmt::Debug; type ModuleIOAnnotations; + type ExternModuleParameters: fmt::Debug; + type ExternModuleClocksForPast: fmt::Debug; } #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash, Default)] @@ -79,6 +80,8 @@ impl ModuleBuildingStatus for ModuleBuilt { type ModuleBody = Block; type StmtAnnotations = Interned<[TargetedAnnotation]>; type ModuleIOAnnotations = Interned<[TargetedAnnotation]>; + type ExternModuleParameters = Interned<[ExternModuleParameter]>; + type ExternModuleClocksForPast = Interned<[Target]>; } #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash, Default)] @@ -91,6 +94,8 @@ impl ModuleBuildingStatus for ModuleBuilding { type ModuleBody = BuilderModuleBody; type StmtAnnotations = (); type ModuleIOAnnotations = Vec; + type ExternModuleParameters = Vec; + type ExternModuleClocksForPast = Vec; } #[derive(Debug)] @@ -1080,26 +1085,65 @@ impl From for ModuleBody { } } +#[track_caller] +fn validate_clock_for_past( + clock_for_past: Option, + module_io: &[AnnotatedModuleIO], +) -> Target { + if let Some(clock_for_past) = clock_for_past { + assert_eq!( + clock_for_past.canonical_ty(), + Clock.canonical(), + "clock_for_past: clock is not of type Clock", + ); + if clock_for_past + .base() + .module_io() + .is_some_and(|v| module_io.iter().any(|module_io| module_io.module_io == *v)) + { + let mut target = clock_for_past; + while let Target::Child(child) = target { + match *child.path_element() { + TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {} + TargetPathElement::DynArrayElement(_) => { + panic!( + "clock_for_past: clock must be a static target (you can't use `Expr` array indexes):\n{clock_for_past:?}" + ); + } + } + target = *child.parent(); + } + return clock_for_past; + } + } + panic!("clock_for_past: clock must be some part of this module's I/O:\n{clock_for_past:?}"); +} + #[derive(PartialEq, Eq, Hash, Copy, Clone, Debug)] -pub struct ExternModuleBody< - P: Deref = Interned<[ExternModuleParameter]>, -> { +pub struct ExternModuleBody { pub verilog_name: Interned, - pub parameters: P, + pub parameters: S::ExternModuleParameters, + /// [`Clock`]s that the [`Simulation`] will store the past values of all [`ModuleIO`] for. + /// + /// [`Simulation`]: crate::sim::Simulation + pub clocks_for_past: S::ExternModuleClocksForPast, pub simulation: Option, } -impl From>> for ExternModuleBody { - fn from(value: ExternModuleBody>) -> Self { +impl From> for ExternModuleBody { + fn from(value: ExternModuleBody) -> Self { let ExternModuleBody { verilog_name, parameters, + clocks_for_past, simulation, } = value; let parameters = Intern::intern_owned(parameters); + let clocks_for_past = Intern::intern_owned(clocks_for_past); Self { verilog_name, parameters, + clocks_for_past, simulation, } } @@ -1112,15 +1156,12 @@ impl From for ModuleBody { } #[derive(Debug)] -pub enum ModuleBody< - S: ModuleBuildingStatus = ModuleBuilt, - P: Deref = Interned<[ExternModuleParameter]>, -> { +pub enum ModuleBody { Normal(NormalModuleBody), - Extern(ExternModuleBody

), + Extern(ExternModuleBody), } -pub(crate) type ModuleBodyBuilding = ModuleBody>; +pub(crate) type ModuleBodyBuilding = ModuleBody; impl ModuleBodyBuilding { pub(crate) fn builder_normal_body_opt( @@ -1141,9 +1182,7 @@ impl ModuleBodyBuilding { } } #[track_caller] - pub(crate) fn builder_extern_body( - &mut self, - ) -> &mut ExternModuleBody> { + pub(crate) fn builder_extern_body(&mut self) -> &mut ExternModuleBody { if let Self::Extern(v) = self { v } else { @@ -1297,11 +1336,13 @@ impl fmt::Debug for DebugModuleBody { ModuleBody::Extern(ExternModuleBody { verilog_name, parameters, + clocks_for_past, simulation, }) => { debug_struct .field("verilog_name", verilog_name) .field("parameters", parameters) + .field("clocks_for_past", clocks_for_past) .field("simulation", simulation); } } @@ -1780,8 +1821,13 @@ impl AssertValidityState { ModuleBody::Extern(ExternModuleBody { verilog_name: _, parameters: _, + clocks_for_past, simulation: _, - }) => {} + }) => { + for clock_for_past in clocks_for_past { + validate_clock_for_past(Some(clock_for_past), &self.module.module_io); + } + } ModuleBody::Normal(NormalModuleBody { body }) => { let body = self.make_block_index(body); assert_eq!(body, 0); @@ -1811,9 +1857,17 @@ impl Module { match &mut body { ModuleBody::Normal(_) => {} ModuleBody::Extern(ExternModuleBody { + verilog_name: _, + parameters: _, + clocks_for_past, simulation: Some(simulation), - .. }) => { + let mut clocks_for_past_set = HashSet::default(); + *clocks_for_past = clocks_for_past + .iter() + .copied() + .filter(|clock_for_past| clocks_for_past_set.insert(*clock_for_past)) + .collect(); if module_io.iter().any(|io| { !simulation .sim_io_to_generator_map @@ -2186,6 +2240,7 @@ impl ModuleBuilder { ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody { verilog_name: name.0, parameters: vec![], + clocks_for_past: vec![], simulation: None, }), ModuleKind::Normal => ModuleBody::Normal(NormalModuleBody { @@ -2308,6 +2363,20 @@ impl ModuleBuilder { value: ExternModuleParameterValue::RawVerilog(raw_verilog.intern()), }); } + /// registers a [`Clock`] so you can use it with the [`ExternModuleSimulationState::read_past()`] family of functions. + /// + /// [`ExternModuleSimulationState::read_past()`]: crate::sim::ExternModuleSimulationState::read_past() + #[track_caller] + pub fn register_clock_for_past(&self, clock_for_past: impl ToExpr) { + let clock_for_past = clock_for_past.to_expr().target().as_deref().copied(); + let mut impl_ = self.impl_.borrow_mut(); + let clock_for_past = validate_clock_for_past(clock_for_past, &impl_.io); + impl_ + .body + .builder_extern_body() + .clocks_for_past + .push(clock_for_past); + } #[track_caller] pub fn extern_module_simulation(&self, generator: G) { let mut impl_ = self.impl_.borrow_mut(); diff --git a/crates/fayalite/src/module/transform/deduce_resets.rs b/crates/fayalite/src/module/transform/deduce_resets.rs index e84d835e..bd4e939c 100644 --- a/crates/fayalite/src/module/transform/deduce_resets.rs +++ b/crates/fayalite/src/module/transform/deduce_resets.rs @@ -2073,6 +2073,7 @@ impl_run_pass_for_struct! { impl[] RunPass for ExternModuleBody { verilog_name: _, parameters: _, + clocks_for_past: _, simulation: _, } } diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 01233cb2..808ead40 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -24,7 +24,7 @@ use crate::{ sim::{ compiler::{ Compiled, CompiledBundleField, CompiledExternModule, CompiledTypeLayoutBody, - CompiledValue, + CompiledValue, ExternModuleClockForPast, }, interpreter::{ BreakAction, BreakpointsSet, RunResult, SmallUInt, State, @@ -57,7 +57,7 @@ use std::{ pin::{Pin, pin}, ptr, rc::Rc, - sync::{Arc, Mutex}, + sync::{Arc, Mutex, MutexGuard}, task::Poll, usize, }; @@ -1040,6 +1040,12 @@ impl MaybeNeedsSettle { MaybeNeedsSettle::NoSettleNeeded(v) => MaybeNeedsSettle::NoSettleNeeded(f(v)), } } + fn into_inner(self) -> T { + match self { + MaybeNeedsSettle::NeedsSettle(v) => v, + MaybeNeedsSettle::NoSettleNeeded(v) => v, + } + } } // workaround implementing FnOnce not being stable @@ -1074,6 +1080,7 @@ struct SimulationModuleState { uninitialized_ios: HashMap>, io_targets: HashMap>, did_initial_settle: bool, + clocks_for_past: HashMap, SimulationExternModuleClockForPast>, } impl fmt::Debug for SimulationModuleState { @@ -1083,23 +1090,37 @@ impl fmt::Debug for SimulationModuleState { uninitialized_ios, io_targets, did_initial_settle, + clocks_for_past, } = self; f.debug_struct("SimulationModuleState") .field("base_targets", base_targets) .field("uninitialized_ios", &SortedSetDebug(uninitialized_ios)) .field("io_targets", &SortedSetDebug(io_targets)) .field("did_initial_settle", did_initial_settle) + .field("clocks_for_past", &SortedMapDebug(clocks_for_past)) .finish() } } impl SimulationModuleState { - fn new(base_targets: impl IntoIterator)>) -> Self { + fn new( + base_targets: impl IntoIterator)>, + clocks_for_past: &[ExternModuleClockForPast], + ) -> Self { let mut retval = Self { base_targets: Vec::new(), uninitialized_ios: HashMap::default(), io_targets: HashMap::default(), did_initial_settle: false, + clocks_for_past: clocks_for_past + .iter() + .map(|clock_for_past| { + ( + clock_for_past.clock_for_past, + SimulationExternModuleClockForPast::new(clock_for_past), + ) + }) + .collect(), }; for (base_target, value) in base_targets { retval.base_targets.push(base_target); @@ -1255,7 +1276,7 @@ impl SimulationModuleState { } } #[track_caller] - fn read_helper( + fn read_helper_current( &self, io: Expr, which_module: WhichModule, @@ -1300,6 +1321,33 @@ impl SimulationModuleState { } } #[track_caller] + fn read_helper( + &self, + io: Expr, + read_time: ReadTime, + which_module: WhichModule, + ) -> MaybeNeedsSettle> { + match read_time { + ReadTime::Current => self.read_helper_current(io, which_module), + ReadTime::Past { clock_for_past } => { + let current = self.read_helper_current(io, which_module); + let clock_for_past_value = self + .read_helper_current(Expr::canonical(clock_for_past), which_module) + .into_inner() + .map_ty(Clock::from_canonical); + let Some(clock_for_past) = self.clocks_for_past.get(&clock_for_past_value) else { + panic!( + "In order to use the `read_past()` family of functions,\n\ + you must call `m.register_clock_for_past(my_io.clk)`\n\ + in the module's body for every clock you use as the\n\ + second argument of the `read_past()` family." + ); + }; + current.map(|current| clock_for_past.current_to_past_map[¤t]) + } + } + } + #[track_caller] fn write_helper( &mut self, io: Expr, @@ -1331,11 +1379,71 @@ impl SimulationModuleState { } } +struct SimulationExternModuleClockForPast { + current_to_past_map: HashMap, CompiledValue>, +} + +impl fmt::Debug for SimulationExternModuleClockForPast { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + current_to_past_map, + } = self; + f.debug_struct("SimulationExternModuleClockForPast") + .field("current_to_past_map", &SortedMapDebug(current_to_past_map)) + .finish() + } +} + +impl SimulationExternModuleClockForPast { + fn new(clock_for_past: &ExternModuleClockForPast) -> Self { + let mut retval = Self { + current_to_past_map: HashMap::default(), + }; + for (current, past) in clock_for_past.current_to_past_map { + retval.add_current_to_past_mapping(current, past); + } + retval + } + fn add_current_to_past_mapping( + &mut self, + current: CompiledValue, + past: CompiledValue, + ) { + self.current_to_past_map.insert(current, past); + match current.layout.body { + CompiledTypeLayoutBody::Scalar | CompiledTypeLayoutBody::PhantomConst => {} + CompiledTypeLayoutBody::Array { .. } => { + let current = current.map_ty(Array::from_canonical); + let past = past.map_ty(Array::from_canonical); + for index in 0..current.layout.ty.len() { + self.add_current_to_past_mapping(current.element(index), past.element(index)); + } + } + CompiledTypeLayoutBody::Bundle { .. } => { + let current = current.map_ty(Bundle::from_canonical); + let past = past.map_ty(Bundle::from_canonical); + for BundleField { name, .. } in current.layout.ty.fields() { + self.add_current_to_past_mapping( + current.field_by_name(name), + past.field_by_name(name), + ); + } + } + } + } +} + +enum ReadTime { + Current, + Past { clock_for_past: Expr }, +} + struct SimulationExternModuleState { module_state: SimulationModuleState, sim: ExternModuleSimulation, running_generator: Option + 'static>>>, waker: Arc, + debug_name: Interned, } impl fmt::Debug for SimulationExternModuleState { @@ -1345,6 +1453,7 @@ impl fmt::Debug for SimulationExternModuleState { sim, running_generator, waker: _, + debug_name: _, } = self; f.debug_struct("SimulationExternModuleState") .field("module_state", module_state) @@ -1489,75 +1598,170 @@ impl Hash for HashableWaker { } } +enum EventWakers { + Wakers(HashSet), + CurrentlyWaking, +} + +impl EventWakers { + fn start_waking(&mut self) -> HashSet { + match std::mem::replace(self, Self::CurrentlyWaking) { + Self::Wakers(retval) => retval, + Self::CurrentlyWaking => unreachable!(), + } + } +} + +impl fmt::Debug for EventWakers { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Wakers(wakers) => f.debug_tuple("Wakers").field(&wakers.len()).finish(), + Self::CurrentlyWaking => write!(f, "CurrentlyWaking"), + } + } +} + struct EventQueueData { instant: SimInstant, - events: BTreeMap>, + events: BTreeMap, + trace: bool, } impl fmt::Debug for EventQueueData { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - struct EventsDebug<'a>(&'a BTreeMap>); - impl fmt::Debug for EventsDebug<'_> { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let mut debug_map = f.debug_map(); - for (k, v) in self.0 { - debug_map.entry(&format_args!("{k:?}"), &v.len()); - } - debug_map.finish() - } - } - let Self { instant, events } = self; + let Self { + instant, + events, + trace: _, + } = self; f.debug_struct("EventQueueData") .field("instant", instant) - .field("events", &EventsDebug(events)) + .field("events", events) .finish() } } -struct EventQueueFirstEntry<'a>( - std::collections::btree_map::OccupiedEntry<'a, Event, HashSet>, -); +struct EventQueueFirstEvent<'a> { + event_queue: Arc, + event_queue_lock: MutexGuard<'a, EventQueueData>, +} -impl<'a> EventQueueFirstEntry<'a> { - fn key(&self) -> &Event { - self.0.key() +impl<'a> EventQueueFirstEvent<'a> { + fn event(&self) -> &Event { + self.event_queue_lock + .events + .first_key_value() + .expect("known to be non-empty") + .0 } - fn remove(self) -> HashSet { - self.0.remove() + fn remove_and_wake_all_wakers(self) { + let Self { + event_queue, + mut event_queue_lock, + } = self; + let trace = event_queue_lock.trace; + let mut entry = event_queue_lock + .events + .first_entry() + .expect("known to be non-empty"); + let wakers = entry.get_mut().start_waking(); + let event = *entry.key(); + if wakers.is_empty() { + entry.remove(); + if trace { + println!( + "EventQueue first_event remove_and_wake_all_wakers(): event={event:?} no wakers", + ); + } + drop(event_queue_lock); + return; + } + drop(event_queue_lock); + if trace { + println!( + "EventQueue first_event remove_and_wake_all_wakers(): event={event:?} wakers_len={}", + wakers.len() + ); + } + for waker in wakers { + waker.0.wake(); + } + event_queue.lock().events.remove(&event); + if trace { + println!( + "EventQueue first_event remove_and_wake_all_wakers(): event={event:?} finished waking", + ); + } + } + fn into_event_queue_lock(self) -> MutexGuard<'a, EventQueueData> { + self.event_queue_lock } } impl EventQueueData { - fn new(instant: SimInstant) -> Self { + fn new(instant: SimInstant, trace: bool) -> Self { Self { instant, events: BTreeMap::new(), + trace, } } fn instant(&self) -> SimInstant { self.instant } fn set_instant(&mut self, instant: SimInstant) { + if self.trace { + println!("EventQueue set_instant({instant:?})"); + } self.instant = instant; } - fn add_event(&mut self, mut event: Event, waker: Option) { + fn add_event( + &mut self, + mut event: Event, + waker: Option, + ) -> Result<(), std::task::Waker> { event.instant = event.instant.max(self.instant); - self.events + let wakers = self + .events .entry(event) - .or_default() - .extend(waker.map(HashableWaker)); + .or_insert_with(|| EventWakers::Wakers(HashSet::default())); + let EventWakers::Wakers(wakers) = wakers else { + return match waker { + Some(waker) => Err(waker), + None => Ok(()), + }; + }; + if self.trace { + println!( + "EventQueue add_event({event:?}, {:?})", + waker.is_some().then_some(format_args!("")) + ); + } + wakers.extend(waker.map(HashableWaker)); + Ok(()) } - fn add_event_for_now(&mut self, kind: EventKind, waker: Option) { + fn add_event_for_now(&mut self, kind: EventKind) { self.add_event( Event { instant: self.instant, kind, }, - waker, - ); + None, + ) + .expect("no waker passed in") } - fn first_entry(&mut self) -> Option> { - self.events.first_entry().map(EventQueueFirstEntry) + fn first_event<'a>( + this: MutexGuard<'a, EventQueueData>, + event_queue: Arc, + ) -> Result, MutexGuard<'a, EventQueueData>> { + if this.events.is_empty() { + Err(this) + } else { + Ok(EventQueueFirstEvent { + event_queue, + event_queue_lock: this, + }) + } } fn peek_first_event(&self) -> Option { Some(*self.events.first_key_value()?.0) @@ -1586,11 +1790,11 @@ impl EventQueue { fn new(data: EventQueueData) -> Self { Self(Mutex::new(data)) } - fn lock(&self) -> std::sync::MutexGuard<'_, EventQueueData> { + fn lock(&self) -> MutexGuard<'_, EventQueueData> { self.0.lock().expect("not poisoned") } - fn add_event_for_now(&self, kind: EventKind, waker: Option) { - self.lock().add_event_for_now(kind, waker); + fn add_event_for_now(&self, kind: EventKind) { + self.lock().add_event_for_now(kind); } fn peek_first_event_for_now(&self) -> Option { self.lock().peek_first_event_for_now() @@ -1608,7 +1812,7 @@ impl std::task::Wake for ExternModuleGeneratorWaker { } fn wake_by_ref(self: &Arc) { if let Some(event_queue) = self.event_queue.upgrade() { - event_queue.add_event_for_now(EventKind::ExternModule(self.module_index), None); + event_queue.add_event_for_now(EventKind::ExternModule(self.module_index)); } } } @@ -1808,10 +2012,10 @@ impl SimulationImpl { } fn new(compiled: Compiled) -> Self { let io_target = Target::from(compiled.io); - let mut event_queue = EventQueueData::new(SimInstant::START); - event_queue.add_event_for_now(EventKind::State, None); + let mut event_queue = EventQueueData::new(SimInstant::START, false); + event_queue.add_event_for_now(EventKind::State); for module_index in 0..compiled.extern_modules.len() { - event_queue.add_event_for_now(EventKind::ExternModule(module_index), None); + event_queue.add_event_for_now(EventKind::ExternModule(module_index)); } let event_queue = Arc::new(EventQueue::new(event_queue)); let extern_modules = Box::from_iter(compiled.extern_modules.iter().enumerate().map( @@ -1820,7 +2024,9 @@ impl SimulationImpl { &CompiledExternModule { module_io_targets, module_io, + clocks_for_past, simulation, + debug_name, }, )| { SimulationExternModuleState { @@ -1829,6 +2035,7 @@ impl SimulationImpl { .iter() .copied() .zip(module_io.iter().copied()), + &clocks_for_past, ), sim: simulation, running_generator: None, @@ -1836,6 +2043,7 @@ impl SimulationImpl { event_queue: Arc::downgrade(&event_queue), module_index, }), + debug_name, } }, )); @@ -1858,6 +2066,7 @@ impl SimulationImpl { value, ) }), + &[], ), extern_modules, trace_decls: compiled.base_module.trace_decls, @@ -2048,6 +2257,9 @@ impl SimulationImpl { // already added return; }; + if self.breakpoints.as_ref().is_some_and(|v| v.trace) { + println!("SimulationImpl::wake_after_change:\n{sensitivity_set:#?}"); + } let SensitivitySet { debug_id: _, compiled_values: _, @@ -2070,6 +2282,9 @@ impl SimulationImpl { else { return; }; + if self.breakpoints.as_ref().is_some_and(|v| v.trace) { + println!("SimulationImpl::cancel_wake_after_change:\n{sensitivity_set:#?}"); + } let SensitivitySet { debug_id: _, compiled_values: _, @@ -2099,13 +2314,19 @@ impl SimulationImpl { let Some(instant) = instant(event_queue.instant()) else { return Err(waker); }; - event_queue.add_event( + match event_queue.add_event( Event { instant, kind: EventKind::ExternModule(module_index), }, Some(waker), - ); + ) { + Ok(()) => {} + Err(waker) => { + drop(event_queue); + waker.wake(); + } + } Ok(()) } async fn yield_advance_time_or_settle( @@ -2248,17 +2469,25 @@ impl SimulationImpl { .iter() .any(|i| self.state.small_slots[*i] != 0) { - self.event_queue.add_event_for_now(EventKind::State, None); + if self.breakpoints.as_ref().is_some_and(|v| v.trace) { + println!("SimulationImpl clocks triggered"); + } + self.event_queue.add_event_for_now(EventKind::State); } } #[track_caller] fn run_extern_module(this_ref: &Rc>, module_index: usize) { let mut this = this_ref.borrow_mut(); + let trace = this.breakpoints.as_ref().is_some_and(|v| v.trace); let extern_module = &mut this.extern_modules[module_index]; + let debug_name = extern_module.debug_name; let waker = std::task::Waker::from(extern_module.waker.clone()); let mut generator = if !extern_module.module_state.did_initial_settle { let sim = extern_module.sim; drop(this); + if trace { + println!("{debug_name}: start"); + } Box::into_pin(sim.run(ExternModuleSimulationState { sim_impl: this_ref.clone(), module_index, @@ -2269,13 +2498,19 @@ impl SimulationImpl { } else { return; }; - let generator = match generator + if trace { + println!("{debug_name}: poll"); + } + let poll_result = generator .as_mut() - .poll(&mut std::task::Context::from_waker(&waker)) - { + .poll(&mut std::task::Context::from_waker(&waker)); + let generator = match poll_result { Poll::Ready(()) => None, Poll::Pending => Some(generator), }; + if trace { + println!("{debug_name}: poll returned {poll_result:?}"); + } this = this_ref.borrow_mut(); this.extern_modules[module_index] .module_state @@ -2378,7 +2613,8 @@ impl SimulationImpl { "didn't initialize all inputs", ); this.check_waiting_sensitivity_sets(); - let mut event_queue = this.event_queue.lock(); + let arc_event_queue = this.event_queue.clone(); // avoid borrow errors + let mut event_queue = arc_event_queue.lock(); let Some(run_target) = run_target(event_queue.instant()) else { drop(event_queue); panic!("SimInstant overflowed"); @@ -2392,10 +2628,14 @@ impl SimulationImpl { } settle_cycle += 1; let event_queue_instant = event_queue.instant(); - let Some(first_entry) = event_queue.first_entry() else { - let changed_time = event_queue_instant != run_target; - event_queue.set_instant(run_target); - drop(event_queue); + let mut changed_time = false; + let first_entry = EventQueueData::first_event(event_queue, arc_event_queue.clone()) + .map_err(|mut event_queue| { + changed_time = event_queue_instant != run_target; + event_queue.set_instant(run_target); + drop(event_queue); + }); + let Ok(first_entry) = first_entry else { if changed_time { this.write_traces_change_time_to(run_target); } @@ -2404,13 +2644,9 @@ impl SimulationImpl { let Event { instant: event_instant, kind: event_kind, - } = *first_entry.key(); + } = *first_entry.event(); if event_instant <= event_queue_instant { - let wakers = first_entry.remove(); - drop(event_queue); - for HashableWaker(waker) in wakers { - waker.wake(); - } + first_entry.remove_and_wake_all_wakers(); match event_kind { EventKind::State => this.run_state_settle_cycle(), EventKind::ExternModule(module_index) => { @@ -2422,6 +2658,7 @@ impl SimulationImpl { this.write_traces_after_event(); this.check_waiting_sensitivity_sets(); } else { + event_queue = first_entry.into_event_queue_lock(); let new_instant = event_instant.min(run_target); let changed_time = event_queue_instant != new_instant; event_queue.set_instant(new_instant); @@ -2433,7 +2670,7 @@ impl SimulationImpl { return; } } - event_queue = this.event_queue.lock(); + event_queue = arc_event_queue.lock(); } } #[track_caller] @@ -2458,10 +2695,11 @@ impl SimulationImpl { fn read_bit( &mut self, io: Expr, + read_time: ReadTime, which_module: WhichModule, ) -> MaybeNeedsSettle { self.get_module(which_module) - .read_helper(Expr::canonical(io), which_module) + .read_helper(Expr::canonical(io), read_time, which_module) .map(|compiled_value| ReadBitFn { compiled_value }) .apply_no_settle(&mut self.state) } @@ -2470,7 +2708,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(io, which_module); - self.event_queue.add_event_for_now(EventKind::State, None); + self.event_queue.add_event_for_now(EventKind::State); match compiled_value.range.len().as_single() { Some(TypeLenSingle::SmallSlot) => { self.state.small_slots[compiled_value.range.small_slots.start] = value as _; @@ -2480,15 +2718,17 @@ impl SimulationImpl { } Some(TypeLenSingle::SimOnlySlot) | None => unreachable!(), } + self.debug_write(compiled_value); } #[track_caller] fn read_bool_or_int( &mut self, io: Expr, + read_time: ReadTime, which_module: WhichModule, ) -> MaybeNeedsSettle, I::Value> { self.get_module(which_module) - .read_helper(Expr::canonical(io), which_module) + .read_helper(Expr::canonical(io), read_time, which_module) .map(|compiled_value| ReadBoolOrIntFn { compiled_value, io }) .apply_no_settle(&mut self.state) } @@ -2502,7 +2742,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(Expr::canonical(io), which_module); - self.event_queue.add_event_for_now(EventKind::State, None); + self.event_queue.add_event_for_now(EventKind::State); let value: BigInt = value.into(); match compiled_value.range.len().as_single() { Some(TypeLenSingle::SmallSlot) => { @@ -2517,6 +2757,7 @@ impl SimulationImpl { } Some(TypeLenSingle::SimOnlySlot) | None => unreachable!(), } + self.debug_write(compiled_value); } #[track_caller] fn read_write_sim_value_helper( @@ -2569,17 +2810,18 @@ impl SimulationImpl { None => unreachable!(), } } - CompiledTypeLayoutBody::Array { element } => { + CompiledTypeLayoutBody::Array { elements_non_empty } => { let ty = ::from_canonical(compiled_value.layout.ty); let element_size = ty.element().size(); for element_index in 0..ty.len() { Self::read_write_sim_value_helper( state, CompiledValue { - layout: *element, - range: compiled_value - .range - .index_array(element.layout.len(), element_index), + layout: elements_non_empty[element_index], + range: compiled_value.range.index_array( + elements_non_empty[element_index].layout.len(), + element_index, + ), write: None, }, start_index + element_index * element_size, @@ -2725,12 +2967,15 @@ impl SimulationImpl { fn read( &mut self, io: Expr, + read_time: ReadTime, which_module: WhichModule, ) -> ( CompiledValue, MaybeNeedsSettle>, ) { - let compiled_value = self.get_module(which_module).read_helper(io, which_module); + let compiled_value = self + .get_module(which_module) + .read_helper(io, read_time, which_module); let value = compiled_value .map(|compiled_value| ReadFn { compiled_value, io }) .apply_no_settle(&mut self.state); @@ -2738,6 +2983,18 @@ impl SimulationImpl { | MaybeNeedsSettle::NoSettleNeeded(compiled_value)) = compiled_value; (compiled_value, value) } + fn debug_write(&self, compiled_value: CompiledValue) { + if self.breakpoints.as_ref().is_some_and(|v| v.trace) { + println!( + "wrote: {:#?}", + compiler::DebugCompiledValueStateAsMap { + compiled_value, + state_layout: self.state.insns.state_layout(), + state: &self.state, + }, + ); + } + } #[track_caller] fn write( &mut self, @@ -2748,7 +3005,7 @@ impl SimulationImpl { let compiled_value = self .get_module_mut(which_module) .write_helper(io, which_module); - self.event_queue.add_event_for_now(EventKind::State, None); + self.event_queue.add_event_for_now(EventKind::State); assert_eq!(Expr::ty(io), SimValue::ty(value)); Self::read_write_sim_value_helper( &mut self.state, @@ -2781,6 +3038,7 @@ impl SimulationImpl { value.clone_from(&opaque.sim_only_values()[index]); }, ); + self.debug_write(compiled_value); } #[track_caller] fn settle_if_needed(this_ref: &Rc>, v: MaybeNeedsSettle) -> O @@ -2946,11 +3204,14 @@ impl fmt::Debug for SortedSetDebug<'_, T, V> { } } -struct SortedMapDebug<'a, K: 'static + Send + Sync, V>(&'a BTreeMap, V>); +struct SortedMapDebug<'a, T>(&'a T); -impl fmt::Debug for SortedMapDebug<'_, K, V> { +impl<'a, K: fmt::Debug + 'a, V: fmt::Debug + 'a, T> fmt::Debug for SortedMapDebug<'a, T> +where + &'a T: IntoIterator, +{ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - let mut entries = Vec::from_iter(self.0.iter().map(|(k, v)| { + let mut entries = Vec::from_iter(self.0.into_iter().map(|(k, v)| { if f.alternate() { (format!("{k:#?}"), format!("{v:#?}")) } else { @@ -3001,7 +3262,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bool_or_int(io, $which_module); + .read_bool_or_int(io, ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? @@ -3032,7 +3293,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bit(Expr::canonical(io), $which_module); + .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? @@ -3046,7 +3307,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bit(Expr::canonical(io), $which_module); + .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } $(#[$track_caller])? @@ -3060,7 +3321,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read_bit(Expr::canonical(io), $which_module); + .read_bit(Expr::canonical(io), ReadTime::Current, $which_module); $self.settle_if_needed(retval)$(.$await)? } #[track_caller] @@ -3075,7 +3336,7 @@ macro_rules! impl_simulation_methods { let retval = $self .sim_impl .borrow_mut() - .read(Expr::canonical(io), $which_module).1; + .read(Expr::canonical(io), ReadTime::Current, $which_module).1; SimValue::from_canonical($self.settle_if_needed(retval)$(.$await)?) } $(#[$track_caller])? @@ -3152,11 +3413,13 @@ impl Simulation { #[doc(hidden)] /// This is explicitly unstable and may be changed/removed at any time pub fn set_breakpoints_unstable(&mut self, pcs: HashSet, trace: bool) { - self.sim_impl.borrow_mut().breakpoints = Some(BreakpointsSet { + let mut sim_impl = self.sim_impl.borrow_mut(); + sim_impl.breakpoints = Some(BreakpointsSet { last_was_break: false, set: pcs, trace, }); + sim_impl.event_queue.lock().trace = trace; } } @@ -3211,7 +3474,10 @@ impl ExternModuleSimulationState { }; for io in iter { let io = Expr::canonical(io.to_expr()); - let (key, value) = self.sim_impl.borrow_mut().read(io, which_module); + let (key, value) = self + .sim_impl + .borrow_mut() + .read(io, ReadTime::Current, which_module); let value = self.settle_if_needed(value).await; let key = Rc::new(key); if sensitivity_set.compiled_values.insert(key.clone()) { @@ -3469,6 +3735,102 @@ impl ExternModuleSimulationState { .expect("filled by running all futures to completion"), } } + /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. + /// + /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] + /// in the module's body for every clock you use as the second argument of the `read_past()` family. + /// + /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past + pub async fn read_past_bool_or_int( + &mut self, + io: Expr, + clock_for_past: Expr, + ) -> I::Value { + let retval = self.sim_impl.borrow_mut().read_bool_or_int( + io, + ReadTime::Past { clock_for_past }, + WhichModule::Extern { + module_index: self.module_index, + }, + ); + self.settle_if_needed(retval).await + } + /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. + /// + /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] + /// in the module's body for every clock you use as the second argument of the `read_past()` family. + /// + /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past + pub async fn read_past_clock(&mut self, io: Expr, clock_for_past: Expr) -> bool { + let retval = self.sim_impl.borrow_mut().read_bit( + Expr::canonical(io), + ReadTime::Past { clock_for_past }, + WhichModule::Extern { + module_index: self.module_index, + }, + ); + self.settle_if_needed(retval).await + } + /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. + /// + /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] + /// in the module's body for every clock you use as the second argument of the `read_past()` family. + /// + /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past + pub async fn read_past_bool(&mut self, io: Expr, clock_for_past: Expr) -> bool { + let retval = self.sim_impl.borrow_mut().read_bit( + Expr::canonical(io), + ReadTime::Past { clock_for_past }, + WhichModule::Extern { + module_index: self.module_index, + }, + ); + self.settle_if_needed(retval).await + } + /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. + /// + /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] + /// in the module's body for every clock you use as the second argument of the `read_past()` family. + /// + /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past + pub async fn read_past_reset( + &mut self, + io: Expr, + clock_for_past: Expr, + ) -> bool { + let retval = self.sim_impl.borrow_mut().read_bit( + Expr::canonical(io), + ReadTime::Past { clock_for_past }, + WhichModule::Extern { + module_index: self.module_index, + }, + ); + self.settle_if_needed(retval).await + } + /// Reads the value of `io` from right before the last clock edge of `clock_for_past`. + /// + /// In order to use the `read_past()` family of functions, you must call [`m.register_clock_for_past(my_io.clk)`] + /// in the module's body for every clock you use as the second argument of the `read_past()` family. + /// + /// [`m.register_clock_for_past(my_io.clk)`]: crate::module::ModuleBuilder::register_clock_for_past + pub async fn read_past( + &mut self, + io: Expr, + clock_for_past: Expr, + ) -> SimValue { + let retval = self + .sim_impl + .borrow_mut() + .read( + Expr::canonical(io), + ReadTime::Past { clock_for_past }, + WhichModule::Extern { + module_index: self.module_index, + }, + ) + .1; + SimValue::from_canonical(self.settle_if_needed(retval).await) + } impl_simulation_methods!( async_await = (async, await), track_caller = (), @@ -3803,7 +4165,7 @@ impl fmt::Debug for ExternModuleSimulation { .field("generator", &self.generator) .field( "sim_io_to_generator_map", - &SortedMapDebug(&self.sim_io_to_generator_map), + &SortedMapDebug(&*self.sim_io_to_generator_map), ) .field("source_location", &self.source_location) .finish() diff --git a/crates/fayalite/src/sim/compiler.rs b/crates/fayalite/src/sim/compiler.rs index 98e5abfb..7a0ac0a2 100644 --- a/crates/fayalite/src/sim/compiler.rs +++ b/crates/fayalite/src/sim/compiler.rs @@ -31,9 +31,9 @@ use crate::{ TraceMemoryLocation, TraceModule, TraceModuleIO, TracePhantomConst, TraceReg, TraceSInt, TraceScalarId, TraceScope, TraceSimOnly, TraceSyncReset, TraceUInt, TraceWire, interpreter::{ - Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding, - InsnsBuildingDone, InsnsBuildingKind, Label, SmallUInt, StatePartArrayIndex, - StatePartArrayIndexed, + self, Insn, InsnField, InsnFieldKind, InsnFieldType, InsnOrLabel, Insns, InsnsBuilding, + InsnsBuildingDone, InsnsBuildingKind, Label, PrefixLinesWrapper, SmallUInt, + StatePartArrayIndex, StatePartArrayIndexed, parts::{ MemoryData, SlotDebugData, StatePartIndex, StatePartIndexRange, StatePartKind, StatePartKindBigSlots, StatePartKindMemories, StatePartKindSimOnlySlots, @@ -82,20 +82,73 @@ pub(crate) struct CompiledBundleField { pub(crate) ty: CompiledTypeLayout, } +impl CompiledBundleField { + fn with_prefixed_debug_names(self, prefix: &str) -> Self { + let Self { offset, ty } = self; + Self { + offset, + ty: ty.with_prefixed_debug_names(prefix), + } + } + fn with_anonymized_debug_info(self) -> Self { + let Self { offset, ty } = self; + Self { + offset, + ty: ty.with_anonymized_debug_info(), + } + } +} + #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)] pub(crate) enum CompiledTypeLayoutBody { Scalar, PhantomConst, Array { - /// debug names are ignored, use parent's layout instead - element: Interned>, + /// always has at least one element even for zero-sized arrays + elements_non_empty: Interned<[CompiledTypeLayout]>, }, Bundle { - /// debug names are ignored, use parent's layout instead fields: Interned<[CompiledBundleField]>, }, } +impl CompiledTypeLayoutBody { + fn with_prefixed_debug_names(self, prefix: &str) -> Self { + match self { + CompiledTypeLayoutBody::Scalar | CompiledTypeLayoutBody::PhantomConst => self, + CompiledTypeLayoutBody::Array { elements_non_empty } => CompiledTypeLayoutBody::Array { + elements_non_empty: elements_non_empty + .iter() + .map(|element| element.with_prefixed_debug_names(prefix)) + .collect(), + }, + CompiledTypeLayoutBody::Bundle { fields } => CompiledTypeLayoutBody::Bundle { + fields: fields + .iter() + .map(|field| field.with_prefixed_debug_names(prefix)) + .collect(), + }, + } + } + fn with_anonymized_debug_info(self) -> Self { + match self { + CompiledTypeLayoutBody::Scalar | CompiledTypeLayoutBody::PhantomConst => self, + CompiledTypeLayoutBody::Array { elements_non_empty } => CompiledTypeLayoutBody::Array { + elements_non_empty: elements_non_empty + .iter() + .map(|element| element.with_anonymized_debug_info()) + .collect(), + }, + CompiledTypeLayoutBody::Bundle { fields } => CompiledTypeLayoutBody::Bundle { + fields: fields + .iter() + .map(|field| field.with_anonymized_debug_info()) + .collect(), + }, + } + } +} + #[derive(Debug, PartialEq, Eq, Hash, Clone, Copy)] pub(crate) struct CompiledTypeLayout { pub(crate) ty: T, @@ -109,7 +162,7 @@ impl CompiledTypeLayout { Self { ty, layout: layout.with_prefixed_debug_names(prefix), - body, + body: body.with_prefixed_debug_names(prefix), } } fn with_anonymized_debug_info(self) -> Self { @@ -117,7 +170,7 @@ impl CompiledTypeLayout { Self { ty, layout: layout.with_anonymized_debug_info(), - body, + body: body.with_anonymized_debug_info(), } } fn get(ty: T) -> Self { @@ -152,18 +205,22 @@ impl CompiledTypeLayout { } CanonicalType::Array(array) => { let mut layout = TypeLayout::empty(); - let element = CompiledTypeLayout::get(array.element()).intern_sized(); + let element = CompiledTypeLayout::get(array.element()); + let mut elements_non_empty = vec![]; for index in 0..array.len() { - layout.allocate( - &element - .layout - .with_prefixed_debug_names(&format!("[{index}]")), - ); + let element = element.with_prefixed_debug_names(&format!("[{index}]")); + layout.allocate(&element.layout); + elements_non_empty.push(element); + } + if array.is_empty() { + elements_non_empty.push(element.with_prefixed_debug_names("[]")); } CompiledTypeLayout { ty: *input, layout: layout.into(), - body: CompiledTypeLayoutBody::Array { element }, + body: CompiledTypeLayoutBody::Array { + elements_non_empty: elements_non_empty.intern_deref(), + }, } } CanonicalType::PhantomConst(_) => CompiledTypeLayout { @@ -182,13 +239,9 @@ impl CompiledTypeLayout { flipped: _, ty, }| { - let ty = CompiledTypeLayout::get(*ty); - let offset = layout - .allocate( - &ty.layout - .with_prefixed_debug_names(&format!(".{name}")), - ) - .start(); + let ty = CompiledTypeLayout::get(*ty) + .with_prefixed_debug_names(&format!(".{name}")); + let offset = layout.allocate(&ty.layout).start(); CompiledBundleField { offset, ty } }, ) @@ -271,6 +324,39 @@ impl CompiledValue { } } +pub(crate) struct DebugCompiledValueStateAsMap<'a> { + pub(crate) compiled_value: CompiledValue, + pub(crate) state_layout: &'a interpreter::parts::StateLayout, + pub(crate) state: &'a interpreter::State, +} + +impl fmt::Debug for DebugCompiledValueStateAsMap<'_> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + use fmt::Write; + if self.compiled_value.range.is_empty() { + return f.write_str("{}"); + } + writeln!(f, "{{")?; + let mut f = PrefixLinesWrapper::new(f, true, " "); + macro_rules! debug_fmt { + ( + type_plural_fields = [$($type_plural_field:ident,)*]; + ) => { + $(for slot in self.compiled_value.range.$type_plural_field.iter() { + slot.debug_fmt(&mut f, ":", " ", " ", "", Some(self.state_layout), Some(self.state))?; + writeln!(f, ",")?; + })* + }; + } + get_state_part_kinds! { + debug_fmt! { + type_plural_fields; + } + } + write!(f.into_inner(), "}}") + } +} + impl CompiledValue { fn field_by_index(self, field_index: usize) -> CompiledValue { self.map(|layout, range| { @@ -299,10 +385,13 @@ impl CompiledValue { impl CompiledValue { pub(crate) fn element(self, index: usize) -> CompiledValue { self.map(|layout, range| { - let CompiledTypeLayoutBody::Array { element } = layout.body else { + let CompiledTypeLayoutBody::Array { elements_non_empty } = layout.body else { unreachable!(); }; - (*element, range.index_array(element.layout.len(), index)) + ( + elements_non_empty[index], + range.index_array(elements_non_empty[index].layout.len(), index), + ) }) } fn element_dyn( @@ -555,10 +644,11 @@ impl CompiledExpr { self, index_slot: StatePartIndex, ) -> CompiledExpr { - let CompiledTypeLayoutBody::Array { element } = self.static_part.layout.body else { + let CompiledTypeLayoutBody::Array { elements_non_empty } = self.static_part.layout.body + else { unreachable!(); }; - let stride = element.layout.len(); + let stride = elements_non_empty[0].layout.len(); let indexes = self.indexes.join(TypeArrayIndex::from_parts( index_slot, self.static_part.layout.ty.len(), @@ -566,10 +656,10 @@ impl CompiledExpr { )); CompiledExpr { static_part: self.static_part.map(|layout, range| { - let CompiledTypeLayoutBody::Array { element } = layout.body else { + let CompiledTypeLayoutBody::Array { elements_non_empty } = layout.body else { unreachable!(); }; - (*element, range.index_array(stride, 0)) + (elements_non_empty[0], range.index_array(stride, 0)) }), indexes, } @@ -1548,6 +1638,13 @@ struct ClockTrigger { source_location: SourceLocation, } +#[derive(Debug, Clone, Copy, Hash, PartialEq, Eq)] +pub(crate) struct ExternModuleClockForPast { + pub(crate) clock_for_past: CompiledValue, + pub(crate) current_to_past_map: + Interned<[(CompiledValue, CompiledValue)]>, +} + #[derive(Debug)] struct Register { value: CompiledValue, @@ -1635,7 +1732,9 @@ impl fmt::Debug for DebugOpaque { pub(crate) struct CompiledExternModule { pub(crate) module_io_targets: Interned<[Target]>, pub(crate) module_io: Interned<[CompiledValue]>, + pub(crate) clocks_for_past: Interned<[ExternModuleClockForPast]>, pub(crate) simulation: ExternModuleSimulation, + pub(crate) debug_name: Interned, } #[derive(Debug)] @@ -3915,18 +4014,15 @@ impl Compiler { self.enum_discriminants.insert(enum_value, retval); retval } - fn compile_stmt_reg( + fn compile_reg( &mut self, - stmt_reg: StmtReg, + clk: CompiledValue, + reset_and_init: Option<(Expr, CompiledValue)>, + source_location: SourceLocation, instantiated_module: InstantiatedModule, value: CompiledValue, ) { - let StmtReg { annotations, reg } = stmt_reg; - let clk = self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().clk)); - let clk = self - .compiled_expr_to_value(clk, reg.source_location()) - .map_ty(Clock::from_canonical); - let clk = self.compile_clock(clk, reg.source_location()); + let clk = self.compile_clock(clk, source_location); struct Dispatch; impl ResetTypeDispatch for Dispatch { type Input = (); @@ -3945,18 +4041,15 @@ impl Compiler { true } } - let reset = if let Some(init) = reg.init() { - let init = self.compile_expr(instantiated_module, init); - let init = self.compiled_expr_to_value(init, reg.source_location()); - let rst = - self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().rst)); - let rst = self.compiled_expr_to_value(rst, reg.source_location()); - let rst = self.compiled_value_bool_dest_is_small(rst, reg.source_location()); + let reset = if let Some((rst_expr, init)) = reset_and_init { + let rst = self.compile_expr(instantiated_module, Expr::canonical(rst_expr)); + let rst = self.compiled_expr_to_value(rst, source_location); + let rst = self.compiled_value_bool_dest_is_small(rst, source_location); let is_async = R::dispatch((), Dispatch); if is_async { - let cond = Expr::canonical(reg.clock_domain().rst.cast_to(Bool)); + let cond = Expr::canonical(rst_expr.cast_to(Bool)); let cond = self.compile_expr(instantiated_module, cond); - let cond = self.compiled_expr_to_value(cond, reg.source_location()); + let cond = self.compiled_expr_to_value(cond, source_location); let cond = cond.map_ty(Bool::from_canonical); // write to the register's current value since asynchronous reset is combinational let lhs = CompiledValue { @@ -3968,12 +4061,12 @@ impl Compiler { self.compile_simple_connect( [Cond { body: CondBody::IfTrue { cond }, - source_location: reg.source_location(), + source_location: source_location, }] .intern_slice(), lhs, init, - reg.source_location(), + source_location, ); } Some(RegisterReset { @@ -3988,9 +4081,33 @@ impl Compiler { value, clk_triggered: clk.clk_triggered, reset, - source_location: reg.source_location(), + source_location, }); } + fn compile_stmt_reg( + &mut self, + stmt_reg: StmtReg, + instantiated_module: InstantiatedModule, + value: CompiledValue, + ) { + let StmtReg { annotations, reg } = stmt_reg; + let clk = self.compile_expr(instantiated_module, Expr::canonical(reg.clock_domain().clk)); + let clk = self + .compiled_expr_to_value(clk, reg.source_location()) + .map_ty(Clock::from_canonical); + let reset_and_init = reg.init().map(|init| { + let init = self.compile_expr(instantiated_module, init); + let init = self.compiled_expr_to_value(init, reg.source_location()); + (reg.clock_domain().rst, init) + }); + self.compile_reg( + clk, + reset_and_init, + reg.source_location(), + instantiated_module, + value, + ); + } fn compile_declaration( &mut self, declaration: StmtDeclaration, @@ -4256,24 +4373,24 @@ impl Compiler { insns.push(end_label.into()); } } - CompiledTypeLayoutBody::Array { element } => { + CompiledTypeLayoutBody::Array { elements_non_empty } => { let CompiledTypeLayoutBody::Array { - element: mask_element, + elements_non_empty: mask_elements_non_empty, } = mask_layout.body else { unreachable!(); }; let ty = ::from_canonical(data_layout.ty); let element_bit_width = ty.element().bit_width(); - let element_size = element.layout.len(); - let mask_element_size = mask_element.layout.len(); + let element_size = elements_non_empty[0].layout.len(); + let mask_element_size = mask_elements_non_empty[0].layout.len(); for element_index in 0..ty.len() { self.compile_memory_port_rw_helper( memory, stride, start, - *element, - *mask_element, + elements_non_empty[element_index], + mask_elements_non_empty[element_index], read.as_mut().map( |MemoryPortReadInsns { addr, @@ -4880,6 +4997,88 @@ impl Compiler { } } } + fn compile_extern_module_clock_for_past( + &mut self, + instantiated_module: InstantiatedModule, + clock_for_past: Target, + ) -> ExternModuleClockForPast { + let clock_for_past = TargetInInstantiatedModule { + instantiated_module, + target: clock_for_past, + }; + let clock_for_past = self + .compile_value(clock_for_past) + .map_ty(Clock::from_canonical); + let clock_for_past_debug_name = match clock_for_past + .range + .len() + .as_single() + .expect("Clock is a single slot") + { + TypeLenSingle::BigSlot => { + self.insns + .state_layout + .ty + .big_slots + .debug_data(clock_for_past.range.start().big_slots) + .name + } + TypeLenSingle::SmallSlot => { + self.insns + .state_layout + .ty + .small_slots + .debug_data(clock_for_past.range.start().small_slots) + .name + } + TypeLenSingle::SimOnlySlot => { + unreachable!() + } + }; + let module_prefix = format!("{instantiated_module:?}."); + let trimmed_clock_for_past_debug_name = clock_for_past_debug_name + .strip_prefix(&module_prefix) + .unwrap_or(&clock_for_past_debug_name); + let current_to_past_map = instantiated_module + .leaf_module() + .module_io() + .iter() + .map( + |&AnnotatedModuleIO { + annotations: _, + module_io, + }| { + let target_base = TargetBase::from(module_io); + let current = self.compile_value(TargetInInstantiatedModule { + instantiated_module, + target: target_base.into(), + }); + let unprefixed_layout = CompiledTypeLayout::get(module_io.ty()); + let past_layout = unprefixed_layout.with_prefixed_debug_names(&format!( + "{module_prefix}{:?}$past({trimmed_clock_for_past_debug_name})", + target_base.target_name(), + )); + let past = CompiledValue { + range: self.insns.allocate_variable(&past_layout.layout), + layout: past_layout, + write: Some((current.layout, current.range)), + }; + self.compile_reg::( + clock_for_past, + None, + module_io.source_location(), + instantiated_module, + past, + ); + (current, past) + }, + ) + .collect(); + ExternModuleClockForPast { + clock_for_past, + current_to_past_map, + } + } fn compile_module(&mut self, module: Interned) -> &CompiledModule { let mut trace_decls = Vec::new(); let module_io = module @@ -4908,6 +5107,7 @@ impl Compiler { ModuleBody::Extern(ExternModuleBody { verilog_name: _, parameters: _, + clocks_for_past, simulation, }) => { let Some(simulation) = simulation else { @@ -4924,10 +5124,18 @@ impl Compiler { Target::from(*simulation.sim_io_to_generator_map[&v.module_io.intern()]) }) .collect(); + let clocks_for_past = clocks_for_past + .iter() + .map(|clock_for_past| { + self.compile_extern_module_clock_for_past(*module, *clock_for_past) + }) + .collect(); self.extern_modules.push(CompiledExternModule { module_io_targets, module_io, + clocks_for_past, simulation, + debug_name: format!("{module:?}").intern_deref(), }); } } diff --git a/crates/fayalite/src/sim/interpreter.rs b/crates/fayalite/src/sim/interpreter.rs index 1a6c2692..391172e0 100644 --- a/crates/fayalite/src/sim/interpreter.rs +++ b/crates/fayalite/src/sim/interpreter.rs @@ -196,13 +196,27 @@ impl fmt::Debug for Insn { } } -struct PrefixLinesWrapper<'a, W> { +pub(crate) struct PrefixLinesWrapper<'a, W> { writer: W, at_beginning_of_line: bool, blank_line_prefix: &'a str, line_prefix: &'a str, } +impl<'a, W> PrefixLinesWrapper<'a, W> { + pub(crate) fn new(writer: W, at_beginning_of_line: bool, line_prefix: &'a str) -> Self { + Self { + writer, + at_beginning_of_line, + blank_line_prefix: line_prefix.trim_end(), + line_prefix, + } + } + pub(crate) fn into_inner(self) -> W { + self.writer + } +} + impl fmt::Write for PrefixLinesWrapper<'_, T> { fn write_str(&mut self, input: &str) -> fmt::Result { for part in input.split_inclusive('\n') { @@ -239,12 +253,7 @@ impl Insn { if fields.len() == 0 { return Ok(()); } - let mut f = PrefixLinesWrapper { - writer: f, - at_beginning_of_line: false, - blank_line_prefix: "", - line_prefix: " ", - }; + let mut f = PrefixLinesWrapper::new(f, false, " "); writeln!(f, " {{")?; for (field_name, field) in fields { write!(f, "{field_name}: ")?; @@ -320,7 +329,7 @@ impl Insn { } writeln!(f, ",")?; } - write!(f.writer, "}}") + write!(f.into_inner(), "}}") } } diff --git a/crates/fayalite/src/sim/interpreter/parts.rs b/crates/fayalite/src/sim/interpreter/parts.rs index 87321466..75427c9a 100644 --- a/crates/fayalite/src/sim/interpreter/parts.rs +++ b/crates/fayalite/src/sim/interpreter/parts.rs @@ -9,7 +9,7 @@ use crate::{ Insn, InsnsBuilding, InsnsBuildingDone, InsnsBuildingKind, PrefixLinesWrapper, SmallSInt, SmallUInt, State, }, - value::{DynSimOnlyValue, DynSimOnly}, + value::{DynSimOnly, DynSimOnlyValue}, }, ty::CanonicalType, util::{chain, const_str_cmp}, @@ -435,12 +435,7 @@ impl StatePartIndex { if state.is_some() || debug_data.is_some() { f.write_str(comment_start)?; } - let mut f = PrefixLinesWrapper { - writer: f, - at_beginning_of_line: false, - blank_line_prefix: comment_line_start.trim_end(), - line_prefix: comment_line_start, - }; + let mut f = PrefixLinesWrapper::new(f, false, comment_line_start); if let Some(state) = state { f.write_str("(")?; K::debug_fmt_state_value(state, *self, &mut f)?; @@ -453,7 +448,7 @@ impl StatePartIndex { write!(f, "{debug_data:?}")?; } if state.is_some() || debug_data.is_some() { - f.writer.write_str(comment_end)?; + f.into_inner().write_str(comment_end)?; } Ok(()) } diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs index 97174178..89eb4e60 100644 --- a/crates/fayalite/src/sim/value.rs +++ b/crates/fayalite/src/sim/value.rs @@ -394,6 +394,30 @@ impl SimValuePartialEq for Bool { } } +impl SimValuePartialEq for Clock { + fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { + **this == **other + } +} + +impl SimValuePartialEq for Reset { + fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { + **this == **other + } +} + +impl SimValuePartialEq for SyncReset { + fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { + **this == **other + } +} + +impl SimValuePartialEq for AsyncReset { + fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { + **this == **other + } +} + pub trait ToSimValue: ToSimValueWithType<::Type> { type Type: Type; @@ -1302,6 +1326,20 @@ impl ToSimValue for SimOnlyValue { } } +impl SimValuePartialEq for DynSimOnly { + fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool { + **this == **other + } +} + +impl, U: SimOnlyValueTrait> SimValuePartialEq> + for SimOnly +{ + fn sim_value_eq(this: &SimValue, other: &SimValue>) -> bool { + ***this == ***other + } +} + #[cfg(test)] mod tests { use super::*; diff --git a/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs b/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs index 98a199c8..3df80a8e 100644 --- a/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs +++ b/crates/fayalite/src/sim/value/sim_only_value_unsafe.rs @@ -206,9 +206,25 @@ impl Default for SimOnly { } /// a value that can only be used in a Fayalite simulation, it can't be converted to FIRRTL -#[derive(Clone, Eq, PartialEq, Hash, Default, PartialOrd, Ord)] +#[derive(Clone, Eq, Hash, Default, Ord)] pub struct SimOnlyValue(Rc); +impl, U: SimOnlyValueTrait> PartialEq> + for SimOnlyValue +{ + fn eq(&self, other: &SimOnlyValue) -> bool { + >::eq(self, other) + } +} + +impl, U: SimOnlyValueTrait> PartialOrd> + for SimOnlyValue +{ + fn partial_cmp(&self, other: &SimOnlyValue) -> Option { + >::partial_cmp(self, other) + } +} + impl SimOnlyValue { pub fn with_dyn_ref R, R>(&self, f: F) -> R { // Safety: creating a copied `Rc` is safe as long as the copy isn't dropped and isn't changed diff --git a/crates/fayalite/tests/sim.rs b/crates/fayalite/tests/sim.rs index 6d0380ba..b4169c68 100644 --- a/crates/fayalite/tests/sim.rs +++ b/crates/fayalite/tests/sim.rs @@ -2375,3 +2375,123 @@ fn test_phantom_const() { panic!(); } } + +#[hdl_module(outline_generated, extern)] +pub fn sim_read_past() +where + ConstUsize: KnownSize, +{ + #[hdl] + let clocks: Array = m.input(); + #[hdl] + let outputs: Array, N> = m.output(); + #[hdl] + let past_clocks: Array = m.output(); + #[hdl] + let past_outputs: Array, N> = m.output(); + for clock in clocks { + m.register_clock_for_past(clock); + } + m.extern_module_simulation_fn( + (clocks, outputs, past_clocks, past_outputs), + |(clocks, outputs, past_clocks, past_outputs), mut sim| async move { + sim.write(outputs, [0u8; N]).await; + sim.write(past_clocks, [false; N]).await; + sim.write(past_outputs, [0u8; N]).await; + loop { + sim.fork_join_scope(|scope, _| async move { + for (clock, output) in clocks.into_iter().zip(outputs) { + scope.spawn_detached( + move |_, mut sim: ExternModuleSimulationState| async move { + sim.wait_for_clock_edge(clock).await; + dbg!(clock); + let v = sim + .read_bool_or_int(output) + .await + .to_bigint() + .try_into() + .expect("known to be in range"); + sim.write(output, 1u8.wrapping_add(v)).await; + let past_outputs_v = sim.read_past(outputs, clock).await; + dbg!(&past_outputs_v); + sim.write(past_outputs, past_outputs_v).await; + let past_clocks_v = sim.read_past(clocks, clock).await; + dbg!(&past_clocks_v); + sim.write(past_clocks, past_clocks_v).await; + }, + ); + } + }) + .await; + } + }, + ); +} + +#[test] +fn test_sim_read_past() { + let _n = SourceLocation::normalize_files_for_tests(); + const N: usize = 3; + let mut sim = Simulation::new(sim_read_past::()); + // sim.set_breakpoints_unstable(Default::default(), true); + let mut writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + sim.write(sim.io().clocks, [false; N]); + let mut clocks_triggered = [false; N]; + let mut expected = [0u8; N]; + let mut past_clocks_expected = [false; N]; + let mut past_expected = expected; + for i0 in 0..N { + for i1 in 0..N { + for i2 in 0..N { + for i3 in 0..N { + let indexes = [i0, i1, i2, i3]; + for i in indexes { + sim.advance_time(SimDuration::from_micros(1)); + sim.write(sim.io().clocks[i], true); + sim.advance_time(SimDuration::from_micros(1)); + sim.write(sim.io().clocks[i], false); + if !clocks_triggered[i] { + past_expected = expected; + expected[i] = expected[i].wrapping_add(1); + past_clocks_expected = [false; N]; + past_clocks_expected[i] = true; + } + dbg!(past_expected); + clocks_triggered[i] = true; + if clocks_triggered == [true; N] { + clocks_triggered = [false; N]; + } + let output = sim.read(sim.io().outputs); + assert_eq!(output, expected.to_sim_value(), "indexes={indexes:?} i={i}"); + let past_clocks = sim.read(sim.io().past_clocks); + assert_eq!( + past_clocks, + past_clocks_expected + .to_sim_value_with_type(Array::::default()), + "indexes={indexes:?} i={i}" + ); + let past_outputs = sim.read(sim.io().past_outputs); + dbg!(&past_outputs); + assert_eq!( + past_outputs, + past_expected.to_sim_value(), + "indexes={indexes:?} i={i}" + ); + } + } + } + } + } + sim.flush_traces().unwrap(); + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("sim/expected/sim_read_past.vcd") { + panic!(); + } + let sim_debug = format!("{sim:#?}"); + println!("#######\n{sim_debug}\n#######"); + if sim_debug != include_str!("sim/expected/sim_read_past.txt") { + panic!(); + } +} diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt index 2f25f359..27b040d2 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.txt +++ b/crates/fayalite/tests/sim/expected/array_rw.txt @@ -826,6 +826,7 @@ Simulation { }.write_index, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt index 47997e5b..d4707926 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt @@ -122,6 +122,7 @@ Simulation { }.i, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt index ac6c052b..56ea4ad7 100644 --- a/crates/fayalite/tests/sim/expected/connect_const.txt +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -98,6 +98,7 @@ Simulation { }.o, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt index 999f414c..a9c18783 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -141,6 +141,7 @@ Simulation { }.reset_out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index 7a43720e..86bde889 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -100,51 +100,51 @@ Simulation { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset }, }, + 3: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, + }, + 4: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 3: Const { + 5: Const { dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, value: 0x3, }, // at: module-XXXXXXXXXX.rs:3:1 - 4: BranchIfZero { - target: 6, + 6: BranchIfZero { + target: 8, value: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, }, - 5: Copy { + 7: Copy { dest: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, src: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:1:1 - 6: Add { + 8: Add { dest: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, lhs: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, rhs: StatePartIndex(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> }, }, - 7: CastToUInt { + 9: CastToUInt { dest: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, src: StatePartIndex(8), // (0x4) SlotDebugData { name: "", ty: UInt<5> }, dest_width: 4, }, // at: module-XXXXXXXXXX.rs:4:1 - 8: Copy { + 10: Copy { dest: StatePartIndex(4), // (0x4) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> }, src: StatePartIndex(9), // (0x4) SlotDebugData { name: "", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:6:1 - 9: Copy { + 11: Copy { dest: StatePartIndex(2), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> }, src: StatePartIndex(3), // (0x3) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> }, }, // at: module-XXXXXXXXXX.rs:3:1 - 10: IsNonZeroDestIsSmall { - dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, - }, - 11: AndSmall { - dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, 12: BranchIfSmallNonZero { target: 16, value: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, @@ -261,6 +261,7 @@ Simulation { }.count, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index b96ce5fd..0a7517e9 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -112,21 +112,21 @@ Simulation { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: SyncReset }, }, - // at: module-XXXXXXXXXX.rs:1:1 - 6: Const { - dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, - value: 0x3, - }, - // at: module-XXXXXXXXXX.rs:3:1 - 7: IsNonZeroDestIsSmall { + 6: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock }, }, - 8: AndSmall { + 7: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + // at: module-XXXXXXXXXX.rs:1:1 + 8: Const { + dest: StatePartIndex(5), // (0x3) SlotDebugData { name: "", ty: UInt<4> }, + value: 0x3, + }, + // at: module-XXXXXXXXXX.rs:3:1 9: BranchIfSmallZero { target: 14, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, @@ -242,6 +242,7 @@ Simulation { }.count, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt index e127210b..64bbbe63 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.txt +++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt @@ -102,6 +102,7 @@ Simulation { uninitialized_ios: {}, io_targets: {}, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index eeef867d..a193e926 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1003,65 +1003,64 @@ Simulation { dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.rst", ty: SyncReset }, }, + 97: IsNonZeroDestIsSmall { + dest: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock }, + }, + 98: AndSmall { + dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, // at: module-XXXXXXXXXX.rs:1:1 - 97: Const { + 99: Const { dest: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, value: 0x0, }, - 98: Copy { + 100: Copy { dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(25), // (0x0) SlotDebugData { name: "", ty: UInt<6> }, }, // at: module-XXXXXXXXXX.rs:12:1 - 99: BranchIfZero { - target: 107, + 101: BranchIfZero { + target: 109, value: StatePartIndex(2), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::en", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:13:1 - 100: BranchIfZero { - target: 102, + 102: BranchIfZero { + target: 104, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:14:1 - 101: Copy { + 103: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(26), // (0x0) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:13:1 - 102: BranchIfNonZero { - target: 107, + 104: BranchIfNonZero { + target: 109, value: StatePartIndex(46), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:15:1 - 103: BranchIfZero { - target: 105, + 105: BranchIfZero { + target: 107, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:16:1 - 104: Copy { + 106: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(65), // (0xd) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, // at: module-XXXXXXXXXX.rs:15:1 - 105: BranchIfNonZero { - target: 107, + 107: BranchIfNonZero { + target: 109, value: StatePartIndex(48), // (0x0) SlotDebugData { name: "", ty: Bool }, }, // at: module-XXXXXXXXXX.rs:17:1 - 106: Copy { + 108: Copy { dest: StatePartIndex(24), // (0x3e) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::the_reg$next", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, src: StatePartIndex(87), // (0x3e) SlotDebugData { name: "", ty: Enum {A, B(Bundle {0: UInt<1>, 1: Bool}), C(Bundle {a: Array, 2>, b: SInt<2>})} }, }, - // at: module-XXXXXXXXXX.rs:11:1 - 107: IsNonZeroDestIsSmall { - dest: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::cd.clk", ty: Clock }, - }, - 108: AndSmall { - dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - lhs: StatePartIndex(4), // (0x1 1) SlotDebugData { name: "", ty: Bool }, - rhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, - }, // at: module-XXXXXXXXXX.rs:10:1 109: Copy { dest: StatePartIndex(15), // (0x0) SlotDebugData { name: "InstantiatedModule(enums: enums).enums::b2_out", ty: Enum {HdlNone, HdlSome(Bundle {0: UInt<1>, 1: Bool})} }, @@ -1454,6 +1453,7 @@ Simulation { }.which_out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/extern_module.txt b/crates/fayalite/tests/sim/expected/extern_module.txt index 03349409..f49106f6 100644 --- a/crates/fayalite/tests/sim/expected/extern_module.txt +++ b/crates/fayalite/tests/sim/expected/extern_module.txt @@ -102,6 +102,7 @@ Simulation { }.o, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -136,6 +137,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -228,7 +230,7 @@ Simulation { index: StatePartIndex(1), }, state: 0x1, - last_state: 0x1, + last_state: 0x0, }, ], trace_memories: {}, @@ -245,7 +247,14 @@ Simulation { event_queue: EventQueue(EventQueueData { instant: 20 μs, events: { - Event { instant: 20.500000000000 μs, kind: ExternModule(0) }: 1, + Event { + instant: 20.500000000000 μs, + kind: ExternModule( + 0, + ), + }: Wakers( + 1, + ), }, }), waiting_sensitivity_sets_by_address: {}, diff --git a/crates/fayalite/tests/sim/expected/extern_module2.txt b/crates/fayalite/tests/sim/expected/extern_module2.txt index 3d7cfaef..fa6e767e 100644 --- a/crates/fayalite/tests/sim/expected/extern_module2.txt +++ b/crates/fayalite/tests/sim/expected/extern_module2.txt @@ -121,6 +121,7 @@ Simulation { }.o, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -167,6 +168,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { diff --git a/crates/fayalite/tests/sim/expected/many_memories.txt b/crates/fayalite/tests/sim/expected/many_memories.txt index f311cf7e..c521d725 100644 --- a/crates/fayalite/tests/sim/expected/many_memories.txt +++ b/crates/fayalite/tests/sim/expected/many_memories.txt @@ -3834,6 +3834,7 @@ Simulation { }.w[7].mask, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt index 03c5ee37..0358bb31 100644 --- a/crates/fayalite/tests/sim/expected/memories.txt +++ b/crates/fayalite/tests/sim/expected/memories.txt @@ -719,6 +719,7 @@ Simulation { }.w.mask.1, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt index f1cb72b6..b4041ba1 100644 --- a/crates/fayalite/tests/sim/expected/memories2.txt +++ b/crates/fayalite/tests/sim/expected/memories2.txt @@ -677,6 +677,7 @@ Simulation { }.rw.wmode, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt index 3166e17b..2213912c 100644 --- a/crates/fayalite/tests/sim/expected/memories3.txt +++ b/crates/fayalite/tests/sim/expected/memories3.txt @@ -1761,6 +1761,7 @@ Simulation { }.w.mask[7], }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt index 355b6ee0..3f7a55e5 100644 --- a/crates/fayalite/tests/sim/expected/mod1.txt +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -274,6 +274,7 @@ Simulation { }.o.o2, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/phantom_const.txt b/crates/fayalite/tests/sim/expected/phantom_const.txt index dbc8f129..8c2237dd 100644 --- a/crates/fayalite/tests/sim/expected/phantom_const.txt +++ b/crates/fayalite/tests/sim/expected/phantom_const.txt @@ -240,6 +240,7 @@ Simulation { }.out[1], }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/ripple_counter.txt b/crates/fayalite/tests/sim/expected/ripple_counter.txt index 58189754..9e46be41 100644 --- a/crates/fayalite/tests/sim/expected/ripple_counter.txt +++ b/crates/fayalite/tests/sim/expected/ripple_counter.txt @@ -743,6 +743,7 @@ Simulation { }.o, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -777,6 +778,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -860,6 +862,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -943,6 +946,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt index 2ca06d2d..7dcf26c5 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -128,21 +128,21 @@ Simulation { dest: StatePartIndex(3), // (0x0 0) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", ty: SyncReset }, }, - // at: module-XXXXXXXXXX.rs:1:1 - 6: Const { - dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, - value: 0x0, - }, - // at: module-XXXXXXXXXX.rs:5:1 - 7: IsNonZeroDestIsSmall { + 6: IsNonZeroDestIsSmall { dest: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, src: StatePartIndex(0), // (0x1) SlotDebugData { name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", ty: Clock }, }, - 8: AndSmall { + 7: AndSmall { dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, lhs: StatePartIndex(2), // (0x1 1) SlotDebugData { name: "", ty: Bool }, rhs: StatePartIndex(0), // (0x0 0) SlotDebugData { name: "", ty: Bool }, }, + // at: module-XXXXXXXXXX.rs:1:1 + 8: Const { + dest: StatePartIndex(6), // (0x0) SlotDebugData { name: "", ty: Bool }, + value: 0x0, + }, + // at: module-XXXXXXXXXX.rs:5:1 9: BranchIfSmallZero { target: 14, value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, @@ -337,6 +337,7 @@ Simulation { }.q, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [], trace_decls: TraceModule { diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join.txt b/crates/fayalite/tests/sim/expected/sim_fork_join.txt index 4ad3e620..680fedb9 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join.txt +++ b/crates/fayalite/tests/sim/expected/sim_fork_join.txt @@ -164,6 +164,7 @@ Simulation { }.outputs[2], }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -234,6 +235,7 @@ Simulation { }[2], }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -433,7 +435,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[0]", ty: Clock, }, ], @@ -482,7 +484,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[0]", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt index ba5577d4..40d16a90 100644 --- a/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt +++ b/crates/fayalite/tests/sim/expected/sim_fork_join_scope.txt @@ -164,6 +164,7 @@ Simulation { }.outputs[2], }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -234,6 +235,7 @@ Simulation { }[2], }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -433,7 +435,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[0]", ty: Clock, }, ], @@ -482,7 +484,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_fork_join_scope: sim_fork_join_scope).sim_fork_join_scope::clocks[0]", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_only_connects.txt b/crates/fayalite/tests/sim/expected/sim_only_connects.txt index 3c1605d1..15456d20 100644 --- a/crates/fayalite/tests/sim/expected/sim_only_connects.txt +++ b/crates/fayalite/tests/sim/expected/sim_only_connects.txt @@ -557,6 +557,7 @@ Simulation { }.out3, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -635,6 +636,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -794,6 +796,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -1559,7 +1562,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock, }, ], @@ -1609,7 +1612,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock, }, ], @@ -1658,7 +1661,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_only_connects.helper1: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock, }, ], @@ -1707,7 +1710,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_only_connects.helper2: sim_only_connects_helper).sim_only_connects_helper::cd.clk", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.txt b/crates/fayalite/tests/sim/expected/sim_read_past.txt new file mode 100644 index 00000000..475943ec --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_read_past.txt @@ -0,0 +1,9724 @@ +Simulation { + state: State { + insns: Insns { + state_layout: StateLayout { + ty: TypeLayout { + small_slots: StatePartLayout { + len: 9, + debug_data: [ + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + SlotDebugData { + name: "", + ty: Bool, + }, + ], + .. + }, + big_slots: StatePartLayout { + len: 48, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[2]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[2]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[0]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[1]", + ty: UInt<8>, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + memories: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + insns: [ + // at: module-XXXXXXXXXX.rs:2:1 + 0: IsNonZeroDestIsSmall { + dest: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, + }, + 1: AndSmall { + dest: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 2: IsNonZeroDestIsSmall { + dest: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, + }, + 3: AndSmall { + dest: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 4: IsNonZeroDestIsSmall { + dest: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, + }, + 5: AndSmall { + dest: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + }, + 6: BranchIfSmallZero { + target: 10, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 7: Copy { + dest: StatePartIndex(12), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[0]", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, + }, + 8: Copy { + dest: StatePartIndex(13), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[1]", ty: Clock }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, + }, + 9: Copy { + dest: StatePartIndex(14), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[0])[2]", ty: Clock }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 10: BranchIfSmallZero { + target: 14, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 11: Copy { + dest: StatePartIndex(15), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[0]", ty: UInt<8> }, + src: StatePartIndex(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> }, + }, + 12: Copy { + dest: StatePartIndex(16), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[1]", ty: UInt<8> }, + src: StatePartIndex(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> }, + }, + 13: Copy { + dest: StatePartIndex(17), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[0])[2]", ty: UInt<8> }, + src: StatePartIndex(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 14: BranchIfSmallZero { + target: 18, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 15: Copy { + dest: StatePartIndex(18), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[0]", ty: Clock }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock }, + }, + 16: Copy { + dest: StatePartIndex(19), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[1]", ty: Clock }, + src: StatePartIndex(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock }, + }, + 17: Copy { + dest: StatePartIndex(20), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[0])[2]", ty: Clock }, + src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 18: BranchIfSmallZero { + target: 22, + value: StatePartIndex(1), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 19: Copy { + dest: StatePartIndex(21), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[0]", ty: UInt<8> }, + src: StatePartIndex(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> }, + }, + 20: Copy { + dest: StatePartIndex(22), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[1]", ty: UInt<8> }, + src: StatePartIndex(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> }, + }, + 21: Copy { + dest: StatePartIndex(23), // (0x30) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[0])[2]", ty: UInt<8> }, + src: StatePartIndex(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + 22: BranchIfSmallZero { + target: 26, + value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 23: Copy { + dest: StatePartIndex(24), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[0]", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, + }, + 24: Copy { + dest: StatePartIndex(25), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[1]", ty: Clock }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, + }, + 25: Copy { + dest: StatePartIndex(26), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[1])[2]", ty: Clock }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 26: BranchIfSmallZero { + target: 30, + value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 27: Copy { + dest: StatePartIndex(27), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[0]", ty: UInt<8> }, + src: StatePartIndex(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> }, + }, + 28: Copy { + dest: StatePartIndex(28), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[1]", ty: UInt<8> }, + src: StatePartIndex(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> }, + }, + 29: Copy { + dest: StatePartIndex(29), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[1])[2]", ty: UInt<8> }, + src: StatePartIndex(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 30: BranchIfSmallZero { + target: 34, + value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 31: Copy { + dest: StatePartIndex(30), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[0]", ty: Clock }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock }, + }, + 32: Copy { + dest: StatePartIndex(31), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[1]", ty: Clock }, + src: StatePartIndex(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock }, + }, + 33: Copy { + dest: StatePartIndex(32), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[1])[2]", ty: Clock }, + src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 34: BranchIfSmallZero { + target: 38, + value: StatePartIndex(4), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 35: Copy { + dest: StatePartIndex(33), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[0]", ty: UInt<8> }, + src: StatePartIndex(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> }, + }, + 36: Copy { + dest: StatePartIndex(34), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[1]", ty: UInt<8> }, + src: StatePartIndex(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> }, + }, + 37: Copy { + dest: StatePartIndex(35), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[1])[2]", ty: UInt<8> }, + src: StatePartIndex(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + 38: BranchIfSmallZero { + target: 42, + value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 39: Copy { + dest: StatePartIndex(36), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[0]", ty: Clock }, + src: StatePartIndex(0), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", ty: Clock }, + }, + 40: Copy { + dest: StatePartIndex(37), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[1]", ty: Clock }, + src: StatePartIndex(1), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", ty: Clock }, + }, + 41: Copy { + dest: StatePartIndex(38), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks$past(sim_read_past::clocks[2])[2]", ty: Clock }, + src: StatePartIndex(2), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:3:1 + 42: BranchIfSmallZero { + target: 46, + value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 43: Copy { + dest: StatePartIndex(39), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[0]", ty: UInt<8> }, + src: StatePartIndex(3), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", ty: UInt<8> }, + }, + 44: Copy { + dest: StatePartIndex(40), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[1]", ty: UInt<8> }, + src: StatePartIndex(4), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", ty: UInt<8> }, + }, + 45: Copy { + dest: StatePartIndex(41), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[2]", ty: UInt<8> }, + src: StatePartIndex(5), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:4:1 + 46: BranchIfSmallZero { + target: 50, + value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 47: Copy { + dest: StatePartIndex(42), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[0]", ty: Clock }, + src: StatePartIndex(6), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", ty: Clock }, + }, + 48: Copy { + dest: StatePartIndex(43), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[1]", ty: Clock }, + src: StatePartIndex(7), // (0x1) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[1]", ty: Clock }, + }, + 49: Copy { + dest: StatePartIndex(44), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[2]", ty: Clock }, + src: StatePartIndex(8), // (0x0) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", ty: Clock }, + }, + // at: module-XXXXXXXXXX.rs:5:1 + 50: BranchIfSmallZero { + target: 54, + value: StatePartIndex(7), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + }, + 51: Copy { + dest: StatePartIndex(45), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[0]", ty: UInt<8> }, + src: StatePartIndex(9), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", ty: UInt<8> }, + }, + 52: Copy { + dest: StatePartIndex(46), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[1]", ty: UInt<8> }, + src: StatePartIndex(10), // (0x31) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", ty: UInt<8> }, + }, + 53: Copy { + dest: StatePartIndex(47), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]", ty: UInt<8> }, + src: StatePartIndex(11), // (0x32) SlotDebugData { name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", ty: UInt<8> }, + }, + // at: module-XXXXXXXXXX.rs:2:1 + 54: XorSmallImmediate { + dest: StatePartIndex(0), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(2), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 55: XorSmallImmediate { + dest: StatePartIndex(3), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(5), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + 56: XorSmallImmediate { + dest: StatePartIndex(6), // (0x1 1) SlotDebugData { name: "", ty: Bool }, + lhs: StatePartIndex(8), // (0x0 0) SlotDebugData { name: "", ty: Bool }, + rhs: 0x1, + }, + // at: module-XXXXXXXXXX.rs:1:1 + 57: Return, + ], + .. + }, + pc: 57, + memory_write_log: [], + memories: StatePart { + value: [], + }, + small_slots: StatePart { + value: [ + 1, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + ], + }, + big_slots: StatePart { + value: [ + 0, + 0, + 0, + 49, + 50, + 50, + 0, + 1, + 0, + 49, + 49, + 50, + 1, + 0, + 0, + 48, + 49, + 49, + 0, + 0, + 1, + 48, + 49, + 48, + 0, + 1, + 0, + 49, + 49, + 50, + 0, + 0, + 1, + 49, + 49, + 49, + 0, + 0, + 1, + 49, + 50, + 50, + 0, + 1, + 0, + 49, + 49, + 50, + ], + }, + sim_only_slots: StatePart { + value: [], + }, + }, + io: Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.clocks, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.outputs, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_clocks, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_outputs, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.clocks, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.clocks[0], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.clocks[1], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.clocks[2], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.outputs, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.outputs[0], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.outputs[1], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.outputs[2], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_clocks, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_clocks[0], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_clocks[1], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_clocks[2], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_outputs, + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_outputs[0], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_outputs[1], + Instance { + name: ::sim_read_past, + instantiated: Module { + name: sim_read_past, + .. + }, + }.past_outputs[2], + }, + did_initial_settle: true, + clocks_for_past: {}, + }, + extern_modules: [ + SimulationExternModuleState { + module_state: SimulationModuleState { + base_targets: [ + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ], + uninitialized_ios: {}, + io_targets: { + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }[0], + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }[1], + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }[2], + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }[0], + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }[1], + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }[2], + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }[0], + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }[1], + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }[2], + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }[0], + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }[1], + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }[2], + }, + did_initial_settle: true, + clocks_for_past: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimulationExternModuleClockForPast { + current_to_past_map: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Array, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 3, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[1]", + ty: Clock, + }, + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Array { + elements_non_empty: [ + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + 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len: 0 }, + big_slots: StatePartIndexRange { start: 42, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 6, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + 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StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 8, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_clocks$past(sim_read_past::clocks[2])[2]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: 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+ layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[0]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 3, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: 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StatePartIndexRange { start: 3, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[1]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 40, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[1]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 4, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs$past(sim_read_past::clocks[2])[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 41, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::outputs[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 5, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 9, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[0]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 45, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[0]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 9, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[1]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 46, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[1]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 10, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 11, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: CompiledValue { + layout: CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs$past(sim_read_past::clocks[2])[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 9, len: 0 }, + big_slots: StatePartIndexRange { start: 47, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: Some( + ( + CompiledTypeLayout { + ty: UInt<8>, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::past_outputs[2]", + ty: UInt<8>, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 11, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + ), + ), + }, + }, + }, + }, + }, + sim: ExternModuleSimulation { + generator: SimGeneratorFn { + args: ( + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ), + f: ..., + }, + sim_io_to_generator_map: { + ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }: ModuleIO { + name: sim_read_past::clocks, + is_input: true, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }: ModuleIO { + name: sim_read_past::outputs, + is_input: false, + ty: Array, 3>, + .. + }, + ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }: ModuleIO { + name: sim_read_past::past_clocks, + is_input: false, + ty: Array, + .. + }, + ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }: ModuleIO { + name: sim_read_past::past_outputs, + is_input: false, + ty: Array, 3>, + .. + }, + }, + source_location: SourceLocation( + module-XXXXXXXXXX.rs:6:1, + ), + }, + running_generator: Some( + ..., + ), + }, + ], + trace_decls: TraceModule { + name: "sim_read_past", + children: [ + TraceModuleIO { + name: "clocks", + child: TraceArray { + name: "clocks", + elements: [ + TraceClock { + location: TraceScalarId(0), + name: "[0]", + flow: Source, + }, + TraceClock { + location: TraceScalarId(1), + name: "[1]", + flow: Source, + }, + TraceClock { + location: TraceScalarId(2), + name: "[2]", + flow: Source, + }, + ], + ty: Array, + flow: Source, + }, + ty: Array, + flow: Source, + }, + TraceModuleIO { + name: "outputs", + child: TraceArray { + name: "outputs", + elements: [ + TraceUInt { + location: TraceScalarId(3), + name: "[0]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(4), + name: "[1]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(5), + name: "[2]", + ty: UInt<8>, + flow: Sink, + }, + ], + ty: Array, 3>, + flow: Sink, + }, + ty: Array, 3>, + flow: Sink, + }, + TraceModuleIO { + name: "past_clocks", + child: TraceArray { + name: "past_clocks", + elements: [ + TraceClock { + location: TraceScalarId(6), + name: "[0]", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(7), + name: "[1]", + flow: Sink, + }, + TraceClock { + location: TraceScalarId(8), + name: "[2]", + flow: Sink, + }, + ], + ty: Array, + flow: Sink, + }, + ty: Array, + flow: Sink, + }, + TraceModuleIO { + name: "past_outputs", + child: TraceArray { + name: "past_outputs", + elements: [ + TraceUInt { + location: TraceScalarId(9), + name: "[0]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(10), + name: "[1]", + ty: UInt<8>, + flow: Sink, + }, + TraceUInt { + location: TraceScalarId(11), + name: "[2]", + ty: UInt<8>, + flow: Sink, + }, + ], + ty: Array, 3>, + flow: Sink, + }, + ty: Array, 3>, + flow: Sink, + }, + ], + }, + traces: [ + SimTrace { + id: TraceScalarId(0), + kind: BigClock { + index: StatePartIndex(0), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(1), + kind: BigClock { + index: StatePartIndex(1), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(2), + kind: BigClock { + index: StatePartIndex(2), + }, + state: 0x0, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(3), + kind: BigUInt { + index: StatePartIndex(3), + ty: UInt<8>, + }, + state: 0x31, + last_state: 0x31, + }, + SimTrace { + id: TraceScalarId(4), + kind: BigUInt { + index: StatePartIndex(4), + ty: UInt<8>, + }, + state: 0x32, + last_state: 0x32, + }, + SimTrace { + id: TraceScalarId(5), + kind: BigUInt { + index: StatePartIndex(5), + ty: UInt<8>, + }, + state: 0x32, + last_state: 0x32, + }, + SimTrace { + id: TraceScalarId(6), + kind: BigClock { + index: StatePartIndex(6), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(7), + kind: BigClock { + index: StatePartIndex(7), + }, + state: 0x1, + last_state: 0x1, + }, + SimTrace { + id: TraceScalarId(8), + kind: BigClock { + index: StatePartIndex(8), + }, + state: 0x0, + last_state: 0x0, + }, + SimTrace { + id: TraceScalarId(9), + kind: BigUInt { + index: StatePartIndex(9), + ty: UInt<8>, + }, + state: 0x31, + last_state: 0x31, + }, + SimTrace { + id: TraceScalarId(10), + kind: BigUInt { + index: StatePartIndex(10), + ty: UInt<8>, + }, + state: 0x31, + last_state: 0x31, + }, + SimTrace { + id: TraceScalarId(11), + kind: BigUInt { + index: StatePartIndex(11), + ty: UInt<8>, + }, + state: 0x32, + last_state: 0x32, + }, + ], + trace_memories: {}, + trace_writers: [ + Running( + VcdWriter { + finished_init: true, + timescale: 1 ps, + .. + }, + ), + ], + clocks_triggered: [ + StatePartIndex(1), + StatePartIndex(4), + StatePartIndex(7), + ], + event_queue: EventQueue(EventQueueData { + instant: 648 μs, + events: {}, + }), + waiting_sensitivity_sets_by_address: { + SensitivitySet { + id: 198, + values: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + }, + changed: Cell { + value: false, + }, + .. + }, + }, + waiting_sensitivity_sets_by_compiled_value: { + CompiledValue { + layout: CompiledTypeLayout { + ty: Clock, + layout: TypeLayout { + small_slots: StatePartLayout { + len: 0, + debug_data: [], + .. + }, + big_slots: StatePartLayout { + len: 1, + debug_data: [ + SlotDebugData { + name: "InstantiatedModule(sim_read_past: sim_read_past).sim_read_past::clocks[0]", + ty: Clock, + }, + ], + .. + }, + sim_only_slots: StatePartLayout { + len: 0, + debug_data: [], + layout_data: [], + .. + }, + }, + body: Scalar, + }, + range: TypeIndexRange { + small_slots: StatePartIndexRange { start: 0, len: 0 }, + big_slots: StatePartIndexRange { start: 0, len: 1 }, + sim_only_slots: StatePartIndexRange { start: 0, len: 0 }, + }, + write: None, + }: ( + SimValue { + ty: Clock, + value: OpaqueSimValue { + bits: 0x0_u1, + sim_only_values: [], + }, + }, + { + SensitivitySet { + id: 198, + .. + }, + }, + ), + }, + .. +} \ No newline at end of file diff --git a/crates/fayalite/tests/sim/expected/sim_read_past.vcd b/crates/fayalite/tests/sim/expected/sim_read_past.vcd new file mode 100644 index 00000000..5d0a932d --- /dev/null +++ b/crates/fayalite/tests/sim/expected/sim_read_past.vcd @@ -0,0 +1,1908 @@ +$timescale 1 ps $end +$scope module sim_read_past $end +$scope struct clocks $end +$var wire 1 ! \[0] $end +$var wire 1 " \[1] $end +$var wire 1 # \[2] $end +$upscope $end +$scope struct outputs $end +$var wire 8 $ \[0] $end +$var wire 8 % \[1] $end +$var wire 8 & \[2] $end +$upscope $end +$scope struct past_clocks $end +$var wire 1 ' \[0] $end +$var wire 1 ( \[1] $end +$var wire 1 ) \[2] $end +$upscope $end +$scope struct past_outputs $end +$var wire 8 * \[0] $end +$var wire 8 + \[1] $end +$var wire 8 , \[2] $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +0" +0# +b0 $ +b0 % +b0 & +0' +0( +0) +b0 * +b0 + +b0 , +$end +#1000000 +1! +b1 $ +1' +#2000000 +0! +#3000000 +1! +#4000000 +0! +#5000000 +1! +#6000000 +0! +#7000000 +1! +#8000000 +0! +#9000000 +1! +#10000000 +0! +#11000000 +1! +#12000000 +0! +#13000000 +1! +#14000000 +0! +#15000000 +1" +b1 % +b1 * +0' +1( +#16000000 +0" +#17000000 +1! +#18000000 +0! +#19000000 +1! +#20000000 +0! +#21000000 +1! +#22000000 +0! +#23000000 +1# +b1 & +b1 + +0( +1) +#24000000 +0# +#25000000 +1! +b10 $ +b1 , +1' +0) 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+1! +b11110 $ +b11110 + +1' +0( +#392000000 +0! +#393000000 +1" +b11111 % +b11110 * +0' +1( +#394000000 +0" +#395000000 +1# +b11111 & +b11111 + +0( +1) +#396000000 +0# +#397000000 +1" +#398000000 +0" +#399000000 +1" +#400000000 +0" +#401000000 +1" +#402000000 +0" +#403000000 +1# +#404000000 +0# +#405000000 +1" +#406000000 +0" +#407000000 +1# +#408000000 +0# +#409000000 +1" +#410000000 +0" +#411000000 +1# +#412000000 +0# +#413000000 +1# +#414000000 +0# +#415000000 +1! +b11111 $ +b11111 , +1' +0) +#416000000 +0! +#417000000 +1" +b100000 % +b11111 * +0' +1( +#418000000 +0" +#419000000 +1# +b100000 & +b100000 + +0( +1) +#420000000 +0# +#421000000 +1# +#422000000 +0# +#423000000 +1" +#424000000 +0" +#425000000 +1" +#426000000 +0" +#427000000 +1# +#428000000 +0# +#429000000 +1# +#430000000 +0# +#431000000 +1# +#432000000 +0# +#433000000 +1# +#434000000 +0# +#435000000 +1! +b100000 $ +b100000 , +1' +0) +#436000000 +0! +#437000000 +1! +b100001 $ +b100000 * +#438000000 +0! +#439000000 +1! +#440000000 +0! +#441000000 +1# +b100001 & +b100001 * +0' +1) +#442000000 +0# +#443000000 +1! +#444000000 +0! +#445000000 +1! +#446000000 +0! +#447000000 +1" +b100001 % +b100001 , +1( +0) +#448000000 +0" +#449000000 +1# +b100010 & +b100001 + +0( +1) +#450000000 +0# +#451000000 +1! +b100010 $ +b100010 , +1' +0) +#452000000 +0! +#453000000 +1! +#454000000 +0! +#455000000 +1# +#456000000 +0# +#457000000 +1# +#458000000 +0# +#459000000 +1! +#460000000 +0! +#461000000 +1" +b100010 % +b100010 * +0' +1( +#462000000 +0" +#463000000 +1! +b100011 $ +b100010 + +1' +0( +#464000000 +0! +#465000000 +1# +b100011 & +b100011 * +0' +1) +#466000000 +0# +#467000000 +1! +#468000000 +0! +#469000000 +1" +b100011 % +b100011 , +1( +0) +#470000000 +0" +#471000000 +1" +b100100 % +b100011 + +#472000000 +0" +#473000000 +1# +b100100 & +b100100 + +0( +1) +#474000000 +0# +#475000000 +1! +b100100 $ +b100100 , +1' +0) +#476000000 +0! +#477000000 +1" +b100101 % +b100100 * +0' +1( +#478000000 +0" +#479000000 +1# +b100101 & +b100101 + +0( +1) +#480000000 +0# +#481000000 +1# +#482000000 +0# +#483000000 +1! +b100101 $ +b100101 , +1' +0) +#484000000 +0! +#485000000 +1# +b100110 & +b100101 * +0' +1) +#486000000 +0# +#487000000 +1! +b100110 $ +b100110 , +1' +0) +#488000000 +0! +#489000000 +1# +#490000000 +0# +#491000000 +1! +#492000000 +0! +#493000000 +1# +#494000000 +0# +#495000000 +1" +b100110 % +b100110 * +0' +1( +#496000000 +0" +#497000000 +1# +b100111 & +b100110 + +0( +1) +#498000000 +0# +#499000000 +1! +b100111 $ +b100111 , +1' +0) +#500000000 +0! +#501000000 +1# +#502000000 +0# +#503000000 +1# +#504000000 +0# +#505000000 +1# +#506000000 +0# +#507000000 +1" +b100111 % +b100111 * +0' +1( +#508000000 +0" +#509000000 +1! +b101000 $ +b100111 + +1' +0( +#510000000 +0! +#511000000 +1! +#512000000 +0! +#513000000 +1# +b101000 & +b101000 * +0' +1) +#514000000 +0# +#515000000 +1" +b101000 % +b101000 , +1( +0) +#516000000 +0" +#517000000 +1! +b101001 $ +b101000 + +1' +0( +#518000000 +0! +#519000000 +1" +b101001 % +b101001 * +0' +1( +#520000000 +0" +#521000000 +1# +b101001 & +b101001 + +0( +1) +#522000000 +0# +#523000000 +1" +b101010 % +b101001 , +1( +0) +#524000000 +0" +#525000000 +1! +b101010 $ +b101010 + +1' +0( +#526000000 +0! +#527000000 +1# +b101010 & +b101010 * +0' +1) +#528000000 +0# +#529000000 +1# +b101011 & +b101010 , +#530000000 +0# +#531000000 +1" +b101011 % +b101011 , +1( +0) +#532000000 +0" +#533000000 +1" +#534000000 +0" +#535000000 +1! +b101011 $ +b101011 + +1' +0( +#536000000 +0! +#537000000 +1# +b101100 & +b101011 * +0' +1) +#538000000 +0# +#539000000 +1" +b101100 % +b101100 , +1( +0) +#540000000 +0" +#541000000 +1" +#542000000 +0" +#543000000 +1" +#544000000 +0" +#545000000 +1# +#546000000 +0# +#547000000 +1" +#548000000 +0" +#549000000 +1" +#550000000 +0" +#551000000 +1# +#552000000 +0# +#553000000 +1# +#554000000 +0# +#555000000 +1" +#556000000 +0" +#557000000 +1# +#558000000 +0# +#559000000 +1! +b101100 $ +b101100 + +1' +0( +#560000000 +0! +#561000000 +1# +b101101 & +b101100 * +0' +1) +#562000000 +0# +#563000000 +1" +b101101 % +b101101 , +1( +0) +#564000000 +0" +#565000000 +1# +#566000000 +0# +#567000000 +1" +#568000000 +0" +#569000000 +1# +#570000000 +0# +#571000000 +1" +#572000000 +0" +#573000000 +1# +#574000000 +0# +#575000000 +1# +#576000000 +0# +#577000000 +1# +#578000000 +0# +#579000000 +1# +#580000000 +0# +#581000000 +1! +b101101 $ +b101101 + +1' +0( +#582000000 +0! +#583000000 +1! +b101110 $ +b101101 * +#584000000 +0! +#585000000 +1# +b101110 & +b101110 * +0' +1) +#586000000 +0# +#587000000 +1# +#588000000 +0# +#589000000 +1! +#590000000 +0! +#591000000 +1" +b101110 % +b101110 , +1( +0) +#592000000 +0" +#593000000 +1# +b101111 & +b101110 + +0( +1) +#594000000 +0# +#595000000 +1# +#596000000 +0# +#597000000 +1! +b101111 $ +b101111 , +1' +0) +#598000000 +0! +#599000000 +1# +#600000000 +0# +#601000000 +1# +#602000000 +0# +#603000000 +1# +#604000000 +0# +#605000000 +1" +b101111 % +b101111 * +0' +1( +#606000000 +0" +#607000000 +1! +b110000 $ +b101111 + +1' +0( +#608000000 +0! +#609000000 +1# +b110000 & +b110000 * +0' +1) +#610000000 +0# +#611000000 +1# +#612000000 +0# +#613000000 +1" +b110000 % +b110000 , +1( +0) +#614000000 +0" +#615000000 +1" +b110001 % +b110000 + +#616000000 +0" +#617000000 +1# +b110001 & +b110001 + +0( +1) +#618000000 +0# +#619000000 +1# +#620000000 +0# +#621000000 +1" +#622000000 +0" +#623000000 +1# +#624000000 +0# +#625000000 +1# +#626000000 +0# +#627000000 +1# +#628000000 +0# +#629000000 +1# +#630000000 +0# +#631000000 +1! +b110001 $ +b110001 , +1' +0) +#632000000 +0! +#633000000 +1# +b110010 & +b110001 * +0' +1) +#634000000 +0# +#635000000 +1# +#636000000 +0# +#637000000 +1# +#638000000 +0# +#639000000 +1" +b110010 % +b110010 , +1( +0) +#640000000 +0" +#641000000 +1# +#642000000 +0# +#643000000 +1# +#644000000 +0# +#645000000 +1# +#646000000 +0# +#647000000 +1# +#648000000 +0# diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt index 351f944c..7b11157c 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async.txt @@ -121,6 +121,7 @@ Simulation { }.out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -187,6 +188,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -361,7 +363,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", ty: AsyncReset, }, ], @@ -411,7 +413,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -460,7 +462,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", ty: AsyncReset, }, ], @@ -509,7 +511,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt index abd7cf65..0ca767a7 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_async_immediate_reset.txt @@ -121,6 +121,7 @@ Simulation { }.out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -187,6 +188,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -361,7 +363,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", ty: AsyncReset, }, ], @@ -411,7 +413,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -460,7 +462,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.rst", ty: AsyncReset, }, ], @@ -509,7 +511,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt index 8ff0c2fd..4af2eb62 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync.txt @@ -121,6 +121,7 @@ Simulation { }.out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -187,6 +188,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -361,7 +363,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -411,7 +413,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -460,7 +462,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], diff --git a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt index e6819475..45f09d20 100644 --- a/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt +++ b/crates/fayalite/tests/sim/expected/sim_resettable_counter_sync_immediate_reset.txt @@ -121,6 +121,7 @@ Simulation { }.out, }, did_initial_settle: true, + clocks_for_past: {}, }, extern_modules: [ SimulationExternModuleState { @@ -187,6 +188,7 @@ Simulation { }, }, did_initial_settle: true, + clocks_for_past: {}, }, sim: ExternModuleSimulation { generator: SimGeneratorFn { @@ -361,7 +363,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -411,7 +413,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], @@ -460,7 +462,7 @@ Simulation { len: 1, debug_data: [ SlotDebugData { - name: "", + name: "InstantiatedModule(sim_resettable_counter: sim_resettable_counter).sim_resettable_counter::cd.clk", ty: Clock, }, ], diff --git a/crates/fayalite/visit_types.json b/crates/fayalite/visit_types.json index 04227efe..a74cef91 100644 --- a/crates/fayalite/visit_types.json +++ b/crates/fayalite/visit_types.json @@ -162,6 +162,7 @@ "$kind": "Struct", "verilog_name": "Visible", "parameters": "Visible", + "clocks_for_past": "Visible", "simulation": "Visible" } }, From 17b58e8edbe9d15be36c3481aaa953ac55327f6b Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 13 Nov 2025 20:21:07 -0800 Subject: [PATCH 10/10] add utility impls for SimValue> --- crates/fayalite/src/sim/value.rs | 72 +++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/crates/fayalite/src/sim/value.rs b/crates/fayalite/src/sim/value.rs index 89eb4e60..ff6660ca 100644 --- a/crates/fayalite/src/sim/value.rs +++ b/crates/fayalite/src/sim/value.rs @@ -23,10 +23,10 @@ use bitvec::{slice::BitSlice, vec::BitVec}; use hashbrown::hash_map::Entry; use serde::{Deserialize, Deserializer, Serialize, Serializer, de::Error as _, ser::Error as _}; use std::{ - borrow::Cow, + borrow::{Borrow, BorrowMut, Cow}, fmt::{self, Write}, hash::{BuildHasher, Hash, Hasher, RandomState}, - ops::{Deref, DerefMut}, + ops::{Deref, DerefMut, Index, IndexMut}, sync::{Arc, Mutex}, }; @@ -364,6 +364,74 @@ impl ToExpr for SimValue { } } +impl Index for SimValue> +where + [SimValue]: Index, +{ + type Output = <[SimValue] as Index>::Output; + + fn index(&self, index: I) -> &Self::Output { + (**self).borrow().index(index) + } +} + +impl IndexMut for SimValue> +where + [SimValue]: IndexMut, +{ + fn index_mut(&mut self, index: I) -> &mut Self::Output { + (**self).borrow_mut().index_mut(index) + } +} + +impl SimValue> { + pub fn iter(&self) -> std::slice::Iter<'_, SimValue> { + (**self).borrow().iter() + } + pub fn iter_mut(&mut self) -> std::slice::IterMut<'_, SimValue> { + (**self).borrow_mut().iter_mut() + } +} + +impl IntoIterator for SimValue> { + type Item = SimValue; + type IntoIter = std::vec::IntoIter>; + + fn into_iter(self) -> Self::IntoIter { + Vec::into_iter(Self::into_value(self).into()) + } +} + +impl<'a, T: Type, Len: Size> IntoIterator for &'a SimValue> { + type Item = &'a SimValue; + type IntoIter = std::slice::Iter<'a, SimValue>; + + fn into_iter(self) -> Self::IntoIter { + self.iter() + } +} + +impl<'a, T: Type, Len: Size> IntoIterator for &'a mut SimValue> { + type Item = &'a mut SimValue; + type IntoIter = std::slice::IterMut<'a, SimValue>; + + fn into_iter(self) -> Self::IntoIter { + self.iter_mut() + } +} + +impl AsRef<[SimValue]> for SimValue> { + fn as_ref(&self) -> &[SimValue] { + (**self).as_ref() + } +} + +impl AsMut<[SimValue]> for SimValue> { + fn as_mut(&mut self) -> &mut [SimValue] { + (**self).as_mut() + } +} + pub trait SimValuePartialEq: Type { #[track_caller] fn sim_value_eq(this: &SimValue, other: &SimValue) -> bool;