make annotations easier to use

crates/fayalite/tests/module.rs

@@ -1,16 +1,8 @@
 // SPDX-License-Identifier: LGPL-3.0-or-later
 // See Notices.txt for copyright information
 use fayalite::{
-    annotations::{
-        BlackBoxInlineAnnotation, BlackBoxPathAnnotation, CustomFirrtlAnnotation,
-        DocStringAnnotation, SVAttributeAnnotation,
-    },
-    assert_export_firrtl,
-    firrtl::ExportOptions,
-    intern::Intern,
-    module::transform::simplify_enums::SimplifyEnumsKind,
-    prelude::*,
-    ty::StaticType,
+    assert_export_firrtl, firrtl::ExportOptions, intern::Intern,
+    module::transform::simplify_enums::SimplifyEnumsKind, prelude::*, ty::StaticType,
 };
 use serde_json::json;
 
@@ -3057,30 +3049,30 @@ circuit check_memory_of_array_of_enum:
 
 #[hdl_module(outline_generated)]
 pub fn check_annotations() {
-    m.annotate_module(Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+    m.annotate_module(CustomFirrtlAnnotation {
         class: "the.annotation.Example".intern(),
         additional_fields: json!({
             "bar": "a nice module!",
         })
         .try_into()
         .unwrap(),
-    }));
-    m.annotate_module(Annotation::DocString(DocStringAnnotation {
+    });
+    m.annotate_module(DocStringAnnotation {
         text: r"This module is used as a test that fayalite's firrtl
 backend properly emits annotations.
 
 Testing...
 "
         .intern(),
-    }));
+    });
     #[hdl]
     let raddr: UInt<8> = m.input();
-    annotate(raddr, Annotation::DontTouch);
+    annotate(raddr, DontTouchAnnotation);
     #[hdl]
     let rdata: Array<UInt<4>, 2> = m.output();
     annotate(
         rdata,
-        Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+        CustomFirrtlAnnotation {
             class: "the.annotation.ExampleClass".intern(),
             additional_fields: json!({
                 "foo": "bar",
@@ -3088,7 +3080,7 @@ Testing...
             })
             .try_into()
             .unwrap(),
-        }),
+        },
     );
     #[hdl]
     let waddr: UInt<8> = m.input();
@@ -3098,21 +3090,21 @@ Testing...
     let wmask: Array<Bool, 2> = m.input();
     annotate(
         wmask[1],
-        Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+        CustomFirrtlAnnotation {
             class: "some.annotation.Class".intern(),
             additional_fields: json!({
                 "baz": "second mask bit",
             })
             .try_into()
             .unwrap(),
-        }),
+        },
     );
     #[hdl]
     let clk: Clock = m.input();
     #[hdl]
     let mut mem = memory();
     mem.depth(0x100);
-    mem.annotate(Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+    mem.annotate(CustomFirrtlAnnotation {
         class: "the.annotation.ExampleClass2".intern(),
         additional_fields: json!({
             "bar": "foo",
@@ -3120,18 +3112,18 @@ Testing...
         })
         .try_into()
         .unwrap(),
-    }));
+    });
     let read_port = mem.new_read_port();
     annotate(
         read_port,
-        Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+        CustomFirrtlAnnotation {
             class: "the.annotation.ExampleClass3".intern(),
             additional_fields: json!({
                 "foo": "my read port",
             })
             .try_into()
             .unwrap(),
-        }),
+        },
     );
     connect_any(read_port.addr, raddr);
     connect(read_port.en, true);
@@ -3140,14 +3132,14 @@ Testing...
     let write_port = mem.new_write_port();
     annotate(
         write_port.data[0],
-        Annotation::CustomFirrtl(CustomFirrtlAnnotation {
+        CustomFirrtlAnnotation {
             class: "some.annotation.Class".intern(),
             additional_fields: json!({
                 "baz": "first mask bit",
             })
             .try_into()
             .unwrap(),
-        }),
+        },
     );
     connect_any(write_port.addr, waddr);
     connect(write_port.en, true);
@@ -3157,35 +3149,35 @@ Testing...
     #[hdl_module(extern)]
     fn black_box1() {
         m.verilog_name("BlackBox1");
-        m.annotate_module(Annotation::BlackBoxInline(BlackBoxInlineAnnotation {
+        m.annotate_module(BlackBoxInlineAnnotation {
             path: "black_box1.v".intern(),
             text: r"(* blackbox *)
 module BlackBox1();
 endmodule
 "
             .intern(),
-        }));
+        });
     }
     #[hdl]
     let black_box1_instance = instance(black_box1());
-    annotate(black_box1_instance, Annotation::DontTouch);
+    annotate(black_box1_instance, DontTouchAnnotation);
     #[hdl_module(extern)]
     fn black_box2() {
         m.verilog_name("BlackBox2");
-        m.annotate_module(Annotation::BlackBoxPath(BlackBoxPathAnnotation {
+        m.annotate_module(BlackBoxPathAnnotation {
             path: "black_box2.v".intern(),
-        }));
+        });
     }
     #[hdl]
     let black_box2_instance = instance(black_box2());
-    annotate(black_box2_instance, Annotation::DontTouch);
+    annotate(black_box2_instance, DontTouchAnnotation);
     #[hdl]
     let a_wire: (SInt<1>, Bool) = wire();
     annotate(
         a_wire.1,
-        Annotation::SVAttribute(SVAttributeAnnotation {
+        SVAttributeAnnotation {
             text: "custom_sv_attr = \"abc\"".intern(),
-        }),
+        },
     );
     connect(a_wire, (0_hdl_i1, false));
 }