forked from libre-chip/fayalite
add firrtl comments when connecting expressions with different types
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parent
30a38bc8da
commit
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SSH key fingerprint:
SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
2 changed files with 111 additions and 0 deletions
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@ -1956,6 +1956,15 @@ impl<'a> Exporter<'a> {
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rhs,
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source_location,
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}) => {
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if Expr::ty(lhs) != Expr::ty(rhs) {
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writeln!(
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body,
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"{indent}; connect different types:\n{indent}; lhs: {:?}\n{indent}; rhs: {:?}",
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Expr::ty(lhs),
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Expr::ty(rhs),
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)
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.unwrap();
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}
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let lhs = self.expr(lhs, &definitions, false);
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let rhs = self.expr(rhs, &definitions, false);
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writeln!(
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@ -722,6 +722,9 @@ circuit check_struct_enum_match:
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A:
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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B(_match_arm_value):
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<9>
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connect o[0], add(_match_arm_value, UInt<8>(0h2)) @[module-XXXXXXXXXX.rs 8:1]
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C(_match_arm_value_1):
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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@ -738,6 +741,9 @@ circuit check_struct_enum_match:
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B(_match_arm_value_4):
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connect o[2], _match_arm_value_4 @[module-XXXXXXXXXX.rs 15:1]
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C(_match_arm_value_5):
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<1>
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connect o[2], _match_arm_value_5[1] @[module-XXXXXXXXXX.rs 16:1]
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match i2: @[module-XXXXXXXXXX.rs 17:1]
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A:
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@ -752,6 +758,9 @@ circuit check_struct_enum_match:
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B(_match_arm_value_8):
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connect o[4], UInt<8>(0h1) @[module-XXXXXXXXXX.rs 23:1]
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C(_match_arm_value_9):
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<1>
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connect o[4], _match_arm_value_9[2] @[module-XXXXXXXXXX.rs 24:1]
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",
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};
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@ -777,6 +786,9 @@ circuit check_struct_enum_match:
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A:
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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B:
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<9>
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connect o[0], add(bits(i2.body, 7, 0), UInt<8>(0h2)) @[module-XXXXXXXXXX.rs 8:1]
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C:
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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@ -801,6 +813,9 @@ circuit check_struct_enum_match:
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connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
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connect _cast_bits_to_array_expr_flattened[2], bits(bits(i2.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<1>
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connect o[2], _cast_bits_to_array_expr[1] @[module-XXXXXXXXXX.rs 16:1]
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match i2.tag: @[module-XXXXXXXXXX.rs 17:1]
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A:
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@ -823,6 +838,9 @@ circuit check_struct_enum_match:
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connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
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connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(i2.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<1>
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connect o[4], _cast_bits_to_array_expr_1[2] @[module-XXXXXXXXXX.rs 24:1]
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",
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};
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@ -843,6 +861,9 @@ circuit check_struct_enum_match:
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when eq(i2.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 6:1]
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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else when eq(i2.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 6:1]
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<9>
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connect o[0], add(bits(i2.body, 7, 0), UInt<8>(0h2)) @[module-XXXXXXXXXX.rs 8:1]
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else:
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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@ -865,6 +886,9 @@ circuit check_struct_enum_match:
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connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
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connect _cast_bits_to_array_expr_flattened[2], bits(bits(i2.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<1>
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connect o[2], _cast_bits_to_array_expr[1] @[module-XXXXXXXXXX.rs 16:1]
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when eq(i2.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 17:1]
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connect o[3], UInt<8>(0h0) @[module-XXXXXXXXXX.rs 18:1]
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@ -885,6 +909,9 @@ circuit check_struct_enum_match:
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connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
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connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(i2.body, 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<1>
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connect o[4], _cast_bits_to_array_expr_1[2] @[module-XXXXXXXXXX.rs 24:1]
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",
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};
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@ -903,6 +930,9 @@ circuit check_struct_enum_match:
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when eq(bits(i2, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 6:1]
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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else when eq(bits(i2, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 6:1]
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<9>
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connect o[0], add(bits(bits(i2, 9, 2), 7, 0), UInt<8>(0h2)) @[module-XXXXXXXXXX.rs 8:1]
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else:
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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@ -925,6 +955,9 @@ circuit check_struct_enum_match:
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connect _cast_bits_to_array_expr[1], _cast_bits_to_array_expr_flattened[1]
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connect _cast_bits_to_array_expr_flattened[2], bits(bits(bits(i2, 9, 2), 2, 0), 2, 2)
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connect _cast_bits_to_array_expr[2], _cast_bits_to_array_expr_flattened[2]
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<1>
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connect o[2], _cast_bits_to_array_expr[1] @[module-XXXXXXXXXX.rs 16:1]
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when eq(bits(i2, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 17:1]
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connect o[3], UInt<8>(0h0) @[module-XXXXXXXXXX.rs 18:1]
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@ -945,6 +978,9 @@ circuit check_struct_enum_match:
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connect _cast_bits_to_array_expr_1[1], _cast_bits_to_array_expr_flattened_1[1]
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connect _cast_bits_to_array_expr_flattened_1[2], bits(bits(bits(i2, 9, 2), 2, 0), 2, 2)
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connect _cast_bits_to_array_expr_1[2], _cast_bits_to_array_expr_flattened_1[2]
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; connect different types:
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; lhs: UInt<8>
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; rhs: UInt<1>
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connect o[4], _cast_bits_to_array_expr_1[2] @[module-XXXXXXXXXX.rs 24:1]
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",
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};
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@ -2454,10 +2490,16 @@ circuit check_memory_of_enum: %[[
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connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
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connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
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connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
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; connect different types:
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; lhs: UInt<4>
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; rhs: UInt<8>
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connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
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connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
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connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
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connect rdata, mem_r0.data @[module-XXXXXXXXXX.rs 13:1]
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; connect different types:
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; lhs: UInt<4>
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; rhs: UInt<8>
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connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
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connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
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connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
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@ -2578,10 +2620,16 @@ circuit check_memory_of_enum: %[[
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connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1]
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connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
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connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
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; connect different types:
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; lhs: UInt<4>
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; rhs: UInt<8>
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connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
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connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
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connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
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connect rdata, mem_r0.data @[module-XXXXXXXXXX.rs 13:1]
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; connect different types:
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; lhs: UInt<4>
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; rhs: UInt<8>
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connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
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connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
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connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
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@ -2702,10 +2750,16 @@ circuit check_memory_of_enum: %[[
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connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1]
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connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
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connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
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; connect different types:
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; lhs: UInt<4>
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; rhs: UInt<8>
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connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
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connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
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connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
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connect rdata, mem_r0.data @[module-XXXXXXXXXX.rs 13:1]
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; connect different types:
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; lhs: UInt<4>
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; rhs: UInt<8>
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connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
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connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
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connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
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@ -2778,10 +2832,16 @@ circuit check_memory_of_enum: %[[
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read-under-write => old
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reader => r0
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writer => w1
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; connect different types:
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; lhs: UInt<4>
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; rhs: UInt<8>
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connect `mem`.r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
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connect `mem`.r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
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connect `mem`.r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
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connect rdata, `mem`.r0.data @[module-XXXXXXXXXX.rs 13:1]
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; connect different types:
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; lhs: UInt<4>
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; rhs: UInt<8>
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connect `mem`.w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
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connect `mem`.w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
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connect `mem`.w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
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@ -3284,7 +3344,13 @@ circuit check_enum_connect_any:
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output o1: Ty3 @[module-XXXXXXXXXX.rs 5:1]
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output o2: Ty5 @[module-XXXXXXXXXX.rs 6:1]
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when swap: @[module-XXXXXXXXXX.rs 7:1]
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; connect different types:
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; lhs: Enum {A(UInt<1>), B(Enum {HdlNone, HdlSome(SInt<1>)}), C(Enum {HdlNone, HdlSome(Bundle {})})}
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; rhs: Enum {A(UInt<2>), B(Enum {HdlNone, HdlSome(SInt<2>)}), C(Enum {HdlNone, HdlSome(Bundle {})})}
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connect o1, i2 @[module-XXXXXXXXXX.rs 8:1]
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; connect different types:
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; lhs: Enum {A(UInt<2>), B(Enum {HdlNone, HdlSome(SInt<2>)}), C(Enum {HdlNone, HdlSome(Bundle {})})}
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; rhs: Enum {A(UInt<1>), B(Enum {HdlNone, HdlSome(SInt<1>)}), C(Enum {HdlNone, HdlSome(Bundle {})})}
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connect o2, i1 @[module-XXXXXXXXXX.rs 9:1]
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else:
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connect o1, i1 @[module-XXXXXXXXXX.rs 10:1]
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@ -3323,6 +3389,9 @@ circuit check_enum_connect_any:
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match i2.tag: @[module-XXXXXXXXXX.rs 8:1]
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A:
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wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
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; connect different types:
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; lhs: UInt<1>
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; rhs: UInt<2>
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connect __connect_variant_body, bits(i2.body, 1, 0) @[module-XXXXXXXXXX.rs 8:1]
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wire _bundle_literal_expr: Ty1
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connect _bundle_literal_expr.tag, {|A, B, C|}(A)
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@ -3360,6 +3429,9 @@ circuit check_enum_connect_any:
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connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1
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connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
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connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
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; connect different types:
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; lhs: SInt<1>
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; rhs: SInt<2>
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connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
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wire _bundle_literal_expr_2: Ty4
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connect _bundle_literal_expr_2.tag, {|HdlNone, HdlSome|}(HdlSome)
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@ -3412,6 +3484,9 @@ circuit check_enum_connect_any:
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match i1.tag: @[module-XXXXXXXXXX.rs 9:1]
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A:
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wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
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; connect different types:
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; lhs: UInt<2>
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; rhs: UInt<1>
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connect __connect_variant_body_4, bits(i1.body, 0, 0) @[module-XXXXXXXXXX.rs 9:1]
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wire _bundle_literal_expr_5: Ty2
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connect _bundle_literal_expr_5.tag, {|A, B, C|}(A)
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@ -3449,6 +3524,9 @@ circuit check_enum_connect_any:
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connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_enum_expr_4
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connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
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connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
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; connect different types:
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; lhs: SInt<2>
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; rhs: SInt<1>
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connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
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wire _bundle_literal_expr_7: Ty5
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connect _bundle_literal_expr_7.tag, {|HdlNone, HdlSome|}(HdlSome)
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@ -3524,6 +3602,9 @@ circuit check_enum_connect_any:
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when swap: @[module-XXXXXXXXXX.rs 7:1]
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when eq(i2.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
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wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
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; connect different types:
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; lhs: UInt<1>
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; rhs: UInt<2>
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connect __connect_variant_body, bits(i2.body, 1, 0) @[module-XXXXXXXXXX.rs 8:1]
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wire _bundle_literal_expr: Ty0
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connect _bundle_literal_expr.tag, UInt<2>(0h0)
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@ -3550,6 +3631,9 @@ circuit check_enum_connect_any:
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connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag
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connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
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connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
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; connect different types:
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; lhs: SInt<1>
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; rhs: SInt<2>
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connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
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wire _bundle_literal_expr_2: Ty2
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connect _bundle_literal_expr_2.tag, UInt<1>(0h1)
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@ -3584,6 +3668,9 @@ circuit check_enum_connect_any:
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connect o1, _bundle_literal_expr_4 @[module-XXXXXXXXXX.rs 8:1]
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when eq(i1.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
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wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
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; connect different types:
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; lhs: UInt<2>
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; rhs: UInt<1>
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connect __connect_variant_body_4, bits(i1.body, 0, 0) @[module-XXXXXXXXXX.rs 9:1]
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wire _bundle_literal_expr_5: Ty1
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connect _bundle_literal_expr_5.tag, UInt<2>(0h0)
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@ -3610,6 +3697,9 @@ circuit check_enum_connect_any:
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connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_bundle_expr_flattened_4.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
|
||||
; connect different types:
|
||||
; lhs: SInt<2>
|
||||
; rhs: SInt<1>
|
||||
connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_7: Ty3
|
||||
connect _bundle_literal_expr_7.tag, UInt<1>(0h1)
|
||||
|
|
@ -3667,6 +3757,9 @@ circuit check_enum_connect_any:
|
|||
when swap: @[module-XXXXXXXXXX.rs 7:1]
|
||||
when eq(bits(i2, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
|
||||
; connect different types:
|
||||
; lhs: UInt<1>
|
||||
; rhs: UInt<2>
|
||||
connect __connect_variant_body, bits(bits(i2, 4, 2), 1, 0) @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr: Ty0
|
||||
connect _bundle_literal_expr.tag, UInt<2>(0h0)
|
||||
|
|
@ -3691,6 +3784,9 @@ circuit check_enum_connect_any:
|
|||
connect __connect_variant_body_1, _cast_to_bits_expr_1 @[module-XXXXXXXXXX.rs 8:1]
|
||||
else:
|
||||
wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
|
||||
; connect different types:
|
||||
; lhs: SInt<1>
|
||||
; rhs: SInt<2>
|
||||
connect __connect_variant_body_2, asSInt(bits(bits(bits(bits(i2, 4, 2), 2, 0), 2, 1), 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_2: Ty1
|
||||
connect _bundle_literal_expr_2.tag, UInt<1>(0h1)
|
||||
|
|
@ -3724,6 +3820,9 @@ circuit check_enum_connect_any:
|
|||
connect o1, _cast_to_bits_expr_4 @[module-XXXXXXXXXX.rs 8:1]
|
||||
when eq(bits(i1, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
; connect different types:
|
||||
; lhs: UInt<2>
|
||||
; rhs: UInt<1>
|
||||
connect __connect_variant_body_4, bits(bits(i1, 3, 2), 0, 0) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_5: Ty2
|
||||
connect _bundle_literal_expr_5.tag, UInt<2>(0h0)
|
||||
|
|
@ -3748,6 +3847,9 @@ circuit check_enum_connect_any:
|
|||
connect __connect_variant_body_5, _cast_to_bits_expr_6 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
; connect different types:
|
||||
; lhs: SInt<2>
|
||||
; rhs: SInt<1>
|
||||
connect __connect_variant_body_6, asSInt(bits(bits(bits(bits(i1, 3, 2), 1, 0), 1, 1), 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_7: Ty3
|
||||
connect _bundle_literal_expr_7.tag, UInt<1>(0h1)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue