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change register names to end in _reg by convention

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This commit is contained in:
Jacob Lifshay 2024-10-06 18:50:09 -07:00
parent ec77559e2b
commit e05c368688
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
4 changed files with 87 additions and 69 deletions
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14
crates/fayalite/tests/module.rs
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@ -41,13 +41,13 @@ pub fn my_module(width: usize) {
#[hdl]
let m2 = instance(module2());
#[hdl]
let r: UInt<8> = reg_builder().clock_domain(clock_domain).reset(8_hdl_u8);
let r_reg: UInt<8> = reg_builder().clock_domain(clock_domain).reset(8_hdl_u8);
connect(m2.i, i);
connect(r, m2.o);
connect(r_reg, m2.o);
connect(
o,
#[hdl]
[r, r, b'\r'_hdl],
[r_reg, r_reg, b'\r'_hdl],
);
connect(o[1], 30_hdl_u8);
connect(o2, i2);
@ -109,12 +109,12 @@ circuit my_module:
connect _bundle_literal_expr.`1`, SInt<5>(-0h3)
connect o3, _bundle_literal_expr @[module-XXXXXXXXXX.rs 12:1]
inst m2 of module2 @[module-XXXXXXXXXX.rs 13:1]
regreset r: UInt<8>, clock_domain.clk, clock_domain.rst, UInt<8>(0h8) @[module-XXXXXXXXXX.rs 14:1]
regreset r_reg: UInt<8>, clock_domain.clk, clock_domain.rst, UInt<8>(0h8) @[module-XXXXXXXXXX.rs 14:1]
connect m2.i, i @[module-XXXXXXXXXX.rs 15:1]
connect r, m2.o @[module-XXXXXXXXXX.rs 16:1]
connect r_reg, m2.o @[module-XXXXXXXXXX.rs 16:1]
wire _array_literal_expr: UInt<8>[3]
connect _array_literal_expr[0], r
connect _array_literal_expr[1], r
connect _array_literal_expr[0], r_reg
connect _array_literal_expr[1], r_reg
connect _array_literal_expr[2], UInt<8>(0hD)
connect o, _array_literal_expr @[module-XXXXXXXXXX.rs 17:1]
connect o[1], UInt<8>(0h1E) @[module-XXXXXXXXXX.rs 18:1]