add sim.fork_join() and fix Simulator to handle running futures with arbitrary wakers

crates/fayalite/tests/sim.rs

@@ -2026,3 +2026,85 @@ fn test_sim_only_connects() {
         panic!();
     }
 }
+
+#[hdl_module(outline_generated, extern)]
+pub fn sim_fork_join<const N: usize>()
+where
+    ConstUsize<N>: KnownSize,
+{
+    #[hdl]
+    let clocks: Array<Clock, N> = m.input();
+    #[hdl]
+    let outputs: Array<UInt<8>, N> = m.output();
+    m.extern_module_simulation_fn((clocks, outputs), |(clocks, outputs), mut sim| async move {
+        sim.write(outputs, [0u8; N]).await;
+        loop {
+            sim.fork_join(
+                clocks
+                    .into_iter()
+                    .zip(outputs)
+                    .map(|(clock, output)| {
+                        move |mut sim: ExternModuleSimulationState| async move {
+                            sim.wait_for_clock_edge(clock).await;
+                            let v = sim
+                                .read_bool_or_int(output)
+                                .await
+                                .to_bigint()
+                                .try_into()
+                                .expect("known to be in range");
+                            sim.write(output, 1u8.wrapping_add(v)).await;
+                        }
+                    })
+                    .collect::<Vec<_>>(),
+            )
+            .await;
+        }
+    });
+}
+
+#[test]
+fn test_sim_fork_join() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    const N: usize = 3;
+    let mut sim = Simulation::new(sim_fork_join::<N>());
+    let mut writer = RcWriter::default();
+    sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
+    sim.write(sim.io().clocks, [false; N]);
+    let mut clocks_triggered = [false; N];
+    let mut expected = [0u8; N];
+    for i0 in 0..N {
+        for i1 in 0..N {
+            for i2 in 0..N {
+                for i3 in 0..N {
+                    let indexes = [i0, i1, i2, i3];
+                    for i in indexes {
+                        sim.advance_time(SimDuration::from_micros(1));
+                        sim.write(sim.io().clocks[i], true);
+                        sim.advance_time(SimDuration::from_micros(1));
+                        sim.write(sim.io().clocks[i], false);
+                        if !clocks_triggered[i] {
+                            expected[i] = expected[i].wrapping_add(1);
+                        }
+                        clocks_triggered[i] = true;
+                        if clocks_triggered == [true; N] {
+                            clocks_triggered = [false; N];
+                        }
+                        let output = sim.read(sim.io().outputs);
+                        assert_eq!(output, expected.to_sim_value(), "indexes={indexes:?} i={i}");
+                    }
+                }
+            }
+        }
+    }
+    sim.flush_traces().unwrap();
+    let vcd = String::from_utf8(writer.take()).unwrap();
+    println!("####### VCD:\n{vcd}\n#######");
+    if vcd != include_str!("sim/expected/sim_fork_join.vcd") {
+        panic!();
+    }
+    let sim_debug = format!("{sim:#?}");
+    println!("#######\n{sim_debug}\n#######");
+    if sim_debug != include_str!("sim/expected/sim_fork_join.txt") {
+        panic!();
+    }
+}

crates/fayalite/tests/sim/expected/array_rw.txt

@@ -828,7 +828,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "array_rw",
         children: [
@@ -1699,7 +1698,12 @@ Simulation {
             },
         ),
     ],
-    instant: 34 μs,
     clocks_triggered: [],
+    event_queue: EventQueue(EventQueueData {
+        instant: 34 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/conditional_assignment_last.txt

@@ -124,7 +124,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "conditional_assignment_last",
         children: [
@@ -177,7 +176,12 @@ Simulation {
             },
         ),
     ],
-    instant: 2 μs,
     clocks_triggered: [],
+    event_queue: EventQueue(EventQueueData {
+        instant: 2 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/connect_const.txt

@@ -100,7 +100,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "connect_const",
         children: [
@@ -130,7 +129,12 @@ Simulation {
     ],
     trace_memories: {},
     trace_writers: [],
-    instant: 0 s,
     clocks_triggered: [],
+    event_queue: EventQueue(EventQueueData {
+        instant: 0 s,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/connect_const_reset.txt

@@ -143,7 +143,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "connect_const_reset",
         children: [
@@ -197,7 +196,12 @@ Simulation {
             },
         ),
     ],
-    instant: 1 μs,
     clocks_triggered: [],
+    event_queue: EventQueue(EventQueueData {
+        instant: 1 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/counter_async.txt

@@ -263,7 +263,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "counter",
         children: [
@@ -329,7 +328,7 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
             },
             state: 0x1,
-            last_state: 0x1,
+            last_state: 0x0,
         },
         SimTrace {
             id: TraceScalarId(1),
@@ -355,7 +354,7 @@ Simulation {
                 ty: UInt<4>,
             },
             state: 0x3,
-            last_state: 0x3,
+            last_state: 0x2,
         },
     ],
     trace_memories: {},
@@ -368,9 +367,14 @@ Simulation {
             },
         ),
     ],
-    instant: 66 μs,
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
     ],
+    event_queue: EventQueue(EventQueueData {
+        instant: 66 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/counter_async.vcd

@@ -26,192 +26,192 @@ b11 $
 0!
 #3000000
 1!
-b100 $
 b100 #
+b100 $
 #4000000
 0!
 #5000000
 1!
-b101 $
 b101 #
+b101 $
 #6000000
 0!
 #7000000
 1!
-b110 $
 b110 #
+b110 $
 #8000000
 0!
 #9000000
 1!
-b111 $
 b111 #
+b111 $
 #10000000
 0!
 #11000000
 1!
-b1000 $
 b1000 #
+b1000 $
 #12000000
 0!
 #13000000
 1!
-b1001 $
 b1001 #
+b1001 $
 #14000000
 0!
 #15000000
 1!
-b1010 $
 b1010 #
+b1010 $
 #16000000
 0!
 #17000000
 1!
-b1011 $
 b1011 #
+b1011 $
 #18000000
 0!
 #19000000
 1!
-b1100 $
 b1100 #
+b1100 $
 #20000000
 0!
 #21000000
 1!
-b1101 $
 b1101 #
+b1101 $
 #22000000
 0!
 #23000000
 1!
-b1110 $
 b1110 #
+b1110 $
 #24000000
 0!
 #25000000
 1!
-b1111 $
 b1111 #
+b1111 $
 #26000000
 0!
 #27000000
 1!
-b0 $
 b0 #
+b0 $
 #28000000
 0!
 #29000000
 1!
-b1 $
 b1 #
+b1 $
 #30000000
 0!
 #31000000
 1!
-b10 $
 b10 #
+b10 $
 #32000000
 0!
 #33000000
 1!
-b11 $
 b11 #
+b11 $
 #34000000
 0!
 #35000000
 1!
-b100 $
 b100 #
+b100 $
 #36000000
 0!
 #37000000
 1!
-b101 $
 b101 #
+b101 $
 #38000000
 0!
 #39000000
 1!
-b110 $
 b110 #
+b110 $
 #40000000
 0!
 #41000000
 1!
-b111 $
 b111 #
+b111 $
 #42000000
 0!
 #43000000
 1!
-b1000 $
 b1000 #
+b1000 $
 #44000000
 0!
 #45000000
 1!
-b1001 $
 b1001 #
+b1001 $
 #46000000
 0!
 #47000000
 1!
-b1010 $
 b1010 #
+b1010 $
 #48000000
 0!
 #49000000
 1!
-b1011 $
 b1011 #
+b1011 $
 #50000000
 0!
 #51000000
 1!
-b1100 $
 b1100 #
+b1100 $
 #52000000
 0!
 #53000000
 1!
-b1101 $
 b1101 #
+b1101 $
 #54000000
 0!
 #55000000
 1!
-b1110 $
 b1110 #
+b1110 $
 #56000000
 0!
 #57000000
 1!
-b1111 $
 b1111 #
+b1111 $
 #58000000
 0!
 #59000000
 1!
-b0 $
 b0 #
+b0 $
 #60000000
 0!
 #61000000
 1!
-b1 $
 b1 #
+b1 $
 #62000000
 0!
 #63000000
 1!
-b10 $
 b10 #
+b10 $
 #64000000
 0!
 #65000000
 1!
-b11 $
 b11 #
+b11 $
 #66000000

crates/fayalite/tests/sim/expected/counter_sync.txt

@@ -244,7 +244,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "counter",
         children: [
@@ -310,7 +309,7 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
             },
             state: 0x1,
-            last_state: 0x1,
+            last_state: 0x0,
         },
         SimTrace {
             id: TraceScalarId(1),
@@ -336,7 +335,7 @@ Simulation {
                 ty: UInt<4>,
             },
             state: 0x3,
-            last_state: 0x3,
+            last_state: 0x2,
         },
     ],
     trace_memories: {},
@@ -349,9 +348,14 @@ Simulation {
             },
         ),
     ],
-    instant: 66 μs,
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
     ],
+    event_queue: EventQueue(EventQueueData {
+        instant: 66 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/counter_sync.vcd

@@ -16,199 +16,199 @@ b0 $
 $end
 #1000000
 1!
-b11 $
 b11 #
+b11 $
 0"
 #2000000
 0!
 #3000000
 1!
-b100 $
 b100 #
+b100 $
 #4000000
 0!
 #5000000
 1!
-b101 $
 b101 #
+b101 $
 #6000000
 0!
 #7000000
 1!
-b110 $
 b110 #
+b110 $
 #8000000
 0!
 #9000000
 1!
-b111 $
 b111 #
+b111 $
 #10000000
 0!
 #11000000
 1!
-b1000 $
 b1000 #
+b1000 $
 #12000000
 0!
 #13000000
 1!
-b1001 $
 b1001 #
+b1001 $
 #14000000
 0!
 #15000000
 1!
-b1010 $
 b1010 #
+b1010 $
 #16000000
 0!
 #17000000
 1!
-b1011 $
 b1011 #
+b1011 $
 #18000000
 0!
 #19000000
 1!
-b1100 $
 b1100 #
+b1100 $
 #20000000
 0!
 #21000000
 1!
-b1101 $
 b1101 #
+b1101 $
 #22000000
 0!
 #23000000
 1!
-b1110 $
 b1110 #
+b1110 $
 #24000000
 0!
 #25000000
 1!
-b1111 $
 b1111 #
+b1111 $
 #26000000
 0!
 #27000000
 1!
-b0 $
 b0 #
+b0 $
 #28000000
 0!
 #29000000
 1!
-b1 $
 b1 #
+b1 $
 #30000000
 0!
 #31000000
 1!
-b10 $
 b10 #
+b10 $
 #32000000
 0!
 #33000000
 1!
-b11 $
 b11 #
+b11 $
 #34000000
 0!
 #35000000
 1!
-b100 $
 b100 #
+b100 $
 #36000000
 0!
 #37000000
 1!
-b101 $
 b101 #
+b101 $
 #38000000
 0!
 #39000000
 1!
-b110 $
 b110 #
+b110 $
 #40000000
 0!
 #41000000
 1!
-b111 $
 b111 #
+b111 $
 #42000000
 0!
 #43000000
 1!
-b1000 $
 b1000 #
+b1000 $
 #44000000
 0!
 #45000000
 1!
-b1001 $
 b1001 #
+b1001 $
 #46000000
 0!
 #47000000
 1!
-b1010 $
 b1010 #
+b1010 $
 #48000000
 0!
 #49000000
 1!
-b1011 $
 b1011 #
+b1011 $
 #50000000
 0!
 #51000000
 1!
-b1100 $
 b1100 #
+b1100 $
 #52000000
 0!
 #53000000
 1!
-b1101 $
 b1101 #
+b1101 $
 #54000000
 0!
 #55000000
 1!
-b1110 $
 b1110 #
+b1110 $
 #56000000
 0!
 #57000000
 1!
-b1111 $
 b1111 #
+b1111 $
 #58000000
 0!
 #59000000
 1!
-b0 $
 b0 #
+b0 $
 #60000000
 0!
 #61000000
 1!
-b1 $
 b1 #
+b1 $
 #62000000
 0!
 #63000000
 1!
-b10 $
 b10 #
+b10 $
 #64000000
 0!
 #65000000
 1!
-b11 $
 b11 #
+b11 $
 #66000000

crates/fayalite/tests/sim/expected/duplicate_names.txt

@@ -104,7 +104,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "duplicate_names",
         children: [
@@ -160,7 +159,12 @@ Simulation {
             },
         ),
     ],
-    instant: 1 μs,
     clocks_triggered: [],
+    event_queue: EventQueue(EventQueueData {
+        instant: 1 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/enums.txt

@@ -1456,7 +1456,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "enums",
         children: [
@@ -1744,7 +1743,7 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
             },
             state: 0x1,
-            last_state: 0x1,
+            last_state: 0x0,
         },
         SimTrace {
             id: TraceScalarId(1),
@@ -1924,9 +1923,14 @@ Simulation {
             },
         ),
     ],
-    instant: 16 μs,
     clocks_triggered: [
         StatePartIndex<SmallSlots>(3),
     ],
+    event_queue: EventQueue(EventQueueData {
+        instant: 16 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/extern_module.txt

@@ -186,14 +186,8 @@ Simulation {
             running_generator: Some(
                 ...,
             ),
-            wait_targets: {
-                Instant(
-                    20.500000000000 μs,
-                ),
-            },
         },
     ],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "extern_module",
         children: [
@@ -247,7 +241,14 @@ Simulation {
             },
         ),
     ],
-    instant: 20 μs,
     clocks_triggered: [],
+    event_queue: EventQueue(EventQueueData {
+        instant: 20 μs,
+        events: {
+            Event { instant: 20.500000000000 μs, kind: ExternModule(0) }: 1,
+        },
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/extern_module.vcd

@@ -6,8 +6,9 @@ $upscope $end
 $enddefinitions $end
 $dumpvars
 0!
-1"
+0"
 $end
+1"
 #500000
 #1500000
 0"

crates/fayalite/tests/sim/expected/extern_module2.txt

@@ -234,55 +234,8 @@ Simulation {
             running_generator: Some(
                 ...,
             ),
-            wait_targets: {
-                Change {
-                    key: CompiledValue {
-                        layout: CompiledTypeLayout {
-                            ty: Clock,
-                            layout: TypeLayout {
-                                small_slots: StatePartLayout<SmallSlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    ..
-                                },
-                                big_slots: StatePartLayout<BigSlots> {
-                                    len: 1,
-                                    debug_data: [
-                                        SlotDebugData {
-                                            name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
-                                            ty: Clock,
-                                        },
-                                    ],
-                                    ..
-                                },
-                                sim_only_slots: StatePartLayout<SimOnlySlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    layout_data: [],
-                                    ..
-                                },
-                            },
-                            body: Scalar,
-                        },
-                        range: TypeIndexRange {
-                            small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                            big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
-                            sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
-                        },
-                        write: None,
-                    },
-                    value: SimValue {
-                        ty: Clock,
-                        value: OpaqueSimValue {
-                            bits: 0x1_u1,
-                            sim_only_values: [],
-                        },
-                    },
-                },
-            },
         },
     ],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "extern_module2",
         children: [
@@ -356,7 +309,113 @@ Simulation {
             },
         ),
     ],
-    instant: 60 μs,
     clocks_triggered: [],
+    event_queue: EventQueue(EventQueueData {
+        instant: 60 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {
+        SensitivitySet {
+            id: 59,
+            values: {
+                CompiledValue {
+                    layout: CompiledTypeLayout {
+                        ty: Clock,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
+                                        ty: Clock,
+                                    },
+                                ],
+                                ..
+                            },
+                            sim_only_slots: StatePartLayout<SimOnlySlots> {
+                                len: 0,
+                                debug_data: [],
+                                layout_data: [],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                    range: TypeIndexRange {
+                        small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                        big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+                        sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
+                    },
+                    write: None,
+                }: SimValue {
+                    ty: Clock,
+                    value: OpaqueSimValue {
+                        bits: 0x1_u1,
+                        sim_only_values: [],
+                    },
+                },
+            },
+            changed: Cell {
+                value: false,
+            },
+            ..
+        },
+    },
+    waiting_sensitivity_sets_by_compiled_value: {
+        CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(extern_module2: extern_module2).extern_module2::clk",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                    sim_only_slots: StatePartLayout<SimOnlySlots> {
+                        len: 0,
+                        debug_data: [],
+                        layout_data: [],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
+                sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
+            },
+            write: None,
+        }: (
+            SimValue {
+                ty: Clock,
+                value: OpaqueSimValue {
+                    bits: 0x1_u1,
+                    sim_only_values: [],
+                },
+            },
+            {
+                SensitivitySet {
+                    id: 59,
+                    ..
+                },
+            },
+        ),
+    },
     ..
 }

crates/fayalite/tests/sim/expected/extern_module2.vcd

@@ -8,8 +8,9 @@ $enddefinitions $end
 $dumpvars
 1!
 0"
-b1001000 #
+b0 #
 $end
+b1001000 #
 #1000000
 1"
 b1100101 #

crates/fayalite/tests/sim/expected/many_memories.txt

@@ -3836,7 +3836,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "many_memories",
         children: [
@@ -7759,7 +7758,6 @@ Simulation {
             },
         ),
     ],
-    instant: 38 μs,
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
         StatePartIndex<SmallSlots>(6),
@@ -7778,5 +7776,11 @@ Simulation {
         StatePartIndex<SmallSlots>(85),
         StatePartIndex<SmallSlots>(90),
     ],
+    event_queue: EventQueue(EventQueueData {
+        instant: 38 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/many_memories.vcd

@@ -1052,12 +1052,16 @@ $end
 1U#
 1e#
 1#
+1$
 1'
 1+
+1,
 1/
 13
+14
 17
 1;
+1<
 1?
 1C
 1H
@@ -1068,29 +1072,25 @@ $end
 1a
 1f
 1k
+1l
 1o
 1t
 1x
 1}
+1~
 1#"
 1("
 1,"
 11"
+12"
 15"
 1:"
 1>"
 1C"
+1D"
 1G"
 1L"
 1P"
-1$
-1,
-14
-1<
-1l
-1~
-12"
-1D"
 #4000000
 0#
 0'
@@ -1150,13 +1150,21 @@ $end
 0U#
 0e#
 1#
+0$
 1'
+0(
 1+
+0,
 1/
+00
 13
+04
 17
+08
 1;
+0<
 1?
+0@
 1C
 1H
 1M
@@ -1166,37 +1174,29 @@ $end
 1a
 1f
 1k
+0l
 1o
 1t
+0u
 1x
 1}
+0~
 1#"
 1("
+0)"
 1,"
 11"
+02"
 15"
 1:"
+0;"
 1>"
 1C"
+0D"
 1G"
 1L"
-1P"
-0$
-0(
-0,
-00
-04
-08
-0<
-0@
-0l
-0u
-0~
-0)"
-02"
-0;"
-0D"
 0M"
+1P"
 #6000000
 0#
 0'

crates/fayalite/tests/sim/expected/memories.txt

@@ -721,7 +721,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "memories",
         children: [
@@ -1616,10 +1615,15 @@ Simulation {
             },
         ),
     ],
-    instant: 22 μs,
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
         StatePartIndex<SmallSlots>(6),
     ],
+    event_queue: EventQueue(EventQueueData {
+        instant: 22 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/memories.vcd

@@ -234,13 +234,13 @@ b100000 6
 b10000 9
 b100000 I
 1#
-1(
-1/
-14
 b10000 $
 b100000 %
+1(
+1/
 b10000 0
 b100000 1
+14
 #4000000
 0#
 0(
@@ -256,11 +256,11 @@ b1000000 6
 b10000 9
 b1000000 I
 1#
+b1000000 %
 1(
 1/
-14
-b1000000 %
 b1000000 1
+14
 #6000000
 0#
 0(
@@ -278,11 +278,11 @@ b1100000 6
 b1010000 9
 b1000000 I
 1#
+b1010000 $
 1(
 1/
-14
-b1010000 $
 b1010000 0
+14
 #8000000
 0#
 0(

crates/fayalite/tests/sim/expected/memories2.txt

@@ -679,7 +679,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "memories2",
         children: [
@@ -1260,9 +1259,14 @@ Simulation {
             },
         ),
     ],
-    instant: 22 μs,
     clocks_triggered: [
         StatePartIndex<SmallSlots>(3),
     ],
+    event_queue: EventQueue(EventQueueData {
+        instant: 22 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/memories2.vcd

@@ -100,8 +100,8 @@ $end
 1)
 #1250000
 1#
-1*
 b11 $
+1*
 sHdlSome\x20(1) +
 1,
 #1500000
@@ -113,8 +113,8 @@ sHdlSome\x20(1) +
 0)
 #2250000
 1#
-1*
 b0 $
+1*
 sHdlNone\x20(0) +
 0,
 #2500000
@@ -303,8 +303,8 @@ b11 !
 b11 (
 #17250000
 1#
-1*
 b11 $
+1*
 sHdlSome\x20(1) +
 1,
 #17500000
@@ -316,8 +316,8 @@ b10 !
 b10 (
 #18250000
 1#
-1*
 b0 $
+1*
 sHdlNone\x20(0) +
 0,
 #18500000
@@ -339,8 +339,8 @@ b1 !
 b1 (
 #20250000
 1#
-1*
 b1 $
+1*
 sHdlSome\x20(1) +
 #20500000
 #20750000
@@ -353,8 +353,8 @@ b0 (
 0)
 #21250000
 1#
-1*
 b0 $
+1*
 sHdlNone\x20(0) +
 #21500000
 #21750000

crates/fayalite/tests/sim/expected/memories3.txt

@@ -1763,7 +1763,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "memories3",
         children: [
@@ -3275,10 +3274,15 @@ Simulation {
             },
         ),
     ],
-    instant: 15 μs,
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
         StatePartIndex<SmallSlots>(6),
     ],
+    event_queue: EventQueue(EventQueueData {
+        instant: 15 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/memories3.vcd

@@ -420,6 +420,10 @@ b10000 T
 1\
 #3250000
 1#
+b110100 %
+b1111000 '
+b10011010 (
+b11110000 +
 1.
 1A
 b110100 C
@@ -427,10 +431,6 @@ b1111000 E
 b10011010 F
 b11110000 I
 1L
-b110100 %
-b1111000 '
-b10011010 (
-b11110000 +
 #3500000
 #3750000
 0#
@@ -508,6 +508,14 @@ b1010100 '"
 b110010 /"
 b10000 7"
 1#
+b11111110 $
+b11011100 %
+b10111010 &
+b10011000 '
+b1110110 (
+b1010100 )
+b110010 *
+b10000 +
 1.
 1A
 b11111110 B
@@ -519,14 +527,6 @@ b1010100 G
 b110010 H
 b10000 I
 1L
-b11111110 $
-b11011100 %
-b10111010 &
-b10011000 '
-b1110110 (
-b1010100 )
-b110010 *
-b10000 +
 #6500000
 #6750000
 0#
@@ -562,6 +562,14 @@ b1000110 ("
 b10001010 0"
 b11001110 8"
 1#
+b0 $
+b0 %
+b0 &
+b0 '
+b0 (
+b0 )
+b0 *
+b0 +
 1.
 1A
 b0 B
@@ -573,14 +581,6 @@ b0 G
 b0 H
 b0 I
 1L
-b0 $
-b0 %
-b0 &
-b0 '
-b0 (
-b0 )
-b0 *
-b0 +
 #7500000
 #7750000
 0#
@@ -688,6 +688,14 @@ b1 !
 b1 ?
 #10250000
 1#
+b11111110 $
+b11011100 %
+b10111010 &
+b10011000 '
+b1110110 (
+b1010100 )
+b110010 *
+b10000 +
 1.
 1A
 b11111110 B
@@ -699,14 +707,6 @@ b1010100 G
 b110010 H
 b10000 I
 1L
-b11111110 $
-b11011100 %
-b10111010 &
-b10011000 '
-b1110110 (
-b1010100 )
-b110010 *
-b10000 +
 #10500000
 #10750000
 0#
@@ -718,6 +718,14 @@ b10 !
 b10 ?
 #11250000
 1#
+b10011 $
+b1010111 %
+b10011011 &
+b11011111 '
+b10 (
+b1000110 )
+b10001010 *
+b11001110 +
 1.
 1A
 b10011 B
@@ -729,14 +737,6 @@ b1000110 G
 b10001010 H
 b11001110 I
 1L
-b10011 $
-b1010111 %
-b10011011 &
-b11011111 '
-b10 (
-b1000110 )
-b10001010 *
-b11001110 +
 #11500000
 #11750000
 0#
@@ -748,6 +748,14 @@ b11 !
 b11 ?
 #12250000
 1#
+b1110100 $
+b1100101 %
+b1110011 &
+b1110100 '
+b1101001 (
+b1101110 )
+b1100111 *
+b100001 +
 1.
 1A
 b1110100 B
@@ -759,14 +767,6 @@ b1101110 G
 b1100111 H
 b100001 I
 1L
-b1110100 $
-b1100101 %
-b1110011 &
-b1110100 '
-b1101001 (
-b1101110 )
-b1100111 *
-b100001 +
 #12500000
 #12750000
 0#
@@ -780,6 +780,14 @@ b0 ?
 0@
 #13250000
 1#
+b1101101 $
+b1101111 %
+b1110010 &
+b1100101 '
+b100000 (
+b1110100 )
+b1110011 *
+b1110100 +
 1.
 1A
 b1101101 B
@@ -791,14 +799,6 @@ b1110100 G
 b1110011 H
 b1110100 I
 1L
-b1101101 $
-b1101111 %
-b1110010 &
-b1100101 '
-b100000 (
-b1110100 )
-b1110011 *
-b1110100 +
 #13500000
 #13750000
 0#
@@ -808,6 +808,14 @@ b1110100 +
 #14000000
 #14250000
 1#
+b0 $
+b0 %
+b0 &
+b0 '
+b0 (
+b0 )
+b0 *
+b0 +
 1.
 1A
 b0 B
@@ -819,14 +827,6 @@ b0 G
 b0 H
 b0 I
 1L
-b0 $
-b0 %
-b0 &
-b0 '
-b0 (
-b0 )
-b0 *
-b0 +
 #14500000
 #14750000
 0#

crates/fayalite/tests/sim/expected/mod1.txt

@@ -276,7 +276,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "mod1",
         children: [
@@ -558,7 +557,12 @@ Simulation {
             },
         ),
     ],
-    instant: 2 μs,
     clocks_triggered: [],
+    event_queue: EventQueue(EventQueueData {
+        instant: 2 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/ripple_counter.txt

@@ -827,52 +827,6 @@ Simulation {
             running_generator: Some(
                 ...,
             ),
-            wait_targets: {
-                Change {
-                    key: CompiledValue {
-                        layout: CompiledTypeLayout {
-                            ty: Clock,
-                            layout: TypeLayout {
-                                small_slots: StatePartLayout<SmallSlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    ..
-                                },
-                                big_slots: StatePartLayout<BigSlots> {
-                                    len: 1,
-                                    debug_data: [
-                                        SlotDebugData {
-                                            name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk",
-                                            ty: Clock,
-                                        },
-                                    ],
-                                    ..
-                                },
-                                sim_only_slots: StatePartLayout<SimOnlySlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    layout_data: [],
-                                    ..
-                                },
-                            },
-                            body: Scalar,
-                        },
-                        range: TypeIndexRange {
-                            small_slots: StatePartIndexRange<SmallSlots> { start: 3, len: 0 },
-                            big_slots: StatePartIndexRange<BigSlots> { start: 33, len: 1 },
-                            sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
-                        },
-                        write: None,
-                    },
-                    value: SimValue {
-                        ty: Clock,
-                        value: OpaqueSimValue {
-                            bits: 0x0_u1,
-                            sim_only_values: [],
-                        },
-                    },
-                },
-            },
         },
         SimulationExternModuleState {
             module_state: SimulationModuleState {
@@ -956,52 +910,6 @@ Simulation {
             running_generator: Some(
                 ...,
             ),
-            wait_targets: {
-                Change {
-                    key: CompiledValue {
-                        layout: CompiledTypeLayout {
-                            ty: Clock,
-                            layout: TypeLayout {
-                                small_slots: StatePartLayout<SmallSlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    ..
-                                },
-                                big_slots: StatePartLayout<BigSlots> {
-                                    len: 1,
-                                    debug_data: [
-                                        SlotDebugData {
-                                            name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk",
-                                            ty: Clock,
-                                        },
-                                    ],
-                                    ..
-                                },
-                                sim_only_slots: StatePartLayout<SimOnlySlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    layout_data: [],
-                                    ..
-                                },
-                            },
-                            body: Scalar,
-                        },
-                        range: TypeIndexRange {
-                            small_slots: StatePartIndexRange<SmallSlots> { start: 6, len: 0 },
-                            big_slots: StatePartIndexRange<BigSlots> { start: 44, len: 1 },
-                            sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
-                        },
-                        write: None,
-                    },
-                    value: SimValue {
-                        ty: Clock,
-                        value: OpaqueSimValue {
-                            bits: 0x0_u1,
-                            sim_only_values: [],
-                        },
-                    },
-                },
-            },
         },
         SimulationExternModuleState {
             module_state: SimulationModuleState {
@@ -1085,55 +993,8 @@ Simulation {
             running_generator: Some(
                 ...,
             ),
-            wait_targets: {
-                Change {
-                    key: CompiledValue {
-                        layout: CompiledTypeLayout {
-                            ty: Clock,
-                            layout: TypeLayout {
-                                small_slots: StatePartLayout<SmallSlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    ..
-                                },
-                                big_slots: StatePartLayout<BigSlots> {
-                                    len: 1,
-                                    debug_data: [
-                                        SlotDebugData {
-                                            name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk",
-                                            ty: Clock,
-                                        },
-                                    ],
-                                    ..
-                                },
-                                sim_only_slots: StatePartLayout<SimOnlySlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    layout_data: [],
-                                    ..
-                                },
-                            },
-                            body: Scalar,
-                        },
-                        range: TypeIndexRange {
-                            small_slots: StatePartIndexRange<SmallSlots> { start: 9, len: 0 },
-                            big_slots: StatePartIndexRange<BigSlots> { start: 55, len: 1 },
-                            sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
-                        },
-                        write: None,
-                    },
-                    value: SimValue {
-                        ty: Clock,
-                        value: OpaqueSimValue {
-                            bits: 0x0_u1,
-                            sim_only_values: [],
-                        },
-                    },
-                },
-            },
         },
     ],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "ripple_counter",
         children: [
@@ -1593,11 +1454,315 @@ Simulation {
             },
         ),
     ],
-    instant: 256 μs,
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
         StatePartIndex<SmallSlots>(4),
         StatePartIndex<SmallSlots>(7),
     ],
+    event_queue: EventQueue(EventQueueData {
+        instant: 256 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {
+        SensitivitySet {
+            id: 152,
+            values: {
+                CompiledValue {
+                    layout: CompiledTypeLayout {
+                        ty: Clock,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk",
+                                        ty: Clock,
+                                    },
+                                ],
+                                ..
+                            },
+                            sim_only_slots: StatePartLayout<SimOnlySlots> {
+                                len: 0,
+                                debug_data: [],
+                                layout_data: [],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                    range: TypeIndexRange {
+                        small_slots: StatePartIndexRange<SmallSlots> { start: 9, len: 0 },
+                        big_slots: StatePartIndexRange<BigSlots> { start: 55, len: 1 },
+                        sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
+                    },
+                    write: None,
+                }: SimValue {
+                    ty: Clock,
+                    value: OpaqueSimValue {
+                        bits: 0x0_u1,
+                        sim_only_values: [],
+                    },
+                },
+            },
+            changed: Cell {
+                value: false,
+            },
+            ..
+        },
+        SensitivitySet {
+            id: 167,
+            values: {
+                CompiledValue {
+                    layout: CompiledTypeLayout {
+                        ty: Clock,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk",
+                                        ty: Clock,
+                                    },
+                                ],
+                                ..
+                            },
+                            sim_only_slots: StatePartLayout<SimOnlySlots> {
+                                len: 0,
+                                debug_data: [],
+                                layout_data: [],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                    range: TypeIndexRange {
+                        small_slots: StatePartIndexRange<SmallSlots> { start: 6, len: 0 },
+                        big_slots: StatePartIndexRange<BigSlots> { start: 44, len: 1 },
+                        sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
+                    },
+                    write: None,
+                }: SimValue {
+                    ty: Clock,
+                    value: OpaqueSimValue {
+                        bits: 0x0_u1,
+                        sim_only_values: [],
+                    },
+                },
+            },
+            changed: Cell {
+                value: false,
+            },
+            ..
+        },
+        SensitivitySet {
+            id: 170,
+            values: {
+                CompiledValue {
+                    layout: CompiledTypeLayout {
+                        ty: Clock,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk",
+                                        ty: Clock,
+                                    },
+                                ],
+                                ..
+                            },
+                            sim_only_slots: StatePartLayout<SimOnlySlots> {
+                                len: 0,
+                                debug_data: [],
+                                layout_data: [],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                    range: TypeIndexRange {
+                        small_slots: StatePartIndexRange<SmallSlots> { start: 3, len: 0 },
+                        big_slots: StatePartIndexRange<BigSlots> { start: 33, len: 1 },
+                        sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
+                    },
+                    write: None,
+                }: SimValue {
+                    ty: Clock,
+                    value: OpaqueSimValue {
+                        bits: 0x0_u1,
+                        sim_only_values: [],
+                    },
+                },
+            },
+            changed: Cell {
+                value: false,
+            },
+            ..
+        },
+    },
+    waiting_sensitivity_sets_by_compiled_value: {
+        CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_1: sw_reg).sw_reg::clk",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                    sim_only_slots: StatePartLayout<SimOnlySlots> {
+                        len: 0,
+                        debug_data: [],
+                        layout_data: [],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 3, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 33, len: 1 },
+                sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
+            },
+            write: None,
+        }: (
+            SimValue {
+                ty: Clock,
+                value: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
+                },
+            },
+            {
+                SensitivitySet {
+                    id: 170,
+                    ..
+                },
+            },
+        ),
+        CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_3: sw_reg).sw_reg::clk",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                    sim_only_slots: StatePartLayout<SimOnlySlots> {
+                        len: 0,
+                        debug_data: [],
+                        layout_data: [],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 6, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 44, len: 1 },
+                sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
+            },
+            write: None,
+        }: (
+            SimValue {
+                ty: Clock,
+                value: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
+                },
+            },
+            {
+                SensitivitySet {
+                    id: 167,
+                    ..
+                },
+            },
+        ),
+        CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(ripple_counter.bit_reg_5: sw_reg).sw_reg::clk",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                    sim_only_slots: StatePartLayout<SimOnlySlots> {
+                        len: 0,
+                        debug_data: [],
+                        layout_data: [],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 9, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 55, len: 1 },
+                sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
+            },
+            write: None,
+        }: (
+            SimValue {
+                ty: Clock,
+                value: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
+                },
+            },
+            {
+                SensitivitySet {
+                    id: 152,
+                    ..
+                },
+            },
+        ),
+    },
     ..
 }

crates/fayalite/tests/sim/expected/shift_register.txt

@@ -339,7 +339,6 @@ Simulation {
         did_initial_settle: true,
     },
     extern_modules: [],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "shift_register",
         children: [
@@ -440,7 +439,7 @@ Simulation {
                 index: StatePartIndex<BigSlots>(0),
             },
             state: 0x1,
-            last_state: 0x1,
+            last_state: 0x0,
         },
         SimTrace {
             id: TraceScalarId(1),
@@ -509,9 +508,14 @@ Simulation {
             },
         ),
     ],
-    instant: 66 μs,
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
     ],
+    event_queue: EventQueue(EventQueueData {
+        instant: 66 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {},
+    waiting_sensitivity_sets_by_compiled_value: {},
     ..
 }

crates/fayalite/tests/sim/expected/shift_register.vcd

@@ -52,9 +52,9 @@ $end
 0!
 #11000000
 1!
+1$
 0&
 1(
-1$
 #12000000
 0!
 1#
@@ -67,10 +67,10 @@ $end
 0#
 #15000000
 1!
+0$
 0%
 1&
 0(
-0$
 #16000000
 0!
 1#
@@ -83,23 +83,23 @@ $end
 0!
 #19000000
 1!
+1$
 1&
 0'
 1(
-1$
 #20000000
 0!
 #21000000
 1!
+0$
 1'
 0(
-0$
 #22000000
 0!
 #23000000
 1!
-1(
 1$
+1(
 #24000000
 0!
 0#
@@ -120,8 +120,8 @@ $end
 0!
 #31000000
 1!
-0(
 0$
+0(
 #32000000
 0!
 #33000000

crates/fayalite/tests/sim/expected/sim_fork_join.txt

@@ -0,0 +1,523 @@
+Simulation {
+    state: State {
+        insns: Insns {
+            state_layout: StateLayout {
+                ty: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 6,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[0]",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[1]",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::clocks[2]",
+                                ty: Clock,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[0]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[1]",
+                                ty: UInt<8>,
+                            },
+                            SlotDebugData {
+                                name: "InstantiatedModule(sim_fork_join: sim_fork_join).sim_fork_join::outputs[2]",
+                                ty: UInt<8>,
+                            },
+                        ],
+                        ..
+                    },
+                    sim_only_slots: StatePartLayout<SimOnlySlots> {
+                        len: 0,
+                        debug_data: [],
+                        layout_data: [],
+                        ..
+                    },
+                },
+                memories: StatePartLayout<Memories> {
+                    len: 0,
+                    debug_data: [],
+                    layout_data: [],
+                    ..
+                },
+            },
+            insns: [
+                // at: module-XXXXXXXXXX.rs:1:1
+                0: Return,
+            ],
+            ..
+        },
+        pc: 0,
+        memory_write_log: [],
+        memories: StatePart {
+            value: [],
+        },
+        small_slots: StatePart {
+            value: [],
+        },
+        big_slots: StatePart {
+            value: [
+                0,
+                0,
+                0,
+                49,
+                50,
+                50,
+            ],
+        },
+        sim_only_slots: StatePart {
+            value: [],
+        },
+    },
+    io: Instance {
+        name: <simulator>::sim_fork_join,
+        instantiated: Module {
+            name: sim_fork_join,
+            ..
+        },
+    },
+    main_module: SimulationModuleState {
+        base_targets: [
+            Instance {
+                name: <simulator>::sim_fork_join,
+                instantiated: Module {
+                    name: sim_fork_join,
+                    ..
+                },
+            }.clocks,
+            Instance {
+                name: <simulator>::sim_fork_join,
+                instantiated: Module {
+                    name: sim_fork_join,
+                    ..
+                },
+            }.outputs,
+        ],
+        uninitialized_ios: {},
+        io_targets: {
+            Instance {
+                name: <simulator>::sim_fork_join,
+                instantiated: Module {
+                    name: sim_fork_join,
+                    ..
+                },
+            }.clocks,
+            Instance {
+                name: <simulator>::sim_fork_join,
+                instantiated: Module {
+                    name: sim_fork_join,
+                    ..
+                },
+            }.clocks[0],
+            Instance {
+                name: <simulator>::sim_fork_join,
+                instantiated: Module {
+                    name: sim_fork_join,
+                    ..
+                },
+            }.clocks[1],
+            Instance {
+                name: <simulator>::sim_fork_join,
+                instantiated: Module {
+                    name: sim_fork_join,
+                    ..
+                },
+            }.clocks[2],
+            Instance {
+                name: <simulator>::sim_fork_join,
+                instantiated: Module {
+                    name: sim_fork_join,
+                    ..
+                },
+            }.outputs,
+            Instance {
+                name: <simulator>::sim_fork_join,
+                instantiated: Module {
+                    name: sim_fork_join,
+                    ..
+                },
+            }.outputs[0],
+            Instance {
+                name: <simulator>::sim_fork_join,
+                instantiated: Module {
+                    name: sim_fork_join,
+                    ..
+                },
+            }.outputs[1],
+            Instance {
+                name: <simulator>::sim_fork_join,
+                instantiated: Module {
+                    name: sim_fork_join,
+                    ..
+                },
+            }.outputs[2],
+        },
+        did_initial_settle: true,
+    },
+    extern_modules: [
+        SimulationExternModuleState {
+            module_state: SimulationModuleState {
+                base_targets: [
+                    ModuleIO {
+                        name: sim_fork_join::clocks,
+                        is_input: true,
+                        ty: Array<Clock, 3>,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sim_fork_join::outputs,
+                        is_input: false,
+                        ty: Array<UInt<8>, 3>,
+                        ..
+                    },
+                ],
+                uninitialized_ios: {},
+                io_targets: {
+                    ModuleIO {
+                        name: sim_fork_join::clocks,
+                        is_input: true,
+                        ty: Array<Clock, 3>,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sim_fork_join::clocks,
+                        is_input: true,
+                        ty: Array<Clock, 3>,
+                        ..
+                    }[0],
+                    ModuleIO {
+                        name: sim_fork_join::clocks,
+                        is_input: true,
+                        ty: Array<Clock, 3>,
+                        ..
+                    }[1],
+                    ModuleIO {
+                        name: sim_fork_join::clocks,
+                        is_input: true,
+                        ty: Array<Clock, 3>,
+                        ..
+                    }[2],
+                    ModuleIO {
+                        name: sim_fork_join::outputs,
+                        is_input: false,
+                        ty: Array<UInt<8>, 3>,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sim_fork_join::outputs,
+                        is_input: false,
+                        ty: Array<UInt<8>, 3>,
+                        ..
+                    }[0],
+                    ModuleIO {
+                        name: sim_fork_join::outputs,
+                        is_input: false,
+                        ty: Array<UInt<8>, 3>,
+                        ..
+                    }[1],
+                    ModuleIO {
+                        name: sim_fork_join::outputs,
+                        is_input: false,
+                        ty: Array<UInt<8>, 3>,
+                        ..
+                    }[2],
+                },
+                did_initial_settle: true,
+            },
+            sim: ExternModuleSimulation {
+                generator: SimGeneratorFn {
+                    args: (
+                        ModuleIO {
+                            name: sim_fork_join::clocks,
+                            is_input: true,
+                            ty: Array<Clock, 3>,
+                            ..
+                        },
+                        ModuleIO {
+                            name: sim_fork_join::outputs,
+                            is_input: false,
+                            ty: Array<UInt<8>, 3>,
+                            ..
+                        },
+                    ),
+                    f: ...,
+                },
+                sim_io_to_generator_map: {
+                    ModuleIO {
+                        name: sim_fork_join::clocks,
+                        is_input: true,
+                        ty: Array<Clock, 3>,
+                        ..
+                    }: ModuleIO {
+                        name: sim_fork_join::clocks,
+                        is_input: true,
+                        ty: Array<Clock, 3>,
+                        ..
+                    },
+                    ModuleIO {
+                        name: sim_fork_join::outputs,
+                        is_input: false,
+                        ty: Array<UInt<8>, 3>,
+                        ..
+                    }: ModuleIO {
+                        name: sim_fork_join::outputs,
+                        is_input: false,
+                        ty: Array<UInt<8>, 3>,
+                        ..
+                    },
+                },
+                source_location: SourceLocation(
+                    module-XXXXXXXXXX.rs:4:1,
+                ),
+            },
+            running_generator: Some(
+                ...,
+            ),
+        },
+    ],
+    trace_decls: TraceModule {
+        name: "sim_fork_join",
+        children: [
+            TraceModuleIO {
+                name: "clocks",
+                child: TraceArray {
+                    name: "clocks",
+                    elements: [
+                        TraceClock {
+                            location: TraceScalarId(0),
+                            name: "[0]",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(1),
+                            name: "[1]",
+                            flow: Source,
+                        },
+                        TraceClock {
+                            location: TraceScalarId(2),
+                            name: "[2]",
+                            flow: Source,
+                        },
+                    ],
+                    ty: Array<Clock, 3>,
+                    flow: Source,
+                },
+                ty: Array<Clock, 3>,
+                flow: Source,
+            },
+            TraceModuleIO {
+                name: "outputs",
+                child: TraceArray {
+                    name: "outputs",
+                    elements: [
+                        TraceUInt {
+                            location: TraceScalarId(3),
+                            name: "[0]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(4),
+                            name: "[1]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                        TraceUInt {
+                            location: TraceScalarId(5),
+                            name: "[2]",
+                            ty: UInt<8>,
+                            flow: Sink,
+                        },
+                    ],
+                    ty: Array<UInt<8>, 3>,
+                    flow: Sink,
+                },
+                ty: Array<UInt<8>, 3>,
+                flow: Sink,
+            },
+        ],
+    },
+    traces: [
+        SimTrace {
+            id: TraceScalarId(0),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(0),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(1),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(1),
+            },
+            state: 0x0,
+            last_state: 0x0,
+        },
+        SimTrace {
+            id: TraceScalarId(2),
+            kind: BigClock {
+                index: StatePartIndex<BigSlots>(2),
+            },
+            state: 0x0,
+            last_state: 0x1,
+        },
+        SimTrace {
+            id: TraceScalarId(3),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(3),
+                ty: UInt<8>,
+            },
+            state: 0x31,
+            last_state: 0x31,
+        },
+        SimTrace {
+            id: TraceScalarId(4),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(4),
+                ty: UInt<8>,
+            },
+            state: 0x32,
+            last_state: 0x32,
+        },
+        SimTrace {
+            id: TraceScalarId(5),
+            kind: BigUInt {
+                index: StatePartIndex<BigSlots>(5),
+                ty: UInt<8>,
+            },
+            state: 0x32,
+            last_state: 0x32,
+        },
+    ],
+    trace_memories: {},
+    trace_writers: [
+        Running(
+            VcdWriter {
+                finished_init: true,
+                timescale: 1 ps,
+                ..
+            },
+        ),
+    ],
+    clocks_triggered: [],
+    event_queue: EventQueue(EventQueueData {
+        instant: 648 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {
+        SensitivitySet {
+            id: 198,
+            values: {
+                CompiledValue {
+                    layout: CompiledTypeLayout {
+                        ty: Clock,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "",
+                                        ty: Clock,
+                                    },
+                                ],
+                                ..
+                            },
+                            sim_only_slots: StatePartLayout<SimOnlySlots> {
+                                len: 0,
+                                debug_data: [],
+                                layout_data: [],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                    range: TypeIndexRange {
+                        small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                        big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+                        sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
+                    },
+                    write: None,
+                }: SimValue {
+                    ty: Clock,
+                    value: OpaqueSimValue {
+                        bits: 0x0_u1,
+                        sim_only_values: [],
+                    },
+                },
+            },
+            changed: Cell {
+                value: false,
+            },
+            ..
+        },
+    },
+    waiting_sensitivity_sets_by_compiled_value: {
+        CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                    sim_only_slots: StatePartLayout<SimOnlySlots> {
+                        len: 0,
+                        debug_data: [],
+                        layout_data: [],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
+                sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 0, len: 0 },
+            },
+            write: None,
+        }: (
+            SimValue {
+                ty: Clock,
+                value: OpaqueSimValue {
+                    bits: 0x0_u1,
+                    sim_only_values: [],
+                },
+            },
+            {
+                SensitivitySet {
+                    id: 198,
+                    ..
+                },
+            },
+        ),
+    },
+    ..
+}

crates/fayalite/tests/sim/expected/sim_only_connects.txt

@@ -717,52 +717,6 @@ Simulation {
             running_generator: Some(
                 ...,
             ),
-            wait_targets: {
-                Change {
-                    key: CompiledValue {
-                        layout: CompiledTypeLayout {
-                            ty: Clock,
-                            layout: TypeLayout {
-                                small_slots: StatePartLayout<SmallSlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    ..
-                                },
-                                big_slots: StatePartLayout<BigSlots> {
-                                    len: 1,
-                                    debug_data: [
-                                        SlotDebugData {
-                                            name: "",
-                                            ty: Clock,
-                                        },
-                                    ],
-                                    ..
-                                },
-                                sim_only_slots: StatePartLayout<SimOnlySlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    layout_data: [],
-                                    ..
-                                },
-                            },
-                            body: Scalar,
-                        },
-                        range: TypeIndexRange {
-                            small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
-                            big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
-                            sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 6, len: 0 },
-                        },
-                        write: None,
-                    },
-                    value: SimValue {
-                        ty: Clock,
-                        value: OpaqueSimValue {
-                            bits: 0x1_u1,
-                            sim_only_values: [],
-                        },
-                    },
-                },
-            },
         },
         SimulationExternModuleState {
             module_state: SimulationModuleState {
@@ -922,55 +876,8 @@ Simulation {
             running_generator: Some(
                 ...,
             ),
-            wait_targets: {
-                Change {
-                    key: CompiledValue {
-                        layout: CompiledTypeLayout {
-                            ty: Clock,
-                            layout: TypeLayout {
-                                small_slots: StatePartLayout<SmallSlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    ..
-                                },
-                                big_slots: StatePartLayout<BigSlots> {
-                                    len: 1,
-                                    debug_data: [
-                                        SlotDebugData {
-                                            name: "",
-                                            ty: Clock,
-                                        },
-                                    ],
-                                    ..
-                                },
-                                sim_only_slots: StatePartLayout<SimOnlySlots> {
-                                    len: 0,
-                                    debug_data: [],
-                                    layout_data: [],
-                                    ..
-                                },
-                            },
-                            body: Scalar,
-                        },
-                        range: TypeIndexRange {
-                            small_slots: StatePartIndexRange<SmallSlots> { start: 4, len: 0 },
-                            big_slots: StatePartIndexRange<BigSlots> { start: 12, len: 1 },
-                            sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 13, len: 0 },
-                        },
-                        write: None,
-                    },
-                    value: SimValue {
-                        ty: Clock,
-                        value: OpaqueSimValue {
-                            bits: 0x1_u1,
-                            sim_only_values: [],
-                        },
-                    },
-                },
-            },
         },
     ],
-    state_ready_to_run: false,
     trace_decls: TraceModule {
         name: "sim_only_connects",
         children: [
@@ -1628,9 +1535,214 @@ Simulation {
             },
         ),
     ],
-    instant: 16 μs,
     clocks_triggered: [
         StatePartIndex<SmallSlots>(1),
     ],
+    event_queue: EventQueue(EventQueueData {
+        instant: 16 μs,
+        events: {},
+    }),
+    waiting_sensitivity_sets_by_address: {
+        SensitivitySet {
+            id: 30,
+            values: {
+                CompiledValue {
+                    layout: CompiledTypeLayout {
+                        ty: Clock,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "",
+                                        ty: Clock,
+                                    },
+                                ],
+                                ..
+                            },
+                            sim_only_slots: StatePartLayout<SimOnlySlots> {
+                                len: 0,
+                                debug_data: [],
+                                layout_data: [],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                    range: TypeIndexRange {
+                        small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                        big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
+                        sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 6, len: 0 },
+                    },
+                    write: None,
+                }: SimValue {
+                    ty: Clock,
+                    value: OpaqueSimValue {
+                        bits: 0x1_u1,
+                        sim_only_values: [],
+                    },
+                },
+            },
+            changed: Cell {
+                value: false,
+            },
+            ..
+        },
+        SensitivitySet {
+            id: 31,
+            values: {
+                CompiledValue {
+                    layout: CompiledTypeLayout {
+                        ty: Clock,
+                        layout: TypeLayout {
+                            small_slots: StatePartLayout<SmallSlots> {
+                                len: 0,
+                                debug_data: [],
+                                ..
+                            },
+                            big_slots: StatePartLayout<BigSlots> {
+                                len: 1,
+                                debug_data: [
+                                    SlotDebugData {
+                                        name: "",
+                                        ty: Clock,
+                                    },
+                                ],
+                                ..
+                            },
+                            sim_only_slots: StatePartLayout<SimOnlySlots> {
+                                len: 0,
+                                debug_data: [],
+                                layout_data: [],
+                                ..
+                            },
+                        },
+                        body: Scalar,
+                    },
+                    range: TypeIndexRange {
+                        small_slots: StatePartIndexRange<SmallSlots> { start: 4, len: 0 },
+                        big_slots: StatePartIndexRange<BigSlots> { start: 12, len: 1 },
+                        sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 13, len: 0 },
+                    },
+                    write: None,
+                }: SimValue {
+                    ty: Clock,
+                    value: OpaqueSimValue {
+                        bits: 0x1_u1,
+                        sim_only_values: [],
+                    },
+                },
+            },
+            changed: Cell {
+                value: false,
+            },
+            ..
+        },
+    },
+    waiting_sensitivity_sets_by_compiled_value: {
+        CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                    sim_only_slots: StatePartLayout<SimOnlySlots> {
+                        len: 0,
+                        debug_data: [],
+                        layout_data: [],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 4, len: 1 },
+                sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 6, len: 0 },
+            },
+            write: None,
+        }: (
+            SimValue {
+                ty: Clock,
+                value: OpaqueSimValue {
+                    bits: 0x1_u1,
+                    sim_only_values: [],
+                },
+            },
+            {
+                SensitivitySet {
+                    id: 30,
+                    ..
+                },
+            },
+        ),
+        CompiledValue {
+            layout: CompiledTypeLayout {
+                ty: Clock,
+                layout: TypeLayout {
+                    small_slots: StatePartLayout<SmallSlots> {
+                        len: 0,
+                        debug_data: [],
+                        ..
+                    },
+                    big_slots: StatePartLayout<BigSlots> {
+                        len: 1,
+                        debug_data: [
+                            SlotDebugData {
+                                name: "",
+                                ty: Clock,
+                            },
+                        ],
+                        ..
+                    },
+                    sim_only_slots: StatePartLayout<SimOnlySlots> {
+                        len: 0,
+                        debug_data: [],
+                        layout_data: [],
+                        ..
+                    },
+                },
+                body: Scalar,
+            },
+            range: TypeIndexRange {
+                small_slots: StatePartIndexRange<SmallSlots> { start: 4, len: 0 },
+                big_slots: StatePartIndexRange<BigSlots> { start: 12, len: 1 },
+                sim_only_slots: StatePartIndexRange<SimOnlySlots> { start: 13, len: 0 },
+            },
+            write: None,
+        }: (
+            SimValue {
+                ty: Clock,
+                value: OpaqueSimValue {
+                    bits: 0x1_u1,
+                    sim_only_values: [],
+                },
+            },
+            {
+                SensitivitySet {
+                    id: 31,
+                    ..
+                },
+            },
+        ),
+    },
     ..
 }

crates/fayalite/tests/sim/expected/sim_only_connects.vcd

@@ -72,22 +72,22 @@ s{} 8
 $end
 #1000000
 1!
+s{\"extra\":\x20\"value\"} $
 1'
+s{\"extra\":\x20\"value\"} )
 1+
+s{\"extra\":\x20\"value\"} -
 10
 11
 15
-s{\"extra\":\x20\"value\"} $
-s{\"extra\":\x20\"value\"} )
-s{\"extra\":\x20\"value\"} -
-s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} *
-s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 4
 s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} %
-s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} &
+s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} *
 s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} .
 s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 3
 s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 7
-s{\"bar\":\x20\"\",\x20\"foo\":\x20\"baz\"} 8
+s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} &
+s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4
+s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8
 #2000000
 0!
 0"
@@ -107,9 +107,6 @@ s{\"extra\":\x20\"value\"} /
 00
 11
 15
-s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4
-s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} &
-s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8
 #4000000
 0!
 0'