diff --git a/crates/fayalite/src/sim.rs b/crates/fayalite/src/sim.rs index 29a8b67..c2cbea4 100644 --- a/crates/fayalite/src/sim.rs +++ b/crates/fayalite/src/sim.rs @@ -6484,12 +6484,382 @@ macro_rules! impl_to_sim_value_for_int_value { impl_to_sim_value_for_int_value!(UIntValue, UInt, UIntType); impl_to_sim_value_for_int_value!(SIntValue, SInt, SIntType); +#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] +enum MaybeNeedsSettle { + NeedsSettle(S), + NoSettleNeeded(N), +} + +impl MaybeNeedsSettle { + fn map(self, f: impl FnOnce(T) -> U) -> MaybeNeedsSettle { + match self { + MaybeNeedsSettle::NeedsSettle(v) => MaybeNeedsSettle::NeedsSettle(f(v)), + MaybeNeedsSettle::NoSettleNeeded(v) => MaybeNeedsSettle::NoSettleNeeded(f(v)), + } + } +} + +// workaround implementing FnOnce not being stable +trait MaybeNeedsSettleFn { + type Output; + + fn call(self, arg: A) -> Self::Output; +} + +impl O, A, O> MaybeNeedsSettleFn for T { + type Output = O; + + fn call(self, arg: A) -> Self::Output { + self(arg) + } +} + +impl MaybeNeedsSettle { + fn apply_no_settle(self, arg: T) -> MaybeNeedsSettle + where + N: MaybeNeedsSettleFn, + { + match self { + MaybeNeedsSettle::NeedsSettle(v) => MaybeNeedsSettle::NeedsSettle(v), + MaybeNeedsSettle::NoSettleNeeded(v) => MaybeNeedsSettle::NoSettleNeeded(v.call(arg)), + } + } +} + +struct SimulationModuleState { + base_targets: Vec, + uninitialized_ios: HashMap>, + io_targets: HashMap>, + did_initial_settle: bool, +} + +impl fmt::Debug for SimulationModuleState { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + base_targets, + uninitialized_ios, + io_targets, + did_initial_settle, + } = self; + f.debug_struct("SimulationModuleState") + .field("base_targets", base_targets) + .field("uninitialized_ios", &SortedSetDebug(uninitialized_ios)) + .field("io_targets", &SortedSetDebug(io_targets)) + .field("did_initial_settle", did_initial_settle) + .finish() + } +} + +impl SimulationModuleState { + fn new(base_targets: impl IntoIterator)>) -> Self { + let mut retval = Self { + base_targets: Vec::new(), + uninitialized_ios: HashMap::new(), + io_targets: HashMap::new(), + did_initial_settle: false, + }; + for (base_target, value) in base_targets { + retval.base_targets.push(base_target); + retval.parse_io(base_target, value); + } + retval + } + /// returns `true` if `target` or any sub-targets are uninitialized inputs + fn parse_io(&mut self, target: Target, value: CompiledValue) -> bool { + self.io_targets.insert(target, value); + match value.layout.body { + CompiledTypeLayoutBody::Scalar => match target.flow() { + Flow::Source => false, + Flow::Sink => { + self.uninitialized_ios.insert(target, vec![]); + true + } + Flow::Duplex => unreachable!(), + }, + CompiledTypeLayoutBody::Array { .. } => { + let value = value.map_ty(Array::from_canonical); + let mut sub_targets = Vec::new(); + for index in 0..value.layout.ty.len() { + let sub_target = target.join( + TargetPathElement::from(TargetPathArrayElement { index }).intern_sized(), + ); + if self.parse_io(sub_target, value.element(index)) { + sub_targets.push(sub_target); + } + } + if sub_targets.is_empty() { + false + } else { + self.uninitialized_ios.insert(target, sub_targets); + true + } + } + CompiledTypeLayoutBody::Bundle { .. } => { + let value = value.map_ty(Bundle::from_canonical); + let mut sub_targets = Vec::new(); + for BundleField { name, .. } in value.layout.ty.fields() { + let sub_target = target.join( + TargetPathElement::from(TargetPathBundleField { name }).intern_sized(), + ); + if self.parse_io(sub_target, value.field_by_name(name)) { + sub_targets.push(sub_target); + } + } + if sub_targets.is_empty() { + false + } else { + self.uninitialized_ios.insert(target, sub_targets); + true + } + } + } + } + fn mark_target_as_initialized(&mut self, mut target: Target) { + fn remove_target_and_children( + uninitialized_ios: &mut HashMap>, + target: Target, + ) { + let Some(children) = uninitialized_ios.remove(&target) else { + return; + }; + for child in children { + remove_target_and_children(uninitialized_ios, child); + } + } + remove_target_and_children(&mut self.uninitialized_ios, target); + while let Some(target_child) = target.child() { + let parent = target_child.parent(); + for child in self + .uninitialized_ios + .get(&*parent) + .map(|v| &**v) + .unwrap_or(&[]) + { + if self.uninitialized_ios.contains_key(child) { + return; + } + } + target = *parent; + self.uninitialized_ios.remove(&target); + } + } + #[track_caller] + fn get_io( + &self, + mut target: Target, + which_module: WhichModule, + ) -> CompiledValue { + if let Some(&retval) = self.io_targets.get(&target) { + return retval; + } + loop { + target = match target { + Target::Base(_) => break, + Target::Child(child) => { + match *child.path_element() { + TargetPathElement::BundleField(_) | TargetPathElement::ArrayElement(_) => {} + TargetPathElement::DynArrayElement(_) => panic!( + "simulator read/write expression must not have dynamic array indexes" + ), + } + *child.parent() + } + }; + } + match which_module { + WhichModule::Main => panic!( + "simulator read/write expression must be \ + an array element/field of `Simulation::io()`" + ), + WhichModule::Extern { .. } => panic!( + "simulator read/write expression must be \ + one of this module's inputs/outputs or an \ + array element/field of one of this module's inputs/outputs" + ), + } + } + #[track_caller] + fn read_helper( + &self, + io: Expr, + which_module: WhichModule, + ) -> MaybeNeedsSettle> { + let Some(target) = io.target() else { + match which_module { + WhichModule::Main => panic!( + "can't read from an expression that's not a field/element of `Simulation::io()`" + ), + WhichModule::Extern { .. } => panic!( + "can't read from an expression that's not based on one of this module's inputs/outputs" + ), + } + }; + let compiled_value = self.get_io(*target, which_module); + match target.flow() { + Flow::Source => { + if !self.uninitialized_ios.is_empty() { + match which_module { + WhichModule::Main => { + panic!("can't read from an output before initializing all inputs"); + } + WhichModule::Extern { .. } => { + panic!("can't read from an input before initializing all outputs"); + } + } + } + MaybeNeedsSettle::NeedsSettle(compiled_value) + } + Flow::Sink => { + if self.uninitialized_ios.contains_key(&*target) { + match which_module { + WhichModule::Main => panic!("can't read from an uninitialized input"), + WhichModule::Extern { .. } => { + panic!("can't read from an uninitialized output"); + } + } + } + MaybeNeedsSettle::NoSettleNeeded(compiled_value) + } + Flow::Duplex => unreachable!(), + } + } + #[track_caller] + fn write_helper( + &mut self, + io: Expr, + which_module: WhichModule, + ) -> CompiledValue { + let Some(target) = io.target() else { + match which_module { + WhichModule::Main => panic!( + "can't write to an expression that's not a field/element of `Simulation::io()`" + ), + WhichModule::Extern { .. } => panic!( + "can't write to an expression that's not based on one of this module's outputs" + ), + } + }; + let compiled_value = self.get_io(*target, which_module); + match target.flow() { + Flow::Source => match which_module { + WhichModule::Main => panic!("can't write to an output"), + WhichModule::Extern { .. } => panic!("can't write to an input"), + }, + Flow::Sink => {} + Flow::Duplex => unreachable!(), + } + if !self.did_initial_settle { + self.mark_target_as_initialized(*target); + } + compiled_value + } +} + +struct SimulationExternModuleState { + module_state: SimulationModuleState, + sim: ExternModuleSimulation, + running_generator: Option + 'static>>, +} + +impl fmt::Debug for SimulationExternModuleState { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + module_state, + sim, + running_generator, + } = self; + f.debug_struct("SimulationExternModuleState") + .field("module_state", module_state) + .field("sim", sim) + .field( + "running_generator", + &running_generator.as_ref().map(|_| DebugAsDisplay("...")), + ) + .finish() + } +} + +#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] +enum WhichModule { + Main, + Extern { index: usize }, +} + +struct ReadBitFn { + compiled_value: CompiledValue, +} + +impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadBitFn { + type Output = bool; + + fn call(self, state: &mut interpreter::State) -> Self::Output { + match self.compiled_value.range.len() { + TypeLen::A_SMALL_SLOT => { + state.small_slots[self.compiled_value.range.small_slots.start] != 0 + } + TypeLen::A_BIG_SLOT => !state.big_slots[self.compiled_value.range.big_slots.start] + .clone() + .is_zero(), + _ => unreachable!(), + } + } +} + +struct ReadBoolOrIntFn { + compiled_value: CompiledValue, + io: Expr, +} + +impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadBoolOrIntFn { + type Output = I::Value; + + fn call(self, state: &mut interpreter::State) -> Self::Output { + let Self { compiled_value, io } = self; + match compiled_value.range.len() { + TypeLen::A_SMALL_SLOT => Expr::ty(io) + .value_from_int_wrapping(state.small_slots[compiled_value.range.small_slots.start]), + TypeLen::A_BIG_SLOT => Expr::ty(io).value_from_int_wrapping( + state.big_slots[compiled_value.range.big_slots.start].clone(), + ), + _ => unreachable!(), + } + } +} + +struct ReadFn { + compiled_value: CompiledValue, + io: Expr, +} + +impl MaybeNeedsSettleFn<&'_ mut interpreter::State> for ReadFn { + type Output = SimValue; + + fn call(self, state: &mut interpreter::State) -> Self::Output { + let Self { compiled_value, io } = self; + let mut bits = BitVec::repeat(false, compiled_value.layout.ty.bit_width()); + SimulationImpl::read_write_sim_value_helper( + state, + compiled_value, + &mut bits, + |_signed, bits, value| ::copy_bits_from_bigint_wrapping(value, bits), + |_signed, bits, value| { + let bytes = value.to_le_bytes(); + let bitslice = BitSlice::::from_slice(&bytes); + bits.clone_from_bitslice(&bitslice[..bits.len()]); + }, + ); + SimValue { + ty: Expr::ty(io), + bits, + } + } +} + struct SimulationImpl { state: interpreter::State, io: Expr, - uninitialized_inputs: HashMap>, - io_targets: HashMap>, - made_initial_step: bool, + main_module: SimulationModuleState, + extern_modules: Vec, needs_settle: bool, trace_decls: TraceModule, traces: SimTraces]>>, @@ -6511,9 +6881,8 @@ impl SimulationImpl { let Self { state, io: self_io, - uninitialized_inputs, - io_targets, - made_initial_step, + main_module, + extern_modules, needs_settle, trace_decls, traces, @@ -6526,12 +6895,8 @@ impl SimulationImpl { f.debug_struct("Simulation") .field("state", state) .field("io", io.unwrap_or(self_io)) - .field( - "uninitialized_inputs", - &SortedSetDebug(uninitialized_inputs), - ) - .field("io_targets", &SortedMapDebug(io_targets)) - .field("made_initial_step", made_initial_step) + .field("main_module", main_module) + .field("extern_modules", extern_modules) .field("needs_settle", needs_settle) .field("trace_decls", trace_decls) .field("traces", traces) @@ -6541,63 +6906,30 @@ impl SimulationImpl { .field("clocks_triggered", clocks_triggered) .finish_non_exhaustive() } - /// returns `true` if `target` or any sub-targets are uninitialized inputs - fn parse_io(&mut self, target: Target, value: CompiledValue) -> bool { - self.io_targets.insert(target, value); - match value.layout.body { - CompiledTypeLayoutBody::Scalar => match target.flow() { - Flow::Source => false, - Flow::Sink => { - self.uninitialized_inputs.insert(target, vec![]); - true - } - Flow::Duplex => unreachable!(), - }, - CompiledTypeLayoutBody::Array { .. } => { - let value = value.map_ty(Array::from_canonical); - let mut sub_targets = Vec::new(); - for index in 0..value.layout.ty.len() { - let sub_target = target.join( - TargetPathElement::from(TargetPathArrayElement { index }).intern_sized(), - ); - if self.parse_io(sub_target, value.element(index)) { - sub_targets.push(sub_target); - } - } - if sub_targets.is_empty() { - false - } else { - self.uninitialized_inputs.insert(target, sub_targets); - true - } - } - CompiledTypeLayoutBody::Bundle { .. } => { - let value = value.map_ty(Bundle::from_canonical); - let mut sub_targets = Vec::new(); - for BundleField { name, .. } in value.layout.ty.fields() { - let sub_target = target.join( - TargetPathElement::from(TargetPathBundleField { name }).intern_sized(), - ); - if self.parse_io(sub_target, value.field_by_name(name)) { - sub_targets.push(sub_target); - } - } - if sub_targets.is_empty() { - false - } else { - self.uninitialized_inputs.insert(target, sub_targets); - true - } - } - } - } fn new(compiled: Compiled) -> Self { - let mut retval = Self { + let io_target = Target::from(compiled.io); + Self { state: State::new(compiled.insns), io: compiled.io.to_expr(), - uninitialized_inputs: HashMap::new(), - io_targets: HashMap::new(), - made_initial_step: false, + main_module: SimulationModuleState::new( + compiled + .io + .ty() + .fields() + .into_iter() + .zip(compiled.base_module.module_io) + .map(|(BundleField { name, .. }, value)| { + ( + io_target.join( + TargetPathElement::from(TargetPathBundleField { name }) + .intern_sized(), + ), + value, + ) + }), + ), + // TODO: add extern_modules + extern_modules: vec![], needs_settle: true, trace_decls: compiled.base_module.trace_decls, traces: SimTraces(Box::from_iter(compiled.traces.0.iter().map( @@ -6616,22 +6948,7 @@ impl SimulationImpl { instant: SimInstant::START, clocks_triggered: compiled.clocks_triggered, breakpoints: None, - }; - let io_target = Target::from(compiled.io); - for (BundleField { name, .. }, value) in compiled - .io - .ty() - .fields() - .into_iter() - .zip(compiled.base_module.module_io) - { - retval.parse_io( - io_target - .join(TargetPathElement::from(TargetPathBundleField { name }).intern_sized()), - value, - ); } - retval } fn write_traces( &mut self, @@ -6786,7 +7103,7 @@ impl SimulationImpl { #[track_caller] fn settle(&mut self) { assert!( - self.uninitialized_inputs.is_empty(), + self.main_module.uninitialized_ios.is_empty(), "didn't initialize all inputs", ); for _ in 0..100000 { @@ -6818,14 +7135,14 @@ impl SimulationImpl { } else { let RunResult::Return(()) = self.state.run(()); } - if self.made_initial_step { + if self.main_module.did_initial_settle { self.read_traces::(); } else { self.read_traces::(); } self.state.memory_write_log.sort_unstable(); self.state.memory_write_log.dedup(); - self.made_initial_step = true; + self.main_module.did_initial_settle = true; self.needs_settle = self .clocks_triggered .iter() @@ -6852,110 +7169,35 @@ impl SimulationImpl { } panic!("settle(): took too many steps"); } - #[track_caller] - fn get_io(&self, target: Target) -> CompiledValue { - if let Some(&retval) = self.io_targets.get(&target) { - return retval; + fn get_module(&self, which_module: WhichModule) -> &SimulationModuleState { + match which_module { + WhichModule::Main => &self.main_module, + WhichModule::Extern { index } => &self.extern_modules[index].module_state, } - if Some(&target) == self.io.target().as_deref() - || Some(target.base()) != self.io.target().map(|v| v.base()) - { - panic!("simulator read/write expression must be an array element/field of `Simulation::io()`"); - }; - panic!("simulator read/write expression must not have dynamic array indexes"); } - fn mark_target_as_initialized(&mut self, mut target: Target) { - fn remove_target_and_children( - uninitialized_inputs: &mut HashMap>, - target: Target, - ) { - let Some(children) = uninitialized_inputs.remove(&target) else { - return; - }; - for child in children { - remove_target_and_children(uninitialized_inputs, child); - } - } - remove_target_and_children(&mut self.uninitialized_inputs, target); - while let Some(target_child) = target.child() { - let parent = target_child.parent(); - for child in self - .uninitialized_inputs - .get(&*parent) - .map(|v| &**v) - .unwrap_or(&[]) - { - if self.uninitialized_inputs.contains_key(child) { - return; - } - } - target = *parent; - self.uninitialized_inputs.remove(&target); + fn get_module_mut(&mut self, which_module: WhichModule) -> &mut SimulationModuleState { + match which_module { + WhichModule::Main => &mut self.main_module, + WhichModule::Extern { index } => &mut self.extern_modules[index].module_state, } } #[track_caller] - fn read_helper(&mut self, io: Expr) -> CompiledValue { - let Some(target) = io.target() else { - panic!("can't read from expression that's not a field/element of `Simulation::io()`"); - }; - let compiled_value = self.get_io(*target); - if self.made_initial_step { - self.settle(); - } else { - match target.flow() { - Flow::Source => { - if !self.uninitialized_inputs.is_empty() { - panic!( - "can't read from an output before the simulation has made any steps" - ); - } - self.settle(); - } - Flow::Sink => { - if self.uninitialized_inputs.contains_key(&*target) { - panic!("can't read from an uninitialized input"); - } - } - Flow::Duplex => unreachable!(), - } - } - compiled_value + fn read_bit( + &mut self, + io: Expr, + which_module: WhichModule, + ) -> MaybeNeedsSettle { + self.get_module(which_module) + .read_helper(Expr::canonical(io), which_module) + .map(|compiled_value| ReadBitFn { compiled_value }) + .apply_no_settle(&mut self.state) } #[track_caller] - fn write_helper(&mut self, io: Expr) -> CompiledValue { - let Some(target) = io.target() else { - panic!("can't write to an expression that's not a field/element of `Simulation::io()`"); - }; - let compiled_value = self.get_io(*target); - match target.flow() { - Flow::Source => { - panic!("can't write to an output"); - } - Flow::Sink => {} - Flow::Duplex => unreachable!(), - } - if !self.made_initial_step { - self.mark_target_as_initialized(*target); - } + fn write_bit(&mut self, io: Expr, value: bool, which_module: WhichModule) { + let compiled_value = self + .get_module_mut(which_module) + .write_helper(io, which_module); self.needs_settle = true; - compiled_value - } - #[track_caller] - fn read_bit(&mut self, io: Expr) -> bool { - let compiled_value = self.read_helper(Expr::canonical(io)); - match compiled_value.range.len() { - TypeLen::A_SMALL_SLOT => { - self.state.small_slots[compiled_value.range.small_slots.start] != 0 - } - TypeLen::A_BIG_SLOT => !self.state.big_slots[compiled_value.range.big_slots.start] - .clone() - .is_zero(), - _ => unreachable!(), - } - } - #[track_caller] - fn write_bit(&mut self, io: Expr, value: bool) { - let compiled_value = self.write_helper(io); match compiled_value.range.len() { TypeLen::A_SMALL_SLOT => { self.state.small_slots[compiled_value.range.small_slots.start] = value as _; @@ -6967,21 +7209,27 @@ impl SimulationImpl { } } #[track_caller] - fn read_bool_or_int(&mut self, io: Expr) -> I::Value { - let compiled_value = self.read_helper(Expr::canonical(io)); - match compiled_value.range.len() { - TypeLen::A_SMALL_SLOT => Expr::ty(io).value_from_int_wrapping( - self.state.small_slots[compiled_value.range.small_slots.start], - ), - TypeLen::A_BIG_SLOT => Expr::ty(io).value_from_int_wrapping( - self.state.big_slots[compiled_value.range.big_slots.start].clone(), - ), - _ => unreachable!(), - } + fn read_bool_or_int( + &mut self, + io: Expr, + which_module: WhichModule, + ) -> MaybeNeedsSettle, I::Value> { + self.get_module(which_module) + .read_helper(Expr::canonical(io), which_module) + .map(|compiled_value| ReadBoolOrIntFn { compiled_value, io }) + .apply_no_settle(&mut self.state) } #[track_caller] - fn write_bool_or_int(&mut self, io: Expr, value: I::Value) { - let compiled_value = self.write_helper(Expr::canonical(io)); + fn write_bool_or_int( + &mut self, + io: Expr, + value: I::Value, + which_module: WhichModule, + ) { + let compiled_value = self + .get_module_mut(which_module) + .write_helper(Expr::canonical(io), which_module); + self.needs_settle = true; let value: BigInt = value.into(); match compiled_value.range.len() { TypeLen::A_SMALL_SLOT => { @@ -6999,7 +7247,7 @@ impl SimulationImpl { } #[track_caller] fn read_write_sim_value_helper( - &mut self, + state: &mut interpreter::State, compiled_value: CompiledValue, bits: &mut BitSlice, read_write_big_scalar: impl Fn(bool, &mut BitSlice, &mut BigInt) + Copy, @@ -7024,12 +7272,12 @@ impl SimulationImpl { TypeLen::A_SMALL_SLOT => read_write_small_scalar( signed, bits, - &mut self.state.small_slots[compiled_value.range.small_slots.start], + &mut state.small_slots[compiled_value.range.small_slots.start], ), TypeLen::A_BIG_SLOT => read_write_big_scalar( signed, bits, - &mut self.state.big_slots[compiled_value.range.big_slots.start], + &mut state.big_slots[compiled_value.range.big_slots.start], ), _ => unreachable!(), } @@ -7038,7 +7286,8 @@ impl SimulationImpl { let ty = ::from_canonical(compiled_value.layout.ty); let element_bit_width = ty.element().bit_width(); for element_index in 0..ty.len() { - self.read_write_sim_value_helper( + Self::read_write_sim_value_helper( + state, CompiledValue { layout: *element, range: compiled_value @@ -7062,7 +7311,8 @@ impl SimulationImpl { }, ) in ty.fields().iter().zip(ty.field_offsets()).zip(fields) { - self.read_write_sim_value_helper( + Self::read_write_sim_value_helper( + state, CompiledValue { layout: field_layout, range: compiled_value.range.slice(TypeIndexRange::new( @@ -7080,29 +7330,30 @@ impl SimulationImpl { } } #[track_caller] - fn read(&mut self, io: Expr) -> SimValue { - let compiled_value = self.read_helper(io); - let mut bits = BitVec::repeat(false, compiled_value.layout.ty.bit_width()); - self.read_write_sim_value_helper( - compiled_value, - &mut bits, - |_signed, bits, value| ::copy_bits_from_bigint_wrapping(value, bits), - |_signed, bits, value| { - let bytes = value.to_le_bytes(); - let bitslice = BitSlice::::from_slice(&bytes); - bits.clone_from_bitslice(&bitslice[..bits.len()]); - }, - ); - SimValue { - ty: Expr::ty(io), - bits, - } + fn read( + &mut self, + io: Expr, + which_module: WhichModule, + ) -> MaybeNeedsSettle> { + self.get_module(which_module) + .read_helper(io, which_module) + .map(|compiled_value| ReadFn { compiled_value, io }) + .apply_no_settle(&mut self.state) } #[track_caller] - fn write(&mut self, io: Expr, value: SimValue) { - let compiled_value = self.write_helper(io); + fn write( + &mut self, + io: Expr, + value: SimValue, + which_module: WhichModule, + ) { + let compiled_value = self + .get_module_mut(which_module) + .write_helper(io, which_module); + self.needs_settle = true; assert_eq!(Expr::ty(io), value.ty()); - self.read_write_sim_value_helper( + Self::read_write_sim_value_helper( + &mut self.state, compiled_value, &mut value.into_bits(), |signed, bits, value| { @@ -7122,6 +7373,19 @@ impl SimulationImpl { }, ); } + #[track_caller] + fn settle_if_needed(&mut self, v: MaybeNeedsSettle) -> O + where + for<'a> F: MaybeNeedsSettleFn<&'a mut interpreter::State, Output = O>, + { + match v { + MaybeNeedsSettle::NeedsSettle(v) => { + self.settle(); + v.call(&mut self.state) + } + MaybeNeedsSettle::NoSettleNeeded(v) => v, + } + } fn close_all_trace_writers(&mut self) -> std::io::Result<()> { let trace_writers = mem::take(&mut self.trace_writers); let mut retval = Ok(()); @@ -7192,13 +7456,13 @@ impl SimulationImpl { retval } fn close(mut self) -> std::io::Result<()> { - if self.made_initial_step { + if self.main_module.did_initial_settle { self.settle(); } self.close_all_trace_writers() } fn flush_traces(&mut self) -> std::io::Result<()> { - if self.made_initial_step { + if self.main_module.did_initial_settle { self.settle(); } self.for_each_trace_writer_getting_error( @@ -7335,7 +7599,8 @@ impl Simulation { } #[track_caller] pub fn read_bool_or_int(&mut self, io: Expr) -> I::Value { - self.sim_impl.read_bool_or_int(io) + let retval = self.sim_impl.read_bool_or_int(io, WhichModule::Main); + self.sim_impl.settle_if_needed(retval) } #[track_caller] pub fn write_bool_or_int( @@ -7348,42 +7613,59 @@ impl Simulation { let value = value .to_literal_bits() .expect("the value that is being written to an input must be a literal"); - self.sim_impl - .write_bool_or_int(io, I::bits_to_value(Cow::Borrowed(&value))); + self.sim_impl.write_bool_or_int( + io, + I::bits_to_value(Cow::Borrowed(&value)), + WhichModule::Main, + ); } #[track_caller] pub fn write_clock(&mut self, io: Expr, value: bool) { - self.sim_impl.write_bit(Expr::canonical(io), value); + self.sim_impl + .write_bit(Expr::canonical(io), value, WhichModule::Main); } #[track_caller] pub fn read_clock(&mut self, io: Expr) -> bool { - self.sim_impl.read_bit(Expr::canonical(io)) + let retval = self + .sim_impl + .read_bit(Expr::canonical(io), WhichModule::Main); + self.sim_impl.settle_if_needed(retval) } #[track_caller] pub fn write_bool(&mut self, io: Expr, value: bool) { - self.sim_impl.write_bit(Expr::canonical(io), value); + self.sim_impl + .write_bit(Expr::canonical(io), value, WhichModule::Main); } #[track_caller] pub fn read_bool(&mut self, io: Expr) -> bool { - self.sim_impl.read_bit(Expr::canonical(io)) + let retval = self + .sim_impl + .read_bit(Expr::canonical(io), WhichModule::Main); + self.sim_impl.settle_if_needed(retval) } #[track_caller] pub fn write_reset(&mut self, io: Expr, value: bool) { - self.sim_impl.write_bit(Expr::canonical(io), value); + self.sim_impl + .write_bit(Expr::canonical(io), value, WhichModule::Main); } #[track_caller] pub fn read_reset(&mut self, io: Expr) -> bool { - self.sim_impl.read_bit(Expr::canonical(io)) + let retval = self + .sim_impl + .read_bit(Expr::canonical(io), WhichModule::Main); + self.sim_impl.settle_if_needed(retval) } #[track_caller] pub fn read(&mut self, io: Expr) -> SimValue { - SimValue::from_canonical(self.sim_impl.read(Expr::canonical(io))) + let retval = self.sim_impl.read(Expr::canonical(io), WhichModule::Main); + SimValue::from_canonical(self.sim_impl.settle_if_needed(retval)) } #[track_caller] pub fn write>(&mut self, io: Expr, value: V) { self.sim_impl.write( Expr::canonical(io), value.into_sim_value(Expr::ty(io)).into_canonical(), + WhichModule::Main, ); } #[doc(hidden)] @@ -7462,39 +7744,60 @@ impl InternedCompare for dyn DynExternModuleSimGenerator { #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)] pub struct ExternModuleSimulation { generator: Interned, + source_location: SourceLocation, _phantom: PhantomData, } impl ExternModuleSimulation { - pub fn new(generator: G) -> Self { + pub fn new_with_loc( + source_location: SourceLocation, + generator: G, + ) -> Self { Self { generator: Interned::cast_unchecked( generator.intern(), |v| -> &dyn DynExternModuleSimGenerator { v }, ), + source_location, _phantom: PhantomData, } } + #[track_caller] + pub fn new(generator: G) -> Self { + Self::new_with_loc(SourceLocation::caller(), generator) + } pub fn canonical(self) -> ExternModuleSimulation { + let Self { + generator, + source_location, + _phantom: _, + } = self; ExternModuleSimulation { - generator: self.generator, + generator, + source_location, _phantom: PhantomData, } } pub fn from_canonical(v: ExternModuleSimulation) -> Self { + let ExternModuleSimulation { + generator, + source_location, + _phantom: _, + } = v; Self { - generator: v.generator, + generator, + source_location, _phantom: PhantomData, } } } impl ExternModuleSimulation { - fn run<'a>( - &'a self, + fn run( + &self, sim: ExternModuleSimulationState, - ) -> Box + 'a> { - self.generator.dyn_run(sim) + ) -> Box + 'static> { + Interned::into_inner(self.generator).dyn_run(sim) } #[track_caller] pub fn check_io_ty(self, io_ty: Bundle) { diff --git a/crates/fayalite/tests/sim/expected/array_rw.txt b/crates/fayalite/tests/sim/expected/array_rw.txt index f016e72..57d985e 100644 --- a/crates/fayalite/tests/sim/expected/array_rw.txt +++ b/crates/fayalite/tests/sim/expected/array_rw.txt @@ -488,1500 +488,337 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in: CompiledValue { - layout: CompiledTypeLayout { - ty: Array, 16>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 16, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[3]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[4]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[5]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[6]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[7]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[8]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[9]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[10]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[11]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[12]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[13]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[14]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_in[15]", - ty: UInt<8>, - }, - ], - .. - }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. }, - body: Array { - element: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, + }.array_in, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 16 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[0]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[10]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 10, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[11]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 11, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[12]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 12, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[13]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 13, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[14]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 14, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[15]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 15, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[1]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[2]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[3]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[4]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[5]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 5, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[6]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 6, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[7]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 7, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[8]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 8, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_in[9]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 9, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out: CompiledValue { - layout: CompiledTypeLayout { - ty: Array, 16>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 16, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[3]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[4]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[5]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[6]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[7]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[8]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[9]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[10]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[11]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[12]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[13]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[14]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::array_out[15]", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Array { - element: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 16, len: 16 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[0]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 16, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[10]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 26, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[11]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 27, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[12]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 28, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[13]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 29, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[14]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 30, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[15]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 31, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[1]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 17, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[2]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 18, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[3]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 19, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[4]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 20, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[5]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 21, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[6]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 22, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[7]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 23, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[8]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 24, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.array_out[9]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 25, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.read_data: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::read_data", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 33, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.read_index: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::read_index", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 32, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.write_data: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::write_data", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 35, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.write_en: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::write_en", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 36, len: 1 }, - }, - write: None, - }, - Instance { - name: ::array_rw, - instantiated: Module { - name: array_rw, - .. - }, - }.write_index: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(array_rw: array_rw).array_rw::write_index", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 34, len: 1 }, - }, - write: None, + }.array_out, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.read_index, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.read_data, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.write_index, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.write_data, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.write_en, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[0], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[10], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[11], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[12], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[13], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[14], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[15], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[1], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[2], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[3], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[4], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[5], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[6], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[7], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[8], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_in[9], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[0], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[10], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[11], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[12], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[13], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[14], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[15], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[1], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[2], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[3], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[4], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[5], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[6], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[7], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[8], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.array_out[9], + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.read_data, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.read_index, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.write_data, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.write_en, + Instance { + name: ::array_rw, + instantiated: Module { + name: array_rw, + .. + }, + }.write_index, }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "array_rw", diff --git a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt index 186e5a5..45f10a5 100644 --- a/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt +++ b/crates/fayalite/tests/sim/expected/conditional_assignment_last.txt @@ -92,44 +92,29 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::conditional_assignment_last, - instantiated: Module { - name: conditional_assignment_last, - .. - }, - }.i: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(conditional_assignment_last: conditional_assignment_last).conditional_assignment_last::i", - ty: Bool, - }, - ], - .. - }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::conditional_assignment_last, + instantiated: Module { + name: conditional_assignment_last, + .. }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, + }.i, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::conditional_assignment_last, + instantiated: Module { + name: conditional_assignment_last, + .. + }, + }.i, }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "conditional_assignment_last", diff --git a/crates/fayalite/tests/sim/expected/connect_const.txt b/crates/fayalite/tests/sim/expected/connect_const.txt index e44c50d..c8802f8 100644 --- a/crates/fayalite/tests/sim/expected/connect_const.txt +++ b/crates/fayalite/tests/sim/expected/connect_const.txt @@ -68,44 +68,29 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::connect_const, - instantiated: Module { - name: connect_const, - .. - }, - }.o: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(connect_const: connect_const).connect_const::o", - ty: UInt<8>, - }, - ], - .. - }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::connect_const, + instantiated: Module { + name: connect_const, + .. }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, + }.o, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::connect_const, + instantiated: Module { + name: connect_const, + .. + }, + }.o, }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "connect_const", diff --git a/crates/fayalite/tests/sim/expected/connect_const_reset.txt b/crates/fayalite/tests/sim/expected/connect_const_reset.txt index d1ab998..8631d44 100644 --- a/crates/fayalite/tests/sim/expected/connect_const_reset.txt +++ b/crates/fayalite/tests/sim/expected/connect_const_reset.txt @@ -97,78 +97,43 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::connect_const_reset, - instantiated: Module { - name: connect_const_reset, - .. - }, - }.bit_out: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::bit_out", - ty: Bool, - }, - ], - .. - }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::connect_const_reset, + instantiated: Module { + name: connect_const_reset, + .. }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::connect_const_reset, - instantiated: Module { - name: connect_const_reset, - .. - }, - }.reset_out: CompiledValue { - layout: CompiledTypeLayout { - ty: AsyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(connect_const_reset: connect_const_reset).connect_const_reset::reset_out", - ty: AsyncReset, - }, - ], - .. - }, + }.reset_out, + Instance { + name: ::connect_const_reset, + instantiated: Module { + name: connect_const_reset, + .. }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, + }.bit_out, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::connect_const_reset, + instantiated: Module { + name: connect_const_reset, + .. + }, + }.bit_out, + Instance { + name: ::connect_const_reset, + instantiated: Module { + name: connect_const_reset, + .. + }, + }.reset_out, }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "connect_const_reset", diff --git a/crates/fayalite/tests/sim/expected/counter_async.txt b/crates/fayalite/tests/sim/expected/counter_async.txt index 2e005a0..1e9012a 100644 --- a/crates/fayalite/tests/sim/expected/counter_async.txt +++ b/crates/fayalite/tests/sim/expected/counter_async.txt @@ -203,212 +203,57 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: AsyncReset, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.rst", - ty: AsyncReset, - }, - ], - .. - }, + }.cd, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: AsyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: AsyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 2 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.rst: CompiledValue { - layout: CompiledTypeLayout { - ty: AsyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: AsyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.count: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::count", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, + }.cd, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.clk, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.rst, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.count, }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "counter", diff --git a/crates/fayalite/tests/sim/expected/counter_sync.txt b/crates/fayalite/tests/sim/expected/counter_sync.txt index 78fc200..029b076 100644 --- a/crates/fayalite/tests/sim/expected/counter_sync.txt +++ b/crates/fayalite/tests/sim/expected/counter_sync.txt @@ -184,212 +184,57 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::cd.rst", - ty: SyncReset, - }, - ], - .. - }, + }.cd, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: SyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], + }.count, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 2 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.cd.rst: CompiledValue { - layout: CompiledTypeLayout { - ty: SyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::counter, - instantiated: Module { - name: counter, - .. - }, - }.count: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(counter: counter).counter::count", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, + }.cd, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.clk, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.cd.rst, + Instance { + name: ::counter, + instantiated: Module { + name: counter, + .. + }, + }.count, }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "counter", diff --git a/crates/fayalite/tests/sim/expected/duplicate_names.txt b/crates/fayalite/tests/sim/expected/duplicate_names.txt index 8a59861..ac89814 100644 --- a/crates/fayalite/tests/sim/expected/duplicate_names.txt +++ b/crates/fayalite/tests/sim/expected/duplicate_names.txt @@ -88,9 +88,13 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: {}, - made_initial_step: true, + main_module: SimulationModuleState { + base_targets: [], + uninitialized_ios: {}, + io_targets: {}, + did_initial_settle: true, + }, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "duplicate_names", diff --git a/crates/fayalite/tests/sim/expected/enums.txt b/crates/fayalite/tests/sim/expected/enums.txt index ebfae3e..1e73407 100644 --- a/crates/fayalite/tests/sim/expected/enums.txt +++ b/crates/fayalite/tests/sim/expected/enums.txt @@ -1215,388 +1215,127 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.b_out: CompiledValue { - layout: CompiledTypeLayout { - ty: Enum { - HdlNone, - HdlSome(Bundle {0: UInt<1>, 1: Bool}), + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(enums: enums).enums::b_out", - ty: Enum { - HdlNone, - HdlSome(Bundle {0: UInt<1>, 1: Bool}), - }, - }, - ], - .. - }, + }.cd, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 7, len: 1 }, - }, - write: None, - }, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.cd: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(enums: enums).enums::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(enums: enums).enums::cd.rst", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: SyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 2 }, - }, - write: None, - }, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.cd.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.cd.rst: CompiledValue { - layout: CompiledTypeLayout { - ty: SyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.data_in: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(enums: enums).enums::data_in", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - }, - write: None, - }, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.data_out: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(enums: enums).enums::data_out", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 6, len: 1 }, - }, - write: None, - }, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.en: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(enums: enums).enums::en", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, - }, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.which_in: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<2>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(enums: enums).enums::which_in", - ty: UInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 1 }, - }, - write: None, - }, - Instance { - name: ::enums, - instantiated: Module { - name: enums, - .. - }, - }.which_out: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<2>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(enums: enums).enums::which_out", - ty: UInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 5, len: 1 }, - }, - write: None, + }.en, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.which_in, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.data_in, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.which_out, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.data_out, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.b_out, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.b_out, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.cd, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.cd.clk, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.cd.rst, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.data_in, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.data_out, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.en, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.which_in, + Instance { + name: ::enums, + instantiated: Module { + name: enums, + .. + }, + }.which_out, }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "enums", diff --git a/crates/fayalite/tests/sim/expected/memories.txt b/crates/fayalite/tests/sim/expected/memories.txt index afccd8a..e3b4f16 100644 --- a/crates/fayalite/tests/sim/expected/memories.txt +++ b/crates/fayalite/tests/sim/expected/memories.txt @@ -570,1308 +570,148 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - #[hdl(flip)] /* offset = 6 */ - data: Bundle { - /* offset = 0 */ - 0: UInt<8>, - /* offset = 8 */ - 1: SInt<8>, - }, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 5, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::r.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::r.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::r.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::r.data.0", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::r.data.1", - ty: SInt<8>, - }, - ], - .. - }, + }.r, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(2), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(3), - }, - ty: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - 0: UInt<8>, - /* offset = 8 */ - 1: SInt<8>, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: ".0", - ty: UInt<8>, - }, - SlotDebugData { - name: ".1", - ty: SInt<8>, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: SInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], - }, - }, - }, - ], + }.w, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 5 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.addr: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.data: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - 0: UInt<8>, - /* offset = 8 */ - 1: SInt<8>, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: ".0", - ty: UInt<8>, - }, - SlotDebugData { - name: ".1", - ty: SInt<8>, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: SInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 2 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.data.0: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.data.1: CompiledValue { - layout: CompiledTypeLayout { - ty: SInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.r.en: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - addr: UInt<4>, - /* offset = 4 */ - en: Bool, - /* offset = 5 */ - clk: Clock, - /* offset = 6 */ - data: Bundle { - /* offset = 0 */ - 0: UInt<8>, - /* offset = 8 */ - 1: SInt<8>, - }, - /* offset = 22 */ - mask: Bundle { - /* offset = 0 */ - 0: Bool, - /* offset = 1 */ - 1: Bool, - }, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 7, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::w.addr", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::w.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::w.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::w.data.0", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::w.data.1", - ty: SInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::w.mask.0", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories: memories).memories::w.mask.1", - ty: Bool, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(2), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(3), - }, - ty: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - 0: UInt<8>, - /* offset = 8 */ - 1: SInt<8>, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: ".0", - ty: UInt<8>, - }, - SlotDebugData { - name: ".1", - ty: SInt<8>, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: SInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], - }, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(5), - }, - ty: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - 0: Bool, - /* offset = 1 */ - 1: Bool, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: ".0", - ty: Bool, - }, - SlotDebugData { - name: ".1", - ty: Bool, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], - }, - }, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 5, len: 7 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.addr: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 5, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 7, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.data: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - 0: UInt<8>, - /* offset = 8 */ - 1: SInt<8>, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: ".0", - ty: UInt<8>, - }, - SlotDebugData { - name: ".1", - ty: SInt<8>, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: SInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 8, len: 2 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.data.0: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 8, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.data.1: CompiledValue { - layout: CompiledTypeLayout { - ty: SInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 9, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.en: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 6, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.mask: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - 0: Bool, - /* offset = 1 */ - 1: Bool, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: ".0", - ty: Bool, - }, - SlotDebugData { - name: ".1", - ty: Bool, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 10, len: 2 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.mask.0: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 10, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories, - instantiated: Module { - name: memories, - .. - }, - }.w.mask.1: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 11, len: 1 }, - }, - write: None, + }.r, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.addr, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.clk, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.data, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.data.0, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.data.1, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.r.en, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.addr, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.clk, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.data, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.data.0, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.data.1, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.en, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.mask, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.mask.0, + Instance { + name: ::memories, + instantiated: Module { + name: memories, + .. + }, + }.w.mask.1, }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "memories", diff --git a/crates/fayalite/tests/sim/expected/memories2.txt b/crates/fayalite/tests/sim/expected/memories2.txt index 5d90815..c838f36 100644 --- a/crates/fayalite/tests/sim/expected/memories2.txt +++ b/crates/fayalite/tests/sim/expected/memories2.txt @@ -598,513 +598,78 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - addr: UInt<3>, - /* offset = 3 */ - en: Bool, - /* offset = 4 */ - clk: Clock, - #[hdl(flip)] /* offset = 5 */ - rdata: UInt<2>, - /* offset = 7 */ - wmode: Bool, - /* offset = 8 */ - wdata: UInt<2>, - /* offset = 10 */ - wmask: Bool, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 7, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(memories2: memories2).memories2::rw.addr", - ty: UInt<3>, - }, - SlotDebugData { - name: "InstantiatedModule(memories2: memories2).memories2::rw.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories2: memories2).memories2::rw.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(memories2: memories2).memories2::rw.rdata", - ty: UInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(memories2: memories2).memories2::rw.wmode", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories2: memories2).memories2::rw.wdata", - ty: UInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(memories2: memories2).memories2::rw.wmask", - ty: Bool, - }, - ], - .. - }, + }.rw, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: UInt<3>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<3>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(2), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(3), - }, - ty: CompiledTypeLayout { - ty: UInt<2>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(4), - }, - ty: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(5), - }, - ty: CompiledTypeLayout { - ty: UInt<2>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(6), - }, - ty: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], + }.rw, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 7 }, - }, - write: None, - }, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.addr: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<3>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<3>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.en: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.rdata: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<2>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.wdata: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<2>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 5, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.wmask: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 6, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories2, - instantiated: Module { - name: memories2, - .. - }, - }.rw.wmode: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - }, - write: None, + }.rw.addr, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.clk, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.en, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.rdata, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.wdata, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.wmask, + Instance { + name: ::memories2, + instantiated: Module { + name: memories2, + .. + }, + }.rw.wmode, }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "memories2", diff --git a/crates/fayalite/tests/sim/expected/memories3.txt b/crates/fayalite/tests/sim/expected/memories3.txt index 7860bc5..01bca44 100644 --- a/crates/fayalite/tests/sim/expected/memories3.txt +++ b/crates/fayalite/tests/sim/expected/memories3.txt @@ -1486,1881 +1486,274 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - addr: UInt<3>, - /* offset = 3 */ - en: Bool, - /* offset = 4 */ - clk: Clock, - #[hdl(flip)] /* offset = 5 */ - data: Array, 8>, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 11, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::r.addr", - ty: UInt<3>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::r.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::r.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::r.data[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::r.data[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::r.data[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::r.data[3]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::r.data[4]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::r.data[5]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::r.data[6]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::r.data[7]", - ty: UInt<8>, - }, - ], - .. - }, + }.r, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: UInt<3>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<3>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(2), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(3), - }, - ty: CompiledTypeLayout { - ty: Array, 8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 8, - debug_data: [ - SlotDebugData { - name: "[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[3]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[4]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[5]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[6]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[7]", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Array { - element: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - }, - }, - ], + }.w, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 11 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.addr: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<3>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<3>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data: CompiledValue { - layout: CompiledTypeLayout { - ty: Array, 8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 8, - debug_data: [ - SlotDebugData { - name: "[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[3]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[4]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[5]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[6]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[7]", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Array { - element: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 8 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[0]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[1]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 4, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[2]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 5, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[3]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 6, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[4]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 7, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[5]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 8, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[6]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 9, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.data[7]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 10, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.r.en: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - addr: UInt<3>, - /* offset = 3 */ - en: Bool, - /* offset = 4 */ - clk: Clock, - /* offset = 5 */ - data: Array, 8>, - /* offset = 69 */ - mask: Array, - }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 19, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.addr", - ty: UInt<3>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.en", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.data[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.data[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.data[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.data[3]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.data[4]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.data[5]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.data[6]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.data[7]", - ty: UInt<8>, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.mask[0]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.mask[1]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.mask[2]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.mask[3]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.mask[4]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.mask[5]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.mask[6]", - ty: Bool, - }, - SlotDebugData { - name: "InstantiatedModule(memories3: memories3).memories3::w.mask[7]", - ty: Bool, - }, - ], - .. - }, - }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: UInt<3>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<3>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(2), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(3), - }, - ty: CompiledTypeLayout { - ty: Array, 8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 8, - debug_data: [ - SlotDebugData { - name: "[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[3]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[4]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[5]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[6]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[7]", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Array { - element: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(11), - }, - ty: CompiledTypeLayout { - ty: Array, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 8, - debug_data: [ - SlotDebugData { - name: "[0]", - ty: Bool, - }, - SlotDebugData { - name: "[1]", - ty: Bool, - }, - SlotDebugData { - name: "[2]", - ty: Bool, - }, - SlotDebugData { - name: "[3]", - ty: Bool, - }, - SlotDebugData { - name: "[4]", - ty: Bool, - }, - SlotDebugData { - name: "[5]", - ty: Bool, - }, - SlotDebugData { - name: "[6]", - ty: Bool, - }, - SlotDebugData { - name: "[7]", - ty: Bool, - }, - ], - .. - }, - }, - body: Array { - element: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - }, - }, - ], - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 11, len: 19 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.addr: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<3>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<3>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 11, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 13, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data: CompiledValue { - layout: CompiledTypeLayout { - ty: Array, 8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 8, - debug_data: [ - SlotDebugData { - name: "[0]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[1]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[2]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[3]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[4]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[5]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[6]", - ty: UInt<8>, - }, - SlotDebugData { - name: "[7]", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Array { - element: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 14, len: 8 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[0]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 14, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[1]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 15, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[2]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 16, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[3]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 17, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[4]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 18, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[5]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 19, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[6]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 20, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.data[7]: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<8>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<8>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 21, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.en: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 12, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask: CompiledValue { - layout: CompiledTypeLayout { - ty: Array, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 8, - debug_data: [ - SlotDebugData { - name: "[0]", - ty: Bool, - }, - SlotDebugData { - name: "[1]", - ty: Bool, - }, - SlotDebugData { - name: "[2]", - ty: Bool, - }, - SlotDebugData { - name: "[3]", - ty: Bool, - }, - SlotDebugData { - name: "[4]", - ty: Bool, - }, - SlotDebugData { - name: "[5]", - ty: Bool, - }, - SlotDebugData { - name: "[6]", - ty: Bool, - }, - SlotDebugData { - name: "[7]", - ty: Bool, - }, - ], - .. - }, - }, - body: Array { - element: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 22, len: 8 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[0]: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 22, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[1]: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 23, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[2]: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 24, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[3]: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 25, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[4]: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 26, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[5]: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 27, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[6]: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 28, len: 1 }, - }, - write: None, - }, - Instance { - name: ::memories3, - instantiated: Module { - name: memories3, - .. - }, - }.w.mask[7]: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 29, len: 1 }, - }, - write: None, + }.r, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.addr, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.clk, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[0], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[1], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[2], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[3], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[4], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[5], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[6], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.data[7], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.r.en, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.addr, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.clk, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[0], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[1], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[2], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[3], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[4], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[5], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[6], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.data[7], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.en, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask, + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[0], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[1], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[2], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[3], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[4], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[5], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[6], + Instance { + name: ::memories3, + instantiated: Module { + name: memories3, + .. + }, + }.w.mask[7], }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "memories3", diff --git a/crates/fayalite/tests/sim/expected/mod1.txt b/crates/fayalite/tests/sim/expected/mod1.txt index 5c2b7eb..f783171 100644 --- a/crates/fayalite/tests/sim/expected/mod1.txt +++ b/crates/fayalite/tests/sim/expected/mod1.txt @@ -216,312 +216,57 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - #[hdl(flip)] /* offset = 0 */ - i: UInt<4>, - /* offset = 4 */ - o: SInt<2>, - #[hdl(flip)] /* offset = 6 */ - i2: SInt<2>, - /* offset = 8 */ - o2: UInt<4>, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 4, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.i", - ty: UInt<4>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.o", - ty: SInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.i2", - ty: SInt<2>, - }, - SlotDebugData { - name: "InstantiatedModule(mod1: mod1).mod1::o.o2", - ty: UInt<4>, - }, - ], - .. - }, + }.o, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: SInt<2>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(2), - }, - ty: CompiledTypeLayout { - ty: SInt<2>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(3), - }, - ty: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], + }.o, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 4 }, - }, - write: None, - }, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o.i: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o.i2: CompiledValue { - layout: CompiledTypeLayout { - ty: SInt<2>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, - }, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o.o: CompiledValue { - layout: CompiledTypeLayout { - ty: SInt<2>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SInt<2>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::mod1, - instantiated: Module { - name: mod1, - .. - }, - }.o.o2: CompiledValue { - layout: CompiledTypeLayout { - ty: UInt<4>, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: UInt<4>, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 1 }, - }, - write: None, + }.o.i, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o.i2, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o.o, + Instance { + name: ::mod1, + instantiated: Module { + name: mod1, + .. + }, + }.o.o2, }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "mod1", diff --git a/crates/fayalite/tests/sim/expected/shift_register.txt b/crates/fayalite/tests/sim/expected/shift_register.txt index 73f6263..e2ca6e2 100644 --- a/crates/fayalite/tests/sim/expected/shift_register.txt +++ b/crates/fayalite/tests/sim/expected/shift_register.txt @@ -265,246 +265,71 @@ Simulation { .. }, }, - uninitialized_inputs: {}, - io_targets: { - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.cd: CompiledValue { - layout: CompiledTypeLayout { - ty: Bundle { - /* offset = 0 */ - clk: Clock, - /* offset = 1 */ - rst: SyncReset, + main_module: SimulationModuleState { + base_targets: [ + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. }, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 2, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.clk", - ty: Clock, - }, - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::cd.rst", - ty: SyncReset, - }, - ], - .. - }, + }.cd, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. }, - body: Bundle { - fields: [ - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(0), - }, - ty: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - CompiledBundleField { - offset: TypeIndex { - small_slots: StatePartIndex(0), - big_slots: StatePartIndex(1), - }, - ty: CompiledTypeLayout { - ty: SyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - }, - ], + }.d, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. }, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 2 }, - }, - write: None, - }, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.cd.clk: CompiledValue { - layout: CompiledTypeLayout { - ty: Clock, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: Clock, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 0, len: 1 }, - }, - write: None, - }, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.cd.rst: CompiledValue { - layout: CompiledTypeLayout { - ty: SyncReset, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "", - ty: SyncReset, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 1, len: 1 }, - }, - write: None, - }, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.d: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::d", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 2, len: 1 }, - }, - write: None, - }, - Instance { - name: ::shift_register, - instantiated: Module { - name: shift_register, - .. - }, - }.q: CompiledValue { - layout: CompiledTypeLayout { - ty: Bool, - layout: TypeLayout { - small_slots: StatePartLayout { - len: 0, - debug_data: [], - .. - }, - big_slots: StatePartLayout { - len: 1, - debug_data: [ - SlotDebugData { - name: "InstantiatedModule(shift_register: shift_register).shift_register::q", - ty: Bool, - }, - ], - .. - }, - }, - body: Scalar, - }, - range: TypeIndexRange { - small_slots: StatePartIndexRange { start: 0, len: 0 }, - big_slots: StatePartIndexRange { start: 3, len: 1 }, - }, - write: None, + }.q, + ], + uninitialized_ios: {}, + io_targets: { + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.cd, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.cd.clk, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.cd.rst, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.d, + Instance { + name: ::shift_register, + instantiated: Module { + name: shift_register, + .. + }, + }.q, }, + did_initial_settle: true, }, - made_initial_step: true, + extern_modules: [], needs_settle: false, trace_decls: TraceModule { name: "shift_register",