forked from libre-chip/fayalite
simplify setting an extern module simulation
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parent
d1bd176b28
commit
ab9ff4f2db
5 changed files with 111 additions and 163 deletions
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@ -128,31 +128,27 @@ Simulation {
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},
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did_initial_settle: true,
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},
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io_ty: Bundle {
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#[hdl(flip)] /* offset = 0 */
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i: Bool,
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/* offset = 1 */
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o: Bool,
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},
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sim: ExternModuleSimulation {
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generator: Sim {
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i: ModuleIO {
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name: extern_module::i,
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is_input: true,
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ty: Bool,
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..
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},
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o: ModuleIO {
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name: extern_module::o,
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is_input: false,
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ty: Bool,
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..
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},
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generator: SimGeneratorFn {
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args: (
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ModuleIO {
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name: extern_module::i,
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is_input: true,
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ty: Bool,
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..
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},
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ModuleIO {
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name: extern_module::o,
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is_input: false,
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ty: Bool,
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..
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},
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),
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f: ...,
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},
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source_location: SourceLocation(
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module-XXXXXXXXXX.rs:4:1,
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),
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_phantom: PhantomData<fayalite::bundle::Bundle>,
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},
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running_generator: Some(
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...,
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