forked from libre-chip/fayalite
add ty.uninit()
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7 changed files with 119 additions and 1 deletions
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@ -3139,3 +3139,46 @@ circuit check_annotations: %[[
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"#,
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};
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}
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#[hdl_module(outline_generated)]
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pub fn check_uninit<T: Type>(ty: T) {
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#[hdl]
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let o: T = m.output(ty);
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connect(o, ty.uninit());
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}
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#[test]
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fn test_uninit() {
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let _n = SourceLocation::normalize_files_for_tests();
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let m = check_uninit((UInt[3], SInt[5], Clock));
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dbg!(m);
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#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
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assert_export_firrtl! {
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m =>
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"/test/check_uninit.fir": r"FIRRTL version 3.2.0
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circuit check_uninit:
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type Ty0 = {`0`: UInt<3>, `1`: SInt<5>, `2`: Clock}
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module check_uninit: @[module-XXXXXXXXXX.rs 1:1]
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output o: Ty0 @[module-XXXXXXXXXX.rs 2:1]
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wire _uninit_expr: Ty0
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invalidate _uninit_expr
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connect o, _uninit_expr @[module-XXXXXXXXXX.rs 3:1]
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",
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};
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let m = check_uninit(Array[HdlOption[()]][3]);
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dbg!(m);
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#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
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assert_export_firrtl! {
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m =>
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"/test/check_uninit_1.fir": r"FIRRTL version 3.2.0
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circuit check_uninit_1:
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type Ty0 = {}
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type Ty1 = {|HdlNone, HdlSome: Ty0|}
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module check_uninit_1: @[module-XXXXXXXXXX.rs 1:1]
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output o: Ty1[3] @[module-XXXXXXXXXX.rs 2:1]
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wire _uninit_expr: Ty1[3]
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invalidate _uninit_expr
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connect o, _uninit_expr @[module-XXXXXXXXXX.rs 3:1]
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",
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};
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}
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