add ty.uninit()

This commit is contained in:
Jacob Lifshay 2024-09-22 17:26:23 -07:00
parent 8449854cac
commit 9ad4ec0f39
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
7 changed files with 119 additions and 1 deletions

View file

@ -3139,3 +3139,46 @@ circuit check_annotations: %[[
"#,
};
}
#[hdl_module(outline_generated)]
pub fn check_uninit<T: Type>(ty: T) {
#[hdl]
let o: T = m.output(ty);
connect(o, ty.uninit());
}
#[test]
fn test_uninit() {
let _n = SourceLocation::normalize_files_for_tests();
let m = check_uninit((UInt[3], SInt[5], Clock));
dbg!(m);
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
assert_export_firrtl! {
m =>
"/test/check_uninit.fir": r"FIRRTL version 3.2.0
circuit check_uninit:
type Ty0 = {`0`: UInt<3>, `1`: SInt<5>, `2`: Clock}
module check_uninit: @[module-XXXXXXXXXX.rs 1:1]
output o: Ty0 @[module-XXXXXXXXXX.rs 2:1]
wire _uninit_expr: Ty0
invalidate _uninit_expr
connect o, _uninit_expr @[module-XXXXXXXXXX.rs 3:1]
",
};
let m = check_uninit(Array[HdlOption[()]][3]);
dbg!(m);
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
assert_export_firrtl! {
m =>
"/test/check_uninit_1.fir": r"FIRRTL version 3.2.0
circuit check_uninit_1:
type Ty0 = {}
type Ty1 = {|HdlNone, HdlSome: Ty0|}
module check_uninit_1: @[module-XXXXXXXXXX.rs 1:1]
output o: Ty1[3] @[module-XXXXXXXXXX.rs 2:1]
wire _uninit_expr: Ty1[3]
invalidate _uninit_expr
connect o, _uninit_expr @[module-XXXXXXXXXX.rs 3:1]
",
};
}