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sim/interpreter: fix StatePartLayout name in debug output

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This commit is contained in:
Jacob Lifshay 2024-12-12 15:06:17 -08:00
parent 393f78a14d
commit 562c479b62
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
8 changed files with 104 additions and 104 deletions
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30
crates/fayalite/tests/sim/expected/counter_async.txt
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@ -3,7 +3,7 @@ Simulation {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 4,
debug_data: [
SlotDebugData {
@ -25,7 +25,7 @@ Simulation {
],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 10,
debug_data: [
SlotDebugData {
@ -72,7 +72,7 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
@ -219,12 +219,12 @@ Simulation {
rst: AsyncReset,
},
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 2,
debug_data: [
SlotDebugData {
@ -249,12 +249,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -276,12 +276,12 @@ Simulation {
ty: CompiledTypeLayout {
ty: AsyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -314,12 +314,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: Clock,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -348,12 +348,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: AsyncReset,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {
@ -382,12 +382,12 @@ Simulation {
layout: CompiledTypeLayout {
ty: UInt<4>,
layout: TypeLayout {
small_slots: StatePartAllocationLayout<SmallSlots> {
small_slots: StatePartLayout<SmallSlots> {
len: 0,
debug_data: [],
..
},
big_slots: StatePartAllocationLayout<BigSlots> {
big_slots: StatePartLayout<BigSlots> {
len: 1,
debug_data: [
SlotDebugData {