forked from libre-chip/fayalite
		
	sim: fix assignments graph by properly including conditions as assignment inputs
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					 1 changed files with 27 additions and 0 deletions
				
			
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			@ -458,6 +458,9 @@ impl Assignments {
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            slot_readers
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                .keys_for_assignment(assignment_index)
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                .extend([&assignment.inputs]);
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            slot_readers
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                .keys_for_assignment(assignment_index)
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                .extend(&assignment.conditions);
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            let SlotSet(TypeParts {
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                small_slots,
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                big_slots,
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			@ -1400,6 +1403,30 @@ impl<'a> Extend<&'a SlotSet> for SlotToAssignmentIndexFullMapKeysForAssignment<'
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    }
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}
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impl<'a> Extend<&'a Cond> for SlotToAssignmentIndexFullMapKeysForAssignment<'_> {
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    fn extend<T: IntoIterator<Item = &'a Cond>>(&mut self, iter: T) {
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        iter.into_iter().for_each(|cond| match cond.body {
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            CondBody::IfTrue { cond } | CondBody::IfFalse { cond } => {
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                let CompiledValue {
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                    range:
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                        TypeIndexRange {
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                            small_slots,
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                            big_slots,
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                        },
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                    layout: _,
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                    write: _,
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                } = cond;
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                self.extend(small_slots.iter());
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                self.extend(big_slots.iter());
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            }
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            CondBody::MatchArm {
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                discriminant,
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                variant_index: _,
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            } => self.extend([discriminant]),
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        });
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    }
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}
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impl Assignment {
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    fn new(
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        conditions: Interned<[Cond]>,
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