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change SimValue to contain and deref to a value and not just contain bits

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This commit is contained in:
Jacob Lifshay 2025-03-27 23:44:36 -07:00
parent e0f978fbb6
commit 5028401a5a
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
19 changed files with 2065 additions and 820 deletions
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4
crates/fayalite/tests/sim/expected/extern_module2.txt
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@ -222,7 +222,9 @@ Simulation {
},
value: SimValue {
ty: Clock,
bits: 0x1,
value: OpaqueSimValue {
bits: 0x1_u1,
},
},
},
},

12
crates/fayalite/tests/sim/expected/ripple_counter.txt
View file

@ -826,7 +826,9 @@ Simulation {
},
value: SimValue {
ty: Clock,
bits: 0x0,
value: OpaqueSimValue {
bits: 0x0_u1,
},
},
},
},
@ -921,7 +923,9 @@ Simulation {
},
value: SimValue {
ty: Clock,
bits: 0x0,
value: OpaqueSimValue {
bits: 0x0_u1,
},
},
},
},
@ -1016,7 +1020,9 @@ Simulation {
},
value: SimValue {
ty: Clock,
bits: 0x0,
value: OpaqueSimValue {
bits: 0x0_u1,
},
},
},
},