programmerjake/fayalite
1
0
Fork 0
forked from libre-chip/fayalite
Code Pull requests Activity

sim: WIP adding memory support

Browse source
This commit is contained in:
Jacob Lifshay 2024-12-05 21:35:23 -08:00
parent e504cfebfe
commit 3ed7827485
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
8 changed files with 335 additions and 38 deletions
Download patch file Download diff file Expand all files Collapse all files

9
crates/fayalite/tests/sim/expected/counter_async.txt
View file

@ -72,6 +72,12 @@ Simulation {
..
},
},
memories: StatePartAllocationLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
insns: [
// at: module-XXXXXXXXXX.rs:1:1
@ -162,6 +168,9 @@ Simulation {
..
},
pc: 18,
memories: StatePart {
value: [],
},
small_slots: StatePart {
value: [
18446744073709551614,