forked from libre-chip/fayalite
sim: add WIP memory test
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parent
8616ee4737
commit
393f78a14d
11 changed files with 1155 additions and 304 deletions
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@ -875,6 +875,7 @@ Simulation {
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..
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},
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pc: 100,
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memory_write_log: [],
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memories: StatePart {
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value: [],
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},
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@ -1333,12 +1334,12 @@ Simulation {
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name: "cd",
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fields: [
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TraceClock {
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id: TraceScalarId(0),
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location: TraceScalarId(0),
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name: "clk",
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flow: Source,
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},
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TraceSyncReset {
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id: TraceScalarId(1),
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location: TraceScalarId(1),
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name: "rst",
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flow: Source,
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},
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@ -1362,7 +1363,7 @@ Simulation {
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TraceModuleIO {
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name: "en",
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child: TraceBool {
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id: TraceScalarId(2),
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location: TraceScalarId(2),
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name: "en",
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flow: Source,
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},
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@ -1372,7 +1373,7 @@ Simulation {
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TraceModuleIO {
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name: "which_in",
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child: TraceUInt {
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id: TraceScalarId(3),
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location: TraceScalarId(3),
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name: "which_in",
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ty: UInt<2>,
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flow: Source,
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@ -1383,7 +1384,7 @@ Simulation {
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TraceModuleIO {
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name: "data_in",
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child: TraceUInt {
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id: TraceScalarId(4),
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location: TraceScalarId(4),
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name: "data_in",
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ty: UInt<4>,
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flow: Source,
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@ -1394,7 +1395,7 @@ Simulation {
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TraceModuleIO {
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name: "which_out",
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child: TraceUInt {
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id: TraceScalarId(5),
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location: TraceScalarId(5),
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name: "which_out",
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ty: UInt<2>,
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flow: Sink,
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@ -1405,7 +1406,7 @@ Simulation {
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TraceModuleIO {
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name: "data_out",
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child: TraceUInt {
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id: TraceScalarId(6),
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location: TraceScalarId(6),
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name: "data_out",
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ty: UInt<4>,
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flow: Sink,
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@ -1418,7 +1419,7 @@ Simulation {
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child: TraceEnumWithFields {
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name: "the_reg",
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discriminant: TraceEnumDiscriminant {
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id: TraceScalarId(7),
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location: TraceScalarId(7),
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name: "$tag",
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ty: Enum {
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A,
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@ -1432,13 +1433,13 @@ Simulation {
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name: "B",
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fields: [
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TraceUInt {
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id: TraceScalarId(8),
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location: TraceScalarId(8),
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name: "0",
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ty: UInt<1>,
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flow: Source,
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},
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TraceBool {
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id: TraceScalarId(9),
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location: TraceScalarId(9),
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name: "1",
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flow: Source,
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},
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@ -1458,13 +1459,13 @@ Simulation {
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name: "a",
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elements: [
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TraceUInt {
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id: TraceScalarId(10),
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location: TraceScalarId(10),
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name: "[0]",
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ty: UInt<1>,
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flow: Source,
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},
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TraceUInt {
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id: TraceScalarId(11),
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location: TraceScalarId(11),
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name: "[1]",
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ty: UInt<1>,
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flow: Source,
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@ -1474,7 +1475,7 @@ Simulation {
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flow: Source,
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},
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TraceSInt {
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id: TraceScalarId(12),
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location: TraceScalarId(12),
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name: "b",
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ty: SInt<2>,
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flow: Source,
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@ -1623,6 +1624,7 @@ Simulation {
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last_state: 0x3,
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},
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],
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trace_memories: {},
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trace_writers: [
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Running(
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VcdWriter {
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