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sim: add WIP memory test

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This commit is contained in:
Jacob Lifshay 2024-12-11 23:28:15 -08:00
parent 8616ee4737
commit 393f78a14d
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
11 changed files with 1155 additions and 304 deletions
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10
crates/fayalite/tests/sim/expected/counter_async.txt
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@ -168,6 +168,7 @@ Simulation {
..
},
pc: 18,
memory_write_log: [],
memories: StatePart {
value: [],
},
@ -417,12 +418,12 @@ Simulation {
name: "cd",
fields: [
TraceClock {
id: TraceScalarId(0),
location: TraceScalarId(0),
name: "clk",
flow: Source,
},
TraceAsyncReset {
id: TraceScalarId(1),
location: TraceScalarId(1),
name: "rst",
flow: Source,
},
@ -446,7 +447,7 @@ Simulation {
TraceModuleIO {
name: "count",
child: TraceUInt {
id: TraceScalarId(2),
location: TraceScalarId(2),
name: "count",
ty: UInt<4>,
flow: Sink,
@ -457,7 +458,7 @@ Simulation {
TraceReg {
name: "count_reg",
child: TraceUInt {
id: TraceScalarId(3),
location: TraceScalarId(3),
name: "count_reg",
ty: UInt<4>,
flow: Duplex,
@ -502,6 +503,7 @@ Simulation {
last_state: 0x3,
},
],
trace_memories: {},
trace_writers: [
Running(
VcdWriter {