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change NameId to have an opaque Id so output firrtl doesn't depend on how many modules of the same name were ever created

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This commit is contained in:
Jacob Lifshay 2024-10-07 19:06:01 -07:00
parent eed0afc6ab
commit 30b9a5e48d
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
6 changed files with 204 additions and 279 deletions
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224
crates/fayalite/tests/module.rs
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@ -175,9 +175,9 @@ circuit check_array_repeat:
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
assert_export_firrtl! {
m =>
"/test/check_array_repeat_1.fir": r"FIRRTL version 3.2.0
circuit check_array_repeat_1:
module check_array_repeat_1: @[module-XXXXXXXXXX.rs 1:1]
"/test/check_array_repeat.fir": r"FIRRTL version 3.2.0
circuit check_array_repeat:
module check_array_repeat: @[module-XXXXXXXXXX.rs 1:1]
input i: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
output o: UInt<8>[4] @[module-XXXXXXXXXX.rs 3:1]
wire _array_literal_expr: UInt<8>[4]
@ -1672,9 +1672,9 @@ fn test_memory_of_arrays() {
circuit check_memory_of_arrays: %[[
{
"class": "firrtl.annotations.MemoryFileInlineAnnotation",
"filename": "/test/check_memory_of_arrays/mem_1.mem",
"filename": "/test/check_memory_of_arrays/mem.mem",
"hexOrBinary": "h",
"target": "~check_memory_of_arrays|check_memory_of_arrays>mem_1"
"target": "~check_memory_of_arrays|check_memory_of_arrays>mem"
}
]]
type Ty0 = {addr: UInt<4>, en: UInt<1>, clk: Clock, flip data: UInt<8>[2][3]}
@ -1688,7 +1688,7 @@ circuit check_memory_of_arrays: %[[
input wdata: UInt<8>[2][3] @[module-XXXXXXXXXX.rs 5:1]
input wmask: UInt<1>[2][3] @[module-XXXXXXXXXX.rs 6:1]
input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
mem mem_1: @[module-XXXXXXXXXX.rs 8:1]
mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
data-type => UInt<8>[6]
depth => 16
read-latency => 0
@ -1698,30 +1698,30 @@ circuit check_memory_of_arrays: %[[
writer => w1
wire mem_r0: Ty0 @[module-XXXXXXXXXX.rs 9:1]
wire mem_w1: Ty1 @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.data[0][0], mem_1.r0.data[0] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[0][1], mem_1.r0.data[1] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[1][0], mem_1.r0.data[2] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[1][1], mem_1.r0.data[3] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[2][0], mem_1.r0.data[4] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[2][1], mem_1.r0.data[5] @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.w1.data[0], mem_w1.data[0][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[0], mem_w1.mask[0][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.data[1], mem_w1.data[0][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[1], mem_w1.mask[0][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.data[2], mem_w1.data[1][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[2], mem_w1.mask[1][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.data[3], mem_w1.data[1][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[3], mem_w1.mask[1][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.data[4], mem_w1.data[2][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[4], mem_w1.mask[2][0] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.data[5], mem_w1.data[2][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[5], mem_w1.mask[2][1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.data[0][0], `mem`.r0.data[0] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[0][1], `mem`.r0.data[1] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[1][0], `mem`.r0.data[2] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[1][1], `mem`.r0.data[3] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[2][0], `mem`.r0.data[4] @[module-XXXXXXXXXX.rs 9:1]
connect mem_r0.data[2][1], `mem`.r0.data[5] @[module-XXXXXXXXXX.rs 9:1]
connect `mem`.w1.data[0], mem_w1.data[0][0] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.mask[0], mem_w1.mask[0][0] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.data[1], mem_w1.data[0][1] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.mask[1], mem_w1.mask[0][1] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.data[2], mem_w1.data[1][0] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.mask[2], mem_w1.mask[1][0] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.data[3], mem_w1.data[1][1] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.mask[3], mem_w1.mask[1][1] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.data[4], mem_w1.data[2][0] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.mask[4], mem_w1.mask[2][0] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.data[5], mem_w1.data[2][1] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.mask[5], mem_w1.mask[2][1] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
@ -1732,7 +1732,7 @@ circuit check_memory_of_arrays: %[[
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
"#,
"/test/check_memory_of_arrays/mem_1.mem": r"000000000000
"/test/check_memory_of_arrays/mem.mem": r"000000000000
020103020101
04080c080402
061b1b120903
@ -2445,9 +2445,9 @@ fn test_memory_of_enum() {
circuit check_memory_of_enum: %[[
{
"class": "firrtl.annotations.MemoryFileInlineAnnotation",
"filename": "/test/check_memory_of_enum/mem_1.mem",
"filename": "/test/check_memory_of_enum/mem.mem",
"hexOrBinary": "b",
"target": "~check_memory_of_enum|check_memory_of_enum>mem_1"
"target": "~check_memory_of_enum|check_memory_of_enum>mem"
}
]]
type Ty0 = {|A, B: UInt<8>, C: UInt<1>[3]|}
@ -2462,7 +2462,7 @@ circuit check_memory_of_enum: %[[
input wdata: Ty0 @[module-XXXXXXXXXX.rs 5:1]
input wmask: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
mem mem_1: @[module-XXXXXXXXXX.rs 8:1]
mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
data-type => UInt<10>
depth => 16
read-latency => 0
@ -2474,10 +2474,10 @@ circuit check_memory_of_enum: %[[
wire mem_w1: Ty2 @[module-XXXXXXXXXX.rs 14:1]
wire _cast_bits_to_enum_expr: Ty0
wire _cast_bits_to_enum_expr_body: UInt<8>
connect _cast_bits_to_enum_expr_body, head(mem_1.r0.data, 8)
when eq(UInt<2>(0), tail(mem_1.r0.data, 8)):
connect _cast_bits_to_enum_expr_body, head(`mem`.r0.data, 8)
when eq(UInt<2>(0), tail(`mem`.r0.data, 8)):
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
else when eq(UInt<2>(1), tail(mem_1.r0.data, 8)):
else when eq(UInt<2>(1), tail(`mem`.r0.data, 8)):
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body)
else:
wire _cast_bits_to_array_expr: UInt<1>[3]
@ -2504,14 +2504,14 @@ circuit check_memory_of_enum: %[[
wire _cast_to_bits_expr: UInt<3>
connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
connect _cast_enum_to_bits_expr, pad(cat(_cast_to_bits_expr, UInt<2>(2)), 10)
connect mem_1.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.mask, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
; connect different types:
; lhs: UInt<4>
; rhs: UInt<8>
@ -2528,7 +2528,7 @@ circuit check_memory_of_enum: %[[
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
"#,
"/test/check_memory_of_enum/mem_1.mem": r"0000000000
"/test/check_memory_of_enum/mem.mem": r"0000000000
0000000110
0000001010
0000010010
@ -2602,7 +2602,7 @@ circuit check_memory_of_enum: %[[
reader => r0
writer => w1
wire mem_r0: Ty2 @[module-XXXXXXXXXX.rs 9:1]
wire mem_w1_1: Ty4 @[module-XXXXXXXXXX.rs 14:1]
wire mem_w1: Ty4 @[module-XXXXXXXXXX.rs 14:1]
wire _cast_bits_to_enum_expr: Ty0
when eq(UInt<2>(0), tail(mem_tag.r0.data, 0)):
connect _cast_bits_to_enum_expr, {|A, B, C|}(A)
@ -2612,7 +2612,7 @@ circuit check_memory_of_enum: %[[
connect _cast_bits_to_enum_expr, {|A, B, C|}(C)
connect mem_r0.data.tag, _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 9:1]
wire _cast_enum_to_bits_expr: UInt<2>
match mem_w1_1.data.tag:
match mem_w1.data.tag:
A:
connect _cast_enum_to_bits_expr, UInt<2>(0)
B:
@ -2620,29 +2620,29 @@ circuit check_memory_of_enum: %[[
C:
connect _cast_enum_to_bits_expr, UInt<2>(2)
connect mem_tag.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.mask, mem_w1_1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.mask, mem_w1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.data.body, mem_body.r0.data @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.w1.data, mem_w1_1.data.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.mask, mem_w1_1.mask.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.data, mem_w1.data.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.mask, mem_w1.mask.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
wire mem_w1: Ty9 @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
wire mem_w1_1: Ty9 @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.data, mem_w1_1.data @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.mask.tag, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.mask.body, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
; connect different types:
; lhs: UInt<4>
; rhs: UInt<8>
@ -2653,11 +2653,11 @@ circuit check_memory_of_enum: %[[
; connect different types:
; lhs: UInt<4>
; rhs: UInt<8>
connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
connect mem_w1_1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
connect mem_w1_1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
connect mem_w1_1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
connect mem_w1_1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
connect mem_w1_1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
"#,
"/test/check_memory_of_enum/mem_body.mem": r"00
01
@ -2748,32 +2748,32 @@ circuit check_memory_of_enum: %[[
reader => r0
writer => w1
wire mem_r0: Ty1 @[module-XXXXXXXXXX.rs 9:1]
wire mem_w1_1: Ty3 @[module-XXXXXXXXXX.rs 14:1]
wire mem_w1: Ty3 @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.data.tag, mem_tag.r0.data @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.w1.data, mem_w1_1.data.tag @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.mask, mem_w1_1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.data, mem_w1.data.tag @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.mask, mem_w1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_tag.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.data.body, mem_body.r0.data @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.w1.data, mem_w1_1.data.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.mask, mem_w1_1.mask.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.data, mem_w1.data.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.mask, mem_w1.mask.body @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_body.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
wire mem_w1: Ty8 @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
wire mem_w1_1: Ty8 @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.data, mem_w1_1.data @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.mask.tag, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
connect mem_w1.mask.body, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
; connect different types:
; lhs: UInt<4>
; rhs: UInt<8>
@ -2784,11 +2784,11 @@ circuit check_memory_of_enum: %[[
; connect different types:
; lhs: UInt<4>
; rhs: UInt<8>
connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
connect mem_w1_1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
connect mem_w1_1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
connect mem_w1_1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
connect mem_w1_1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
connect mem_w1_1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
"#,
"/test/check_memory_of_enum/mem_body.mem": r"00
01
@ -2950,7 +2950,7 @@ circuit check_memory_of_array_of_enum:
input wdata: Ty0[2] @[module-XXXXXXXXXX.rs 5:1]
input wmask: UInt<1>[2] @[module-XXXXXXXXXX.rs 6:1]
input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
mem mem_1: @[module-XXXXXXXXXX.rs 8:1]
mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
data-type => UInt<10>[2]
depth => 256
read-latency => 0
@ -2962,10 +2962,10 @@ circuit check_memory_of_array_of_enum:
wire mem_w1: Ty2 @[module-XXXXXXXXXX.rs 14:1]
wire _cast_bits_to_enum_expr: Ty0
wire _cast_bits_to_enum_expr_body: UInt<8>
connect _cast_bits_to_enum_expr_body, head(mem_1.r0.data[0], 8)
when eq(UInt<2>(0), tail(mem_1.r0.data[0], 8)):
connect _cast_bits_to_enum_expr_body, head(`mem`.r0.data[0], 8)
when eq(UInt<2>(0), tail(`mem`.r0.data[0], 8)):
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
else when eq(UInt<2>(1), tail(mem_1.r0.data[0], 8)):
else when eq(UInt<2>(1), tail(`mem`.r0.data[0], 8)):
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body)
else:
wire _cast_bits_to_array_expr: UInt<1>[3]
@ -2980,10 +2980,10 @@ circuit check_memory_of_array_of_enum:
connect mem_r0.data[0], _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 9:1]
wire _cast_bits_to_enum_expr_1: Ty0
wire _cast_bits_to_enum_expr_body_1: UInt<8>
connect _cast_bits_to_enum_expr_body_1, head(mem_1.r0.data[1], 8)
when eq(UInt<2>(0), tail(mem_1.r0.data[1], 8)):
connect _cast_bits_to_enum_expr_body_1, head(`mem`.r0.data[1], 8)
when eq(UInt<2>(0), tail(`mem`.r0.data[1], 8)):
connect _cast_bits_to_enum_expr_1, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
else when eq(UInt<2>(1), tail(mem_1.r0.data[1], 8)):
else when eq(UInt<2>(1), tail(`mem`.r0.data[1], 8)):
connect _cast_bits_to_enum_expr_1, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body_1)
else:
wire _cast_bits_to_array_expr_1: UInt<1>[3]
@ -3010,8 +3010,8 @@ circuit check_memory_of_array_of_enum:
wire _cast_to_bits_expr: UInt<3>
connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
connect _cast_enum_to_bits_expr, pad(cat(_cast_to_bits_expr, UInt<2>(2)), 10)
connect mem_1.w1.data[0], _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[0], mem_w1.mask[0] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.data[0], _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.mask[0], mem_w1.mask[0] @[module-XXXXXXXXXX.rs 14:1]
wire _cast_enum_to_bits_expr_1: UInt<10>
match mem_w1.data[1]:
A:
@ -3026,14 +3026,14 @@ circuit check_memory_of_array_of_enum:
wire _cast_to_bits_expr_1: UInt<3>
connect _cast_to_bits_expr_1, cat(_cast_array_to_bits_expr_1[2], cat(_cast_array_to_bits_expr_1[1], _cast_array_to_bits_expr_1[0]))
connect _cast_enum_to_bits_expr_1, pad(cat(_cast_to_bits_expr_1, UInt<2>(2)), 10)
connect mem_1.w1.data[1], _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.mask[1], mem_w1.mask[1] @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.data[1], _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.mask[1], mem_w1.mask[1] @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
@ -3344,11 +3344,11 @@ circuit check_uninit:
simplify_enums: None,
..ExportOptions::default()
},
"/test/check_uninit_1.fir": r"FIRRTL version 3.2.0
circuit check_uninit_1:
"/test/check_uninit.fir": r"FIRRTL version 3.2.0
circuit check_uninit:
type Ty0 = {}
type Ty1 = {|HdlNone, HdlSome: Ty0|}
module check_uninit_1: @[module-XXXXXXXXXX.rs 1:1]
module check_uninit: @[module-XXXXXXXXXX.rs 1:1]
output o: Ty1[3] @[module-XXXXXXXXXX.rs 2:1]
wire _uninit_expr: Ty1[3]
invalidate _uninit_expr