forked from libre-chip/fayalite
change NameId to have an opaque Id so output firrtl doesn't depend on how many modules of the same name were ever created
This commit is contained in:
parent
eed0afc6ab
commit
30b9a5e48d
SSH key fingerprint:
SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
6 changed files with 204 additions and 279 deletions
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@ -27,7 +27,7 @@ use crate::{
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simplify_memories::simplify_memories,
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},
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AnnotatedModuleIO, Block, ExternModuleBody, ExternModuleParameter,
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ExternModuleParameterValue, Module, ModuleBody, NameId, NormalModuleBody, Stmt,
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ExternModuleParameterValue, Module, ModuleBody, NameOptId, NormalModuleBody, Stmt,
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StmtConnect, StmtDeclaration, StmtFormal, StmtIf, StmtInstance, StmtMatch, StmtReg,
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StmtWire,
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},
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@ -187,9 +187,9 @@ struct NameMaker {
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}
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impl NameMaker {
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fn make(&mut self, name: NameId) -> Ident {
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let mut num: usize = name.1;
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let name = String::from(&*name.0);
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fn make(&mut self, name: impl Into<String>) -> Ident {
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let mut num = 0usize;
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let name: String = name.into();
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// remove all invalid characters -- all valid characters are ASCII, so we can just remove invalid bytes
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let mut name = String::from_iter(
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name.bytes()
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@ -221,7 +221,7 @@ impl NameMaker {
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#[derive(Default)]
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struct Namespace {
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name_maker: NameMaker,
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map: HashMap<NameId, Ident>,
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map: HashMap<NameOptId, Ident>,
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}
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#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
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@ -247,10 +247,11 @@ impl From<PortName> for Ident {
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}
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impl Namespace {
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fn get(&mut self, name: NameId) -> Ident {
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fn get(&mut self, name: impl Into<NameOptId>) -> Ident {
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let name: NameOptId = name.into();
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#[cold]
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fn make(name_maker: &mut NameMaker, name: NameId) -> Ident {
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name_maker.make(name)
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fn make(name_maker: &mut NameMaker, name: NameOptId) -> Ident {
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name_maker.make(name.0)
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}
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*self
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.map
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@ -258,7 +259,7 @@ impl Namespace {
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.or_insert_with(|| make(&mut self.name_maker, name))
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}
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fn make_new(&mut self, prefix: &str) -> Ident {
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self.name_maker.make(NameId(prefix.intern(), 0))
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self.name_maker.make(prefix)
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}
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}
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@ -368,7 +369,7 @@ impl TypeState {
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Ident(Intern::intern_owned(format!("Ty{id}")))
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}
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fn get_bundle_field(&mut self, ty: Bundle, name: Interned<str>) -> Ident {
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self.bundle_ns(ty).borrow_mut().get(NameId(name, 0))
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self.bundle_ns(ty).borrow_mut().get(name)
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}
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fn bundle_def(&self, ty: Bundle) -> (Ident, Rc<RefCell<Namespace>>) {
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self.bundle_defs.get_or_make(ty, |&ty, definitions| {
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@ -382,7 +383,7 @@ impl TypeState {
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if flipped {
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body.push_str("flip ");
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}
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write!(body, "{}: ", ns.get(NameId(name, 0))).unwrap();
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write!(body, "{}: ", ns.get(name)).unwrap();
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body.push_str(&self.ty(ty));
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}
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body.push('}');
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@ -406,7 +407,7 @@ impl TypeState {
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for EnumVariant { name, ty } in ty.variants() {
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body.push_str(separator);
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separator = ", ";
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write!(body, "{}", variants.get(NameId(name, 0))).unwrap();
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write!(body, "{}", variants.get(name)).unwrap();
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if let Some(ty) = ty {
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body.push_str(": ");
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body.push_str(&self.ty(ty));
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@ -428,11 +429,7 @@ impl TypeState {
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self.enum_def(ty).0
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}
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fn get_enum_variant(&mut self, ty: Enum, name: Interned<str>) -> Ident {
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self.enum_def(ty)
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.1
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.variants
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.borrow_mut()
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.get(NameId(name, 0))
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self.enum_def(ty).1.variants.borrow_mut().get(name)
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}
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fn ty<T: Type>(&self, ty: T) -> String {
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match ty.canonical() {
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@ -929,7 +926,7 @@ impl<'a> Exporter<'a> {
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) in expr.field_values().into_iter().zip(ty.fields())
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{
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debug_assert!(!flipped, "can't have bundle literal with flipped field -- this should have been caught in BundleLiteral::new_unchecked");
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let name = bundle_ns.borrow_mut().get(NameId(name, 0));
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let name = bundle_ns.borrow_mut().get(name);
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let field_value = self.expr(Expr::canonical(field_value), definitions, const_ty);
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definitions.add_definition_line(format_args!("connect {ident}.{name}, {field_value}"));
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}
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@ -2199,7 +2196,7 @@ impl<'a> Exporter<'a> {
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} in module.module_io().iter()
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{
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self.targeted_annotations(module_name, vec![], annotations);
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let name = self.module.ns.get(NameId(module_io.name(), 0));
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let name = self.module.ns.get(module_io.name_id());
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let ty = self.type_state.ty(module_io.ty());
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if module_io.is_input() {
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writeln!(
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@ -36,9 +36,10 @@ use std::{
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iter::FusedIterator,
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marker::PhantomData,
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mem,
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num::NonZeroU64,
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ops::Deref,
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rc::Rc,
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sync::Mutex,
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sync::atomic::AtomicU64,
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};
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pub mod transform;
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@ -602,8 +603,48 @@ impl BlockStack {
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}
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}
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#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
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pub struct Id(NonZeroU64);
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impl Id {
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pub fn new() -> Self {
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static NEXT_ID: AtomicU64 = AtomicU64::new(1);
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Self(
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NonZeroU64::new(NEXT_ID.fetch_add(1, std::sync::atomic::Ordering::Relaxed))
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.expect("Id::new ran out of ids"),
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)
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}
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}
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#[derive(Copy, Clone, Eq, PartialEq, Hash)]
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pub struct NameId(pub Interned<str>, pub usize);
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pub struct NameOptId(pub Interned<str>, pub Option<Id>);
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impl fmt::Debug for NameOptId {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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fmt::Display::fmt(self, f)
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}
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}
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impl fmt::Display for NameOptId {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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f.write_str(&self.0)
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}
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}
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impl From<Interned<str>> for NameOptId {
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fn from(name: Interned<str>) -> Self {
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Self(name, None)
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}
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}
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impl From<NameId> for NameOptId {
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fn from(name_id: NameId) -> Self {
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Self(name_id.0, Some(name_id.1))
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}
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}
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#[derive(Copy, Clone, Eq, PartialEq, Hash)]
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pub struct NameId(pub Interned<str>, pub Id);
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impl fmt::Debug for NameId {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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@ -613,13 +654,7 @@ impl fmt::Debug for NameId {
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impl fmt::Display for NameId {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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if self.0.is_empty() {
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write!(f, "{}", self.1)
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} else if self.1 == 0 {
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f.write_str(&self.0)
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} else {
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write!(f, "{}_{}", self.0, self.1)
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}
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f.write_str(&self.0)
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}
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}
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@ -648,106 +683,6 @@ impl fmt::Debug for TargetName {
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}
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}
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#[derive(Default)]
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pub struct NameIdGen(HashMap<Interned<str>, usize>);
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impl NameIdGen {
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pub fn gen(&mut self, name: Interned<str>) -> NameId {
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let next_id = self.0.entry(name).or_default();
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let id = *next_id;
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*next_id += 1;
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NameId(name, id)
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}
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pub fn mark_as_used(&mut self, name_id: NameId) {
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let next_id = self.0.entry(name_id.0).or_default();
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*next_id = (*next_id).max(name_id.1 + 1);
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}
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pub fn for_module(module: Module<Bundle>) -> Self {
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let mut retval = Self::default();
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let Module {
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name: _,
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source_location: _,
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body,
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io_ty: _,
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module_io,
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module_annotations: _,
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} = module;
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for module_io in &module_io {
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retval.mark_as_used(module_io.module_io.name_id());
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}
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match body {
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ModuleBody::Extern(ExternModuleBody {
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verilog_name: _,
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parameters: _,
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}) => {}
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ModuleBody::Normal(NormalModuleBody { body }) => {
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let mut blocks = vec![body];
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while let Some(block) = blocks.pop() {
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let Block { memories, stmts } = block;
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for memory in memories {
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retval.mark_as_used(memory.scoped_name().1);
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}
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for stmt in &stmts {
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blocks.extend_from_slice(stmt.sub_stmt_blocks());
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match stmt {
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Stmt::Connect(StmtConnect {
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lhs: _,
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rhs: _,
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source_location: _,
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})
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| Stmt::Formal(StmtFormal {
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kind: _,
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clk: _,
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pred: _,
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en: _,
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text: _,
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source_location: _,
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})
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| Stmt::If(StmtIf {
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cond: _,
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source_location: _,
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blocks: _,
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})
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| Stmt::Match(StmtMatch {
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expr: _,
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source_location: _,
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blocks: _,
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}) => {}
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Stmt::Declaration(StmtDeclaration::Instance(StmtInstance {
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annotations: _,
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instance,
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})) => {
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retval.mark_as_used(instance.name_id());
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}
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Stmt::Declaration(StmtDeclaration::Reg(StmtReg {
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annotations: _,
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reg,
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})) => {
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retval.mark_as_used(reg.name_id());
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}
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Stmt::Declaration(StmtDeclaration::Wire(StmtWire {
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annotations: _,
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wire,
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})) => {
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retval.mark_as_used(wire.name_id());
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}
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}
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}
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}
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}
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}
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retval
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}
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pub fn gen_module_name(name: Interned<str>) -> NameId {
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static MODULE_NAME_GEN: Mutex<Option<NameIdGen>> = Mutex::new(None);
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MODULE_NAME_GEN
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.lock()
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.unwrap()
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.get_or_insert_with(NameIdGen::default)
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.gen(name)
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}
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}
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#[derive(Copy, Clone, Eq, PartialEq, Hash)]
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pub struct Instance<T: BundleType> {
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scoped_name: ScopedNameId,
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@ -836,7 +771,6 @@ struct ModuleBuilderImpl {
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body: ModuleBodyBuilding,
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io: Vec<AnnotatedModuleIO<ModuleBuilding>>,
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io_indexes: HashMap<ModuleIO<CanonicalType>, usize>,
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name_id_gen: NameIdGen,
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module_annotations: Vec<Annotation>,
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}
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@ -1941,9 +1875,7 @@ impl<T: Type> RegBuilder<Expr<ClockDomain>, Option<Expr<T>>, T> {
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ty,
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} = self;
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ModuleBuilder::with(|module_builder| {
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let mut impl_ = module_builder.impl_.borrow_mut();
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let scoped_name = ScopedNameId(module_builder.name, impl_.name_id_gen.gen(name));
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drop(impl_);
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let scoped_name = ScopedNameId(module_builder.name, NameId(name, Id::new()));
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let reg = Reg::new_unchecked(scoped_name, source_location, ty, clock_domain, init);
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let retval = reg.to_expr();
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// convert before borrow_mut since ModuleBuilder could be reentered by T::canonical()
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@ -1991,8 +1923,13 @@ impl ModuleBuilder {
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is_input: bool,
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ty: IO,
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) -> Expr<IO> {
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let module_io =
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ModuleIO::<IO>::new_unchecked(self.name, name.intern(), source_location, is_input, ty);
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let module_io = ModuleIO::<IO>::new_unchecked(
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self.name,
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NameId(name.intern(), Id::new()),
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source_location,
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is_input,
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ty,
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);
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let retval = module_io.to_expr();
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let module_io = module_io.canonical();
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let mut impl_ = self.impl_.borrow_mut();
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@ -2080,7 +2017,7 @@ impl ModuleBuilder {
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module_kind: ModuleKind,
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f: impl FnOnce(&Self) -> Result<(), E>,
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) -> Result<Interned<Module<T>>, E> {
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let name = NameIdGen::gen_module_name(name.intern());
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let name = NameId(name.intern(), Id::new());
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let body = match module_kind {
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ModuleKind::Extern => ModuleBody::Extern(ExternModuleBody {
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verilog_name: name.0,
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@ -2105,7 +2042,6 @@ impl ModuleBuilder {
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body,
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io: vec![],
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io_indexes: HashMap::new(),
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name_id_gen: NameIdGen::default(),
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module_annotations: vec![],
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}),
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};
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@ -2277,9 +2213,7 @@ pub fn annotate<T: Type>(target: Expr<T>, annotations: impl IntoAnnotations) {
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#[track_caller]
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pub fn wire_with_loc<T: Type>(name: &str, source_location: SourceLocation, ty: T) -> Expr<T> {
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ModuleBuilder::with(|m| {
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let mut impl_ = m.impl_.borrow_mut();
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let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
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drop(impl_);
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let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
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let wire = Wire::<T>::new_unchecked(scoped_name, source_location, ty);
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let retval = wire.to_expr();
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let canonical_wire = wire.canonical();
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@ -2311,9 +2245,7 @@ fn incomplete_declaration(
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source_location: SourceLocation,
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) -> Rc<RefCell<IncompleteDeclaration>> {
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ModuleBuilder::with(|m| {
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let mut impl_ = m.impl_.borrow_mut();
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let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
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drop(impl_);
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let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
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let retval = Rc::new(RefCell::new(IncompleteDeclaration::Incomplete {
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name: scoped_name,
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source_location,
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@ -2489,9 +2421,7 @@ pub fn instance_with_loc<T: BundleType>(
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source_location: SourceLocation,
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) -> Expr<T> {
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ModuleBuilder::with(|m| {
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let mut impl_ = m.impl_.borrow_mut();
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let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
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drop(impl_);
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let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
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let instance = Instance::<T> {
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scoped_name,
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instantiated,
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|
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@ -2530,9 +2460,7 @@ fn memory_impl<Element: Type, Len: Size>(
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source_location: SourceLocation,
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) -> MemBuilder<Element, Len> {
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ModuleBuilder::with(|m| {
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let mut impl_ = m.impl_.borrow_mut();
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let scoped_name = ScopedNameId(m.name, impl_.name_id_gen.gen(name.intern()));
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drop(impl_);
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let scoped_name = ScopedNameId(m.name, NameId(name.intern(), Id::new()));
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let (retval, target_mem) = MemBuilder::new(scoped_name, source_location, mem_element_type);
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let mut impl_ = m.impl_.borrow_mut();
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let body = impl_.body.builder_normal_body();
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@ -2608,6 +2536,7 @@ pub fn memory<Element: Type>(
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pub struct ModuleIO<T: Type> {
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containing_module_name: NameId,
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bundle_field: BundleField,
|
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id: Id,
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ty: T,
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source_location: SourceLocation,
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}
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|
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@ -2627,12 +2556,14 @@ impl<T: Type> ModuleIO<T> {
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let Self {
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containing_module_name,
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bundle_field,
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id,
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ty: _,
|
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source_location,
|
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} = *self;
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ModuleIO {
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containing_module_name,
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bundle_field,
|
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id,
|
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ty: bundle_field.ty,
|
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source_location,
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}
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|
|
@ -2656,7 +2587,7 @@ impl<T: Type> ModuleIO<T> {
|
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self.bundle_field.name
|
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}
|
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pub fn name_id(&self) -> NameId {
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NameId(self.bundle_field.name, 0)
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NameId(self.bundle_field.name, self.id)
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}
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pub fn scoped_name(&self) -> ScopedNameId {
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ScopedNameId(self.containing_module_name, self.name_id())
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|
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@ -2666,7 +2597,7 @@ impl<T: Type> ModuleIO<T> {
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}
|
||||
pub fn new_unchecked(
|
||||
containing_module_name: NameId,
|
||||
name: Interned<str>,
|
||||
name: NameId,
|
||||
source_location: SourceLocation,
|
||||
is_input: bool,
|
||||
ty: T,
|
||||
|
|
@ -2674,10 +2605,11 @@ impl<T: Type> ModuleIO<T> {
|
|||
Self {
|
||||
containing_module_name,
|
||||
bundle_field: BundleField {
|
||||
name,
|
||||
name: name.0,
|
||||
flipped: is_input,
|
||||
ty: ty.canonical(),
|
||||
},
|
||||
id: name.1,
|
||||
ty,
|
||||
source_location,
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,8 +14,7 @@ use crate::{
|
|||
memory::{DynPortType, Mem, MemPort},
|
||||
module::{
|
||||
transform::visit::{Fold, Folder},
|
||||
Block, Module, NameId, NameIdGen, ScopedNameId, Stmt, StmtConnect, StmtIf, StmtMatch,
|
||||
StmtWire,
|
||||
Block, Id, Module, NameId, ScopedNameId, Stmt, StmtConnect, StmtIf, StmtMatch, StmtWire,
|
||||
},
|
||||
source_location::SourceLocation,
|
||||
ty::{CanonicalType, Type},
|
||||
|
|
@ -92,13 +91,12 @@ enum EnumTypeState {
|
|||
}
|
||||
|
||||
struct ModuleState {
|
||||
name_id_gen: NameIdGen,
|
||||
module_name: NameId,
|
||||
}
|
||||
|
||||
impl ModuleState {
|
||||
fn gen_name(&mut self, name: &str) -> ScopedNameId {
|
||||
ScopedNameId(self.module_name, self.name_id_gen.gen(name.intern()))
|
||||
ScopedNameId(self.module_name, NameId(name.intern(), Id::new()))
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -632,7 +630,6 @@ impl Folder for State {
|
|||
|
||||
fn fold_module<T: BundleType>(&mut self, v: Module<T>) -> Result<Module<T>, Self::Error> {
|
||||
self.module_state_stack.push(ModuleState {
|
||||
name_id_gen: NameIdGen::for_module(v.canonical()),
|
||||
module_name: v.name_id(),
|
||||
});
|
||||
let retval = Fold::default_fold(v, self);
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ use crate::{
|
|||
memory::{Mem, MemPort, PortType},
|
||||
module::{
|
||||
transform::visit::{Fold, Folder},
|
||||
Block, Module, NameId, NameIdGen, ScopedNameId, Stmt, StmtConnect, StmtWire,
|
||||
Block, Id, Module, NameId, ScopedNameId, Stmt, StmtConnect, StmtWire,
|
||||
},
|
||||
source_location::SourceLocation,
|
||||
ty::{CanonicalType, Type},
|
||||
|
|
@ -417,7 +417,6 @@ impl SplitMemState<'_, '_> {
|
|||
|
||||
struct ModuleState {
|
||||
output_module: Option<Interned<Module<Bundle>>>,
|
||||
name_id_gen: NameIdGen,
|
||||
memories: HashMap<ScopedNameId, MemState>,
|
||||
}
|
||||
|
||||
|
|
@ -626,10 +625,10 @@ impl ModuleState {
|
|||
mem_name_path: &str,
|
||||
split_state: &SplitState<'_>,
|
||||
) -> Mem {
|
||||
let mem_name = self.name_id_gen.gen(Intern::intern_owned(format!(
|
||||
"{}{mem_name_path}",
|
||||
input_mem.scoped_name().1 .0
|
||||
)));
|
||||
let mem_name = NameId(
|
||||
Intern::intern_owned(format!("{}{mem_name_path}", input_mem.scoped_name().1 .0)),
|
||||
Id::new(),
|
||||
);
|
||||
let mem_name = ScopedNameId(input_mem.scoped_name().0, mem_name);
|
||||
let output_element_type = match single_type {
|
||||
SingleType::UInt(ty) => ty.canonical(),
|
||||
|
|
@ -753,9 +752,10 @@ impl ModuleState {
|
|||
let port_ty = port.ty();
|
||||
let NameId(mem_name, _) = input_mem.scoped_name().1;
|
||||
let port_name = port.port_name();
|
||||
let wire_name = self
|
||||
.name_id_gen
|
||||
.gen(Intern::intern_owned(format!("{mem_name}_{port_name}")));
|
||||
let wire_name = NameId(
|
||||
Intern::intern_owned(format!("{mem_name}_{port_name}")),
|
||||
Id::new(),
|
||||
);
|
||||
let wire = Wire::new_unchecked(
|
||||
ScopedNameId(input_mem.scoped_name().0, wire_name),
|
||||
port.source_location(),
|
||||
|
|
@ -887,7 +887,6 @@ impl Folder for State {
|
|||
module,
|
||||
ModuleState {
|
||||
output_module: None,
|
||||
name_id_gen: NameIdGen::for_module(*module),
|
||||
memories: HashMap::new(),
|
||||
},
|
||||
);
|
||||
|
|
|
|||
|
|
@ -175,9 +175,9 @@ circuit check_array_repeat:
|
|||
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
|
||||
assert_export_firrtl! {
|
||||
m =>
|
||||
"/test/check_array_repeat_1.fir": r"FIRRTL version 3.2.0
|
||||
circuit check_array_repeat_1:
|
||||
module check_array_repeat_1: @[module-XXXXXXXXXX.rs 1:1]
|
||||
"/test/check_array_repeat.fir": r"FIRRTL version 3.2.0
|
||||
circuit check_array_repeat:
|
||||
module check_array_repeat: @[module-XXXXXXXXXX.rs 1:1]
|
||||
input i: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
|
||||
output o: UInt<8>[4] @[module-XXXXXXXXXX.rs 3:1]
|
||||
wire _array_literal_expr: UInt<8>[4]
|
||||
|
|
@ -1672,9 +1672,9 @@ fn test_memory_of_arrays() {
|
|||
circuit check_memory_of_arrays: %[[
|
||||
{
|
||||
"class": "firrtl.annotations.MemoryFileInlineAnnotation",
|
||||
"filename": "/test/check_memory_of_arrays/mem_1.mem",
|
||||
"filename": "/test/check_memory_of_arrays/mem.mem",
|
||||
"hexOrBinary": "h",
|
||||
"target": "~check_memory_of_arrays|check_memory_of_arrays>mem_1"
|
||||
"target": "~check_memory_of_arrays|check_memory_of_arrays>mem"
|
||||
}
|
||||
]]
|
||||
type Ty0 = {addr: UInt<4>, en: UInt<1>, clk: Clock, flip data: UInt<8>[2][3]}
|
||||
|
|
@ -1688,7 +1688,7 @@ circuit check_memory_of_arrays: %[[
|
|||
input wdata: UInt<8>[2][3] @[module-XXXXXXXXXX.rs 5:1]
|
||||
input wmask: UInt<1>[2][3] @[module-XXXXXXXXXX.rs 6:1]
|
||||
input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
|
||||
mem mem_1: @[module-XXXXXXXXXX.rs 8:1]
|
||||
mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
|
||||
data-type => UInt<8>[6]
|
||||
depth => 16
|
||||
read-latency => 0
|
||||
|
|
@ -1698,30 +1698,30 @@ circuit check_memory_of_arrays: %[[
|
|||
writer => w1
|
||||
wire mem_r0: Ty0 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire mem_w1: Ty1 @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_r0.data[0][0], mem_1.r0.data[0] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_r0.data[0][1], mem_1.r0.data[1] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_r0.data[1][0], mem_1.r0.data[2] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_r0.data[1][1], mem_1.r0.data[3] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_r0.data[2][0], mem_1.r0.data[4] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_r0.data[2][1], mem_1.r0.data[5] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_1.w1.data[0], mem_w1.data[0][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.mask[0], mem_w1.mask[0][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.data[1], mem_w1.data[0][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.mask[1], mem_w1.mask[0][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.data[2], mem_w1.data[1][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.mask[2], mem_w1.mask[1][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.data[3], mem_w1.data[1][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.mask[3], mem_w1.mask[1][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.data[4], mem_w1.data[2][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.mask[4], mem_w1.mask[2][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.data[5], mem_w1.data[2][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.mask[5], mem_w1.mask[2][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_r0.data[0][0], `mem`.r0.data[0] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_r0.data[0][1], `mem`.r0.data[1] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_r0.data[1][0], `mem`.r0.data[2] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_r0.data[1][1], `mem`.r0.data[3] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_r0.data[2][0], `mem`.r0.data[4] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_r0.data[2][1], `mem`.r0.data[5] @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect `mem`.w1.data[0], mem_w1.data[0][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.mask[0], mem_w1.mask[0][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.data[1], mem_w1.data[0][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.mask[1], mem_w1.mask[0][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.data[2], mem_w1.data[1][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.mask[2], mem_w1.mask[1][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.data[3], mem_w1.data[1][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.mask[3], mem_w1.mask[1][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.data[4], mem_w1.data[2][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.mask[4], mem_w1.mask[2][0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.data[5], mem_w1.data[2][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.mask[5], mem_w1.mask[2][1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
|
||||
connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
|
||||
connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
|
||||
|
|
@ -1732,7 +1732,7 @@ circuit check_memory_of_arrays: %[[
|
|||
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
|
||||
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
|
||||
"#,
|
||||
"/test/check_memory_of_arrays/mem_1.mem": r"000000000000
|
||||
"/test/check_memory_of_arrays/mem.mem": r"000000000000
|
||||
020103020101
|
||||
04080c080402
|
||||
061b1b120903
|
||||
|
|
@ -2445,9 +2445,9 @@ fn test_memory_of_enum() {
|
|||
circuit check_memory_of_enum: %[[
|
||||
{
|
||||
"class": "firrtl.annotations.MemoryFileInlineAnnotation",
|
||||
"filename": "/test/check_memory_of_enum/mem_1.mem",
|
||||
"filename": "/test/check_memory_of_enum/mem.mem",
|
||||
"hexOrBinary": "b",
|
||||
"target": "~check_memory_of_enum|check_memory_of_enum>mem_1"
|
||||
"target": "~check_memory_of_enum|check_memory_of_enum>mem"
|
||||
}
|
||||
]]
|
||||
type Ty0 = {|A, B: UInt<8>, C: UInt<1>[3]|}
|
||||
|
|
@ -2462,7 +2462,7 @@ circuit check_memory_of_enum: %[[
|
|||
input wdata: Ty0 @[module-XXXXXXXXXX.rs 5:1]
|
||||
input wmask: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
|
||||
input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
|
||||
mem mem_1: @[module-XXXXXXXXXX.rs 8:1]
|
||||
mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
|
||||
data-type => UInt<10>
|
||||
depth => 16
|
||||
read-latency => 0
|
||||
|
|
@ -2474,10 +2474,10 @@ circuit check_memory_of_enum: %[[
|
|||
wire mem_w1: Ty2 @[module-XXXXXXXXXX.rs 14:1]
|
||||
wire _cast_bits_to_enum_expr: Ty0
|
||||
wire _cast_bits_to_enum_expr_body: UInt<8>
|
||||
connect _cast_bits_to_enum_expr_body, head(mem_1.r0.data, 8)
|
||||
when eq(UInt<2>(0), tail(mem_1.r0.data, 8)):
|
||||
connect _cast_bits_to_enum_expr_body, head(`mem`.r0.data, 8)
|
||||
when eq(UInt<2>(0), tail(`mem`.r0.data, 8)):
|
||||
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
|
||||
else when eq(UInt<2>(1), tail(mem_1.r0.data, 8)):
|
||||
else when eq(UInt<2>(1), tail(`mem`.r0.data, 8)):
|
||||
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body)
|
||||
else:
|
||||
wire _cast_bits_to_array_expr: UInt<1>[3]
|
||||
|
|
@ -2504,14 +2504,14 @@ circuit check_memory_of_enum: %[[
|
|||
wire _cast_to_bits_expr: UInt<3>
|
||||
connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
|
||||
connect _cast_enum_to_bits_expr, pad(cat(_cast_to_bits_expr, UInt<2>(2)), 10)
|
||||
connect mem_1.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.mask, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.mask, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
; connect different types:
|
||||
; lhs: UInt<4>
|
||||
; rhs: UInt<8>
|
||||
|
|
@ -2528,7 +2528,7 @@ circuit check_memory_of_enum: %[[
|
|||
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
|
||||
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
|
||||
"#,
|
||||
"/test/check_memory_of_enum/mem_1.mem": r"0000000000
|
||||
"/test/check_memory_of_enum/mem.mem": r"0000000000
|
||||
0000000110
|
||||
0000001010
|
||||
0000010010
|
||||
|
|
@ -2602,7 +2602,7 @@ circuit check_memory_of_enum: %[[
|
|||
reader => r0
|
||||
writer => w1
|
||||
wire mem_r0: Ty2 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire mem_w1_1: Ty4 @[module-XXXXXXXXXX.rs 14:1]
|
||||
wire mem_w1: Ty4 @[module-XXXXXXXXXX.rs 14:1]
|
||||
wire _cast_bits_to_enum_expr: Ty0
|
||||
when eq(UInt<2>(0), tail(mem_tag.r0.data, 0)):
|
||||
connect _cast_bits_to_enum_expr, {|A, B, C|}(A)
|
||||
|
|
@ -2612,7 +2612,7 @@ circuit check_memory_of_enum: %[[
|
|||
connect _cast_bits_to_enum_expr, {|A, B, C|}(C)
|
||||
connect mem_r0.data.tag, _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_enum_to_bits_expr: UInt<2>
|
||||
match mem_w1_1.data.tag:
|
||||
match mem_w1.data.tag:
|
||||
A:
|
||||
connect _cast_enum_to_bits_expr, UInt<2>(0)
|
||||
B:
|
||||
|
|
@ -2620,29 +2620,29 @@ circuit check_memory_of_enum: %[[
|
|||
C:
|
||||
connect _cast_enum_to_bits_expr, UInt<2>(2)
|
||||
connect mem_tag.w1.data, _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.mask, mem_w1_1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.mask, mem_w1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_tag.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_r0.data.body, mem_body.r0.data @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_body.w1.data, mem_w1_1.data.body @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.mask, mem_w1_1.mask.body @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.data, mem_w1.data.body @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.mask, mem_w1.mask.body @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_body.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
wire mem_w1: Ty9 @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
wire mem_w1_1: Ty9 @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.data, mem_w1_1.data @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.mask.tag, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.mask.body, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
|
||||
; connect different types:
|
||||
; lhs: UInt<4>
|
||||
; rhs: UInt<8>
|
||||
|
|
@ -2653,11 +2653,11 @@ circuit check_memory_of_enum: %[[
|
|||
; connect different types:
|
||||
; lhs: UInt<4>
|
||||
; rhs: UInt<8>
|
||||
connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
|
||||
connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
|
||||
connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
|
||||
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
|
||||
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
|
||||
connect mem_w1_1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
|
||||
connect mem_w1_1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
|
||||
connect mem_w1_1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
|
||||
connect mem_w1_1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
|
||||
connect mem_w1_1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
|
||||
"#,
|
||||
"/test/check_memory_of_enum/mem_body.mem": r"00
|
||||
01
|
||||
|
|
@ -2748,32 +2748,32 @@ circuit check_memory_of_enum: %[[
|
|||
reader => r0
|
||||
writer => w1
|
||||
wire mem_r0: Ty1 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire mem_w1_1: Ty3 @[module-XXXXXXXXXX.rs 14:1]
|
||||
wire mem_w1: Ty3 @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_r0.data.tag, mem_tag.r0.data @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_tag.w1.data, mem_w1_1.data.tag @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.mask, mem_w1_1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.data, mem_w1.data.tag @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.mask, mem_w1.mask.tag @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_tag.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_tag.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_tag.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_tag.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_r0.data.body, mem_body.r0.data @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_body.w1.data, mem_w1_1.data.body @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.mask, mem_w1_1.mask.body @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.data, mem_w1.data.body @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.mask, mem_w1.mask.body @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_body.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_body.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_body.w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
wire mem_w1: Ty8 @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.data, mem_w1.data @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.mask.tag, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1_1.mask.body, mem_w1.mask @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_body.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
wire mem_w1_1: Ty8 @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.addr, mem_w1_1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.en, mem_w1_1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.clk, mem_w1_1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.data, mem_w1_1.data @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.mask.tag, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_w1.mask.body, mem_w1_1.mask @[module-XXXXXXXXXX.rs 14:1]
|
||||
; connect different types:
|
||||
; lhs: UInt<4>
|
||||
; rhs: UInt<8>
|
||||
|
|
@ -2784,11 +2784,11 @@ circuit check_memory_of_enum: %[[
|
|||
; connect different types:
|
||||
; lhs: UInt<4>
|
||||
; rhs: UInt<8>
|
||||
connect mem_w1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
|
||||
connect mem_w1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
|
||||
connect mem_w1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
|
||||
connect mem_w1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
|
||||
connect mem_w1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
|
||||
connect mem_w1_1.addr, waddr @[module-XXXXXXXXXX.rs 15:1]
|
||||
connect mem_w1_1.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 16:1]
|
||||
connect mem_w1_1.clk, clk @[module-XXXXXXXXXX.rs 17:1]
|
||||
connect mem_w1_1.data, wdata @[module-XXXXXXXXXX.rs 18:1]
|
||||
connect mem_w1_1.mask, wmask @[module-XXXXXXXXXX.rs 19:1]
|
||||
"#,
|
||||
"/test/check_memory_of_enum/mem_body.mem": r"00
|
||||
01
|
||||
|
|
@ -2950,7 +2950,7 @@ circuit check_memory_of_array_of_enum:
|
|||
input wdata: Ty0[2] @[module-XXXXXXXXXX.rs 5:1]
|
||||
input wmask: UInt<1>[2] @[module-XXXXXXXXXX.rs 6:1]
|
||||
input clk: Clock @[module-XXXXXXXXXX.rs 7:1]
|
||||
mem mem_1: @[module-XXXXXXXXXX.rs 8:1]
|
||||
mem `mem`: @[module-XXXXXXXXXX.rs 8:1]
|
||||
data-type => UInt<10>[2]
|
||||
depth => 256
|
||||
read-latency => 0
|
||||
|
|
@ -2962,10 +2962,10 @@ circuit check_memory_of_array_of_enum:
|
|||
wire mem_w1: Ty2 @[module-XXXXXXXXXX.rs 14:1]
|
||||
wire _cast_bits_to_enum_expr: Ty0
|
||||
wire _cast_bits_to_enum_expr_body: UInt<8>
|
||||
connect _cast_bits_to_enum_expr_body, head(mem_1.r0.data[0], 8)
|
||||
when eq(UInt<2>(0), tail(mem_1.r0.data[0], 8)):
|
||||
connect _cast_bits_to_enum_expr_body, head(`mem`.r0.data[0], 8)
|
||||
when eq(UInt<2>(0), tail(`mem`.r0.data[0], 8)):
|
||||
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
|
||||
else when eq(UInt<2>(1), tail(mem_1.r0.data[0], 8)):
|
||||
else when eq(UInt<2>(1), tail(`mem`.r0.data[0], 8)):
|
||||
connect _cast_bits_to_enum_expr, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body)
|
||||
else:
|
||||
wire _cast_bits_to_array_expr: UInt<1>[3]
|
||||
|
|
@ -2980,10 +2980,10 @@ circuit check_memory_of_array_of_enum:
|
|||
connect mem_r0.data[0], _cast_bits_to_enum_expr @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_enum_expr_1: Ty0
|
||||
wire _cast_bits_to_enum_expr_body_1: UInt<8>
|
||||
connect _cast_bits_to_enum_expr_body_1, head(mem_1.r0.data[1], 8)
|
||||
when eq(UInt<2>(0), tail(mem_1.r0.data[1], 8)):
|
||||
connect _cast_bits_to_enum_expr_body_1, head(`mem`.r0.data[1], 8)
|
||||
when eq(UInt<2>(0), tail(`mem`.r0.data[1], 8)):
|
||||
connect _cast_bits_to_enum_expr_1, {|A, B: UInt<8>, C: UInt<1>[3]|}(A)
|
||||
else when eq(UInt<2>(1), tail(mem_1.r0.data[1], 8)):
|
||||
else when eq(UInt<2>(1), tail(`mem`.r0.data[1], 8)):
|
||||
connect _cast_bits_to_enum_expr_1, {|A, B: UInt<8>, C: UInt<1>[3]|}(B, _cast_bits_to_enum_expr_body_1)
|
||||
else:
|
||||
wire _cast_bits_to_array_expr_1: UInt<1>[3]
|
||||
|
|
@ -3010,8 +3010,8 @@ circuit check_memory_of_array_of_enum:
|
|||
wire _cast_to_bits_expr: UInt<3>
|
||||
connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
|
||||
connect _cast_enum_to_bits_expr, pad(cat(_cast_to_bits_expr, UInt<2>(2)), 10)
|
||||
connect mem_1.w1.data[0], _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.mask[0], mem_w1.mask[0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.data[0], _cast_enum_to_bits_expr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.mask[0], mem_w1.mask[0] @[module-XXXXXXXXXX.rs 14:1]
|
||||
wire _cast_enum_to_bits_expr_1: UInt<10>
|
||||
match mem_w1.data[1]:
|
||||
A:
|
||||
|
|
@ -3026,14 +3026,14 @@ circuit check_memory_of_array_of_enum:
|
|||
wire _cast_to_bits_expr_1: UInt<3>
|
||||
connect _cast_to_bits_expr_1, cat(_cast_array_to_bits_expr_1[2], cat(_cast_array_to_bits_expr_1[1], _cast_array_to_bits_expr_1[0]))
|
||||
connect _cast_enum_to_bits_expr_1, pad(cat(_cast_to_bits_expr_1, UInt<2>(2)), 10)
|
||||
connect mem_1.w1.data[1], _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.mask[1], mem_w1.mask[1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_1.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_1.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect mem_1.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_1.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.data[1], _cast_enum_to_bits_expr_1 @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.mask[1], mem_w1.mask[1] @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.r0.addr, mem_r0.addr @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect `mem`.r0.clk, mem_r0.clk @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect `mem`.r0.en, mem_r0.en @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect `mem`.w1.addr, mem_w1.addr @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.clk, mem_w1.clk @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect `mem`.w1.en, mem_w1.en @[module-XXXXXXXXXX.rs 14:1]
|
||||
connect mem_r0.addr, raddr @[module-XXXXXXXXXX.rs 10:1]
|
||||
connect mem_r0.en, UInt<1>(0h1) @[module-XXXXXXXXXX.rs 11:1]
|
||||
connect mem_r0.clk, clk @[module-XXXXXXXXXX.rs 12:1]
|
||||
|
|
@ -3344,11 +3344,11 @@ circuit check_uninit:
|
|||
simplify_enums: None,
|
||||
..ExportOptions::default()
|
||||
},
|
||||
"/test/check_uninit_1.fir": r"FIRRTL version 3.2.0
|
||||
circuit check_uninit_1:
|
||||
"/test/check_uninit.fir": r"FIRRTL version 3.2.0
|
||||
circuit check_uninit:
|
||||
type Ty0 = {}
|
||||
type Ty1 = {|HdlNone, HdlSome: Ty0|}
|
||||
module check_uninit_1: @[module-XXXXXXXXXX.rs 1:1]
|
||||
module check_uninit: @[module-XXXXXXXXXX.rs 1:1]
|
||||
output o: Ty1[3] @[module-XXXXXXXXXX.rs 2:1]
|
||||
wire _uninit_expr: Ty1[3]
|
||||
invalidate _uninit_expr
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
"$kind": "Struct",
|
||||
"$constructor": "ModuleIO::new_unchecked",
|
||||
"containing_module_name_id()": "Visible",
|
||||
"name()": "Visible",
|
||||
"name_id()": "Visible",
|
||||
"source_location()": "Visible",
|
||||
"is_input()": "Visible",
|
||||
"ty()": "Visible"
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue