forked from libre-chip/fayalite
fix simplify_enums to properly handle nested enums and connects with different types
This commit is contained in:
parent
1e2831da47
commit
30a38bc8da
SSH key fingerprint:
SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
2 changed files with 1028 additions and 250 deletions
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@ -514,7 +514,6 @@ circuit check_enum_literals:
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type Ty1 = {tag: Ty0, body: UInt<8>}
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type Ty2 = {|A, B, C|}
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type Ty3 = {tag: Ty2, body: UInt<8>}
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type Ty4 = {tag: Ty2, body: UInt<3>}
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module check_enum_literals: @[module-XXXXXXXXXX.rs 1:1]
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input i: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
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output o: Ty1 @[module-XXXXXXXXXX.rs 3:1]
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@ -534,7 +533,7 @@ circuit check_enum_literals:
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connect _bundle_literal_expr_2.body, i
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connect o2, _bundle_literal_expr_2 @[module-XXXXXXXXXX.rs 9:1]
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else:
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wire _bundle_literal_expr_3: Ty4
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wire _bundle_literal_expr_3: Ty3
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connect _bundle_literal_expr_3.tag, {|A, B, C|}(C)
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wire _array_literal_expr: UInt<1>[3]
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connect _array_literal_expr[0], bits(i, 0, 0)
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@ -546,7 +545,7 @@ circuit check_enum_literals:
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connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
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wire _cast_to_bits_expr: UInt<3>
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connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
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connect _bundle_literal_expr_3.body, _cast_to_bits_expr
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connect _bundle_literal_expr_3.body, pad(_cast_to_bits_expr, 8)
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connect o2, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 10:1]
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",
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};
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@ -559,7 +558,6 @@ circuit check_enum_literals:
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circuit check_enum_literals:
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type Ty0 = {tag: UInt<1>, body: UInt<8>}
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type Ty1 = {tag: UInt<2>, body: UInt<8>}
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type Ty2 = {tag: UInt<2>, body: UInt<3>}
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module check_enum_literals: @[module-XXXXXXXXXX.rs 1:1]
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input i: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
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output o: Ty0 @[module-XXXXXXXXXX.rs 3:1]
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@ -579,7 +577,7 @@ circuit check_enum_literals:
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connect _bundle_literal_expr_2.body, i
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connect o2, _bundle_literal_expr_2 @[module-XXXXXXXXXX.rs 9:1]
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else:
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wire _bundle_literal_expr_3: Ty2
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wire _bundle_literal_expr_3: Ty1
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connect _bundle_literal_expr_3.tag, UInt<2>(0h2)
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wire _array_literal_expr: UInt<1>[3]
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connect _array_literal_expr[0], bits(i, 0, 0)
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@ -591,7 +589,7 @@ circuit check_enum_literals:
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connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
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wire _cast_to_bits_expr: UInt<3>
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connect _cast_to_bits_expr, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
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connect _bundle_literal_expr_3.body, _cast_to_bits_expr
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connect _bundle_literal_expr_3.body, pad(_cast_to_bits_expr, 8)
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connect o2, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 10:1]
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",
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};
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@ -604,7 +602,6 @@ circuit check_enum_literals:
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circuit check_enum_literals:
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type Ty0 = {tag: UInt<1>, body: UInt<8>}
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type Ty1 = {tag: UInt<2>, body: UInt<8>}
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type Ty2 = {tag: UInt<2>, body: UInt<3>}
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module check_enum_literals: @[module-XXXXXXXXXX.rs 1:1]
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input i: UInt<8> @[module-XXXXXXXXXX.rs 2:1]
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output o: UInt<9> @[module-XXXXXXXXXX.rs 3:1]
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@ -639,7 +636,7 @@ circuit check_enum_literals:
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connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.body, _cast_bundle_to_bits_expr_2.tag)
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connect o2, _cast_to_bits_expr_2 @[module-XXXXXXXXXX.rs 9:1]
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else:
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wire _bundle_literal_expr_3: Ty2
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wire _bundle_literal_expr_3: Ty1
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connect _bundle_literal_expr_3.tag, UInt<2>(0h2)
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wire _array_literal_expr: UInt<1>[3]
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connect _array_literal_expr[0], bits(i, 0, 0)
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@ -651,11 +648,11 @@ circuit check_enum_literals:
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connect _cast_array_to_bits_expr[2], _array_literal_expr[2]
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wire _cast_to_bits_expr_3: UInt<3>
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connect _cast_to_bits_expr_3, cat(_cast_array_to_bits_expr[2], cat(_cast_array_to_bits_expr[1], _cast_array_to_bits_expr[0]))
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connect _bundle_literal_expr_3.body, _cast_to_bits_expr_3
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wire _cast_bundle_to_bits_expr_3: Ty2
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connect _bundle_literal_expr_3.body, pad(_cast_to_bits_expr_3, 8)
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wire _cast_bundle_to_bits_expr_3: Ty1
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connect _cast_bundle_to_bits_expr_3.tag, _bundle_literal_expr_3.tag
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connect _cast_bundle_to_bits_expr_3.body, _bundle_literal_expr_3.body
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wire _cast_to_bits_expr_4: UInt<5>
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wire _cast_to_bits_expr_4: UInt<10>
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connect _cast_to_bits_expr_4, cat(_cast_bundle_to_bits_expr_3.body, _cast_bundle_to_bits_expr_3.tag)
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connect o2, _cast_to_bits_expr_4 @[module-XXXXXXXXXX.rs 10:1]
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",
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@ -3245,48 +3242,25 @@ pub enum OneOfThree<A, B, C> {
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#[hdl_module(outline_generated)]
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pub fn check_enum_connect_any() {
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#[hdl]
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let index: UInt<2> = m.input();
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let swap: Bool = m.input();
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#[hdl]
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let i0: OneOfThree<UInt<0>, HdlOption<SInt<0>>, Bool> = m.input();
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let i1: OneOfThree<UInt<1>, HdlOption<SInt<1>>, HdlOption<()>> = m.input();
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#[hdl]
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let i1: OneOfThree<UInt<1>, HdlOption<SInt<1>>, Bool> = m.input();
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let i2: OneOfThree<UInt<2>, HdlOption<SInt<2>>, HdlOption<()>> = m.input();
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#[hdl]
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let i2: OneOfThree<UInt<2>, HdlOption<SInt<2>>, Bool> = m.input();
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let o1: OneOfThree<UInt<1>, HdlOption<SInt<1>>, HdlOption<()>> = m.output();
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#[hdl]
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let i3: OneOfThree<UInt<3>, HdlOption<SInt<3>>, Bool> = m.input();
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let o2: OneOfThree<UInt<2>, HdlOption<SInt<2>>, HdlOption<()>> = m.output();
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#[hdl]
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let o0: OneOfThree<UInt<0>, HdlOption<SInt<0>>, Bool> = m.output();
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#[hdl]
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let o1: OneOfThree<UInt<1>, HdlOption<SInt<1>>, Bool> = m.output();
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#[hdl]
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let o2: OneOfThree<UInt<2>, HdlOption<SInt<2>>, Bool> = m.output();
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#[hdl]
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let o3: OneOfThree<UInt<3>, HdlOption<SInt<3>>, Bool> = m.output();
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#[hdl]
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if index.cmp_eq(0u8) {
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connect_any(o0, i0);
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if swap {
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connect_any(o1, i2);
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connect_any(o2, i1);
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} else {
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connect_any(o1, i1);
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connect_any(o2, i2);
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connect_any(o3, i3);
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} else if index.cmp_eq(1u8) {
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connect_any(o0, i1);
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connect_any(o1, i2);
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connect_any(o2, i3);
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connect_any(o3, i0);
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} else if index.cmp_eq(2u8) {
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connect_any(o0, i2);
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connect_any(o1, i3);
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connect_any(o2, i0);
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connect_any(o3, i1);
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} else {
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connect_any(o0, i3);
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connect_any(o1, i0);
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connect_any(o2, i1);
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connect_any(o3, i2);
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}
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}
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#[cfg(todo)]
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#[test]
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fn test_enum_connect_any() {
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let _n = SourceLocation::normalize_files_for_tests();
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@ -3297,44 +3271,24 @@ fn test_enum_connect_any() {
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m =>
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"/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
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circuit check_enum_connect_any:
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type Ty0 = {|HdlNone, HdlSome: SInt<0>|}
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type Ty1 = {|A: UInt<0>, B: Ty0, C: UInt<1>|}
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type Ty2 = {|HdlNone, HdlSome: SInt<1>|}
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type Ty3 = {|A: UInt<1>, B: Ty2, C: UInt<1>|}
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type Ty0 = {|HdlNone, HdlSome: SInt<1>|}
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type Ty1 = {}
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type Ty2 = {|HdlNone, HdlSome: Ty1|}
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type Ty3 = {|A: UInt<1>, B: Ty0, C: Ty2|}
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type Ty4 = {|HdlNone, HdlSome: SInt<2>|}
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type Ty5 = {|A: UInt<2>, B: Ty4, C: UInt<1>|}
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type Ty6 = {|HdlNone, HdlSome: SInt<3>|}
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type Ty7 = {|A: UInt<3>, B: Ty6, C: UInt<1>|}
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type Ty5 = {|A: UInt<2>, B: Ty4, C: Ty2|}
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module check_enum_connect_any: @[module-XXXXXXXXXX.rs 1:1]
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input index: UInt<2> @[module-XXXXXXXXXX.rs 2:1]
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input i0: Ty1 @[module-XXXXXXXXXX.rs 3:1]
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input i1: Ty3 @[module-XXXXXXXXXX.rs 4:1]
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input i2: Ty5 @[module-XXXXXXXXXX.rs 5:1]
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input i3: Ty7 @[module-XXXXXXXXXX.rs 6:1]
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output o0: Ty1 @[module-XXXXXXXXXX.rs 7:1]
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output o1: Ty3 @[module-XXXXXXXXXX.rs 8:1]
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output o2: Ty5 @[module-XXXXXXXXXX.rs 9:1]
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output o3: Ty7 @[module-XXXXXXXXXX.rs 10:1]
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when eq(index, UInt<8>(0h0)): @[module-XXXXXXXXXX.rs 11:1]
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connect o0, i0 @[module-XXXXXXXXXX.rs 12:1]
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connect o1, i1 @[module-XXXXXXXXXX.rs 13:1]
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connect o2, i2 @[module-XXXXXXXXXX.rs 14:1]
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connect o3, i3 @[module-XXXXXXXXXX.rs 15:1]
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else when eq(index, UInt<8>(0h1)): @[module-XXXXXXXXXX.rs 16:1]
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connect o0, i1 @[module-XXXXXXXXXX.rs 17:1]
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connect o1, i2 @[module-XXXXXXXXXX.rs 18:1]
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connect o2, i3 @[module-XXXXXXXXXX.rs 19:1]
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connect o3, i0 @[module-XXXXXXXXXX.rs 20:1]
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else when eq(index, UInt<8>(0h2)): @[module-XXXXXXXXXX.rs 21:1]
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connect o0, i2 @[module-XXXXXXXXXX.rs 22:1]
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connect o1, i3 @[module-XXXXXXXXXX.rs 23:1]
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connect o2, i0 @[module-XXXXXXXXXX.rs 24:1]
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connect o3, i1 @[module-XXXXXXXXXX.rs 25:1]
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input swap: UInt<1> @[module-XXXXXXXXXX.rs 2:1]
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input i1: Ty3 @[module-XXXXXXXXXX.rs 3:1]
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input i2: Ty5 @[module-XXXXXXXXXX.rs 4:1]
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output o1: Ty3 @[module-XXXXXXXXXX.rs 5:1]
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output o2: Ty5 @[module-XXXXXXXXXX.rs 6:1]
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when swap: @[module-XXXXXXXXXX.rs 7:1]
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connect o1, i2 @[module-XXXXXXXXXX.rs 8:1]
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connect o2, i1 @[module-XXXXXXXXXX.rs 9:1]
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else:
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connect o0, i3 @[module-XXXXXXXXXX.rs 26:1]
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connect o1, i0 @[module-XXXXXXXXXX.rs 27:1]
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connect o2, i1 @[module-XXXXXXXXXX.rs 28:1]
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connect o3, i2 @[module-XXXXXXXXXX.rs 29:1]
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connect o1, i1 @[module-XXXXXXXXXX.rs 10:1]
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connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
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",
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};
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// FIXME: simplify_enums is broken when connecting enums that contain
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@ -3347,20 +3301,487 @@ circuit check_enum_connect_any:
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#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
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assert_export_firrtl! {
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m =>
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"/test/check_enum_connect_any.fir": r"TODO",
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"/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
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circuit check_enum_connect_any:
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type Ty0 = {|A, B, C|}
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type Ty1 = {tag: Ty0, body: UInt<2>}
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type Ty2 = {tag: Ty0, body: UInt<3>}
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type Ty3 = {|HdlNone, HdlSome|}
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type Ty4 = {tag: Ty3, body: UInt<1>}
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type Ty5 = {tag: Ty3, body: UInt<2>}
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type Ty6 = {tag: UInt<1>, body: UInt<2>}
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type Ty7 = {tag: UInt<1>, body: UInt<1>}
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type Ty8 = {tag: Ty3, body: UInt<0>}
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type Ty9 = {tag: UInt<1>, body: UInt<0>}
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module check_enum_connect_any: @[module-XXXXXXXXXX.rs 1:1]
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input swap: UInt<1> @[module-XXXXXXXXXX.rs 2:1]
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input i1: Ty1 @[module-XXXXXXXXXX.rs 3:1]
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input i2: Ty2 @[module-XXXXXXXXXX.rs 4:1]
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output o1: Ty1 @[module-XXXXXXXXXX.rs 5:1]
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output o2: Ty2 @[module-XXXXXXXXXX.rs 6:1]
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when swap: @[module-XXXXXXXXXX.rs 7:1]
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match i2.tag: @[module-XXXXXXXXXX.rs 8:1]
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A:
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wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
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connect __connect_variant_body, bits(i2.body, 1, 0) @[module-XXXXXXXXXX.rs 8:1]
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wire _bundle_literal_expr: Ty1
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connect _bundle_literal_expr.tag, {|A, B, C|}(A)
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connect _bundle_literal_expr.body, pad(__connect_variant_body, 2)
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connect o1, _bundle_literal_expr @[module-XXXXXXXXXX.rs 8:1]
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B:
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wire __connect_variant_body_1: Ty4 @[module-XXXXXXXXXX.rs 8:1]
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wire _cast_bits_to_bundle_expr: Ty5
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wire _cast_bits_to_bundle_expr_flattened: Ty6
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connect _cast_bits_to_bundle_expr_flattened.tag, bits(bits(i2.body, 2, 0), 0, 0)
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wire _cast_bits_to_enum_expr: Ty3
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when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened.tag, 0)):
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connect _cast_bits_to_enum_expr, {|HdlNone, HdlSome|}(HdlNone)
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else:
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connect _cast_bits_to_enum_expr, {|HdlNone, HdlSome|}(HdlSome)
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connect _cast_bits_to_bundle_expr.tag, _cast_bits_to_enum_expr
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connect _cast_bits_to_bundle_expr_flattened.body, bits(bits(i2.body, 2, 0), 2, 1)
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connect _cast_bits_to_bundle_expr.body, _cast_bits_to_bundle_expr_flattened.body
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match _cast_bits_to_bundle_expr.tag: @[module-XXXXXXXXXX.rs 8:1]
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HdlNone:
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wire _bundle_literal_expr_1: Ty4
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connect _bundle_literal_expr_1.tag, {|HdlNone, HdlSome|}(HdlNone)
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connect _bundle_literal_expr_1.body, UInt<1>(0h0)
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connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1]
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HdlSome:
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wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
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wire _cast_bits_to_bundle_expr_1: Ty5
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wire _cast_bits_to_bundle_expr_flattened_1: Ty6
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connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0)
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wire _cast_bits_to_enum_expr_1: Ty3
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when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_1.tag, 0)):
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connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlNone)
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else:
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connect _cast_bits_to_enum_expr_1, {|HdlNone, HdlSome|}(HdlSome)
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connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_enum_expr_1
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connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
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connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
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connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
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wire _bundle_literal_expr_2: Ty4
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connect _bundle_literal_expr_2.tag, {|HdlNone, HdlSome|}(HdlSome)
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connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
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connect __connect_variant_body_1, _bundle_literal_expr_2 @[module-XXXXXXXXXX.rs 8:1]
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wire _bundle_literal_expr_3: Ty1
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connect _bundle_literal_expr_3.tag, {|A, B, C|}(B)
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wire _cast_bundle_to_bits_expr: Ty7
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wire _cast_enum_to_bits_expr: UInt<1>
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match __connect_variant_body_1.tag:
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HdlNone:
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connect _cast_enum_to_bits_expr, UInt<1>(0)
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HdlSome:
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connect _cast_enum_to_bits_expr, UInt<1>(1)
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connect _cast_bundle_to_bits_expr.tag, _cast_enum_to_bits_expr
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connect _cast_bundle_to_bits_expr.body, __connect_variant_body_1.body
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wire _cast_to_bits_expr: UInt<2>
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connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.body, _cast_bundle_to_bits_expr.tag)
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connect _bundle_literal_expr_3.body, _cast_to_bits_expr
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connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1]
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C:
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wire __connect_variant_body_3: Ty8 @[module-XXXXXXXXXX.rs 8:1]
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wire _cast_bits_to_bundle_expr_2: Ty8
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wire _cast_bits_to_bundle_expr_flattened_2: Ty9
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connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0)
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wire _cast_bits_to_enum_expr_2: Ty3
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when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_2.tag, 0)):
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connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlNone)
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else:
|
||||
connect _cast_bits_to_enum_expr_2, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_enum_expr_2
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
|
||||
connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_4: Ty1
|
||||
connect _bundle_literal_expr_4.tag, {|A, B, C|}(C)
|
||||
wire _cast_bundle_to_bits_expr_1: Ty9
|
||||
wire _cast_enum_to_bits_expr_1: UInt<1>
|
||||
match __connect_variant_body_3.tag:
|
||||
HdlNone:
|
||||
connect _cast_enum_to_bits_expr_1, UInt<1>(0)
|
||||
HdlSome:
|
||||
connect _cast_enum_to_bits_expr_1, UInt<1>(1)
|
||||
connect _cast_bundle_to_bits_expr_1.tag, _cast_enum_to_bits_expr_1
|
||||
connect _cast_bundle_to_bits_expr_1.body, __connect_variant_body_3.body
|
||||
wire _cast_to_bits_expr_1: UInt<1>
|
||||
connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.body, _cast_bundle_to_bits_expr_1.tag)
|
||||
connect _bundle_literal_expr_4.body, pad(_cast_to_bits_expr_1, 2)
|
||||
connect o1, _bundle_literal_expr_4 @[module-XXXXXXXXXX.rs 8:1]
|
||||
match i1.tag: @[module-XXXXXXXXXX.rs 9:1]
|
||||
A:
|
||||
wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect __connect_variant_body_4, bits(i1.body, 0, 0) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_5: Ty2
|
||||
connect _bundle_literal_expr_5.tag, {|A, B, C|}(A)
|
||||
connect _bundle_literal_expr_5.body, pad(__connect_variant_body_4, 3)
|
||||
connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
B:
|
||||
wire __connect_variant_body_5: Ty5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_3: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_3: Ty7
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_3: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_3.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlNone)
|
||||
else:
|
||||
connect _cast_bits_to_enum_expr_3, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_enum_expr_3
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
|
||||
match _cast_bits_to_bundle_expr_3.tag: @[module-XXXXXXXXXX.rs 9:1]
|
||||
HdlNone:
|
||||
wire _bundle_literal_expr_6: Ty5
|
||||
connect _bundle_literal_expr_6.tag, {|HdlNone, HdlSome|}(HdlNone)
|
||||
connect _bundle_literal_expr_6.body, UInt<2>(0h0)
|
||||
connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1]
|
||||
HdlSome:
|
||||
wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_4: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_4: Ty7
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_4: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_4.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlNone)
|
||||
else:
|
||||
connect _cast_bits_to_enum_expr_4, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_enum_expr_4
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
|
||||
connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_7: Ty5
|
||||
connect _bundle_literal_expr_7.tag, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
|
||||
connect __connect_variant_body_5, _bundle_literal_expr_7 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_8: Ty2
|
||||
connect _bundle_literal_expr_8.tag, {|A, B, C|}(B)
|
||||
wire _cast_bundle_to_bits_expr_2: Ty6
|
||||
wire _cast_enum_to_bits_expr_2: UInt<1>
|
||||
match __connect_variant_body_5.tag:
|
||||
HdlNone:
|
||||
connect _cast_enum_to_bits_expr_2, UInt<1>(0)
|
||||
HdlSome:
|
||||
connect _cast_enum_to_bits_expr_2, UInt<1>(1)
|
||||
connect _cast_bundle_to_bits_expr_2.tag, _cast_enum_to_bits_expr_2
|
||||
connect _cast_bundle_to_bits_expr_2.body, __connect_variant_body_5.body
|
||||
wire _cast_to_bits_expr_2: UInt<3>
|
||||
connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.body, _cast_bundle_to_bits_expr_2.tag)
|
||||
connect _bundle_literal_expr_8.body, _cast_to_bits_expr_2
|
||||
connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1]
|
||||
C:
|
||||
wire __connect_variant_body_7: Ty8 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_5: Ty8
|
||||
wire _cast_bits_to_bundle_expr_flattened_5: Ty9
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0)
|
||||
wire _cast_bits_to_enum_expr_5: Ty3
|
||||
when eq(UInt<1>(0), tail(_cast_bits_to_bundle_expr_flattened_5.tag, 0)):
|
||||
connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlNone)
|
||||
else:
|
||||
connect _cast_bits_to_enum_expr_5, {|HdlNone, HdlSome|}(HdlSome)
|
||||
connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_enum_expr_5
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body
|
||||
connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_9: Ty2
|
||||
connect _bundle_literal_expr_9.tag, {|A, B, C|}(C)
|
||||
wire _cast_bundle_to_bits_expr_3: Ty9
|
||||
wire _cast_enum_to_bits_expr_3: UInt<1>
|
||||
match __connect_variant_body_7.tag:
|
||||
HdlNone:
|
||||
connect _cast_enum_to_bits_expr_3, UInt<1>(0)
|
||||
HdlSome:
|
||||
connect _cast_enum_to_bits_expr_3, UInt<1>(1)
|
||||
connect _cast_bundle_to_bits_expr_3.tag, _cast_enum_to_bits_expr_3
|
||||
connect _cast_bundle_to_bits_expr_3.body, __connect_variant_body_7.body
|
||||
wire _cast_to_bits_expr_3: UInt<1>
|
||||
connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.body, _cast_bundle_to_bits_expr_3.tag)
|
||||
connect _bundle_literal_expr_9.body, pad(_cast_to_bits_expr_3, 3)
|
||||
connect o2, _bundle_literal_expr_9 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
connect o1, i1 @[module-XXXXXXXXXX.rs 10:1]
|
||||
connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
|
||||
",
|
||||
};
|
||||
let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithBundleOfUInts).unwrap();
|
||||
dbg!(m);
|
||||
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
|
||||
assert_export_firrtl! {
|
||||
m =>
|
||||
"/test/check_enum_connect_any.fir": r"TODO",
|
||||
};
|
||||
"/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
|
||||
circuit check_enum_connect_any:
|
||||
type Ty0 = {tag: UInt<2>, body: UInt<2>}
|
||||
type Ty1 = {tag: UInt<2>, body: UInt<3>}
|
||||
type Ty2 = {tag: UInt<1>, body: UInt<1>}
|
||||
type Ty3 = {tag: UInt<1>, body: UInt<2>}
|
||||
type Ty4 = {tag: UInt<1>, body: UInt<0>}
|
||||
module check_enum_connect_any: @[module-XXXXXXXXXX.rs 1:1]
|
||||
input swap: UInt<1> @[module-XXXXXXXXXX.rs 2:1]
|
||||
input i1: Ty0 @[module-XXXXXXXXXX.rs 3:1]
|
||||
input i2: Ty1 @[module-XXXXXXXXXX.rs 4:1]
|
||||
output o1: Ty0 @[module-XXXXXXXXXX.rs 5:1]
|
||||
output o2: Ty1 @[module-XXXXXXXXXX.rs 6:1]
|
||||
when swap: @[module-XXXXXXXXXX.rs 7:1]
|
||||
when eq(i2.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
|
||||
connect __connect_variant_body, bits(i2.body, 1, 0) @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr: Ty0
|
||||
connect _bundle_literal_expr.tag, UInt<2>(0h0)
|
||||
connect _bundle_literal_expr.body, pad(__connect_variant_body, 2)
|
||||
connect o1, _bundle_literal_expr @[module-XXXXXXXXXX.rs 8:1]
|
||||
else when eq(i2.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire __connect_variant_body_1: Ty2 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _cast_bits_to_bundle_expr: Ty3
|
||||
wire _cast_bits_to_bundle_expr_flattened: Ty3
|
||||
connect _cast_bits_to_bundle_expr_flattened.tag, bits(bits(i2.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr.tag, _cast_bits_to_bundle_expr_flattened.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened.body, bits(bits(i2.body, 2, 0), 2, 1)
|
||||
connect _cast_bits_to_bundle_expr.body, _cast_bits_to_bundle_expr_flattened.body
|
||||
when eq(_cast_bits_to_bundle_expr.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_1: Ty2
|
||||
connect _bundle_literal_expr_1.tag, UInt<1>(0h0)
|
||||
connect _bundle_literal_expr_1.body, UInt<1>(0h0)
|
||||
connect __connect_variant_body_1, _bundle_literal_expr_1 @[module-XXXXXXXXXX.rs 8:1]
|
||||
else:
|
||||
wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _cast_bits_to_bundle_expr_1: Ty3
|
||||
wire _cast_bits_to_bundle_expr_flattened_1: Ty3
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.tag, bits(bits(i2.body, 2, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_1.tag, _cast_bits_to_bundle_expr_flattened_1.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_1.body, bits(bits(i2.body, 2, 0), 2, 1)
|
||||
connect _cast_bits_to_bundle_expr_1.body, _cast_bits_to_bundle_expr_flattened_1.body
|
||||
connect __connect_variant_body_2, asSInt(bits(_cast_bits_to_bundle_expr_1.body, 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_2: Ty2
|
||||
connect _bundle_literal_expr_2.tag, UInt<1>(0h1)
|
||||
connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
|
||||
connect __connect_variant_body_1, _bundle_literal_expr_2 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_3: Ty0
|
||||
connect _bundle_literal_expr_3.tag, UInt<2>(0h1)
|
||||
wire _cast_bundle_to_bits_expr: Ty2
|
||||
connect _cast_bundle_to_bits_expr.tag, __connect_variant_body_1.tag
|
||||
connect _cast_bundle_to_bits_expr.body, __connect_variant_body_1.body
|
||||
wire _cast_to_bits_expr: UInt<2>
|
||||
connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.body, _cast_bundle_to_bits_expr.tag)
|
||||
connect _bundle_literal_expr_3.body, _cast_to_bits_expr
|
||||
connect o1, _bundle_literal_expr_3 @[module-XXXXXXXXXX.rs 8:1]
|
||||
else:
|
||||
wire __connect_variant_body_3: Ty4 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _cast_bits_to_bundle_expr_2: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_2: Ty4
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.tag, bits(bits(i2.body, 0, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_2.tag, _cast_bits_to_bundle_expr_flattened_2.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_2.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_2.body, _cast_bits_to_bundle_expr_flattened_2.body
|
||||
connect __connect_variant_body_3, _cast_bits_to_bundle_expr_2 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_4: Ty0
|
||||
connect _bundle_literal_expr_4.tag, UInt<2>(0h2)
|
||||
wire _cast_bundle_to_bits_expr_1: Ty4
|
||||
connect _cast_bundle_to_bits_expr_1.tag, __connect_variant_body_3.tag
|
||||
connect _cast_bundle_to_bits_expr_1.body, __connect_variant_body_3.body
|
||||
wire _cast_to_bits_expr_1: UInt<1>
|
||||
connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.body, _cast_bundle_to_bits_expr_1.tag)
|
||||
connect _bundle_literal_expr_4.body, pad(_cast_to_bits_expr_1, 2)
|
||||
connect o1, _bundle_literal_expr_4 @[module-XXXXXXXXXX.rs 8:1]
|
||||
when eq(i1.tag, UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect __connect_variant_body_4, bits(i1.body, 0, 0) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_5: Ty1
|
||||
connect _bundle_literal_expr_5.tag, UInt<2>(0h0)
|
||||
connect _bundle_literal_expr_5.body, pad(__connect_variant_body_4, 3)
|
||||
connect o2, _bundle_literal_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else when eq(i1.tag, UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire __connect_variant_body_5: Ty3 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_3: Ty2
|
||||
wire _cast_bits_to_bundle_expr_flattened_3: Ty2
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_3.tag, _cast_bits_to_bundle_expr_flattened_3.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_3.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_3.body, _cast_bits_to_bundle_expr_flattened_3.body
|
||||
when eq(_cast_bits_to_bundle_expr_3.tag, UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_6: Ty3
|
||||
connect _bundle_literal_expr_6.tag, UInt<1>(0h0)
|
||||
connect _bundle_literal_expr_6.body, UInt<2>(0h0)
|
||||
connect __connect_variant_body_5, _bundle_literal_expr_6 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_4: Ty2
|
||||
wire _cast_bits_to_bundle_expr_flattened_4: Ty2
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.tag, bits(bits(i1.body, 1, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_4.tag, _cast_bits_to_bundle_expr_flattened_4.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_4.body, bits(bits(i1.body, 1, 0), 1, 1)
|
||||
connect _cast_bits_to_bundle_expr_4.body, _cast_bits_to_bundle_expr_flattened_4.body
|
||||
connect __connect_variant_body_6, asSInt(bits(_cast_bits_to_bundle_expr_4.body, 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_7: Ty3
|
||||
connect _bundle_literal_expr_7.tag, UInt<1>(0h1)
|
||||
connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
|
||||
connect __connect_variant_body_5, _bundle_literal_expr_7 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_8: Ty1
|
||||
connect _bundle_literal_expr_8.tag, UInt<2>(0h1)
|
||||
wire _cast_bundle_to_bits_expr_2: Ty3
|
||||
connect _cast_bundle_to_bits_expr_2.tag, __connect_variant_body_5.tag
|
||||
connect _cast_bundle_to_bits_expr_2.body, __connect_variant_body_5.body
|
||||
wire _cast_to_bits_expr_2: UInt<3>
|
||||
connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.body, _cast_bundle_to_bits_expr_2.tag)
|
||||
connect _bundle_literal_expr_8.body, _cast_to_bits_expr_2
|
||||
connect o2, _bundle_literal_expr_8 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
wire __connect_variant_body_7: Ty4 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _cast_bits_to_bundle_expr_5: Ty4
|
||||
wire _cast_bits_to_bundle_expr_flattened_5: Ty4
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.tag, bits(bits(i1.body, 0, 0), 0, 0)
|
||||
connect _cast_bits_to_bundle_expr_5.tag, _cast_bits_to_bundle_expr_flattened_5.tag
|
||||
connect _cast_bits_to_bundle_expr_flattened_5.body, UInt<0>(0)
|
||||
connect _cast_bits_to_bundle_expr_5.body, _cast_bits_to_bundle_expr_flattened_5.body
|
||||
connect __connect_variant_body_7, _cast_bits_to_bundle_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_9: Ty1
|
||||
connect _bundle_literal_expr_9.tag, UInt<2>(0h2)
|
||||
wire _cast_bundle_to_bits_expr_3: Ty4
|
||||
connect _cast_bundle_to_bits_expr_3.tag, __connect_variant_body_7.tag
|
||||
connect _cast_bundle_to_bits_expr_3.body, __connect_variant_body_7.body
|
||||
wire _cast_to_bits_expr_3: UInt<1>
|
||||
connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.body, _cast_bundle_to_bits_expr_3.tag)
|
||||
connect _bundle_literal_expr_9.body, pad(_cast_to_bits_expr_3, 3)
|
||||
connect o2, _bundle_literal_expr_9 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
connect o1, i1 @[module-XXXXXXXXXX.rs 10:1]
|
||||
connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
|
||||
",
|
||||
}
|
||||
let m = simplify_enums(orig_m, SimplifyEnumsKind::ReplaceWithUInt).unwrap();
|
||||
dbg!(m);
|
||||
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
|
||||
assert_export_firrtl! {
|
||||
m =>
|
||||
"/test/check_enum_connect_any.fir": r"TODO",
|
||||
"/test/check_enum_connect_any.fir": r"FIRRTL version 3.2.0
|
||||
circuit check_enum_connect_any:
|
||||
type Ty0 = {tag: UInt<2>, body: UInt<2>}
|
||||
type Ty1 = {tag: UInt<1>, body: UInt<1>}
|
||||
type Ty2 = {tag: UInt<2>, body: UInt<3>}
|
||||
type Ty3 = {tag: UInt<1>, body: UInt<2>}
|
||||
module check_enum_connect_any: @[module-XXXXXXXXXX.rs 1:1]
|
||||
input swap: UInt<1> @[module-XXXXXXXXXX.rs 2:1]
|
||||
input i1: UInt<4> @[module-XXXXXXXXXX.rs 3:1]
|
||||
input i2: UInt<5> @[module-XXXXXXXXXX.rs 4:1]
|
||||
output o1: UInt<4> @[module-XXXXXXXXXX.rs 5:1]
|
||||
output o2: UInt<5> @[module-XXXXXXXXXX.rs 6:1]
|
||||
when swap: @[module-XXXXXXXXXX.rs 7:1]
|
||||
when eq(bits(i2, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire __connect_variant_body: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
|
||||
connect __connect_variant_body, bits(bits(i2, 4, 2), 1, 0) @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr: Ty0
|
||||
connect _bundle_literal_expr.tag, UInt<2>(0h0)
|
||||
connect _bundle_literal_expr.body, pad(__connect_variant_body, 2)
|
||||
wire _cast_bundle_to_bits_expr: Ty0
|
||||
connect _cast_bundle_to_bits_expr.tag, _bundle_literal_expr.tag
|
||||
connect _cast_bundle_to_bits_expr.body, _bundle_literal_expr.body
|
||||
wire _cast_to_bits_expr: UInt<4>
|
||||
connect _cast_to_bits_expr, cat(_cast_bundle_to_bits_expr.body, _cast_bundle_to_bits_expr.tag)
|
||||
connect o1, _cast_to_bits_expr @[module-XXXXXXXXXX.rs 8:1]
|
||||
else when eq(bits(i2, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire __connect_variant_body_1: UInt<2> @[module-XXXXXXXXXX.rs 8:1]
|
||||
when eq(bits(bits(bits(i2, 4, 2), 2, 0), 0, 0), UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_1: Ty1
|
||||
connect _bundle_literal_expr_1.tag, UInt<1>(0h0)
|
||||
connect _bundle_literal_expr_1.body, UInt<1>(0h0)
|
||||
wire _cast_bundle_to_bits_expr_1: Ty1
|
||||
connect _cast_bundle_to_bits_expr_1.tag, _bundle_literal_expr_1.tag
|
||||
connect _cast_bundle_to_bits_expr_1.body, _bundle_literal_expr_1.body
|
||||
wire _cast_to_bits_expr_1: UInt<2>
|
||||
connect _cast_to_bits_expr_1, cat(_cast_bundle_to_bits_expr_1.body, _cast_bundle_to_bits_expr_1.tag)
|
||||
connect __connect_variant_body_1, _cast_to_bits_expr_1 @[module-XXXXXXXXXX.rs 8:1]
|
||||
else:
|
||||
wire __connect_variant_body_2: SInt<1> @[module-XXXXXXXXXX.rs 8:1]
|
||||
connect __connect_variant_body_2, asSInt(bits(bits(bits(bits(i2, 4, 2), 2, 0), 2, 1), 1, 0)) @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_2: Ty1
|
||||
connect _bundle_literal_expr_2.tag, UInt<1>(0h1)
|
||||
connect _bundle_literal_expr_2.body, asUInt(__connect_variant_body_2)
|
||||
wire _cast_bundle_to_bits_expr_2: Ty1
|
||||
connect _cast_bundle_to_bits_expr_2.tag, _bundle_literal_expr_2.tag
|
||||
connect _cast_bundle_to_bits_expr_2.body, _bundle_literal_expr_2.body
|
||||
wire _cast_to_bits_expr_2: UInt<2>
|
||||
connect _cast_to_bits_expr_2, cat(_cast_bundle_to_bits_expr_2.body, _cast_bundle_to_bits_expr_2.tag)
|
||||
connect __connect_variant_body_1, _cast_to_bits_expr_2 @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_3: Ty0
|
||||
connect _bundle_literal_expr_3.tag, UInt<2>(0h1)
|
||||
connect _bundle_literal_expr_3.body, __connect_variant_body_1
|
||||
wire _cast_bundle_to_bits_expr_3: Ty0
|
||||
connect _cast_bundle_to_bits_expr_3.tag, _bundle_literal_expr_3.tag
|
||||
connect _cast_bundle_to_bits_expr_3.body, _bundle_literal_expr_3.body
|
||||
wire _cast_to_bits_expr_3: UInt<4>
|
||||
connect _cast_to_bits_expr_3, cat(_cast_bundle_to_bits_expr_3.body, _cast_bundle_to_bits_expr_3.tag)
|
||||
connect o1, _cast_to_bits_expr_3 @[module-XXXXXXXXXX.rs 8:1]
|
||||
else:
|
||||
wire __connect_variant_body_3: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
|
||||
connect __connect_variant_body_3, bits(bits(i2, 4, 2), 0, 0) @[module-XXXXXXXXXX.rs 8:1]
|
||||
wire _bundle_literal_expr_4: Ty0
|
||||
connect _bundle_literal_expr_4.tag, UInt<2>(0h2)
|
||||
connect _bundle_literal_expr_4.body, pad(__connect_variant_body_3, 2)
|
||||
wire _cast_bundle_to_bits_expr_4: Ty0
|
||||
connect _cast_bundle_to_bits_expr_4.tag, _bundle_literal_expr_4.tag
|
||||
connect _cast_bundle_to_bits_expr_4.body, _bundle_literal_expr_4.body
|
||||
wire _cast_to_bits_expr_4: UInt<4>
|
||||
connect _cast_to_bits_expr_4, cat(_cast_bundle_to_bits_expr_4.body, _cast_bundle_to_bits_expr_4.tag)
|
||||
connect o1, _cast_to_bits_expr_4 @[module-XXXXXXXXXX.rs 8:1]
|
||||
when eq(bits(i1, 1, 0), UInt<2>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire __connect_variant_body_4: UInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect __connect_variant_body_4, bits(bits(i1, 3, 2), 0, 0) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_5: Ty2
|
||||
connect _bundle_literal_expr_5.tag, UInt<2>(0h0)
|
||||
connect _bundle_literal_expr_5.body, pad(__connect_variant_body_4, 3)
|
||||
wire _cast_bundle_to_bits_expr_5: Ty2
|
||||
connect _cast_bundle_to_bits_expr_5.tag, _bundle_literal_expr_5.tag
|
||||
connect _cast_bundle_to_bits_expr_5.body, _bundle_literal_expr_5.body
|
||||
wire _cast_to_bits_expr_5: UInt<5>
|
||||
connect _cast_to_bits_expr_5, cat(_cast_bundle_to_bits_expr_5.body, _cast_bundle_to_bits_expr_5.tag)
|
||||
connect o2, _cast_to_bits_expr_5 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else when eq(bits(i1, 1, 0), UInt<2>(0h1)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire __connect_variant_body_5: UInt<3> @[module-XXXXXXXXXX.rs 9:1]
|
||||
when eq(bits(bits(bits(i1, 3, 2), 1, 0), 0, 0), UInt<1>(0h0)): @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_6: Ty3
|
||||
connect _bundle_literal_expr_6.tag, UInt<1>(0h0)
|
||||
connect _bundle_literal_expr_6.body, UInt<2>(0h0)
|
||||
wire _cast_bundle_to_bits_expr_6: Ty3
|
||||
connect _cast_bundle_to_bits_expr_6.tag, _bundle_literal_expr_6.tag
|
||||
connect _cast_bundle_to_bits_expr_6.body, _bundle_literal_expr_6.body
|
||||
wire _cast_to_bits_expr_6: UInt<3>
|
||||
connect _cast_to_bits_expr_6, cat(_cast_bundle_to_bits_expr_6.body, _cast_bundle_to_bits_expr_6.tag)
|
||||
connect __connect_variant_body_5, _cast_to_bits_expr_6 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
wire __connect_variant_body_6: SInt<2> @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect __connect_variant_body_6, asSInt(bits(bits(bits(bits(i1, 3, 2), 1, 0), 1, 1), 0, 0)) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_7: Ty3
|
||||
connect _bundle_literal_expr_7.tag, UInt<1>(0h1)
|
||||
connect _bundle_literal_expr_7.body, asUInt(__connect_variant_body_6)
|
||||
wire _cast_bundle_to_bits_expr_7: Ty3
|
||||
connect _cast_bundle_to_bits_expr_7.tag, _bundle_literal_expr_7.tag
|
||||
connect _cast_bundle_to_bits_expr_7.body, _bundle_literal_expr_7.body
|
||||
wire _cast_to_bits_expr_7: UInt<3>
|
||||
connect _cast_to_bits_expr_7, cat(_cast_bundle_to_bits_expr_7.body, _cast_bundle_to_bits_expr_7.tag)
|
||||
connect __connect_variant_body_5, _cast_to_bits_expr_7 @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_8: Ty2
|
||||
connect _bundle_literal_expr_8.tag, UInt<2>(0h1)
|
||||
connect _bundle_literal_expr_8.body, __connect_variant_body_5
|
||||
wire _cast_bundle_to_bits_expr_8: Ty2
|
||||
connect _cast_bundle_to_bits_expr_8.tag, _bundle_literal_expr_8.tag
|
||||
connect _cast_bundle_to_bits_expr_8.body, _bundle_literal_expr_8.body
|
||||
wire _cast_to_bits_expr_8: UInt<5>
|
||||
connect _cast_to_bits_expr_8, cat(_cast_bundle_to_bits_expr_8.body, _cast_bundle_to_bits_expr_8.tag)
|
||||
connect o2, _cast_to_bits_expr_8 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
wire __connect_variant_body_7: UInt<1> @[module-XXXXXXXXXX.rs 9:1]
|
||||
connect __connect_variant_body_7, bits(bits(i1, 3, 2), 0, 0) @[module-XXXXXXXXXX.rs 9:1]
|
||||
wire _bundle_literal_expr_9: Ty2
|
||||
connect _bundle_literal_expr_9.tag, UInt<2>(0h2)
|
||||
connect _bundle_literal_expr_9.body, pad(__connect_variant_body_7, 3)
|
||||
wire _cast_bundle_to_bits_expr_9: Ty2
|
||||
connect _cast_bundle_to_bits_expr_9.tag, _bundle_literal_expr_9.tag
|
||||
connect _cast_bundle_to_bits_expr_9.body, _bundle_literal_expr_9.body
|
||||
wire _cast_to_bits_expr_9: UInt<5>
|
||||
connect _cast_to_bits_expr_9, cat(_cast_bundle_to_bits_expr_9.body, _cast_bundle_to_bits_expr_9.tag)
|
||||
connect o2, _cast_to_bits_expr_9 @[module-XXXXXXXXXX.rs 9:1]
|
||||
else:
|
||||
connect o1, i1 @[module-XXXXXXXXXX.rs 10:1]
|
||||
connect o2, i2 @[module-XXXXXXXXXX.rs 11:1]
|
||||
",
|
||||
};
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue