forked from libre-chip/fayalite
#[hdl] match works!
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4 changed files with 83 additions and 24 deletions
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@ -21,7 +21,7 @@ use crate::{
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wire::Wire,
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};
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use bitvec::slice::BitSlice;
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use std::{fmt, ops::Deref};
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use std::{convert::Infallible, fmt, ops::Deref};
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pub mod ops;
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pub mod target;
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@ -690,3 +690,10 @@ pub trait CastTo: ToExpr {
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}
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impl<T: ToExpr + ?Sized> CastTo for T {}
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#[doc(hidden)]
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pub fn check_match_expr<T: Type>(
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_expr: Expr<T>,
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_check_fn: impl FnOnce(T::MatchVariant, Infallible),
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) {
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}
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@ -662,7 +662,6 @@ circuit check_enum_literals:
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};
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}
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#[cfg(todo)]
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#[hdl_module(outline_generated)]
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pub fn check_struct_enum_match() {
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#[hdl]
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@ -688,7 +687,7 @@ pub fn check_struct_enum_match() {
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match i2 {
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TestEnum::A => connect(o[2], 0_hdl_u8),
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TestEnum::B(v) => connect(o[2], v),
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TestEnum::C(v) => connect_any(o[2], v[1]),
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TestEnum::C(v) => connect_any(o[2], v[1].cast_to(UInt[1])),
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}
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#[hdl]
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match i2 {
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@ -699,12 +698,11 @@ pub fn check_struct_enum_match() {
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#[hdl]
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match i2 {
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TestEnum::B(_) => connect(o[4], 1_hdl_u8),
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TestEnum::C(v) => connect_any(o[4], v[2]),
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TestEnum::C(v) => connect_any(o[4], v[2].cast_to(UInt[1])),
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_ => connect(o[4], 0_hdl_u8),
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}
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}
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#[cfg(todo)]
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#[test]
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fn test_struct_enum_match() {
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let _n = SourceLocation::normalize_files_for_tests();
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@ -715,14 +713,14 @@ fn test_struct_enum_match() {
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m =>
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"/test/check_struct_enum_match.fir": r"FIRRTL version 3.2.0
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circuit check_struct_enum_match:
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type Ty0 = {|None, Some: UInt<8>|}
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type Ty0 = {|HdlNone, HdlSome: UInt<8>|}
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type Ty1 = {|A, B: UInt<8>, C: UInt<1>[3]|}
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module check_struct_enum_match: @[module-XXXXXXXXXX.rs 1:1]
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input i1: Ty0 @[module-XXXXXXXXXX.rs 2:1]
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input i2: Ty1 @[module-XXXXXXXXXX.rs 3:1]
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output o: UInt<8>[5] @[module-XXXXXXXXXX.rs 4:1]
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match i1: @[module-XXXXXXXXXX.rs 5:1]
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None:
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HdlNone:
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match i2: @[module-XXXXXXXXXX.rs 6:1]
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A:
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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@ -730,12 +728,12 @@ circuit check_struct_enum_match:
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connect o[0], add(_match_arm_value, UInt<8>(0h2)) @[module-XXXXXXXXXX.rs 8:1]
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C(_match_arm_value_1):
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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Some(_match_arm_value_2):
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HdlSome(_match_arm_value_2):
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connect o[0], _match_arm_value_2 @[module-XXXXXXXXXX.rs 9:1]
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match i1: @[module-XXXXXXXXXX.rs 10:1]
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None:
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HdlNone:
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connect o[1], UInt<8>(0h0) @[module-XXXXXXXXXX.rs 11:1]
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Some(_match_arm_value_3):
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HdlSome(_match_arm_value_3):
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connect o[1], UInt<8>(0h1) @[module-XXXXXXXXXX.rs 12:1]
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match i2: @[module-XXXXXXXXXX.rs 13:1]
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A:
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@ -768,7 +766,7 @@ circuit check_struct_enum_match:
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m =>
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"/test/check_struct_enum_match.fir": r"FIRRTL version 3.2.0
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circuit check_struct_enum_match:
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type Ty0 = {|None, Some|}
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type Ty0 = {|HdlNone, HdlSome|}
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type Ty1 = {tag: Ty0, body: UInt<8>}
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type Ty2 = {|A, B, C|}
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type Ty3 = {tag: Ty2, body: UInt<8>}
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@ -777,7 +775,7 @@ circuit check_struct_enum_match:
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input i2: Ty3 @[module-XXXXXXXXXX.rs 3:1]
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output o: UInt<8>[5] @[module-XXXXXXXXXX.rs 4:1]
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match i1.tag: @[module-XXXXXXXXXX.rs 5:1]
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None:
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HdlNone:
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match i2.tag: @[module-XXXXXXXXXX.rs 6:1]
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A:
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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@ -785,12 +783,12 @@ circuit check_struct_enum_match:
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connect o[0], add(bits(i2.body, 7, 0), UInt<8>(0h2)) @[module-XXXXXXXXXX.rs 8:1]
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C:
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connect o[0], UInt<8>(0h17) @[module-XXXXXXXXXX.rs 7:1]
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Some:
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HdlSome:
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connect o[0], bits(i1.body, 7, 0) @[module-XXXXXXXXXX.rs 9:1]
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match i1.tag: @[module-XXXXXXXXXX.rs 10:1]
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None:
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HdlNone:
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connect o[1], UInt<8>(0h0) @[module-XXXXXXXXXX.rs 11:1]
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Some:
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HdlSome:
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connect o[1], UInt<8>(0h1) @[module-XXXXXXXXXX.rs 12:1]
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match i2.tag: @[module-XXXXXXXXXX.rs 13:1]
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A:
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