add assert/assume/cover

This commit is contained in:
Jacob Lifshay 2024-09-23 19:10:51 -07:00
parent 716c65edcd
commit 28aad19bf5
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
7 changed files with 282 additions and 9 deletions

View file

@ -3182,3 +3182,55 @@ circuit check_uninit_1:
",
};
}
#[hdl_module(outline_generated)]
pub fn check_formal() {
#[hdl]
let clk: Clock = m.input();
#[hdl]
let en1: Bool = m.input();
#[hdl]
let en2: Bool = m.input();
#[hdl]
let en3: Bool = m.input();
#[hdl]
let pred1: Bool = m.input();
#[hdl]
let pred2: Bool = m.input();
#[hdl]
let pred3: Bool = m.input();
hdl_assert_with_enable(clk, pred1, en1, "en check 1");
hdl_assume_with_enable(clk, pred2, en2, "en check 2");
hdl_cover_with_enable(clk, pred3, en3, "en check 3");
hdl_assert(clk, pred1, "check 1");
hdl_assume(clk, pred2, "check 2");
hdl_cover(clk, pred3, "check 3");
}
#[test]
fn test_formal() {
let _n = SourceLocation::normalize_files_for_tests();
let m = check_formal();
dbg!(m);
#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
assert_export_firrtl! {
m =>
"/test/check_formal.fir": r#"FIRRTL version 3.2.0
circuit check_formal:
module check_formal: @[module-XXXXXXXXXX.rs 1:1]
input clk: Clock @[module-XXXXXXXXXX.rs 2:1]
input en1: UInt<1> @[module-XXXXXXXXXX.rs 3:1]
input en2: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
input en3: UInt<1> @[module-XXXXXXXXXX.rs 5:1]
input pred1: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
input pred2: UInt<1> @[module-XXXXXXXXXX.rs 7:1]
input pred3: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
assert(clk, pred1, en1, "en check 1") @[module-XXXXXXXXXX.rs 9:1]
assume(clk, pred2, en2, "en check 2") @[module-XXXXXXXXXX.rs 10:1]
cover(clk, pred3, en3, "en check 3") @[module-XXXXXXXXXX.rs 11:1]
assert(clk, pred1, UInt<1>(0h1), "check 1") @[module-XXXXXXXXXX.rs 12:1]
assume(clk, pred2, UInt<1>(0h1), "check 2") @[module-XXXXXXXXXX.rs 13:1]
cover(clk, pred3, UInt<1>(0h1), "check 3") @[module-XXXXXXXXXX.rs 14:1]
"#,
};
}