forked from libre-chip/fayalite
add assert/assume/cover
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716c65edcd
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28aad19bf5
7 changed files with 282 additions and 9 deletions
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@ -3182,3 +3182,55 @@ circuit check_uninit_1:
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",
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};
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}
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#[hdl_module(outline_generated)]
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pub fn check_formal() {
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#[hdl]
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let clk: Clock = m.input();
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#[hdl]
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let en1: Bool = m.input();
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#[hdl]
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let en2: Bool = m.input();
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#[hdl]
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let en3: Bool = m.input();
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#[hdl]
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let pred1: Bool = m.input();
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#[hdl]
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let pred2: Bool = m.input();
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#[hdl]
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let pred3: Bool = m.input();
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hdl_assert_with_enable(clk, pred1, en1, "en check 1");
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hdl_assume_with_enable(clk, pred2, en2, "en check 2");
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hdl_cover_with_enable(clk, pred3, en3, "en check 3");
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hdl_assert(clk, pred1, "check 1");
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hdl_assume(clk, pred2, "check 2");
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hdl_cover(clk, pred3, "check 3");
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}
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#[test]
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fn test_formal() {
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let _n = SourceLocation::normalize_files_for_tests();
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let m = check_formal();
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dbg!(m);
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#[rustfmt::skip] // work around https://github.com/rust-lang/rustfmt/issues/6161
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assert_export_firrtl! {
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m =>
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"/test/check_formal.fir": r#"FIRRTL version 3.2.0
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circuit check_formal:
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module check_formal: @[module-XXXXXXXXXX.rs 1:1]
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input clk: Clock @[module-XXXXXXXXXX.rs 2:1]
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input en1: UInt<1> @[module-XXXXXXXXXX.rs 3:1]
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input en2: UInt<1> @[module-XXXXXXXXXX.rs 4:1]
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input en3: UInt<1> @[module-XXXXXXXXXX.rs 5:1]
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input pred1: UInt<1> @[module-XXXXXXXXXX.rs 6:1]
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input pred2: UInt<1> @[module-XXXXXXXXXX.rs 7:1]
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input pred3: UInt<1> @[module-XXXXXXXXXX.rs 8:1]
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assert(clk, pred1, en1, "en check 1") @[module-XXXXXXXXXX.rs 9:1]
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assume(clk, pred2, en2, "en check 2") @[module-XXXXXXXXXX.rs 10:1]
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cover(clk, pred3, en3, "en check 3") @[module-XXXXXXXXXX.rs 11:1]
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assert(clk, pred1, UInt<1>(0h1), "check 1") @[module-XXXXXXXXXX.rs 12:1]
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assume(clk, pred2, UInt<1>(0h1), "check 2") @[module-XXXXXXXXXX.rs 13:1]
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cover(clk, pred3, UInt<1>(0h1), "check 3") @[module-XXXXXXXXXX.rs 14:1]
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"#,
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};
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}
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