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sim: properly update all VCD wires when they share simulation state

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This commit is contained in:
Jacob Lifshay 2026-05-05 21:12:00 -07:00
parent 2266315944
commit 26224abe1c
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
41 changed files with 2666 additions and 1621 deletions
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18
crates/fayalite/tests/sim/expected/shift_register.txt
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@ -259,10 +259,10 @@ Simulation {
},
small_slots: StatePart {
value: [
0 (modified),
0 (modified),
1 (modified),
0 (modified),
0,
0,
1,
0,
],
},
big_slots: StatePart {
@ -272,14 +272,14 @@ Simulation {
0,
0,
0,
0 (modified),
0 (modified),
0,
0 (modified),
0,
0 (modified),
0,
0 (modified),
0,
0,
0,
0,
0,
],
},
sim_only_slots: StatePart {