programmerjake/fayalite
1
0
Fork 0
forked from libre-chip/fayalite
Code Pull requests Activity

tests/sim: split expected output text into separate files

Browse source
This commit is contained in:
Jacob Lifshay 2024-12-05 18:15:38 -08:00
parent 643816d5b5
commit 259bee39c2
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
13 changed files with 3508 additions and 3513 deletions
Download patch file Download diff file Expand all files Collapse all files

47
crates/fayalite/tests/sim/expected/mod1.vcd Normal file
View file

@ -0,0 +1,47 @@
$timescale 1 ps $end
$scope module mod1 $end
$scope struct o $end
$var wire 4 ! i $end
$var wire 2 " o $end
$var wire 2 # i2 $end
$var wire 4 $ o2 $end
$upscope $end
$scope struct child $end
$var wire 4 ) i $end
$var wire 2 * o $end
$var wire 2 + i2 $end
$var wire 4 , o2 $end
$upscope $end
$scope module mod1_child $end
$var wire 4 % i $end
$var wire 2 & o $end
$var wire 2 ' i2 $end
$var wire 4 ( o2 $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
b11 !
b11 "
b10 #
b1110 $
b11 %
b11 &
b10 '
b1110 (
b11 )
b11 *
b10 +
b1110 ,
$end
#1000000
b1010 !
b10 "
b1111 $
b1010 %
b10 &
b1111 (
b1010 )
b10 *
b1111 ,
#2000000