tests/sim: split expected output text into separate files

crates/fayalite/tests/sim/expected/counter_sync.vcd

@@ -0,0 +1,214 @@
+$timescale 1 ps $end
+$scope module counter $end
+$scope struct cd $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$upscope $end
+$var wire 4 # count $end
+$var reg 4 $ count_reg $end
+$upscope $end
+$enddefinitions $end
+$dumpvars
+0!
+1"
+b0 #
+b0 $
+$end
+#1000000
+1!
+b11 $
+b11 #
+0"
+#2000000
+0!
+#3000000
+1!
+b100 $
+b100 #
+#4000000
+0!
+#5000000
+1!
+b101 $
+b101 #
+#6000000
+0!
+#7000000
+1!
+b110 $
+b110 #
+#8000000
+0!
+#9000000
+1!
+b111 $
+b111 #
+#10000000
+0!
+#11000000
+1!
+b1000 $
+b1000 #
+#12000000
+0!
+#13000000
+1!
+b1001 $
+b1001 #
+#14000000
+0!
+#15000000
+1!
+b1010 $
+b1010 #
+#16000000
+0!
+#17000000
+1!
+b1011 $
+b1011 #
+#18000000
+0!
+#19000000
+1!
+b1100 $
+b1100 #
+#20000000
+0!
+#21000000
+1!
+b1101 $
+b1101 #
+#22000000
+0!
+#23000000
+1!
+b1110 $
+b1110 #
+#24000000
+0!
+#25000000
+1!
+b1111 $
+b1111 #
+#26000000
+0!
+#27000000
+1!
+b0 $
+b0 #
+#28000000
+0!
+#29000000
+1!
+b1 $
+b1 #
+#30000000
+0!
+#31000000
+1!
+b10 $
+b10 #
+#32000000
+0!
+#33000000
+1!
+b11 $
+b11 #
+#34000000
+0!
+#35000000
+1!
+b100 $
+b100 #
+#36000000
+0!
+#37000000
+1!
+b101 $
+b101 #
+#38000000
+0!
+#39000000
+1!
+b110 $
+b110 #
+#40000000
+0!
+#41000000
+1!
+b111 $
+b111 #
+#42000000
+0!
+#43000000
+1!
+b1000 $
+b1000 #
+#44000000
+0!
+#45000000
+1!
+b1001 $
+b1001 #
+#46000000
+0!
+#47000000
+1!
+b1010 $
+b1010 #
+#48000000
+0!
+#49000000
+1!
+b1011 $
+b1011 #
+#50000000
+0!
+#51000000
+1!
+b1100 $
+b1100 #
+#52000000
+0!
+#53000000
+1!
+b1101 $
+b1101 #
+#54000000
+0!
+#55000000
+1!
+b1110 $
+b1110 #
+#56000000
+0!
+#57000000
+1!
+b1111 $
+b1111 #
+#58000000
+0!
+#59000000
+1!
+b0 $
+b0 #
+#60000000
+0!
+#61000000
+1!
+b1 $
+b1 #
+#62000000
+0!
+#63000000
+1!
+b10 $
+b10 #
+#64000000
+0!
+#65000000
+1!
+b11 $
+b11 #
+#66000000