forked from libre-chip/fayalite
tests/sim: split expected output text into separate files
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13 changed files with 3508 additions and 3513 deletions
509
crates/fayalite/tests/sim/expected/counter_async.txt
Normal file
509
crates/fayalite/tests/sim/expected/counter_async.txt
Normal file
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@ -0,0 +1,509 @@
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Simulation {
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state: State {
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insns: Insns {
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state_layout: StateLayout {
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ty: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 4,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 10,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(counter: counter).counter::cd.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(counter: counter).counter::cd.rst",
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ty: AsyncReset,
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},
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SlotDebugData {
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name: "InstantiatedModule(counter: counter).counter::count",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(counter: counter).counter::count_reg",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "InstantiatedModule(counter: counter).counter::count_reg$next",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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SlotDebugData {
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name: "",
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ty: Bool,
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},
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SlotDebugData {
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name: "",
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ty: UInt<1>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<5>,
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},
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SlotDebugData {
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name: "",
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ty: UInt<4>,
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},
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],
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..
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},
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},
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},
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insns: [
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// at: module-XXXXXXXXXX.rs:1:1
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Const {
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dest: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
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value: 1,
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},
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Copy {
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dest: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
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},
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// at: module-XXXXXXXXXX.rs:3:1
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IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(1), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.rst", ty: AsyncReset },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Const {
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dest: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
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value: 3,
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},
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// at: module-XXXXXXXXXX.rs:3:1
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BranchIfZero {
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target: 6,
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value: StatePartIndex<BigSlots>(6), // SlotDebugData { name: "", ty: Bool },
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},
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Copy {
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dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Add {
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dest: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
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lhs: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
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rhs: StatePartIndex<BigSlots>(7), // SlotDebugData { name: "", ty: UInt<1> },
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},
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CastToUInt {
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dest: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(8), // SlotDebugData { name: "", ty: UInt<5> },
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dest_width: 4,
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},
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// at: module-XXXXXXXXXX.rs:4:1
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Copy {
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dest: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(9), // SlotDebugData { name: "", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:6:1
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Copy {
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dest: StatePartIndex<BigSlots>(2), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
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},
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// at: module-XXXXXXXXXX.rs:3:1
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IsNonZeroDestIsSmall {
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dest: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<BigSlots>(0), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::cd.clk", ty: Clock },
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},
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AndSmall {
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dest: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
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lhs: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
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rhs: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
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},
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BranchIfSmallNonZero {
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target: 16,
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value: StatePartIndex<SmallSlots>(3), // SlotDebugData { name: "", ty: Bool },
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},
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BranchIfSmallZero {
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target: 17,
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value: StatePartIndex<SmallSlots>(1), // SlotDebugData { name: "", ty: Bool },
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},
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Copy {
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dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(4), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg$next", ty: UInt<4> },
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},
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Branch {
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target: 17,
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},
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Copy {
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dest: StatePartIndex<BigSlots>(3), // SlotDebugData { name: "InstantiatedModule(counter: counter).counter::count_reg", ty: UInt<4> },
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src: StatePartIndex<BigSlots>(5), // SlotDebugData { name: "", ty: UInt<4> },
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},
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NotSmall {
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dest: StatePartIndex<SmallSlots>(0), // SlotDebugData { name: "", ty: Bool },
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src: StatePartIndex<SmallSlots>(2), // SlotDebugData { name: "", ty: Bool },
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},
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// at: module-XXXXXXXXXX.rs:1:1
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Return,
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],
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..
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},
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pc: 18,
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small_slots: StatePart {
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value: [
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18446744073709551614,
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0,
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1,
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0,
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],
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},
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big_slots: StatePart {
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value: [
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1,
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0,
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3,
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3,
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4,
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3,
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0,
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1,
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4,
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4,
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],
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},
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},
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io: Instance {
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name: <simulator>::counter,
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instantiated: Module {
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name: counter,
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..
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},
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},
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uninitialized_inputs: {},
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io_targets: {
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Instance {
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name: <simulator>::counter,
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instantiated: Module {
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name: counter,
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..
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},
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}.cd: CompiledValue {
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layout: CompiledTypeLayout {
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ty: Bundle {
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/* offset = 0 */
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clk: Clock,
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/* offset = 1 */
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rst: AsyncReset,
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},
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 2,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(counter: counter).counter::cd.clk",
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ty: Clock,
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},
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SlotDebugData {
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name: "InstantiatedModule(counter: counter).counter::cd.rst",
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ty: AsyncReset,
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},
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],
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..
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},
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},
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body: Bundle {
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fields: [
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CompiledBundleField {
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offset: TypeIndex {
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small_slots: StatePartIndex<SmallSlots>(0),
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big_slots: StatePartIndex<BigSlots>(0),
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},
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ty: CompiledTypeLayout {
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ty: Clock,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Clock,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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},
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CompiledBundleField {
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offset: TypeIndex {
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small_slots: StatePartIndex<SmallSlots>(0),
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big_slots: StatePartIndex<BigSlots>(1),
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},
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ty: CompiledTypeLayout {
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ty: AsyncReset,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: AsyncReset,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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},
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],
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},
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 2 },
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},
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write: None,
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},
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Instance {
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name: <simulator>::counter,
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instantiated: Module {
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name: counter,
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..
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},
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}.cd.clk: CompiledValue {
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layout: CompiledTypeLayout {
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ty: Clock,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: Clock,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 0, len: 1 },
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},
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write: None,
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},
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Instance {
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name: <simulator>::counter,
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instantiated: Module {
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name: counter,
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..
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},
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}.cd.rst: CompiledValue {
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layout: CompiledTypeLayout {
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ty: AsyncReset,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "",
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ty: AsyncReset,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 1, len: 1 },
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},
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write: None,
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},
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Instance {
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name: <simulator>::counter,
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instantiated: Module {
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name: counter,
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..
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},
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}.count: CompiledValue {
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layout: CompiledTypeLayout {
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ty: UInt<4>,
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layout: TypeLayout {
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small_slots: StatePartAllocationLayout<SmallSlots> {
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len: 0,
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debug_data: [],
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..
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},
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big_slots: StatePartAllocationLayout<BigSlots> {
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len: 1,
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debug_data: [
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SlotDebugData {
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name: "InstantiatedModule(counter: counter).counter::count",
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ty: UInt<4>,
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},
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],
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..
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},
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},
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body: Scalar,
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},
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range: TypeIndexRange {
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small_slots: StatePartIndexRange<SmallSlots> { start: 0, len: 0 },
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big_slots: StatePartIndexRange<BigSlots> { start: 2, len: 1 },
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},
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write: None,
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},
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},
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made_initial_step: true,
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needs_settle: false,
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trace_decls: TraceModule {
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name: "counter",
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children: [
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TraceModuleIO {
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name: "cd",
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child: TraceBundle {
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name: "cd",
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fields: [
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TraceClock {
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id: TraceScalarId(0),
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name: "clk",
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flow: Source,
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},
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TraceAsyncReset {
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id: TraceScalarId(1),
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name: "rst",
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flow: Source,
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},
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],
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ty: Bundle {
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/* offset = 0 */
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clk: Clock,
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/* offset = 1 */
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rst: AsyncReset,
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},
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flow: Source,
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},
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ty: Bundle {
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/* offset = 0 */
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clk: Clock,
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/* offset = 1 */
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rst: AsyncReset,
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},
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flow: Source,
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},
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TraceModuleIO {
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name: "count",
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child: TraceUInt {
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id: TraceScalarId(2),
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name: "count",
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ty: UInt<4>,
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flow: Sink,
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},
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ty: UInt<4>,
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flow: Sink,
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},
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TraceReg {
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name: "count_reg",
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child: TraceUInt {
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id: TraceScalarId(3),
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name: "count_reg",
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ty: UInt<4>,
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flow: Duplex,
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},
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ty: UInt<4>,
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},
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],
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},
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traces: [
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SimTrace {
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id: TraceScalarId(0),
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kind: BigClock {
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index: StatePartIndex<BigSlots>(0),
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},
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state: 0x1,
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last_state: 0x1,
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},
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SimTrace {
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id: TraceScalarId(1),
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kind: BigAsyncReset {
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index: StatePartIndex<BigSlots>(1),
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},
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state: 0x0,
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last_state: 0x0,
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},
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SimTrace {
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id: TraceScalarId(2),
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kind: BigUInt {
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index: StatePartIndex<BigSlots>(2),
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ty: UInt<4>,
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},
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state: 0x3,
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last_state: 0x2,
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},
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SimTrace {
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id: TraceScalarId(3),
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kind: BigUInt {
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index: StatePartIndex<BigSlots>(3),
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ty: UInt<4>,
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},
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state: 0x3,
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last_state: 0x3,
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},
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],
|
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trace_writers: [
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Running(
|
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VcdWriter {
|
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finished_init: true,
|
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timescale: 1 ps,
|
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..
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},
|
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),
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],
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instant: 66 μs,
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clocks_triggered: [
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StatePartIndex<SmallSlots>(1),
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],
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}
|
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