programmerjake/fayalite
1
0
Fork 0
forked from libre-chip/fayalite
Code Pull requests Activity

fix doctests to use Expr<UInt<1>> instead of bool for example conditions

Browse source
This commit is contained in:
Jacob Lifshay 2024-07-22 02:20:06 -07:00
parent 0edf380c79
commit 180ecad017
Signed by: programmerjake
SSH key fingerprint: SHA256:B1iRVvUJkvd7upMIiMqn6OyxvD2SgJkAH3ZnUOj6z+c
2 changed files with 4 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/registers.rs
View file

@ -11,7 +11,8 @@
//! # use fayalite::{hdl_module, int::UInt, array::Array, clock::ClockDomain}; //! # use fayalite::{hdl_module, int::UInt, array::Array, clock::ClockDomain};
//! # #[hdl_module] //! # #[hdl_module]
//! # fn module() { //! # fn module() {
//! # let v = true; //! # #[hdl]
//! # let v: UInt<1> = m.input();
//! #[hdl] //! #[hdl]
//! let cd: ClockDomain = m.input(); //! let cd: ClockDomain = m.input();
//! #[hdl] //! #[hdl]

3
crates/fayalite/src/_docs/modules/module_bodies/hdl_let_statements/wires.rs
View file

@ -12,7 +12,8 @@
//! # use fayalite::{hdl_module, int::UInt, array::Array, clock::ClockDomain}; //! # use fayalite::{hdl_module, int::UInt, array::Array, clock::ClockDomain};
//! # #[hdl_module] //! # #[hdl_module]
//! # fn module() { //! # fn module() {
//! # let v = true; //! # #[hdl]
//! # let v: UInt<1> = m.input();
//! #[hdl] //! #[hdl]
//! let cd: ClockDomain = m.input(); //! let cd: ClockDomain = m.input();
//! #[hdl] //! #[hdl]