diff --git a/Cargo.lock b/Cargo.lock
index 3a6980a..0444993 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -304,7 +304,7 @@ checksum = "e8c02a5121d4ea3eb16a80748c74f5549a5665e4c21333c6098f283870fbdea6"
 [[package]]
 name = "fayalite"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#fbc8ffa5aea6cc76d643880cd21a34993fb1ec4f"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#45fea70c1841aedbb32377d88c0280c7a83e6208"
 dependencies = [
  "base64",
  "bitvec",
@@ -331,7 +331,7 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#fbc8ffa5aea6cc76d643880cd21a34993fb1ec4f"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#45fea70c1841aedbb32377d88c0280c7a83e6208"
 dependencies = [
  "fayalite-proc-macros-impl",
 ]
@@ -339,7 +339,7 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros-impl"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#fbc8ffa5aea6cc76d643880cd21a34993fb1ec4f"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#45fea70c1841aedbb32377d88c0280c7a83e6208"
 dependencies = [
  "base16ct",
  "num-bigint",
@@ -354,7 +354,7 @@ dependencies = [
 [[package]]
 name = "fayalite-visit-gen"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#fbc8ffa5aea6cc76d643880cd21a34993fb1ec4f"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#45fea70c1841aedbb32377d88c0280c7a83e6208"
 dependencies = [
  "indexmap",
  "prettyplease",
diff --git a/crates/cpu/src/next_pc.rs b/crates/cpu/src/next_pc.rs
index 4ce87b3..0338cc4 100644
--- a/crates/cpu/src/next_pc.rs
+++ b/crates/cpu/src/next_pc.rs
@@ -545,14 +545,17 @@ pub fn next_pc(config: PhantomConst<CpuConfig>) {
                     sim.write(to_fetch.inner.data, HdlNone()).await;
                 },
                 |mut sim: ExternModuleSimulationState, ()| async move {
-                    for step in 0usize.. {
-                        sim.wait_for_clock_edge(cd.clk).await;
-                        match ResetSteps::reset_step(state_for_debug, &mut sim, step).await {
-                            ResetStatus::Done => break,
-                            ResetStatus::Working => {}
+                    sim.fork_join_scope(|scope, mut sim: ExternModuleSimulationState| async move {
+                        for step in 0usize.. {
+                            sim.wait_for_clock_edge(cd.clk).await;
+                            match ResetSteps::reset_step(state_for_debug, &mut sim, step).await {
+                                ResetStatus::Done => break,
+                                ResetStatus::Working => {}
+                            }
                         }
-                    }
-                    // TODO: finish
+                        // TODO: finish
+                    })
+                    .await
                 },
             )
             .await;