forked from libre-chip/cpu
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2 commits
9cc556c988
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241255e12c
| Author | SHA1 | Date | |
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| 241255e12c | |||
| 14df664277 |
2 changed files with 20 additions and 10 deletions
8
Cargo.lock
generated
8
Cargo.lock
generated
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@ -388,7 +388,7 @@ checksum = "e8c02a5121d4ea3eb16a80748c74f5549a5665e4c21333c6098f283870fbdea6"
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[[package]]
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name = "fayalite"
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version = "0.3.0"
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source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#cf3e6cfc6bc33eebf2d2862c7a1948b9cf40ecac"
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source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#31353862ceba3d255fd6712813a457688b269358"
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dependencies = [
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"base64",
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"bitvec",
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@ -417,7 +417,7 @@ dependencies = [
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[[package]]
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name = "fayalite-proc-macros"
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version = "0.3.0"
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source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#cf3e6cfc6bc33eebf2d2862c7a1948b9cf40ecac"
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source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#31353862ceba3d255fd6712813a457688b269358"
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dependencies = [
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"fayalite-proc-macros-impl",
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]
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@ -425,7 +425,7 @@ dependencies = [
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[[package]]
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name = "fayalite-proc-macros-impl"
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version = "0.3.0"
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source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#cf3e6cfc6bc33eebf2d2862c7a1948b9cf40ecac"
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source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#31353862ceba3d255fd6712813a457688b269358"
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dependencies = [
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"base16ct 0.2.0",
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"num-bigint",
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@ -440,7 +440,7 @@ dependencies = [
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[[package]]
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name = "fayalite-visit-gen"
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version = "0.3.0"
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source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#cf3e6cfc6bc33eebf2d2862c7a1948b9cf40ecac"
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source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#31353862ceba3d255fd6712813a457688b269358"
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dependencies = [
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"indexmap",
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"prettyplease",
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@ -28,9 +28,7 @@ use std::num::NonZero;
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#[hdl_module]
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fn formal_harness(config: PhantomConst<CpuConfig>) {
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#[hdl]
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let cd: ClockDomain = m.output();
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connect(cd.clk, fayalite::formal::formal_global_clock());
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connect(cd.rst, fayalite::formal::formal_reset().to_reset());
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let cd: ClockDomain = m.input();
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#[hdl]
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let input: DecodeAndRunSingleInsnInput<
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@ -99,9 +97,21 @@ fn formal_harness(config: PhantomConst<CpuConfig>) {
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#[hdl_module]
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fn check_power_isa_add_formal(config: PhantomConst<CpuConfig>) {
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#[hdl]
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let clk: Clock = m.input();
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#[hdl]
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let cd = wire();
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connect(
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cd,
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#[hdl]
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ClockDomain {
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clk,
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rst: formal_reset().to_reset(),
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},
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);
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#[hdl]
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let harness = instance(formal_harness(config));
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let cd = harness.cd;
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connect(harness.cd, cd);
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#[hdl]
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let DecodeAndRunSingleInsnInput::<_, _> {
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decoder_input,
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@ -208,11 +218,11 @@ fn test_power_isa_add_formal() {
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vec![UnitConfig::new(UnitKind::AluBranch)],
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NonZero::new(20).unwrap(),
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));
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let dut = check_power_isa_add_formal(config);
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let m = check_power_isa_add_formal(config);
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println!("starting assert formal");
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assert_formal(
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"test_power_isa_add_formal",
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dut,
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m,
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FormalMode::Prove,
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10,
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None,
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