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programmerjake:master
programmerjake:decode-and-test-harness
libre-chip:master
libre-chip:wip-splitting-reg-alloc
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compare: programmerjake:fca2ff8c91bb89e2cf20c5b87ad8cec68fcb1d15
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programmerjake:decode-and-test-harness
programmerjake:master
libre-chip:master
libre-chip:wip-splitting-reg-alloc

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3300e7ca01 ... fca2ff8c91

Author SHA1 Message Date
Jacob Lifshay
fca2ff8c91
WIP adding new test for L2 reg file store 2026-05-06 20:11:50 -07:00
21 changed files with 157573 additions and 408136 deletions
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176
crates/cpu/src/decoder/simple_power_isa.rs
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@ -604,7 +604,7 @@ impl DecodeState<'_> {
}], }],
[], [],
), ),
[MOpRegNum::const_zero(); 2], MOpRegNum::const_zero().value,
(li << 2).cast_to_static(), (li << 2).cast_to_static(),
!aa, !aa,
lk, lk,
@ -646,7 +646,7 @@ impl DecodeState<'_> {
#[hdl] #[hdl]
let branch_ctr_reg: MOpRegNum = wire(); let branch_ctr_reg: MOpRegNum = wire();
let dest = MOpDestReg::new([branch_lr_dest_reg], []); let dest = MOpDestReg::new([branch_lr_dest_reg], []);
let src1 = addr_reg.unwrap_or_else(|| MOpRegNum::const_zero()); let src1 = addr_reg.unwrap_or_else(|| MOpRegNum::const_zero()).value;
let imm: Expr<SInt<_>> = (bd.unwrap_or(0_hdl_i14) << 2).cast_to_static(); let imm: Expr<SInt<_>> = (bd.unwrap_or(0_hdl_i14) << 2).cast_to_static();
let invert_src2_eq_zero = !use_eq_for_ctr_compare; let invert_src2_eq_zero = !use_eq_for_ctr_compare;
let pc_relative = match aa { let pc_relative = match aa {
@ -659,7 +659,7 @@ impl DecodeState<'_> {
branch_mop, branch_mop,
BranchMOp::branch_i( BranchMOp::branch_i(
dest, dest,
[MOpRegNum::const_zero(), src1], src1,
imm.cast_to_static::<SInt<_>>(), imm.cast_to_static::<SInt<_>>(),
pc_relative, pc_relative,
lk, lk,
@ -671,7 +671,8 @@ impl DecodeState<'_> {
branch_mop, branch_mop,
BranchMOp::branch_ctr( BranchMOp::branch_ctr(
dest, dest,
[MOpRegNum::const_zero(), src1, branch_ctr_reg], src1,
branch_ctr_reg.value,
imm, imm,
invert_src2_eq_zero, invert_src2_eq_zero,
pc_relative, pc_relative,
@ -684,7 +685,7 @@ impl DecodeState<'_> {
branch_mop, branch_mop,
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
dest, dest,
[cr_field, src1, branch_ctr_reg], [cr_field.value, src1, branch_ctr_reg.value],
imm, imm,
!expected_cr_bit_value, !expected_cr_bit_value,
condition_mode, condition_mode,
@ -712,7 +713,10 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []), MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []),
[MOpRegNum::power_isa_ctr_reg(), MOpRegNum::const_zero()], [
MOpRegNum::power_isa_ctr_reg().value,
MOpRegNum::const_zero().value,
],
(-1).cast_to_static::<SInt<_>>(), (-1).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -785,7 +789,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new([bt_reg], []), MOpDestReg::new([bt_reg], []),
[ba_reg, bb_reg, bt_reg], [ba_reg.value, bb_reg.value, bt_reg.value],
#[hdl] #[hdl]
LogicalFlagsMOpImm { LogicalFlagsMOpImm {
src0_start: src0_start.cast_to(LogicalFlagsMOpImm.src0_start), src0_start: src0_start.cast_to(LogicalFlagsMOpImm.src0_start),
@ -811,7 +815,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[crf(bfa)], [crf(bfa).value],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
), ),
); );
@ -888,7 +892,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[MOpRegNum::const_zero(); 2], [MOpRegNum::const_zero().value; 2],
d, d,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -902,7 +906,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra), MOpRegNum::const_zero()], [gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
d, d,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -914,7 +918,12 @@ impl DecodeState<'_> {
} }
connect( connect(
this.output[1], this.output[1],
LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion), LoadMOp::load(
MOpDestReg::new([gpr(rt)], []),
[ea_reg.value],
width,
conversion,
),
); );
}, },
); );
@ -930,7 +939,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra), gpr(rb)], [gpr_or_zero(ra).value, gpr(rb).value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -941,7 +950,12 @@ impl DecodeState<'_> {
); );
connect( connect(
this.output[1], this.output[1],
LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion), LoadMOp::load(
MOpDestReg::new([gpr(rt)], []),
[ea_reg.value],
width,
conversion,
),
); );
}); });
} else if self.arguments == Some("RT,disp(RA)") { } else if self.arguments == Some("RT,disp(RA)") {
@ -955,7 +969,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra), MOpRegNum::const_zero()], [gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
(ds << 2).cast_to_static::<SInt<_>>(), (ds << 2).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -966,7 +980,12 @@ impl DecodeState<'_> {
); );
connect( connect(
this.output[1], this.output[1],
LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion), LoadMOp::load(
MOpDestReg::new([gpr(rt)], []),
[ea_reg.value],
width,
conversion,
),
); );
}); });
} else { } else {
@ -986,7 +1005,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra), MOpRegNum::const_zero()], [gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
d.cast_to_static::<SInt<_>>(), d.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -997,7 +1016,12 @@ impl DecodeState<'_> {
); );
connect( connect(
this.output[1], this.output[1],
LoadMOp::load(MOpDestReg::new([gpr(rt)], []), [ea_reg], width, conversion), LoadMOp::load(
MOpDestReg::new([gpr(rt)], []),
[ea_reg.value],
width,
conversion,
),
); );
}); });
} }
@ -1068,7 +1092,7 @@ impl DecodeState<'_> {
this.output[1], this.output[1],
StoreMOp::store( StoreMOp::store(
MOpDestReg::new([], []), MOpDestReg::new([], []),
[ea_reg, gpr(rs)], [ea_reg.value, gpr(rs).value],
width, width,
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
), ),
@ -1083,7 +1107,7 @@ impl DecodeState<'_> {
this.output[2], this.output[2],
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new([gpr(ra)], []), MOpDestReg::new([gpr(ra)], []),
[ea_reg], [ea_reg.value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
); );
@ -1102,7 +1126,7 @@ impl DecodeState<'_> {
insn, insn,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[MOpRegNum::const_zero(); 2], [MOpRegNum::const_zero().value; 2],
d, d,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1116,7 +1140,7 @@ impl DecodeState<'_> {
insn, insn,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra), MOpRegNum::const_zero()], [gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
d, d,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1137,7 +1161,7 @@ impl DecodeState<'_> {
insn, insn,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra), gpr(rb)], [gpr_or_zero(ra).value, gpr(rb).value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1155,7 +1179,7 @@ impl DecodeState<'_> {
insn, insn,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra), MOpRegNum::const_zero()], [gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
(ds << 2).cast_to_static::<SInt<_>>(), (ds << 2).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1179,7 +1203,7 @@ impl DecodeState<'_> {
insn, insn,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([ea_reg], []), MOpDestReg::new([ea_reg], []),
[gpr_or_zero(ra), MOpRegNum::const_zero()], [gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
d.cast_to_static::<SInt<_>>(), d.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1206,7 +1230,7 @@ impl DecodeState<'_> {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([gpr(rt)], []), MOpDestReg::new([gpr(rt)], []),
#[hdl] #[hdl]
[gpr_or_zero(ra), MOpRegNum::const_zero()], [gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
si.cast_to_static(), si.cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1229,7 +1253,7 @@ impl DecodeState<'_> {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([gpr(rt)], []), MOpDestReg::new([gpr(rt)], []),
#[hdl] #[hdl]
[gpr_or_zero(ra), MOpRegNum::const_zero()], [gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
((si0 << 16) + si1.cast_to(SInt[34])).cast_to_static(), ((si0 << 16) + si1.cast_to(SInt[34])).cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1256,7 +1280,7 @@ impl DecodeState<'_> {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([gpr(rt)], []), MOpDestReg::new([gpr(rt)], []),
#[hdl] #[hdl]
[gpr_or_zero(ra), MOpRegNum::const_zero()], [gpr_or_zero(ra).value, MOpRegNum::const_zero().value],
(si << 16).cast_to_static(), (si << 16).cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1283,7 +1307,7 @@ impl DecodeState<'_> {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new([gpr(rt)], []), MOpDestReg::new([gpr(rt)], []),
#[hdl] #[hdl]
[MOpRegNum::const_zero(); 2], [MOpRegNum::const_zero().value; 2],
(4i8 + (d << 16)).cast_to_static(), (4i8 + (d << 16)).cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1316,7 +1340,7 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[gpr(ra), gpr(rb), MOpRegNum::const_zero()], [gpr(ra).value, gpr(rb).value, MOpRegNum::const_zero().value],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1347,7 +1371,7 @@ impl DecodeState<'_> {
)], )],
), ),
#[hdl] #[hdl]
[gpr(ra), MOpRegNum::const_zero()], [gpr(ra).value, MOpRegNum::const_zero().value],
si.cast_to_static(), si.cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1386,7 +1410,7 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[gpr(ra), gpr(rb), MOpRegNum::const_zero()], [gpr(ra).value, gpr(rb).value, MOpRegNum::const_zero().value],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
true, true,
@ -1416,7 +1440,7 @@ impl DecodeState<'_> {
)], )],
), ),
#[hdl] #[hdl]
[gpr(ra), MOpRegNum::const_zero()], [gpr(ra).value, MOpRegNum::const_zero().value],
si.cast_to_static(), si.cast_to_static(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
true, true,
@ -1448,7 +1472,7 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[gpr(ra), gpr(rb), MOpRegNum::const_zero()], [gpr(ra).value, gpr(rb).value, MOpRegNum::const_zero().value],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1481,7 +1505,11 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg(), gpr(rb)], [
gpr(ra).value,
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
gpr(rb).value,
],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -1514,7 +1542,11 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg(), gpr(rb)], [
gpr(ra).value,
MOpRegNum::power_isa_xer_ca_ca32_reg().value,
gpr(rb).value,
],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
true, true,
@ -1548,9 +1580,9 @@ impl DecodeState<'_> {
), ),
#[hdl] #[hdl]
[ [
gpr(ra), gpr(ra).value,
MOpRegNum::power_isa_xer_ca_ca32_reg(), MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
if this.mnemonic.contains('m') { -1i8 } else { 0 } if this.mnemonic.contains('m') { -1i8 } else { 0 }
.cast_to_static::<SInt<_>>(), .cast_to_static::<SInt<_>>(),
@ -1585,7 +1617,11 @@ impl DecodeState<'_> {
], ],
), ),
#[hdl] #[hdl]
[gpr(ra), MOpRegNum::const_zero(), MOpRegNum::const_zero()], [
gpr(ra).value,
MOpRegNum::const_zero().value,
MOpRegNum::const_zero().value,
],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
true, true,
@ -1618,7 +1654,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra)], [gpr(ra).value],
si.cast_to_static::<SInt<_>>(), si.cast_to_static::<SInt<_>>(),
compare_mode, compare_mode,
), ),
@ -1646,7 +1682,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra), gpr(rb)], [gpr(ra).value, gpr(rb).value],
compare_mode, compare_mode,
), ),
); );
@ -1673,7 +1709,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra)], [gpr(ra).value],
ui.cast_to_static::<SInt<_>>(), ui.cast_to_static::<SInt<_>>(),
compare_mode, compare_mode,
), ),
@ -1701,7 +1737,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra), gpr(rb)], [gpr(ra).value, gpr(rb).value],
compare_mode, compare_mode,
), ),
); );
@ -1728,7 +1764,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra), gpr(rb)], [gpr(ra).value, gpr(rb).value],
compare_mode, compare_mode,
), ),
); );
@ -1747,7 +1783,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[gpr(ra), gpr(rb)], [gpr(ra).value, gpr(rb).value],
CompareMode.CmpEqB(), CompareMode.CmpEqB(),
), ),
); );
@ -1779,7 +1815,7 @@ impl DecodeState<'_> {
this.mnemonic.contains('.').to_expr(), this.mnemonic.contains('.').to_expr(),
)], )],
), ),
[gpr(rs)], [gpr(rs).value],
if this.mnemonic.contains('s') { if this.mnemonic.contains('s') {
(ui << 16).cast_to_static::<SInt<_>>() (ui << 16).cast_to_static::<SInt<_>>()
} else { } else {
@ -1827,7 +1863,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
LogicalMOp::logical( LogicalMOp::logical(
MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]), MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]),
[gpr(rs), gpr(rb)], [gpr(rs).value, gpr(rb).value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
lut, lut,
@ -1841,7 +1877,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new([gpr(ra)], []), MOpDestReg::new([gpr(ra)], []),
[gpr(rs)], [gpr(rs).value],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
), ),
); );
@ -1870,7 +1906,7 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
LogicalMOp::logical_i( LogicalMOp::logical_i(
MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]), MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]),
[gpr(rs)], [gpr(rs).value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
output_integer_mode, output_integer_mode,
Lut4::from_fn(|a, b| a | b), Lut4::from_fn(|a, b| a | b),
@ -1948,7 +1984,7 @@ impl DecodeState<'_> {
self.output[0], self.output[0],
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]), MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]),
[gpr(rs.0), gpr(rs.0), gpr(rb.0)], [gpr(rs.0).value, gpr(rs.0).value, gpr(rb.0).value],
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
shift_rotate_amount: HdlNone(), shift_rotate_amount: HdlNone(),
@ -1985,20 +2021,20 @@ impl DecodeState<'_> {
self.rotate_dest_logic_op(msb0_mask_begin, msb0_mask_end, fallback_is_src2); self.rotate_dest_logic_op(msb0_mask_begin, msb0_mask_end, fallback_is_src2);
#[hdl] #[hdl]
let rotate_imm_src2 = wire(); let rotate_imm_src2 = wire();
connect(rotate_imm_src2, MOpRegNum::const_zero()); connect(rotate_imm_src2, MOpRegNum::const_zero().value);
// if dest_logic_op is HdlNone, we don't need to read from src2 // if dest_logic_op is HdlNone, we don't need to read from src2
#[hdl] #[hdl]
if let HdlSome(dest_logic_op) = dest_logic_op { if let HdlSome(dest_logic_op) = dest_logic_op {
#[hdl] #[hdl]
if dest_logic_op.fallback_is_src2 { if dest_logic_op.fallback_is_src2 {
connect(rotate_imm_src2, gpr(ra.0)); connect(rotate_imm_src2, gpr(ra.0).value);
} }
} }
connect( connect(
self.output[0], self.output[0],
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]), MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]),
[gpr(rs.0), gpr(rs.0), rotate_imm_src2], [gpr(rs.0).value, gpr(rs.0).value, rotate_imm_src2],
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
shift_rotate_amount: HdlSome(rotate_amount), shift_rotate_amount: HdlSome(rotate_amount),
@ -2148,7 +2184,11 @@ impl DecodeState<'_> {
[gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()], [gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()],
[(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
), ),
[gpr(rs), MOpRegNum::const_zero(), MOpRegNum::const_zero()], [
gpr(rs).value,
MOpRegNum::const_zero().value,
MOpRegNum::const_zero().value,
],
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
shift_rotate_amount: HdlSome(sh.cast_to_static::<UInt<_>>()), shift_rotate_amount: HdlSome(sh.cast_to_static::<UInt<_>>()),
@ -2176,7 +2216,11 @@ impl DecodeState<'_> {
[gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()], [gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()],
[(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
), ),
[gpr(rs), MOpRegNum::const_zero(), MOpRegNum::const_zero()], [
gpr(rs).value,
MOpRegNum::const_zero().value,
MOpRegNum::const_zero().value,
],
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
shift_rotate_amount: HdlSome(sh.rotate_right(1)), shift_rotate_amount: HdlSome(sh.rotate_right(1)),
@ -2214,9 +2258,9 @@ impl DecodeState<'_> {
[(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
), ),
if !is_signed && is_right_shift { if !is_signed && is_right_shift {
[MOpRegNum::const_zero(), gpr(rs), gpr(rb)] [MOpRegNum::const_zero().value, gpr(rs).value, gpr(rb).value]
} else { } else {
[gpr(rs), MOpRegNum::const_zero(), gpr(rb)] [gpr(rs).value, MOpRegNum::const_zero().value, gpr(rb).value]
}, },
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
@ -2252,7 +2296,11 @@ impl DecodeState<'_> {
this.output[0], this.output[0],
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]), MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]),
[gpr(rs), MOpRegNum::const_zero(), MOpRegNum::const_zero()], [
gpr(rs).value,
MOpRegNum::const_zero().value,
MOpRegNum::const_zero().value,
],
#[hdl] #[hdl]
ShiftRotateMOpImm { ShiftRotateMOpImm {
shift_rotate_amount: HdlSome(sh.rotate_right(1)), shift_rotate_amount: HdlSome(sh.rotate_right(1)),
@ -2282,7 +2330,7 @@ impl DecodeState<'_> {
self.output[0], self.output[0],
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new([spr], []), MOpDestReg::new([spr], []),
[gpr(reg)], [gpr(reg).value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
); );
@ -2291,7 +2339,7 @@ impl DecodeState<'_> {
self.output[0], self.output[0],
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new([gpr(reg)], []), MOpDestReg::new([gpr(reg)], []),
[spr], [spr.value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
); );
@ -2307,7 +2355,7 @@ impl DecodeState<'_> {
self.output[0], self.output[0],
ReadSpecialMOp::read_special( ReadSpecialMOp::read_special(
MOpDestReg::new([gpr(reg)], []), MOpDestReg::new([gpr(reg)], []),
[MOpRegNum::const_zero(); 0], [MOpRegNum::const_zero().value; 0],
imm, imm,
), ),
); );
@ -2383,9 +2431,9 @@ impl DecodeState<'_> {
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new([crf(bf)], []), MOpDestReg::new([crf(bf)], []),
[ [
MOpRegNum::power_isa_xer_ca_ca32_reg(), MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::power_isa_xer_so_ov_ov32_reg(), MOpRegNum::power_isa_xer_so_ov_ov32_reg().value,
], ],
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| { LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
let mut dest = PRegFlagsPowerISAView::splat(None); let mut dest = PRegFlagsPowerISAView::splat(None);

694
crates/cpu/src/instruction.rs
View file

File diff suppressed because it is too large Load diff

281
crates/cpu/src/instruction/power_isa.rs
View file

@ -25,206 +25,89 @@ pub struct PowerIsaCrBitNum {
pub bit_in_field: UInt<2>, pub bit_in_field: UInt<2>,
} }
macro_rules! suffix_str_with_0_to_31 { impl MOpRegNum {
($str:literal) => {
suffix_str_with_0_to_31!(
$str,
[
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
23, 24, 25, 26, 27, 28, 29, 30, 31,
]
)
};
($str:literal, [$($num:literal),* $(,)?]) => {
[$(concat!($str, $num)),*]
};
}
const fn fill_names_range<'a>(dest: &mut [Option<&'a str>], range: Range<u32>, src: &[&'a str]) {
assert!((range.end - range.start) as usize == src.len());
let mut i = 0;
while i < src.len() {
dest[i + range.start as usize] = Some(src[i]);
i += 1;
}
}
macro_rules! power_isa_regs {
(
$(
#[name_str = $name_str:literal, expr_fn = $expr_fn:ident, sim_fn = $sim_fn:ident]
$(#[doc = $($doc:tt)*])*
pub const $REG_NUM:ident: u32 = $reg_num_expr:expr;
)*
$(
#[names_fn = |$names_var:ident| $names_body:expr $(,
reg_num_fn = $reg_num_fn_multi:ident,
expr_fn = $expr_fn_multi:ident($fn_multi_arg:ty),
expr_imm_fn = $expr_imm_fn_multi:ident,
sim_fn = $sim_fn_multi:ident,)?
]
$(#[doc = $($doc_multi:tt)*])*
pub const $REG_NUM_MULTI:ident: Range<u32> = $reg_num_multi_expr:expr;
)*
) => {
impl MOpRegNum {
pub const POWER_ISA_REG_NAMES: &[Option<&str>; 1 << Self::WIDTH] = &{
let mut retval = [None; _];
$(retval[Self::$REG_NUM as usize] = Some($name_str);)*
$({
let $names_var = &mut retval;
$names_body
})*
retval
};
$(
$(#[doc = $($doc)*])*
pub const $REG_NUM: u32 = $reg_num_expr;
$(#[doc = $($doc)*])*
#[hdl]
pub fn $expr_fn() -> Expr<Self> {
#[hdl]
Self {
value: Self::$REG_NUM.cast_to_static::<UInt<_>>(),
}
}
$(#[doc = $($doc)*])*
#[hdl]
pub fn $sim_fn() -> SimValue<Self> {
#[hdl(sim)]
Self {
value: Self::$REG_NUM.cast_to_static::<UInt<_>>(),
}
}
)*
$(
$(#[doc = $($doc_multi)*])*
pub const $REG_NUM_MULTI: Range<u32> = $reg_num_multi_expr;
power_isa_regs! {
@helper_fns
#[names_fn = |$names_var| $names_body $(,
reg_num_fn = $reg_num_fn_multi,
expr_fn = $expr_fn_multi($fn_multi_arg),
expr_imm_fn = $expr_imm_fn_multi,
sim_fn = $sim_fn_multi,)?
]
$(#[doc = $($doc_multi)*])*
pub const $REG_NUM_MULTI: Range<u32> = $reg_num_multi_expr;
}
)*
}
};
(
@helper_fns
#[names_fn = |$names_var:ident| $names_body:expr]
$(#[doc = $($doc_multi:tt)*])*
pub const $REG_NUM_MULTI:ident: Range<u32> = $reg_num_multi_expr:expr;
) => {};
(
@helper_fns
#[
names_fn = |$names_var:ident| $names_body:expr,
reg_num_fn = $reg_num_fn_multi:ident,
expr_fn = $expr_fn_multi:ident($fn_multi_arg:ty),
expr_imm_fn = $expr_imm_fn_multi:ident,
sim_fn = $sim_fn_multi:ident,
]
$(#[doc = $($doc_multi:tt)*])*
pub const $REG_NUM_MULTI:ident: Range<u32> = $reg_num_multi_expr:expr;
) => {
$(#[doc = $($doc_multi)*])*
pub const fn $reg_num_fn_multi(index: usize) -> u32 {
range_u32_nth_or_panic(&Self::$REG_NUM_MULTI, index)
}
$(#[doc = $($doc_multi)*])*
#[hdl]
pub fn $expr_fn_multi(input: Expr<$fn_multi_arg>) -> Expr<Self> {
#[hdl]
Self {
value: (Self::$REG_NUM_MULTI.start + input).cast_to_static::<UInt<_>>(),
}
}
$(#[doc = $($doc_multi)*])*
#[hdl]
pub fn $expr_imm_fn_multi(input: usize) -> Expr<Self> {
#[hdl]
Self {
value: Self::$reg_num_fn_multi(input).cast_to_static::<UInt<_>>(),
}
}
$(#[doc = $($doc_multi)*])*
#[hdl]
pub fn $sim_fn_multi(reg_num: &SimValue<$fn_multi_arg>) -> SimValue<Self> {
#[hdl(sim)]
Self {
value: (Self::$REG_NUM_MULTI.start + reg_num).cast_to_static::<UInt<_>>(),
}
}
};
}
power_isa_regs! {
#[name_str = "lr", expr_fn = power_isa_lr_reg, sim_fn = power_isa_lr_reg_sim]
pub const POWER_ISA_LR_REG_NUM: u32 = 1; pub const POWER_ISA_LR_REG_NUM: u32 = 1;
#[name_str = "ctr", expr_fn = power_isa_ctr_reg, sim_fn = power_isa_ctr_reg_sim] #[hdl]
pub fn power_isa_lr_reg() -> Expr<Self> {
#[hdl]
Self {
value: Self::POWER_ISA_LR_REG_NUM.cast_to_static::<UInt<_>>(),
}
}
pub const POWER_ISA_CTR_REG_NUM: u32 = 2; pub const POWER_ISA_CTR_REG_NUM: u32 = 2;
#[name_str = "tar", expr_fn = power_isa_tar_reg, sim_fn = power_isa_tar_reg_sim] #[hdl]
pub fn power_isa_ctr_reg() -> Expr<Self> {
#[hdl]
Self {
value: Self::POWER_ISA_CTR_REG_NUM.cast_to_static::<UInt<_>>(),
}
}
pub const POWER_ISA_TAR_REG_NUM: u32 = 3; pub const POWER_ISA_TAR_REG_NUM: u32 = 3;
#[hdl]
pub fn power_isa_tar_reg() -> Expr<Self> {
#[hdl]
Self {
value: Self::POWER_ISA_TAR_REG_NUM.cast_to_static::<UInt<_>>(),
}
}
#[name_str = "xer[so,ov,ov32]", expr_fn = power_isa_xer_so_ov_ov32_reg, sim_fn = power_isa_xer_so_ov_ov32_reg_sim]
/// SO, OV, and OV32 XER bits -- in [`PRegValue.flags`] /// SO, OV, and OV32 XER bits -- in [`PRegValue.flags`]
/// ///
/// [`PRegValue.flags`]: struct@crate::register::PRegValue /// [`PRegValue.flags`]: struct@crate::register::PRegValue
pub const POWER_ISA_XER_SO_OV_OV32_REG_NUM: u32 = pub const POWER_ISA_XER_SO_OV_OV32_REG_NUM: u32 =
range_u32_nth_or_panic(&Self::FLAG_REG_NUMS, 0); range_u32_nth_or_panic(&Self::FLAG_REG_NUMS, 0);
#[name_str = "xer[ca,ca32]", expr_fn = power_isa_xer_ca_ca32_reg, sim_fn = power_isa_xer_ca_ca32_reg_sim]
/// CA and CA32 XER bits -- in [`PRegValue.flags`] /// CA and CA32 XER bits -- in [`PRegValue.flags`]
/// ///
/// [`PRegValue.flags`]: struct@crate::register::PRegValue /// [`PRegValue.flags`]: struct@crate::register::PRegValue
pub const POWER_ISA_XER_CA_CA32_REG_NUM: u32 = 4; pub const POWER_ISA_XER_CA_CA32_REG_NUM: u32 = 4;
#[name_str = "xer[other]", expr_fn = power_isa_xer_other_reg, sim_fn = power_isa_xer_other_reg_sim]
/// only the XER bits that don't exist in [`PRegValue.flags`] /// only the XER bits that don't exist in [`PRegValue.flags`]
/// ///
/// [`PRegValue.flags`]: struct@crate::register::PRegValue /// [`PRegValue.flags`]: struct@crate::register::PRegValue
pub const POWER_ISA_XER_OTHER_REG_NUM: u32 = 5; pub const POWER_ISA_XER_OTHER_REG_NUM: u32 = 5;
#[name_str = "temp", expr_fn = power_isa_temp_reg, sim_fn = power_isa_temp_reg_sim]
/// used as a temporary for things like computing the effective address before loading/storing memory /// used as a temporary for things like computing the effective address before loading/storing memory
pub const POWER_ISA_TEMP_REG_NUM: u32 = 8; pub const POWER_ISA_TEMP_REG_NUM: u32 = 8;
#[hdl]
pub fn power_isa_temp_reg() -> Expr<Self> {
#[hdl]
Self {
value: Self::POWER_ISA_TEMP_REG_NUM.cast_to_static::<UInt<_>>(),
}
}
/// SO, OV, and OV32 XER bits -- in [`PRegValue.flags`]
///
/// [`PRegValue.flags`]: struct@crate::register::PRegValue
#[hdl]
pub fn power_isa_xer_so_ov_ov32_reg() -> Expr<Self> {
#[hdl]
Self {
value: Self::POWER_ISA_XER_SO_OV_OV32_REG_NUM.cast_to_static::<UInt<_>>(),
}
}
/// CA and CA32 XER bits -- in [`PRegValue.flags`]
///
/// [`PRegValue.flags`]: struct@crate::register::PRegValue
#[hdl]
pub fn power_isa_xer_ca_ca32_reg() -> Expr<Self> {
#[hdl]
Self {
value: Self::POWER_ISA_XER_CA_CA32_REG_NUM.cast_to_static::<UInt<_>>(),
}
}
/// only the XER bits that don't exist in [`PRegValue.flags`]
///
/// [`PRegValue.flags`]: struct@crate::register::PRegValue
#[hdl]
pub fn power_isa_xer_other_reg() -> Expr<Self> {
#[hdl]
Self {
value: Self::POWER_ISA_XER_OTHER_REG_NUM.cast_to_static::<UInt<_>>(),
}
}
#[name_str = "cr0", expr_fn = power_isa_cr_0_reg, sim_fn = power_isa_cr_0_reg_sim]
pub const POWER_ISA_CR_0_REG_NUM: u32 = range_u32_nth_or_panic(&Self::FLAG_REG_NUMS, 1); pub const POWER_ISA_CR_0_REG_NUM: u32 = range_u32_nth_or_panic(&Self::FLAG_REG_NUMS, 1);
#[names_fn = |names| {
fill_names_range(names, Self::POWER_ISA_CR_1_THRU_7_REG_NUMS, &["cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7"]);
}]
pub const POWER_ISA_CR_1_THRU_7_REG_NUMS: Range<u32> = 9..16; pub const POWER_ISA_CR_1_THRU_7_REG_NUMS: Range<u32> = 9..16;
#[
names_fn = |names| {
fill_names_range(names, Self::POWER_ISA_GPR_REG_NUMS, &suffix_str_with_0_to_31!("r"));
},
reg_num_fn = power_isa_gpr_reg_num,
expr_fn = power_isa_gpr_reg(UInt<5>),
expr_imm_fn = power_isa_gpr_reg_imm,
sim_fn = power_isa_gpr_reg_sim,
]
pub const POWER_ISA_GPR_REG_NUMS: Range<u32> = 32..64;
#[
names_fn = |names| {
fill_names_range(names, Self::POWER_ISA_FPR_REG_NUMS, &suffix_str_with_0_to_31!("f"));
},
reg_num_fn = power_isa_fpr_reg_num,
expr_fn = power_isa_fpr_reg(UInt<5>),
expr_imm_fn = power_isa_fpr_reg_imm,
sim_fn = power_isa_fpr_reg_sim,
]
pub const POWER_ISA_FPR_REG_NUMS: Range<u32> = 64..96;
}
impl MOpRegNum {
pub const fn power_isa_cr_reg_num(index: usize) -> u32 { pub const fn power_isa_cr_reg_num(index: usize) -> u32 {
if index == 0 { if index == 0 {
Self::POWER_ISA_CR_0_REG_NUM Self::POWER_ISA_CR_0_REG_NUM
@ -265,6 +148,31 @@ impl MOpRegNum {
} }
} }
pub const POWER_ISA_GPR_REG_NUMS: Range<u32> = 32..64;
pub const fn power_isa_gpr_reg_num(index: usize) -> u32 {
range_u32_nth_or_panic(&Self::POWER_ISA_GPR_REG_NUMS, index)
}
#[hdl]
pub fn power_isa_gpr_reg(reg_num: Expr<UInt<5>>) -> Expr<Self> {
#[hdl]
Self {
value: (Self::POWER_ISA_GPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
}
}
#[hdl]
pub fn power_isa_gpr_reg_imm(index: usize) -> Expr<Self> {
#[hdl]
Self {
value: Self::power_isa_gpr_reg_num(index).cast_to_static::<UInt<_>>(),
}
}
#[hdl]
pub fn power_isa_gpr_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
#[hdl(sim)]
Self {
value: (Self::POWER_ISA_GPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
}
}
pub const fn power_isa_gpr_or_zero_reg_num(index: usize) -> u32 { pub const fn power_isa_gpr_or_zero_reg_num(index: usize) -> u32 {
if index == 0 { if index == 0 {
Self::CONST_ZERO_REG_NUM Self::CONST_ZERO_REG_NUM
@ -300,6 +208,25 @@ impl MOpRegNum {
.cast_to_static::<UInt<_>>(), .cast_to_static::<UInt<_>>(),
} }
} }
pub const POWER_ISA_FPR_REG_NUMS: Range<u32> = 64..96;
pub const fn power_isa_fpr_reg_num(index: usize) -> u32 {
range_u32_nth_or_panic(&Self::POWER_ISA_FPR_REG_NUMS, index)
}
#[hdl]
pub fn power_isa_fpr_reg(reg_num: Expr<UInt<5>>) -> Expr<Self> {
#[hdl]
Self {
value: (Self::POWER_ISA_FPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
}
}
#[hdl]
pub fn power_isa_fpr_reg_sim(reg_num: &SimValue<UInt<5>>) -> SimValue<Self> {
#[hdl(sim)]
Self {
value: (Self::POWER_ISA_FPR_REG_NUMS.start + reg_num).cast_to_static::<UInt<_>>(),
}
}
} }
#[hdl(cmp_eq)] #[hdl(cmp_eq)]

58
crates/cpu/src/register.rs
View file

@ -6,7 +6,7 @@ use fayalite::{
expr::CastToImpl, expr::CastToImpl,
int::{BoolOrIntType, UIntInRange}, int::{BoolOrIntType, UIntInRange},
prelude::*, prelude::*,
ty::{SimValueDebug, StaticType}, ty::StaticType,
}; };
use std::{any::Any, fmt}; use std::{any::Any, fmt};
@ -49,7 +49,6 @@ pub trait PRegFlagsViewTrait: Type + PRegFlagsViewTraitSealed {
fn view_into_view_unused<T>(view: Self::View<T>) -> ViewUnused<T, PRegFlagsAllUnused>; fn view_into_view_unused<T>(view: Self::View<T>) -> ViewUnused<T, PRegFlagsAllUnused>;
fn debug_fmt<'a, T: 'a, F: FnMut(&'a T, bool) -> Option<D>, D: fmt::Debug>( fn debug_fmt<'a, T: 'a, F: FnMut(&'a T, bool) -> Option<D>, D: fmt::Debug>(
view: &'a Self::View<T>, view: &'a Self::View<T>,
type_name: Option<&str>,
field: F, field: F,
f: &mut fmt::Formatter<'_>, f: &mut fmt::Formatter<'_>,
) -> fmt::Result; ) -> fmt::Result;
@ -476,7 +475,6 @@ macro_rules! impl_view_trait {
fn debug_fmt<'a, T: 'a, F: FnMut(&'a T, bool) -> Option<D>, D: fmt::Debug>( fn debug_fmt<'a, T: 'a, F: FnMut(&'a T, bool) -> Option<D>, D: fmt::Debug>(
view: &'a Self::View<T>, view: &'a Self::View<T>,
type_name: Option<&str>,
mut field: F, mut field: F,
f: &mut fmt::Formatter<'_>, f: &mut fmt::Formatter<'_>,
) -> fmt::Result { ) -> fmt::Result {
@ -484,7 +482,7 @@ macro_rules! impl_view_trait {
$unused: ViewUnused([$($unused_field,)*]), $unused: ViewUnused([$($unused_field,)*]),
$($view_field: $flags_field,)* $($view_field: $flags_field,)*
} = view; } = view;
let mut debug_struct = f.debug_struct(type_name.unwrap_or(stringify!($FlagsMode))); let mut debug_struct = f.debug_struct(stringify!($FlagsMode));
#[allow(unused_mut)] #[allow(unused_mut)]
let mut any_skipped = false; let mut any_skipped = false;
$(if let Some(v) = field($flags_field, true) { $(if let Some(v) = field($flags_field, true) {
@ -776,40 +774,25 @@ impl<T: Type> PRegFlags<T> {
#[hdl] #[hdl]
pub fn debug_fmt<V: PRegFlagsViewTrait>( pub fn debug_fmt<V: PRegFlagsViewTrait>(
this: &SimValue<Self>, this: &SimValue<Self>,
type_name: Option<&str>,
f: &mut fmt::Formatter<'_>, f: &mut fmt::Formatter<'_>,
) -> fmt::Result { ) -> fmt::Result {
if let Some(this) = <dyn Any>::downcast_ref::<SimValue<PRegFlags>>(this) { if let Some(this) = <dyn Any>::downcast_ref::<SimValue<PRegFlags>>(this) {
V::debug_fmt( V::debug_fmt(
&PRegFlags::view_sim_ref::<V>(this), &PRegFlags::view_sim_ref::<V>(this),
type_name,
|v, _| v.then_some(*v), |v, _| v.then_some(*v),
f, f,
) )
} else { } else {
V::debug_fmt( V::debug_fmt(&PRegFlags::view_sim_ref::<V>(this), |v, _| Some(*v), f)
&PRegFlags::view_sim_ref::<V>(this),
type_name,
|v, _| Some(*v),
f,
)
} }
} }
#[hdl] #[hdl]
pub fn debug_fmt_mode( pub fn debug_fmt_mode(this: &SimValue<Self>, mode: &SimValue<FlagsMode>) -> impl fmt::Debug {
this: &SimValue<Self>,
short_name: bool,
mode: &SimValue<FlagsMode>,
) -> impl fmt::Debug {
fmt::from_fn(move |f| { fmt::from_fn(move |f| {
#[hdl(sim)] #[hdl(sim)]
match mode { match mode {
FlagsMode::PowerISA(_) => { FlagsMode::PowerISA(_) => Self::debug_fmt::<PRegFlagsPowerISA>(this, f),
Self::debug_fmt::<PRegFlagsPowerISA>(this, short_name.then_some("Pwr"), f) FlagsMode::X86(_) => Self::debug_fmt::<PRegFlagsX86>(this, f),
}
FlagsMode::X86(_) => {
Self::debug_fmt::<PRegFlagsX86>(this, short_name.then_some("X86"), f)
}
} }
}) })
} }
@ -836,7 +819,7 @@ impl PRegFlags {
pub const FLAG_COUNT: usize = PRegFlagsAllUnused::UNUSED_INNER_LEN; pub const FLAG_COUNT: usize = PRegFlagsAllUnused::UNUSED_INNER_LEN;
} }
#[hdl(cmp_eq, custom_debug(sim))] #[hdl(cmp_eq)]
/// Unit output register's value -- a combination of an integer/fp register /// Unit output register's value -- a combination of an integer/fp register
/// and flags register and CR field. /// and flags register and CR field.
/// ///
@ -847,15 +830,6 @@ pub struct PRegValue {
pub flags: PRegFlags, pub flags: PRegFlags,
} }
impl SimValueDebug for PRegValue {
fn sim_value_debug(
value: &<Self as Type>::SimValue,
f: &mut fmt::Formatter<'_>,
) -> fmt::Result {
fmt::Debug::fmt(&Self::debug_fmt::<PRegFlagsPowerISA>(value, Some("Pwr")), f)
}
}
impl PRegValue { impl PRegValue {
#[hdl] #[hdl]
pub fn zeroed() -> Expr<Self> { pub fn zeroed() -> Expr<Self> {
@ -874,10 +848,7 @@ impl PRegValue {
} }
} }
#[hdl] #[hdl]
pub fn debug_fmt<V: PRegFlagsViewTrait>( pub fn debug_fmt<V: PRegFlagsViewTrait>(this: &SimValue<Self>) -> impl fmt::Debug {
this: &<Self as Type>::SimValue,
flags_type_name: Option<&str>,
) -> impl fmt::Debug {
fmt::from_fn(move |f| { fmt::from_fn(move |f| {
#[hdl(sim)] #[hdl(sim)]
let Self { int_fp, flags } = this; let Self { int_fp, flags } = this;
@ -885,26 +856,19 @@ impl PRegValue {
.field("int_fp", int_fp) .field("int_fp", int_fp)
.field( .field(
"flags", "flags",
&fmt::from_fn(|f| PRegFlags::debug_fmt::<V>(flags, flags_type_name, f)), &fmt::from_fn(|f| PRegFlags::debug_fmt::<V>(flags, f)),
) )
.finish() .finish()
}) })
} }
#[hdl] #[hdl]
pub fn debug_fmt_mode( pub fn debug_fmt_mode(this: &SimValue<Self>, mode: &SimValue<FlagsMode>) -> impl fmt::Debug {
this: &SimValue<Self>,
flags_short_name: bool,
mode: &SimValue<FlagsMode>,
) -> impl fmt::Debug {
fmt::from_fn(move |f| { fmt::from_fn(move |f| {
#[hdl(sim)] #[hdl(sim)]
let Self { int_fp, flags } = this; let Self { int_fp, flags } = this;
f.debug_struct("PRegValue") f.debug_struct("PRegValue")
.field("int_fp", int_fp) .field("int_fp", int_fp)
.field( .field("flags", &PRegFlags::debug_fmt_mode(flags, mode))
"flags",
&PRegFlags::debug_fmt_mode(flags, flags_short_name, mode),
)
.finish() .finish()
}) })
} }

95
crates/cpu/src/rename_execute_retire.rs
View file

@ -6,8 +6,8 @@
use crate::{ use crate::{
config::{ config::{
CpuConfig, CpuConfig2PowOutRegNumWidth, CpuConfigFetchWidth, CpuConfigRobSize, CpuConfig, CpuConfig2PowOutRegNumWidth, CpuConfigFetchWidth, CpuConfigPRegNumWidth,
CpuConfigUnitCount, PhantomConstCpuConfig, TwiceCpuConfigFetchWidth, CpuConfigRobSize, CpuConfigUnitCount, PhantomConstCpuConfig, TwiceCpuConfigFetchWidth,
}, },
instruction::{ instruction::{
COMMON_MOP_SRC_LEN, L2RegNum, L2RegisterFileMOp, MOp, MOpDestReg, MOpRegNum, MOpTrait, COMMON_MOP_SRC_LEN, L2RegNum, L2RegisterFileMOp, MOp, MOpDestReg, MOpRegNum, MOpTrait,
@ -118,7 +118,10 @@ pub struct RetireToNextPcInterface<C: PhantomConstGet<CpuConfig>> {
#[hdl] #[hdl]
pub type RenamedMOp<C: PhantomConstGet<CpuConfig>> = pub type RenamedMOp<C: PhantomConstGet<CpuConfig>> =
crate::instruction::RenamedMOp<PRegNum<C>, PRegNum<C>>; crate::instruction::RenamedMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>;
#[hdl]
pub type RenamedSrcRegUInt<C: PhantomConstGet<CpuConfig>> = UIntType<CpuConfigPRegNumWidth<C>>;
/// Enqueues happen in program order, they are not re-ordered by out-of-order execution. /// Enqueues happen in program order, they are not re-ordered by out-of-order execution.
/// the whole `MOpInstance` is sent again in [`UnitInputsReady`] so Units can just ignore all /// the whole `MOpInstance` is sent again in [`UnitInputsReady`] so Units can just ignore all
@ -570,7 +573,7 @@ struct RobEntryDebugState<C: PhantomConstGet<CpuConfig>> {
mop: MOpInstance<RenamedMOp<C>>, mop: MOpInstance<RenamedMOp<C>>,
mop_in_unit_state: SimOnlyMOpInUnitState, mop_in_unit_state: SimOnlyMOpInUnitState,
is_speculative: Bool, is_speculative: Bool,
output: HdlOption<NextPcPredictorOp<C>>, finished: HdlOption<NextPcPredictorOp<C>>,
caused_cancel: HdlOption<UnitCausedCancel<C>>, caused_cancel: HdlOption<UnitCausedCancel<C>>,
} }
@ -581,7 +584,7 @@ impl<C: PhantomConstCpuConfig> SimValueDefault for RobEntryDebugState<C> {
mop, mop,
mop_in_unit_state: _, mop_in_unit_state: _,
is_speculative: _, is_speculative: _,
output, finished,
caused_cancel, caused_cancel,
} = self; } = self;
#[hdl(sim)] #[hdl(sim)]
@ -589,8 +592,8 @@ impl<C: PhantomConstCpuConfig> SimValueDefault for RobEntryDebugState<C> {
mop: zeroed(mop), mop: zeroed(mop),
mop_in_unit_state: SimOnlyValue::default(), mop_in_unit_state: SimOnlyValue::default(),
is_speculative: false, is_speculative: false,
output: #[hdl(sim)] finished: #[hdl(sim)]
output.HdlNone(), finished.HdlNone(),
caused_cancel: #[hdl(sim)] caused_cancel: #[hdl(sim)]
caused_cancel.HdlNone(), caused_cancel.HdlNone(),
} }
@ -602,7 +605,7 @@ struct RobEntry<C: PhantomConstCpuConfig> {
mop: SimValue<MOpInstance<RenamedMOp<C>>>, mop: SimValue<MOpInstance<RenamedMOp<C>>>,
mop_in_unit_state: MOpInUnitState, mop_in_unit_state: MOpInUnitState,
is_speculative: bool, is_speculative: bool,
output: Option<SimValue<NextPcPredictorOp<C>>>, finished: Option<SimValue<NextPcPredictorOp<C>>>,
caused_cancel: Option<SimValue<UnitCausedCancel<C>>>, caused_cancel: Option<SimValue<UnitCausedCancel<C>>>,
} }
@ -612,7 +615,7 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
mop, mop,
mop_in_unit_state: MOpInUnitState::NotYetEnqueued, mop_in_unit_state: MOpInUnitState::NotYetEnqueued,
is_speculative: true, is_speculative: true,
output: None, finished: None,
caused_cancel: None, caused_cancel: None,
} }
} }
@ -637,7 +640,7 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
mop, mop,
mop_in_unit_state, mop_in_unit_state,
is_speculative, is_speculative,
output, finished,
caused_cancel, caused_cancel,
} = self; } = self;
let ret_ty = RobEntryDebugState[config]; let ret_ty = RobEntryDebugState[config];
@ -646,7 +649,7 @@ impl<C: PhantomConstCpuConfig> RobEntry<C> {
mop, mop,
mop_in_unit_state: SimOnlyValue::new(*mop_in_unit_state), mop_in_unit_state: SimOnlyValue::new(*mop_in_unit_state),
is_speculative, is_speculative,
output: output.into_sim_value_with_type(ret_ty.output), finished: finished.into_sim_value_with_type(ret_ty.finished),
caused_cancel: caused_cancel.into_sim_value_with_type(ret_ty.caused_cancel), caused_cancel: caused_cancel.into_sim_value_with_type(ret_ty.caused_cancel),
} }
} }
@ -1044,8 +1047,8 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
let masked_id = rob.mop.id.as_int() as usize & mask; let masked_id = rob.mop.id.as_int() as usize & mask;
**retval[masked_id] = fmt::from_fn(|f| { **retval[masked_id] = fmt::from_fn(|f| {
f.write_str(rob.mop_in_unit_state.debug_str())?; f.write_str(rob.mop_in_unit_state.debug_str())?;
if rob.output.is_some() { if rob.finished.is_some() {
f.write_str("(output)")?; f.write_str("(finished)")?;
} }
if rob.caused_cancel.is_some() { if rob.caused_cancel.is_some() {
f.write_str("(caused cancel)")?; f.write_str("(caused cancel)")?;
@ -1167,7 +1170,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
let PRegNum::<_> { let PRegNum::<_> {
unit_num, unit_num,
unit_out_reg, unit_out_reg,
} = src_reg; } = src_reg.cast_bits_to(PRegNum[self.config]);
if Some(unit_index) == UnitNum::index_sim(&unit_num) { if Some(unit_index) == UnitNum::index_sim(&unit_num) {
allocated_regs[UnitOutRegNum::value_sim(&unit_out_reg)] = true; allocated_regs[UnitOutRegNum::value_sim(&unit_out_reg)] = true;
} }
@ -1256,14 +1259,13 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
let unit_kind = UnitMOp::kind_sim(&insn.mop); let unit_kind = UnitMOp::kind_sim(&insn.mop);
#[hdl(sim)] #[hdl(sim)]
if let MOp::TransformedMove(move_reg_mop) = &insn.mop { if let MOp::TransformedMove(move_reg_mop) = &insn.mop {
let mut src_regs = [MOpRegNum::const_zero_sim()]; let mut src_regs = [MOpRegNum::CONST_ZERO_REG_NUM; 1];
MOpTrait::for_each_src_reg_sim_ref(move_reg_mop, &mut |src_reg, index| { MOpTrait::for_each_src_reg_sim_ref(move_reg_mop, &mut |src_reg, index| {
src_regs[index] = src_reg.clone(); src_regs[index] = src_reg.as_int() as u32;
}); });
let [src_reg] = src_regs; let [src_reg] = src_regs;
let renamed_reg = let renamed_reg = self.rename_table.entries[src_reg as usize].clone();
self.rename_table.entries[MOpRegNum::reg_num_sim(&src_reg) as usize].clone(); println!("moving from {src_reg:#x} renamed: {renamed_reg:?}");
println!("moving from {src_reg:?} renamed: {renamed_reg:?}");
let unrenamed_dest_regs = let unrenamed_dest_regs =
MOpDestReg::regs_sim(MOpTrait::dest_reg_sim_ref(move_reg_mop)); MOpDestReg::regs_sim(MOpTrait::dest_reg_sim_ref(move_reg_mop));
assert!(self.rob.incomplete_back_entry.is_none()); assert!(self.rob.incomplete_back_entry.is_none());
@ -1361,16 +1363,19 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
let mop = MOpTrait::map_regs_sim( let mop = MOpTrait::map_regs_sim(
mop, mop,
&renamed_dest_reg, &renamed_dest_reg,
PRegNum[self.config], CpuConfigPRegNumWidth[self.config],
&mut |src_reg, index| { &mut |src_reg, index| {
let renamed = &self.rename_table.entries[MOpRegNum::reg_num_sim(&src_reg) as usize]; let renamed = &self.rename_table.entries[src_reg.as_int() as usize];
println!("renaming src[{index}] from {src_reg:?} to {renamed:?}"); println!("renaming src[{index}] from {src_reg:?} to {renamed:?}");
#[hdl(sim)] #[hdl(sim)]
match renamed { match renamed {
RenameTableEntry::<_>::L1(v) => v.clone(), RenameTableEntry::<_>::L1(v) => v.cast_to_bits(),
RenameTableEntry::<_>::L2(v) => { RenameTableEntry::<_>::L2(v) => {
needed_load.get_or_insert_with(|| v.clone()); needed_load.get_or_insert_with(|| v.clone());
PRegNum[self.config].const_zero_sim() PRegNum[self.config]
.const_zero()
.cast_to_bits()
.into_sim_value()
} }
} }
}, },
@ -1405,7 +1410,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
is_last_mop_in_insn, is_last_mop_in_insn,
mop: ReadL2RegMOp::read_l2_reg::<RenamedMOp<C>>( mop: ReadL2RegMOp::read_l2_reg::<RenamedMOp<C>>(
dest, dest,
repeat(PRegNum[self.config].const_zero_sim(), ConstUsize), repeat(RenamedSrcRegUInt[self.config].zero(), ConstUsize),
needed_load, needed_load,
), ),
}, },
@ -1495,6 +1500,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
let mut src_values: [_; COMMON_MOP_SRC_LEN] = let mut src_values: [_; COMMON_MOP_SRC_LEN] =
std::array::from_fn(|_| Some(zero_value.clone())); std::array::from_fn(|_| Some(zero_value.clone()));
MOpTrait::for_each_src_reg_sim_ref(&rob.mop.mop, &mut |src_reg, index| { MOpTrait::for_each_src_reg_sim_ref(&rob.mop.mop, &mut |src_reg, index| {
let src_reg = src_reg.cast_bits_to(zero_reg.ty());
#[hdl(sim)] #[hdl(sim)]
let PRegNum::<_> { let PRegNum::<_> {
unit_num, unit_num,
@ -1505,7 +1511,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
[UnitOutRegNum::value_sim(unit_out_reg)] [UnitOutRegNum::value_sim(unit_out_reg)]
.clone(); .clone();
} else { } else {
assert_eq!(*src_reg, zero_reg); assert_eq!(src_reg, zero_reg);
src_values[index] = Some(zeroed(PRegValue)); src_values[index] = Some(zeroed(PRegValue));
} }
}); });
@ -1573,15 +1579,15 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
mop: _, mop: _,
mop_in_unit_state, mop_in_unit_state,
is_speculative: _, is_speculative: _,
output, finished,
caused_cancel, caused_cancel,
} = rob; } = rob;
assert!(output.is_none()); assert!(finished.is_none());
assert!(caused_cancel.is_none()); assert!(caused_cancel.is_none());
let l1_reg = &mut self.l1_reg_file[unit_index][out_reg_index]; let l1_reg = &mut self.l1_reg_file[unit_index][out_reg_index];
assert!(l1_reg.is_none()); assert!(l1_reg.is_none());
*l1_reg = Some(dest_value); *l1_reg = Some(dest_value);
*output = Some(predictor_op); *finished = Some(predictor_op);
*mop_in_unit_state = mop_in_unit_state *mop_in_unit_state = mop_in_unit_state
.after_output_ready() .after_output_ready()
.expect("should be valid state for output to become ready"); .expect("should be valid state for output to become ready");
@ -1602,7 +1608,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
mop: _, mop: _,
mop_in_unit_state, mop_in_unit_state,
is_speculative: _, is_speculative: _,
output, finished,
caused_cancel, caused_cancel,
} = self.rob.renamed_by_id_mut(&id); } = self.rob.renamed_by_id_mut(&id);
assert!(caused_cancel.is_none()); assert!(caused_cancel.is_none());
@ -1622,7 +1628,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
panic!( panic!(
"MOp {id:?} made an invalid attempt to finish/cause a cancel:\n\ "MOp {id:?} made an invalid attempt to finish/cause a cancel:\n\
mop_in_unit_state={mop_in_unit_state:?}\n\ mop_in_unit_state={mop_in_unit_state:?}\n\
output={output:?}\n\ finished={finished:?}\n\
caused_cancel={caused_cancel:?}" caused_cancel={caused_cancel:?}"
); );
} }
@ -1701,7 +1707,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
mop: _, mop: _,
mop_in_unit_state: MOpInUnitState::FinishedAndOrCausedCancel, mop_in_unit_state: MOpInUnitState::FinishedAndOrCausedCancel,
is_speculative: _, is_speculative: _,
output, finished,
caused_cancel, caused_cancel,
} = renamed_entry } = renamed_entry
{ {
@ -1709,7 +1715,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
// only the part before the cancel needs to be ready // only the part before the cancel needs to be ready
break; break;
} }
assert!(output.is_some()); assert!(finished.is_some());
} else { } else {
// group isn't ready // group isn't ready
return retval; return retval;
@ -1746,7 +1752,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
config: self.config, config: self.config,
}; };
for renamed in renamed_entries { for renamed in renamed_entries {
let Some(output) = &renamed.output else { let Some(finished) = &renamed.finished else {
unreachable!(); unreachable!();
}; };
#[hdl(sim)] #[hdl(sim)]
@ -1754,7 +1760,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
call_stack_op, call_stack_op,
cond_br_taken, cond_br_taken,
config: _, config: _,
} = output; } = finished;
#[hdl(sim)] #[hdl(sim)]
if let CallStackOp::None = &unrenamed_op.call_stack_op { if let CallStackOp::None = &unrenamed_op.call_stack_op {
unrenamed_op.call_stack_op = call_stack_op.clone(); unrenamed_op.call_stack_op = call_stack_op.clone();
@ -1832,7 +1838,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
mop: _, mop: _,
mop_in_unit_state, mop_in_unit_state,
is_speculative: _, is_speculative: _,
output: _, finished: _,
caused_cancel, caused_cancel,
} in renamed_entries } in renamed_entries
{ {
@ -1885,7 +1891,7 @@ impl<C: PhantomConstCpuConfig> RenameExecuteRetireState<C> {
mop: _, mop: _,
mop_in_unit_state: MOpInUnitState::FinishedAndOrCausedCancel, mop_in_unit_state: MOpInUnitState::FinishedAndOrCausedCancel,
is_speculative: _, is_speculative: _,
output: _, finished: _,
caused_cancel: Some(caused_cancel), caused_cancel: Some(caused_cancel),
}) = first_renamed }) = first_renamed
&& !*caused_cancel.cancel_after_retire && !*caused_cancel.cancel_after_retire
@ -1995,10 +2001,10 @@ async fn rename_execute_retire_run(
mop: _, mop: _,
mop_in_unit_state, mop_in_unit_state,
is_speculative: _, is_speculative: _,
output, finished,
caused_cancel, caused_cancel,
} = state.rob.renamed_by_id_mut(&enqueue.mop.id); } = state.rob.renamed_by_id_mut(&enqueue.mop.id);
assert!(output.is_none()); assert!(finished.is_none());
assert!(caused_cancel.is_none()); assert!(caused_cancel.is_none());
*mop_in_unit_state = mop_in_unit_state *mop_in_unit_state = mop_in_unit_state
.after_enqueue() .after_enqueue()
@ -2012,10 +2018,10 @@ async fn rename_execute_retire_run(
mop: _, mop: _,
mop_in_unit_state, mop_in_unit_state,
is_speculative: _, is_speculative: _,
output, finished,
caused_cancel, caused_cancel,
} = state.rob.renamed_by_id_mut(&inputs_ready.mop.id); } = state.rob.renamed_by_id_mut(&inputs_ready.mop.id);
assert!(output.is_none()); assert!(finished.is_none());
assert!(caused_cancel.is_none()); assert!(caused_cancel.is_none());
*mop_in_unit_state = mop_in_unit_state *mop_in_unit_state = mop_in_unit_state
.with_inputs_ready() .with_inputs_ready()
@ -2030,9 +2036,11 @@ async fn rename_execute_retire_run(
mop: _, mop: _,
mop_in_unit_state, mop_in_unit_state,
is_speculative: _, is_speculative: _,
output: _, finished,
caused_cancel: _, caused_cancel,
} = state.rob.renamed_by_id_mut(&is_no_longer_speculative.id); } = state.rob.renamed_by_id_mut(&is_no_longer_speculative.id);
assert!(finished.is_none());
assert!(caused_cancel.is_none());
*mop_in_unit_state = mop_in_unit_state *mop_in_unit_state = mop_in_unit_state
.without_speculative() .without_speculative()
.expect("UnitMOpIsNoLongerSpeculative is known to be valid"); .expect("UnitMOpIsNoLongerSpeculative is known to be valid");
@ -2047,9 +2055,10 @@ async fn rename_execute_retire_run(
mop: _, mop: _,
mop_in_unit_state, mop_in_unit_state,
is_speculative: _, is_speculative: _,
output: _, finished,
caused_cancel, caused_cancel,
} = state.rob.renamed_by_id_mut(&id); } = state.rob.renamed_by_id_mut(&id);
assert!(finished.is_none());
assert!(caused_cancel.is_none()); assert!(caused_cancel.is_none());
*mop_in_unit_state = mop_in_unit_state *mop_in_unit_state = mop_in_unit_state
.with_cant_cause_cancel() .with_cant_cause_cancel()

96
crates/cpu/src/unit.rs
View file

@ -5,8 +5,8 @@ use crate::{
config::{CpuConfig, PhantomConstCpuConfig}, config::{CpuConfig, PhantomConstCpuConfig},
instruction::{ instruction::{
AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait, AluBranchMOp, LoadStoreMOp, MOp, MOpDestReg, MOpInto, MOpRegNum, MOpTrait,
MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, PRegNum, RenamedMOp, MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, RenamedMOp, UnitOutRegNum,
UnitOutRegNum, mop_enum, mop_enum,
}, },
register::{FlagsMode, PRegValue}, register::{FlagsMode, PRegValue},
unit::unit_base::UnitToRegAlloc, unit::unit_base::UnitToRegAlloc,
@ -28,7 +28,7 @@ macro_rules! all_units {
#[unit_kind = $UnitKind:ident] #[unit_kind = $UnitKind:ident]
#[hdl(custom_debug(sim))] #[hdl(custom_debug(sim))]
$(#[$enum_meta:meta])* $(#[$enum_meta:meta])*
$vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcReg:ident: Type, #[MOp(get_ty = $transformed_move_op_get_ty:expr)] $TransformedMoveOp:ident: Type> { $vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcRegWidth:ident: Size, #[MOp(get_ty = $transformed_move_op_get_ty:expr)] $TransformedMoveOp:ident: Type> {
$( $(
$(#[transformed_move $($transformed_move:tt)*])? $(#[transformed_move $($transformed_move:tt)*])?
#[create_dyn_unit_fn = $create_dyn_unit_fn:expr] #[create_dyn_unit_fn = $create_dyn_unit_fn:expr]
@ -87,11 +87,11 @@ macro_rules! all_units {
$(#[$enum_meta])* $(#[$enum_meta])*
$vis enum $UnitMOpEnum< $vis enum $UnitMOpEnum<
$DestReg: Type, $DestReg: Type,
$SrcReg: Type, $SrcRegWidth: Size,
#[MOp(get_ty = $transformed_move_op_get_ty)] $TransformedMoveOp: Type, #[MOp(get_ty = $transformed_move_op_get_ty)] $TransformedMoveOp: Type,
#[MOpVisitVariants] [ #[MOpVisitVariants] [
$TransformedMoveOp: MOpVisitVariants<DestReg = $DestReg, SrcReg = $SrcReg>, $TransformedMoveOp: MOpVisitVariants<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
$($Op: MOpVisitVariants<DestReg = $DestReg, SrcReg = $SrcReg>,)* $($Op: MOpVisitVariants<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,)*
] ]
> { > {
$( $(
@ -101,7 +101,7 @@ macro_rules! all_units {
} }
} }
impl<$DestReg: Type, $SrcReg: Type, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcReg, $TransformedMoveOp> { impl<$DestReg: Type, $SrcRegWidth: Size, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcRegWidth, $TransformedMoveOp> {
#[hdl] #[hdl]
$vis fn kind(expr: impl ToExpr<Type = Self>) -> Expr<$HdlUnitKind> { $vis fn kind(expr: impl ToExpr<Type = Self>) -> Expr<$HdlUnitKind> {
#[hdl] #[hdl]
@ -164,18 +164,18 @@ macro_rules! all_units {
} }
} }
)* )*
$vis fn with_transformed_move_op_ty<T>(self, new_transformed_move_op_ty: T) -> $UnitMOpEnum<$DestReg, $SrcReg, T> $vis fn with_transformed_move_op_ty<T>(self, new_transformed_move_op_ty: T) -> $UnitMOpEnum<$DestReg, $SrcRegWidth, T>
where where
T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>, T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>, $TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
{ {
$UnitMOpEnum[self.dest_reg_ty()][self.src_reg_ty()][new_transformed_move_op_ty] $UnitMOpEnum[self.dest_reg_ty()][self.src_reg_width()][new_transformed_move_op_ty]
} }
} }
all_units! { all_units! {
@split_by_transformed_move @split_by_transformed_move
$vis enum $UnitMOpEnum<$DestReg: Type, $SrcReg: Type, $TransformedMoveOp: Type> { $vis enum $UnitMOpEnum<$DestReg: Type, $SrcRegWidth: Size, $TransformedMoveOp: Type> {
$( $(
$(#[transformed_move $($transformed_move)*])? $(#[transformed_move $($transformed_move)*])?
$Unit($Op), $Unit($Op),
@ -200,23 +200,23 @@ macro_rules! all_units {
}; };
( (
@split_by_transformed_move @split_by_transformed_move
$vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcReg:ident: Type, $TransformedMoveOp:ident: Type> { $vis:vis enum $UnitMOpEnum:ident<$DestReg:ident: Type, $SrcRegWidth:ident: Size, $TransformedMoveOp:ident: Type> {
$($BeforeUnit:ident($BeforeOp:ty),)* $($BeforeUnit:ident($BeforeOp:ty),)*
#[transformed_move] #[transformed_move]
$TransformedMove:ident($TransformedMoveOp2:ty), $TransformedMove:ident($TransformedMoveOp2:ty),
$($AfterUnit:ident($AfterOp:ty),)* $($AfterUnit:ident($AfterOp:ty),)*
} }
) => { ) => {
impl<$DestReg: Type, $SrcReg: Type, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcReg, $TransformedMoveOp> { impl<$DestReg: Type, $SrcRegWidth: Size, $TransformedMoveOp: Type> $UnitMOpEnum<$DestReg, $SrcRegWidth, $TransformedMoveOp> {
#[hdl] #[hdl]
$vis fn try_with_transformed_move_op<T>( $vis fn try_with_transformed_move_op<T>(
this: impl ToExpr<Type = Self>, this: impl ToExpr<Type = Self>,
new_transformed_move_op_ty: T, new_transformed_move_op_ty: T,
connect_transformed_move_op: impl FnOnce(Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcReg, T>>>, Expr<$TransformedMoveOp>), connect_transformed_move_op: impl FnOnce(Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>>, Expr<$TransformedMoveOp>),
) -> Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcReg, T>>> ) -> Expr<HdlOption<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>>
where where
T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>, T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>, $TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
{ {
let this = this.to_expr(); let this = this.to_expr();
let new_ty = this.ty().with_transformed_move_op_ty(new_transformed_move_op_ty); let new_ty = this.ty().with_transformed_move_op_ty(new_transformed_move_op_ty);
@ -237,11 +237,11 @@ macro_rules! all_units {
$vis fn try_with_transformed_move_op_sim<T, E>( $vis fn try_with_transformed_move_op_sim<T, E>(
this: impl ToSimValue<Type = Self>, this: impl ToSimValue<Type = Self>,
new_transformed_move_op_ty: T, new_transformed_move_op_ty: T,
f: impl FnOnce(SimValue<$TransformedMoveOp>) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>>, E>, f: impl FnOnce(SimValue<$TransformedMoveOp>) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>, E>,
) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>>, E> ) -> Result<SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>, E>
where where
T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>, T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>, $TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
{ {
#![allow(unreachable_patterns)] #![allow(unreachable_patterns)]
let this = this.into_sim_value(); let this = this.into_sim_value();
@ -263,11 +263,11 @@ macro_rules! all_units {
$vis fn with_transformed_move_op_sim<T>( $vis fn with_transformed_move_op_sim<T>(
this: impl ToSimValue<Type = Self>, this: impl ToSimValue<Type = Self>,
new_transformed_move_op_ty: T, new_transformed_move_op_ty: T,
f: impl FnOnce(SimValue<$TransformedMoveOp>) -> SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>>, f: impl FnOnce(SimValue<$TransformedMoveOp>) -> SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>,
) -> SimValue<$UnitMOpEnum<$DestReg, $SrcReg, T>> ) -> SimValue<$UnitMOpEnum<$DestReg, $SrcRegWidth, T>>
where where
T: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>, T: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
$TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcReg = $SrcReg>, $TransformedMoveOp: MOpTrait<DestReg = $DestReg, SrcRegWidth = $SrcRegWidth>,
{ {
let Ok::<_, std::convert::Infallible>(retval) = Self::try_with_transformed_move_op_sim(this, new_transformed_move_op_ty, move |v| Ok(f(v))); let Ok::<_, std::convert::Infallible>(retval) = Self::try_with_transformed_move_op_sim(this, new_transformed_move_op_ty, move |v| Ok(f(v)));
retval retval
@ -277,7 +277,7 @@ macro_rules! all_units {
const _: () = { const _: () = {
#[hdl] #[hdl]
type $DestReg = MOpDestReg; type $DestReg = MOpDestReg;
type $SrcReg = MOpRegNum; type $SrcRegWidth = ConstUsize<{ MOpRegNum::WIDTH }>;
$(impl MOpInto<MOp> for $BeforeOp { $(impl MOpInto<MOp> for $BeforeOp {
fn mop_into_ty(self) -> MOp { fn mop_into_ty(self) -> MOp {
@ -298,21 +298,21 @@ macro_rules! all_units {
})* })*
}; };
$(impl<$DestReg: Type, $SrcReg: Type> MOpInto<RenamedMOp<$DestReg, $SrcReg>> for $BeforeOp { $(impl<$DestReg: Type, $SrcRegWidth: Size> MOpInto<RenamedMOp<$DestReg, $SrcRegWidth>> for $BeforeOp {
fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcReg> { fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcRegWidth> {
RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_ty(self)] RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]
} }
fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcReg>> { fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> {
MOpInto::<RenamedMOp<$DestReg, $SrcReg>>::mop_into_ty(this.ty()).$BeforeUnit(this) MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$BeforeUnit(this)
} }
})* })*
$(impl<$DestReg: Type, $SrcReg: Type> MOpInto<RenamedMOp<$DestReg, $SrcReg>> for $AfterOp { $(impl<$DestReg: Type, $SrcRegWidth: Size> MOpInto<RenamedMOp<$DestReg, $SrcRegWidth>> for $AfterOp {
fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcReg> { fn mop_into_ty(self) -> RenamedMOp<$DestReg, $SrcRegWidth> {
RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_ty(self)] RenamedMOp[MOpTrait::dest_reg_ty(self)][MOpTrait::src_reg_width(self)]
} }
fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcReg>> { fn mop_into(this: Expr<Self>) -> Expr<RenamedMOp<$DestReg, $SrcRegWidth>> {
MOpInto::<RenamedMOp<$DestReg, $SrcReg>>::mop_into_ty(this.ty()).$AfterUnit(this) MOpInto::<RenamedMOp<$DestReg, $SrcRegWidth>>::mop_into_ty(this.ty()).$AfterUnit(this)
} }
})* })*
}; };
@ -324,21 +324,21 @@ all_units! {
#[hdl(custom_debug(sim))] #[hdl(custom_debug(sim))]
pub enum UnitMOp< pub enum UnitMOp<
DestReg: Type, DestReg: Type,
SrcReg: Type, SrcRegWidth: Size,
#[MOp(get_ty = |this: UnitMOp<DestReg, SrcReg, TransformedMoveOp>, new_dest_reg, new_src_reg| { #[MOp(get_ty = |this: UnitMOp<DestReg, SrcRegWidth, TransformedMoveOp>, new_dest_reg, new_src_reg_width| {
this.TransformedMove.mapped_ty(new_dest_reg, new_src_reg) this.TransformedMove.mapped_ty(new_dest_reg, new_src_reg_width)
})] TransformedMoveOp: Type })] TransformedMoveOp: Type
> { > {
#[create_dyn_unit_fn = |config, unit_index| alu_branch::AluBranch::new(config, unit_index).to_dyn()] #[create_dyn_unit_fn = |config, unit_index| alu_branch::AluBranch::new(config, unit_index).to_dyn()]
#[extract(alu_branch_mop, alu_branch_mop_sim, alu_branch_mop_sim_ref, alu_branch_mop_sim_mut)] #[extract(alu_branch_mop, alu_branch_mop_sim, alu_branch_mop_sim_ref, alu_branch_mop_sim_mut)]
AluBranch(AluBranchMOp<DestReg, SrcReg>), AluBranch(AluBranchMOp<DestReg, SrcRegWidth>),
#[transformed_move] #[transformed_move]
#[create_dyn_unit_fn = |config, unit_index| todo!()] #[create_dyn_unit_fn = |config, unit_index| todo!()]
#[extract(transformed_move_mop, transformed_move_mop_sim, transformed_move_mop_sim_ref, transformed_move_mop_sim_mut)] #[extract(transformed_move_mop, transformed_move_mop_sim, transformed_move_mop_sim_ref, transformed_move_mop_sim_mut)]
TransformedMove(TransformedMoveOp), TransformedMove(TransformedMoveOp),
#[create_dyn_unit_fn = |config, unit_index| todo!()] #[create_dyn_unit_fn = |config, unit_index| todo!()]
#[extract(load_store_mop, load_store_mop_sim, load_store_mop_sim_ref, load_store_mop_sim_mut)] #[extract(load_store_mop, load_store_mop_sim, load_store_mop_sim_ref, load_store_mop_sim_mut)]
LoadStore(LoadStoreMOp<DestReg, SrcReg>), LoadStore(LoadStoreMOp<DestReg, SrcRegWidth>),
} }
} }
@ -408,9 +408,7 @@ pub trait UnitTrait:
fn extract_mop( fn extract_mop(
&self, &self,
mop: Expr< mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
) -> Expr<HdlOption<Self::MOp>>; ) -> Expr<HdlOption<Self::MOp>>;
fn module(&self) -> Interned<Module<Self::Type>>; fn module(&self) -> Interned<Module<Self::Type>>;
@ -468,9 +466,7 @@ impl UnitTrait for DynUnit {
fn extract_mop( fn extract_mop(
&self, &self,
mop: Expr< mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
) -> Expr<HdlOption<Self::MOp>> { ) -> Expr<HdlOption<Self::MOp>> {
self.unit.extract_mop(mop) self.unit.extract_mop(mop)
} }
@ -525,9 +521,7 @@ impl<T: UnitTrait + Clone + std::hash::Hash + Eq> UnitTrait for DynUnitWrapper<T
fn extract_mop( fn extract_mop(
&self, &self,
mop: Expr< mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
) -> Expr<HdlOption<Self::MOp>> { ) -> Expr<HdlOption<Self::MOp>> {
Expr::from_enum(Expr::as_enum(self.0.extract_mop(mop))) Expr::from_enum(Expr::as_enum(self.0.extract_mop(mop)))
} }

70
crates/cpu/src/unit/alu_branch.rs
View file

@ -5,8 +5,8 @@ use crate::{
config::CpuConfig, config::CpuConfig,
instruction::{ instruction::{
AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOpDefaultImm, AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOpDefaultImm,
CompareMOp, LogicalFlagsMOp, LogicalMOp, MOpTrait, OutputIntegerMode, PRegNum, CompareMOp, LogicalFlagsMOp, LogicalMOp, MOpTrait, OutputIntegerMode, ReadSpecialMOp,
ReadSpecialMOp, RenamedMOp, ShiftRotateMOp, UnitOutRegNum, RenamedMOp, ShiftRotateMOp, UnitOutRegNum,
}, },
register::{ register::{
FlagsMode, PRegFlagsPowerISA, PRegFlagsPowerISAView, PRegFlagsViewTrait, PRegFlagsX86, FlagsMode, PRegFlagsPowerISA, PRegFlagsPowerISAView, PRegFlagsViewTrait, PRegFlagsX86,
@ -25,13 +25,7 @@ use std::{collections::HashMap, ops::RangeTo};
#[hdl] #[hdl]
fn add_sub<SrcCount: KnownSize>( fn add_sub<SrcCount: KnownSize>(
mop: Expr< mop: Expr<AddSubMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, SrcCount>>,
AddSubMOp<
UnitOutRegNum<PhantomConst<CpuConfig>>,
PRegNum<PhantomConst<CpuConfig>>,
SrcCount,
>,
>,
pc: Expr<UInt<64>>, pc: Expr<UInt<64>>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
@ -248,9 +242,7 @@ fn add_sub<SrcCount: KnownSize>(
#[hdl] #[hdl]
fn logical_flags( fn logical_flags(
mop: Expr< mop: Expr<LogicalFlagsMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
LogicalFlagsMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
) -> Expr<UnitResultCompleted<()>> { ) -> Expr<UnitResultCompleted<()>> {
@ -264,13 +256,7 @@ fn logical_flags(
#[hdl] #[hdl]
fn logical( fn logical(
mop: Expr< mop: Expr<LogicalMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, ConstUsize<2>>>,
LogicalMOp<
UnitOutRegNum<PhantomConst<CpuConfig>>,
PRegNum<PhantomConst<CpuConfig>>,
ConstUsize<2>,
>,
>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
) -> Expr<UnitResultCompleted<()>> { ) -> Expr<UnitResultCompleted<()>> {
@ -284,13 +270,7 @@ fn logical(
#[hdl] #[hdl]
fn logical_i( fn logical_i(
mop: Expr< mop: Expr<LogicalMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, ConstUsize<1>>>,
LogicalMOp<
UnitOutRegNum<PhantomConst<CpuConfig>>,
PRegNum<PhantomConst<CpuConfig>>,
ConstUsize<1>,
>,
>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
) -> Expr<UnitResultCompleted<()>> { ) -> Expr<UnitResultCompleted<()>> {
@ -304,9 +284,7 @@ fn logical_i(
#[hdl] #[hdl]
fn shift_rotate( fn shift_rotate(
mop: Expr< mop: Expr<ShiftRotateMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
ShiftRotateMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
) -> Expr<UnitResultCompleted<()>> { ) -> Expr<UnitResultCompleted<()>> {
@ -320,13 +298,7 @@ fn shift_rotate(
#[hdl] #[hdl]
fn compare<SrcCount: KnownSize>( fn compare<SrcCount: KnownSize>(
mop: Expr< mop: Expr<CompareMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, SrcCount>>,
CompareMOp<
UnitOutRegNum<PhantomConst<CpuConfig>>,
PRegNum<PhantomConst<CpuConfig>>,
SrcCount,
>,
>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
) -> Expr<UnitResultCompleted<()>> { ) -> Expr<UnitResultCompleted<()>> {
@ -340,13 +312,7 @@ fn compare<SrcCount: KnownSize>(
#[hdl] #[hdl]
fn branch<SrcCount: KnownSize>( fn branch<SrcCount: KnownSize>(
mop: Expr< mop: Expr<BranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize, SrcCount>>,
BranchMOp<
UnitOutRegNum<PhantomConst<CpuConfig>>,
PRegNum<PhantomConst<CpuConfig>>,
SrcCount,
>,
>,
pc: Expr<UInt<64>>, pc: Expr<UInt<64>>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
@ -361,9 +327,7 @@ fn branch<SrcCount: KnownSize>(
#[hdl] #[hdl]
fn read_special( fn read_special(
mop: Expr< mop: Expr<ReadSpecialMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
ReadSpecialMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
pc: Expr<UInt<64>>, pc: Expr<UInt<64>>,
flags_mode: Expr<FlagsMode>, flags_mode: Expr<FlagsMode>,
src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
@ -383,9 +347,12 @@ pub fn alu_branch(config: PhantomConst<CpuConfig>, unit_index: usize) {
#[hdl] #[hdl]
let unit_to_reg_alloc: UnitToRegAlloc< let unit_to_reg_alloc: UnitToRegAlloc<
PhantomConst<CpuConfig>, PhantomConst<CpuConfig>,
AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>, AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>,
(), (),
> = m.output(UnitToRegAlloc[config][AluBranchMOp[UnitOutRegNum[config]][PRegNum[config]]][()]); > = m.output(
UnitToRegAlloc[config][AluBranchMOp[UnitOutRegNum[config]][config.get().p_reg_num_width()]]
[()],
);
#[hdl] #[hdl]
let global_state: GlobalState = m.input(); let global_state: GlobalState = m.input();
@ -625,8 +592,7 @@ impl AluBranch {
impl UnitTrait for AluBranch { impl UnitTrait for AluBranch {
type Type = alu_branch; type Type = alu_branch;
type ExtraOut = (); type ExtraOut = ();
type MOp = type MOp = AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>;
AluBranchMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>;
fn ty(&self) -> Self::Type { fn ty(&self) -> Self::Type {
self.module.io_ty() self.module.io_ty()
@ -646,9 +612,7 @@ impl UnitTrait for AluBranch {
fn extract_mop( fn extract_mop(
&self, &self,
mop: Expr< mop: Expr<RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, DynSize>>,
RenamedMOp<UnitOutRegNum<PhantomConst<CpuConfig>>, PRegNum<PhantomConst<CpuConfig>>>,
>,
) -> Expr<HdlOption<Self::MOp>> { ) -> Expr<HdlOption<Self::MOp>> {
UnitMOp::alu_branch_mop(mop) UnitMOp::alu_branch_mop(mop)
} }

25
crates/cpu/src/unit/unit_base.rs
View file

@ -234,11 +234,7 @@ impl InFlightOpsSummary<DynSize> {
#[hdl_module] #[hdl_module]
pub fn unit_base< pub fn unit_base<
MOp: Type MOp: Type + MOpTrait<DestReg = UnitOutRegNum<PhantomConst<CpuConfig>>, SrcRegWidth = DynSize>,
+ MOpTrait<
DestReg = UnitOutRegNum<PhantomConst<CpuConfig>>,
SrcReg = PRegNum<PhantomConst<CpuConfig>>,
>,
ExtraOut: Type, ExtraOut: Type,
>( >(
config: PhantomConst<CpuConfig>, config: PhantomConst<CpuConfig>,
@ -286,7 +282,7 @@ pub fn unit_base<
let read_src_regs = wire(mop_ty.src_regs_ty()); let read_src_regs = wire(mop_ty.src_regs_ty());
connect( connect(
read_src_regs, read_src_regs,
repeat(PRegNum[config].const_zero(), ConstUsize), repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize),
); );
#[hdl] #[hdl]
let read_src_values = wire(); let read_src_values = wire();
@ -295,7 +291,7 @@ pub fn unit_base<
let input_src_regs = wire(mop_ty.src_regs_ty()); let input_src_regs = wire(mop_ty.src_regs_ty());
connect( connect(
input_src_regs, input_src_regs,
repeat(PRegNum[config].const_zero(), ConstUsize), repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize),
); );
#[hdl] #[hdl]
let input_src_regs_valid = wire(); let input_src_regs_valid = wire();
@ -321,7 +317,7 @@ pub fn unit_base<
for src_index in 0..COMMON_MOP_SRC_LEN { for src_index in 0..COMMON_MOP_SRC_LEN {
let read_port = unit_output_regs.new_read_port(); let read_port = unit_output_regs.new_read_port();
let p_reg_num = read_src_regs[src_index]; let p_reg_num = read_src_regs[src_index].cast_bits_to(PRegNum[config]);
connect_any(read_port.addr, p_reg_num.unit_out_reg.value); connect_any(read_port.addr, p_reg_num.unit_out_reg.value);
connect(read_port.en, false); connect(read_port.en, false);
connect(read_port.clk, cd.clk); connect(read_port.clk, cd.clk);
@ -334,7 +330,7 @@ pub fn unit_base<
for src_index in 0..COMMON_MOP_SRC_LEN { for src_index in 0..COMMON_MOP_SRC_LEN {
let read_port = unit_output_regs_valid[unit_index].new_read_port(); let read_port = unit_output_regs_valid[unit_index].new_read_port();
let p_reg_num = input_src_regs[src_index]; let p_reg_num = input_src_regs[src_index].cast_bits_to(PRegNum[config]);
connect_any(read_port.addr, p_reg_num.unit_out_reg.value); connect_any(read_port.addr, p_reg_num.unit_out_reg.value);
connect(read_port.en, false); connect(read_port.en, false);
connect(read_port.clk, cd.clk); connect(read_port.clk, cd.clk);
@ -371,7 +367,7 @@ pub fn unit_base<
}; };
for src_index in 0..COMMON_MOP_SRC_LEN { for src_index in 0..COMMON_MOP_SRC_LEN {
#[hdl] #[hdl]
if input_src_regs[src_index].cmp_eq(p_reg_num) { if input_src_regs[src_index].cmp_eq(p_reg_num.cast_to_bits()) {
connect(input_src_regs_valid[src_index], true); connect(input_src_regs_valid[src_index], true);
} }
} }
@ -424,7 +420,7 @@ pub fn unit_base<
let input_mop_src_regs = wire(mop_ty.src_regs_ty()); let input_mop_src_regs = wire(mop_ty.src_regs_ty());
connect( connect(
input_mop_src_regs, input_mop_src_regs,
repeat(PRegNum[config].const_zero(), ConstUsize), repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize),
); );
MOp::connect_src_regs(mop, input_mop_src_regs); MOp::connect_src_regs(mop, input_mop_src_regs);
let src_ready_flags = wire_with_loc( let src_ready_flags = wire_with_loc(
@ -494,7 +490,10 @@ pub fn unit_base<
SourceLocation::caller(), SourceLocation::caller(),
mop_ty.src_regs_ty(), mop_ty.src_regs_ty(),
); );
connect(src_regs, repeat(PRegNum[config].const_zero(), ConstUsize)); connect(
src_regs,
repeat(PRegNum[config].const_zero().cast_to_bits(), ConstUsize),
);
MOp::connect_src_regs(mop, src_regs); MOp::connect_src_regs(mop, src_regs);
#[hdl] #[hdl]
@ -523,7 +522,7 @@ pub fn unit_base<
}; };
for src_index in 0..COMMON_MOP_SRC_LEN { for src_index in 0..COMMON_MOP_SRC_LEN {
#[hdl] #[hdl]
if p_reg_num.cmp_eq(src_regs[src_index]) { if p_reg_num.cast_to_bits().cmp_eq(src_regs[src_index]) {
connect( connect(
in_flight_op_next_src_ready_flags[in_flight_op_index][src_index], in_flight_op_next_src_ready_flags[in_flight_op_index][src_index],
true, true,

260685
crates/cpu/tests/expected/rename_execute_retire_fibonacci.vcd generated
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File diff suppressed because it is too large Load diff

253726
crates/cpu/tests/expected/rename_execute_retire_slow_loop.vcd generated
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File diff suppressed because it is too large Load diff

106
crates/cpu/tests/rename_execute_retire.rs
View file

@ -3,8 +3,8 @@
use cpu::{ use cpu::{
config::{ config::{
CpuConfig, CpuConfigFetchWidth, CpuConfigMaxUnitMaxInFlight, PhantomConstCpuConfig, CpuConfig, CpuConfigFetchWidth, CpuConfigMaxUnitMaxInFlight, CpuConfigPRegNumWidth,
UnitConfig, PhantomConstCpuConfig, UnitConfig,
}, },
instruction::{ instruction::{
AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOp, AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOp,
@ -246,7 +246,7 @@ impl InsnsBuilder {
move |labels| { move |labels| {
[BranchMOp::branch_i( [BranchMOp::branch_i(
MOpDestReg::new([], []), MOpDestReg::new([], []),
[MOpRegNum::const_zero(); 2], MOpRegNum::const_zero().value,
labels[target.0] labels[target.0]
.pc() .pc()
.wrapping_sub(pc) .wrapping_sub(pc)
@ -264,7 +264,7 @@ impl InsnsBuilder {
format!("blr"), format!("blr"),
[BranchMOp::branch_i( [BranchMOp::branch_i(
MOpDestReg::new([], []), MOpDestReg::new([], []),
[MOpRegNum::const_zero(), MOpRegNum::power_isa_lr_reg()], MOpRegNum::power_isa_lr_reg().value,
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
false, false,
false, false,
@ -281,9 +281,9 @@ impl InsnsBuilder {
[BranchMOp::branch_cond_ctr( [BranchMOp::branch_cond_ctr(
MOpDestReg::new([], []), MOpDestReg::new([], []),
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
labels[target.0] labels[target.0]
.pc() .pc()
@ -308,9 +308,9 @@ impl InsnsBuilder {
[BranchMOp::branch_cond_ctr( [BranchMOp::branch_cond_ctr(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
labels[target.0] labels[target.0]
.pc() .pc()
@ -334,7 +334,7 @@ impl InsnsBuilder {
move |labels| { move |labels| {
[BranchMOp::branch_i( [BranchMOp::branch_i(
MOpDestReg::new([MOpRegNum::power_isa_lr_reg()], []), MOpDestReg::new([MOpRegNum::power_isa_lr_reg()], []),
[MOpRegNum::const_zero(); 2], MOpRegNum::const_zero().value,
labels[target.0] labels[target.0]
.pc() .pc()
.wrapping_sub(pc) .wrapping_sub(pc)
@ -353,9 +353,9 @@ impl InsnsBuilder {
[AddSubMOp::add_sub( [AddSubMOp::add_sub(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(src1), MOpRegNum::power_isa_gpr_reg_imm(src1).value,
MOpRegNum::power_isa_gpr_reg_imm(src2), MOpRegNum::power_isa_gpr_reg_imm(src2).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -373,8 +373,8 @@ impl InsnsBuilder {
[AddSubMOp::add_sub_i( [AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src), MOpRegNum::power_isa_gpr_or_zero_reg_imm(src).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
imm.cast_to_static::<SInt<_>>(), imm.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -391,7 +391,7 @@ impl InsnsBuilder {
format!("cmpldi {dest}, {src}, {imm:#x}"), format!("cmpldi {dest}, {src}, {imm:#x}"),
[CompareMOp::compare_i( [CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(src)], [MOpRegNum::power_isa_gpr_reg_imm(src).value],
imm.cast_to_static::<SInt<_>>(), imm.cast_to_static::<SInt<_>>(),
CompareMode.U64(), CompareMode.U64(),
)], )],
@ -405,8 +405,8 @@ impl InsnsBuilder {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
MOpRegNum::power_isa_gpr_or_zero_reg_imm(src), MOpRegNum::power_isa_gpr_or_zero_reg_imm(src).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
disp.cast_to_static::<SInt<_>>(), disp.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -417,7 +417,7 @@ impl InsnsBuilder {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_temp_reg()], [MOpRegNum::power_isa_temp_reg().value],
LoadStoreWidth.Width64Bit(), LoadStoreWidth.Width64Bit(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
), ),
@ -432,8 +432,8 @@ impl InsnsBuilder {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
MOpRegNum::power_isa_gpr_or_zero_reg_imm(addr_src), MOpRegNum::power_isa_gpr_or_zero_reg_imm(addr_src).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
disp.cast_to_static::<SInt<_>>(), disp.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -445,8 +445,8 @@ impl InsnsBuilder {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg(), MOpRegNum::power_isa_temp_reg().value,
MOpRegNum::power_isa_gpr_reg_imm(value_src), MOpRegNum::power_isa_gpr_reg_imm(value_src).value,
], ],
LoadStoreWidth.Width64Bit(), LoadStoreWidth.Width64Bit(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
@ -460,7 +460,7 @@ impl InsnsBuilder {
format!("mflr {dest}"), format!("mflr {dest}"),
[MoveRegMOp::move_reg( [MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_lr_reg()], [MOpRegNum::power_isa_lr_reg().value],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
)], )],
)); ));
@ -471,7 +471,7 @@ impl InsnsBuilder {
format!("mtlr {src}"), format!("mtlr {src}"),
[MoveRegMOp::move_reg( [MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(src)], [MOpRegNum::power_isa_gpr_reg_imm(src).value],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
)], )],
)); ));
@ -482,7 +482,7 @@ impl InsnsBuilder {
format!("mr {dest}, {src}"), format!("mr {dest}, {src}"),
[MoveRegMOp::move_reg( [MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(dest)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(src)], [MOpRegNum::power_isa_gpr_reg_imm(src).value],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
)], )],
)); ));
@ -606,7 +606,7 @@ impl BrPredState {
} }
fn predict_branch<SrcCount: KnownSize>( fn predict_branch<SrcCount: KnownSize>(
&mut self, &mut self,
mop: &SimValue<BranchMOp<MOpDestReg, MOpRegNum, SrcCount>>, mop: &SimValue<BranchMOp<MOpDestReg, ConstUsize<{ MOpRegNum::WIDTH }>, SrcCount>>,
branch_pc: u64, branch_pc: u64,
fallthrough_pc: u64, fallthrough_pc: u64,
) -> u64 { ) -> u64 {
@ -617,7 +617,7 @@ impl BrPredState {
} }
let mut src_regs = [MOpRegNum::CONST_ZERO_REG_NUM; 3]; let mut src_regs = [MOpRegNum::CONST_ZERO_REG_NUM; 3];
MOpTrait::for_each_src_reg_sim_ref(mop, &mut |reg, index| { MOpTrait::for_each_src_reg_sim_ref(mop, &mut |reg, index| {
src_regs[index] = MOpRegNum::reg_num_sim(reg); src_regs[index] = reg.cast_to_static::<UInt<32>>().as_int();
}); });
if src_regs[1] != MOpRegNum::CONST_ZERO_REG_NUM { if src_regs[1] != MOpRegNum::CONST_ZERO_REG_NUM {
// indirect branch -- this test doesn't implement predicting them, so just use the fallthrough_pc // indirect branch -- this test doesn't implement predicting them, so just use the fallthrough_pc
@ -1295,14 +1295,17 @@ impl MockMemory {
#[hdl] #[hdl]
fn run_mop<C: PhantomConstCpuConfig>( fn run_mop<C: PhantomConstCpuConfig>(
&mut self, &mut self,
mop: &SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>>, mop: &SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN], src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
is_speculative: bool, is_speculative: bool,
) -> Result<SimValue<PRegValue>, AddressCantBeSpeculativelyAccessed> { ) -> Result<SimValue<PRegValue>, AddressCantBeSpeculativelyAccessed> {
println!("MockMemory::run_mop: {:#x}: {:?}", mop.pc.as_int(), mop.mop); println!("MockMemory::run_mop: {:#x}: {:?}", mop.pc.as_int(), mop.mop);
println!( println!(
"<- {}{src_values:?}", "<- {}{:?}",
if is_speculative { "(speculative) " } else { "" }, if is_speculative { "(speculative) " } else { "" },
src_values
.each_ref()
.map(PRegValue::debug_fmt::<PRegFlagsPowerISA>),
); );
let retval = #[hdl(sim)] let retval = #[hdl(sim)]
match &mop.mop { match &mop.mop {
@ -1396,7 +1399,10 @@ impl MockMemory {
PRegValue::zeroed_sim() PRegValue::zeroed_sim()
} }
}; };
println!("-> {retval:?}"); println!(
"-> {:?}",
PRegValue::debug_fmt::<PRegFlagsPowerISA>(&retval),
);
Ok(retval) Ok(retval)
} }
} }
@ -1421,7 +1427,7 @@ trait MockExecutionStateTrait: Default {
fn run_add_sub<C: PhantomConstCpuConfig, SrcCount: KnownSize>( fn run_add_sub<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
&mut self, &mut self,
pc: u64, pc: u64,
mop: &SimValue<AddSubMOp<PRegNum<C>, PRegNum<C>, SrcCount>>, mop: &SimValue<AddSubMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN], src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
) -> SimValue<PRegValue> { ) -> SimValue<PRegValue> {
#[hdl(sim)] #[hdl(sim)]
@ -1485,7 +1491,7 @@ trait MockExecutionStateTrait: Default {
#[hdl] #[hdl]
fn run_compare<C: PhantomConstCpuConfig, SrcCount: KnownSize>( fn run_compare<C: PhantomConstCpuConfig, SrcCount: KnownSize>(
&mut self, &mut self,
mop: &SimValue<CompareMOp<PRegNum<C>, PRegNum<C>, SrcCount>>, mop: &SimValue<CompareMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN], src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
) -> SimValue<PRegValue> { ) -> SimValue<PRegValue> {
#[hdl(sim)] #[hdl(sim)]
@ -1545,7 +1551,7 @@ trait MockExecutionStateTrait: Default {
pc: u64, pc: u64,
fallthrough_pc: u64, fallthrough_pc: u64,
predicted_next_pc: u64, predicted_next_pc: u64,
mop: &SimValue<BranchMOp<PRegNum<C>, PRegNum<C>, SrcCount>>, mop: &SimValue<BranchMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>, SrcCount>>,
src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN], src_values: &[SimValue<PRegValue>; COMMON_MOP_SRC_LEN],
config: C, config: C,
) -> ( ) -> (
@ -1571,14 +1577,12 @@ trait MockExecutionStateTrait: Default {
imm, imm,
} = common; } = common;
let [src0, src1, src2] = src_values; let [src0, src1, src2] = src_values;
let has_src0 = src let has_src0 = src.as_ref().get(0).is_some_and(|src0| {
.as_ref() src0.cast_bits_to(PRegNum[config]) != PRegNum[config].const_zero().into_sim_value()
.get(0) });
.is_some_and(|src0| *src0 != PRegNum[config].const_zero_sim()); let has_src2 = src.as_ref().get(2).is_some_and(|src2| {
let has_src2 = src src2.cast_bits_to(PRegNum[config]) != PRegNum[config].const_zero().into_sim_value()
.as_ref() });
.get(2)
.is_some_and(|src2| *src2 != PRegNum[config].const_zero_sim());
let src2_cond = if has_src2 { let src2_cond = if has_src2 {
let _ = invert_src2_eq_zero; let _ = invert_src2_eq_zero;
let _ = src2; let _ = src2;
@ -1867,9 +1871,17 @@ impl<C: PhantomConstCpuConfig> MockUnitOp<C> {
execution_state.run_mop(&self.mop, &self.src_values, self.config); execution_state.run_mop(&self.mop, &self.src_values, self.config);
assert!(output.is_some() || caused_cancel.is_some()); assert!(output.is_some() || caused_cancel.is_some());
println!("try_run: {:#x}: {:?}", self.mop.pc.as_int(), self.mop.mop); println!("try_run: {:#x}: {:?}", self.mop.pc.as_int(), self.mop.mop);
println!("<- {:?}", self.src_values); println!(
"<- {:?}",
self.src_values
.each_ref()
.map(PRegValue::debug_fmt::<PRegFlagsPowerISA>),
);
self.output_ready = output.map(|(dest_value, predictor_op)| { self.output_ready = output.map(|(dest_value, predictor_op)| {
println!("-> {dest_value:?}"); println!(
"-> {:?}",
PRegValue::debug_fmt::<PRegFlagsPowerISA>(&dest_value),
);
#[hdl(sim)] #[hdl(sim)]
let NextPcPredictorOp::<_> { let NextPcPredictorOp::<_> {
call_stack_op, call_stack_op,
@ -2262,7 +2274,7 @@ fn mock_unit<#[hdl(skip)] E: MockExecutionStateTrait>(
#[hdl(no_static)] #[hdl(no_static)]
struct MockLoadStoreOpDebugState<C: PhantomConstGet<CpuConfig>> { struct MockLoadStoreOpDebugState<C: PhantomConstGet<CpuConfig>> {
mop: MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>, mop: MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>,
is_speculative: Bool, is_speculative: Bool,
src_values: HdlOption<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>, src_values: HdlOption<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
dest_value: HdlOption<PRegValue>, dest_value: HdlOption<PRegValue>,
@ -2274,7 +2286,7 @@ struct MockLoadStoreOpDebugState<C: PhantomConstGet<CpuConfig>> {
#[derive(Debug)] #[derive(Debug)]
struct MockLoadStoreOp<C: PhantomConstCpuConfig> { struct MockLoadStoreOp<C: PhantomConstCpuConfig> {
mop: SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, PRegNum<C>>>>, mop: SimValue<MOpInstance<LoadStoreMOp<PRegNum<C>, CpuConfigPRegNumWidth<C>>>>,
is_speculative: bool, is_speculative: bool,
src_values: Option<[SimValue<PRegValue>; COMMON_MOP_SRC_LEN]>, src_values: Option<[SimValue<PRegValue>; COMMON_MOP_SRC_LEN]>,
dest_value: Option<SimValue<PRegValue>>, dest_value: Option<SimValue<PRegValue>>,

49238
crates/cpu/tests/simple_power_isa_decoder/expected/decode_one_insn.vcd generated
View file

File diff suppressed because it is too large Load diff

84
crates/cpu/tests/simple_power_isa_decoder/test_cases/branch.rs
View file

@ -15,7 +15,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_i( BranchMOp::branch_i(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[MOpRegNum::const_zero(); 2], MOpRegNum::const_zero().value,
0x345678.cast_to_static::<SInt<_>>(), 0x345678.cast_to_static::<SInt<_>>(),
true, true,
false, false,
@ -28,7 +28,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_i( BranchMOp::branch_i(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[MOpRegNum::const_zero(); 2], MOpRegNum::const_zero().value,
0x345678.cast_to_static::<SInt<_>>(), 0x345678.cast_to_static::<SInt<_>>(),
false, false,
false, false,
@ -41,7 +41,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_i( BranchMOp::branch_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
[MOpRegNum::const_zero(); 2], MOpRegNum::const_zero().value,
0x345678.cast_to_static::<SInt<_>>(), 0x345678.cast_to_static::<SInt<_>>(),
true, true,
true, true,
@ -54,7 +54,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_i( BranchMOp::branch_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
[MOpRegNum::const_zero(); 2], MOpRegNum::const_zero().value,
0x345678.cast_to_static::<SInt<_>>(), 0x345678.cast_to_static::<SInt<_>>(),
false, false,
true, true,
@ -74,7 +74,10 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
[ [
AddSubMOp::add_sub_i::<MOp>( AddSubMOp::add_sub_i::<MOp>(
MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []), MOpDestReg::new([MOpRegNum::power_isa_ctr_reg()], []),
[MOpRegNum::power_isa_ctr_reg(), MOpRegNum::const_zero()], [
MOpRegNum::power_isa_ctr_reg().value,
MOpRegNum::const_zero().value,
],
(-1).cast_to_static::<SInt<_>>(), (-1).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -140,9 +143,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
$src1, $src1,
MOpRegNum::power_isa_ctr_reg(), MOpRegNum::power_isa_ctr_reg().value,
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -160,9 +163,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
$src1, $src1,
MOpRegNum::power_isa_ctr_reg(), MOpRegNum::power_isa_ctr_reg().value,
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -180,9 +183,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
$src1, $src1,
MOpRegNum::power_isa_ctr_reg(), MOpRegNum::power_isa_ctr_reg().value,
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -200,9 +203,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
$src1, $src1,
MOpRegNum::power_isa_ctr_reg(), MOpRegNum::power_isa_ctr_reg().value,
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -220,9 +223,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(2), MOpRegNum::power_isa_cr_reg_imm(2).value,
$src1, $src1,
MOpRegNum::power_isa_ctr_reg(), MOpRegNum::power_isa_ctr_reg().value,
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -240,9 +243,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
$src1, $src1,
MOpRegNum::power_isa_ctr_reg(), MOpRegNum::power_isa_ctr_reg().value,
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -261,9 +264,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
$src1, $src1,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
@ -282,9 +285,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
$src1, $src1,
MOpRegNum::power_isa_ctr_reg(), MOpRegNum::power_isa_ctr_reg().value,
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
false, false,
@ -302,9 +305,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
$src1, $src1,
MOpRegNum::power_isa_ctr_reg(), MOpRegNum::power_isa_ctr_reg().value,
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
false, false,
@ -323,9 +326,9 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
BranchMOp::branch_cond_ctr( BranchMOp::branch_cond_ctr(
$dest, $dest,
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
$src1, $src1,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
false, false,
@ -343,11 +346,8 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_ctr( BranchMOp::branch_ctr(
$dest, $dest,
[ $src1,
MOpRegNum::const_zero(), MOpRegNum::power_isa_ctr_reg().value,
$src1,
MOpRegNum::power_isa_ctr_reg(),
],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
true, true,
$pc_relative, $pc_relative,
@ -361,11 +361,8 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_ctr( BranchMOp::branch_ctr(
$dest, $dest,
[ $src1,
MOpRegNum::const_zero(), MOpRegNum::power_isa_ctr_reg().value,
$src1,
MOpRegNum::power_isa_ctr_reg(),
],
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
false, false,
$pc_relative, $pc_relative,
@ -380,7 +377,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_i( BranchMOp::branch_i(
$dest, $dest,
[MOpRegNum::const_zero(), $src1], $src1,
$imm.cast_to_static::<SInt<_>>(), $imm.cast_to_static::<SInt<_>>(),
$pc_relative, $pc_relative,
$lk, $lk,
@ -395,7 +392,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
asm_last_arg = "0x1234"; asm_last_arg = "0x1234";
imm = 0x1234; imm = 0x1234;
encoding = 0x40001234; encoding = 0x40001234;
src1 = MOpRegNum::const_zero(); src1 = MOpRegNum::const_zero().value;
pc_relative = true; pc_relative = true;
is_ret = false; is_ret = false;
} }
@ -405,7 +402,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
asm_last_arg = "0x1234"; asm_last_arg = "0x1234";
imm = 0x1234; imm = 0x1234;
encoding = 0x40001236; encoding = 0x40001236;
src1 = MOpRegNum::const_zero(); src1 = MOpRegNum::const_zero().value;
pc_relative = false; pc_relative = false;
is_ret = false; is_ret = false;
} }
@ -415,7 +412,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
asm_last_arg = "0"; asm_last_arg = "0";
imm = 0; imm = 0;
encoding = 0x4c000020; encoding = 0x4c000020;
src1 = MOpRegNum::power_isa_lr_reg(); src1 = MOpRegNum::power_isa_lr_reg().value;
pc_relative = false; pc_relative = false;
is_ret = true; is_ret = true;
} }
@ -425,7 +422,7 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
asm_last_arg = "0"; asm_last_arg = "0";
imm = 0; imm = 0;
encoding = 0x4c000420; encoding = 0x4c000420;
src1 = MOpRegNum::power_isa_ctr_reg(); src1 = MOpRegNum::power_isa_ctr_reg().value;
pc_relative = false; pc_relative = false;
is_ret = false; is_ret = false;
} }
@ -437,11 +434,8 @@ pub fn test_cases_book_i_2_4_branch(retval: &mut Vec<TestCase>) {
None, None,
BranchMOp::branch_ctr( BranchMOp::branch_ctr(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
[ MOpRegNum::power_isa_tar_reg().value,
MOpRegNum::const_zero(), MOpRegNum::power_isa_ctr_reg().value,
MOpRegNum::power_isa_tar_reg(),
MOpRegNum::power_isa_ctr_reg(),
],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
false, false,
false, false,

20
crates/cpu/tests/simple_power_isa_decoder/test_cases/condition_register.rs
View file

@ -23,9 +23,9 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_cr_reg_imm(1), MOpRegNum::power_isa_cr_reg_imm(1).value,
MOpRegNum::power_isa_cr_reg_imm(5), MOpRegNum::power_isa_cr_reg_imm(5).value,
MOpRegNum::power_isa_cr_reg_imm(3), MOpRegNum::power_isa_cr_reg_imm(3).value,
], ],
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| { LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
let mut dest = src2.map(|v| Some(v.into())); let mut dest = src2.map(|v| Some(v.into()));
@ -42,9 +42,9 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]),
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
], ],
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| { LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
let mut dest = src2.map(|v| Some(v.into())); let mut dest = src2.map(|v| Some(v.into()));
@ -61,9 +61,9 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(0)], &[]),
[ [
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
MOpRegNum::power_isa_cr_reg_imm(0), MOpRegNum::power_isa_cr_reg_imm(0).value,
], ],
LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| { LogicalFlagsMOpImm::from_swizzle_fn::<PRegFlagsPowerISA>(|src0, src1, src2| {
let mut dest = src2.map(|v| Some(v.into())); let mut dest = src2.map(|v| Some(v.into()));
@ -91,7 +91,7 @@ pub fn test_cases_book_i_2_5_condition_register(retval: &mut Vec<TestCase>) {
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_cr_reg_imm($src)], [MOpRegNum::power_isa_cr_reg_imm($src).value],
0i8.cast_to_static::<SInt<_>>(), 0i8.cast_to_static::<SInt<_>>(),
), ),
)); ));

95
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_arithmetic.rs
View file

@ -13,7 +13,10 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
None, None,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()], [
MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value,
],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -28,7 +31,10 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
Some(0x38646789), Some(0x38646789),
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()], [
MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value,
],
0x123456789i64.cast_to_static::<SInt<_>>(), 0x123456789i64.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -43,7 +49,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
Some(0x38606789), Some(0x38606789),
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero(), MOpRegNum::const_zero()], [MOpRegNum::const_zero().value, MOpRegNum::const_zero().value],
0x123456789i64.cast_to_static::<SInt<_>>(), 0x123456789i64.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -58,7 +64,10 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
None, None,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()], [
MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value,
],
0x12340000.cast_to_static::<SInt<_>>(), 0x12340000.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -73,7 +82,7 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
None, None,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero(); _], [MOpRegNum::const_zero().value; _],
0x12340004.cast_to_static::<SInt<_>>(), 0x12340004.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -92,9 +101,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -116,7 +125,10 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
], ],
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()], [
MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value,
],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
false, false,
@ -135,9 +147,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -159,7 +171,10 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
], ],
&[], &[],
), ),
[MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::const_zero()], [
MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero().value,
],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
true, true,
@ -181,9 +196,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -206,9 +221,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -231,9 +246,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg(), MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -256,9 +271,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg(), MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -281,9 +296,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg(), MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
(-1i8).cast_to_static::<SInt<_>>(), (-1i8).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -306,9 +321,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg(), MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
(-1i8).cast_to_static::<SInt<_>>(), (-1i8).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -331,9 +346,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg(), MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -356,9 +371,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_xer_ca_ca32_reg(), MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -378,9 +393,9 @@ pub fn test_cases_book_i_3_3_9_fixed_point_arithmetic(retval: &mut Vec<TestCase>
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),

36
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_compare.rs
View file

@ -13,7 +13,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4)], [MOpRegNum::power_isa_gpr_reg_imm(4).value],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
CompareMode.S32(), CompareMode.S32(),
), ),
@ -24,7 +24,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4)], [MOpRegNum::power_isa_gpr_reg_imm(4).value],
(0x89abu16 as i16).cast_to_static::<SInt<_>>(), (0x89abu16 as i16).cast_to_static::<SInt<_>>(),
CompareMode.S64(), CompareMode.S64(),
), ),
@ -36,8 +36,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
CompareMode.S32(), CompareMode.S32(),
), ),
@ -49,8 +49,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
CompareMode.S64(), CompareMode.S64(),
), ),
@ -61,7 +61,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4)], [MOpRegNum::power_isa_gpr_reg_imm(4).value],
0x1234.cast_to_static::<SInt<_>>(), 0x1234.cast_to_static::<SInt<_>>(),
CompareMode.U32(), CompareMode.U32(),
), ),
@ -72,7 +72,7 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
None, None,
CompareMOp::compare_i( CompareMOp::compare_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4)], [MOpRegNum::power_isa_gpr_reg_imm(4).value],
0x89ab.cast_to_static::<SInt<_>>(), 0x89ab.cast_to_static::<SInt<_>>(),
CompareMode.U64(), CompareMode.U64(),
), ),
@ -84,8 +84,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
CompareMode.U32(), CompareMode.U32(),
), ),
@ -97,8 +97,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
CompareMode.U64(), CompareMode.U64(),
), ),
@ -110,8 +110,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
CompareMode.CmpRBOne(), CompareMode.CmpRBOne(),
), ),
@ -123,8 +123,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
CompareMode.CmpRBTwo(), CompareMode.CmpRBTwo(),
), ),
@ -136,8 +136,8 @@ pub fn test_cases_book_i_3_3_10_fixed_point_compare(retval: &mut Vec<TestCase>)
CompareMOp::compare( CompareMOp::compare(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm(4), MOpRegNum::power_isa_gpr_reg_imm(4).value,
MOpRegNum::power_isa_gpr_reg_imm(5), MOpRegNum::power_isa_gpr_reg_imm(5).value,
], ],
CompareMode.CmpEqB(), CompareMode.CmpEqB(),
), ),

36
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_load.rs
View file

@ -26,11 +26,11 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $r != 0 || $ra == 0 { if $r != 0 || $ra == 0 {
MOpRegNum::const_zero() MOpRegNum::const_zero().value
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra) MOpRegNum::power_isa_gpr_reg_imm($ra).value
}, },
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -41,7 +41,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_temp_reg()], [MOpRegNum::power_isa_temp_reg().value],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.$conversion(), LoadStoreConversion.$conversion(),
), ),
@ -65,11 +65,11 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $ra == 0 { if $ra == 0 {
MOpRegNum::const_zero() MOpRegNum::const_zero().value
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra) MOpRegNum::power_isa_gpr_reg_imm($ra).value
}, },
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -80,7 +80,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_temp_reg()], [MOpRegNum::power_isa_temp_reg().value],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.$conversion(), LoadStoreConversion.$conversion(),
), ),
@ -103,8 +103,8 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra), MOpRegNum::power_isa_gpr_reg_imm($ra).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -115,7 +115,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm($ra)], [MOpRegNum::power_isa_gpr_reg_imm($ra).value],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.$conversion(), LoadStoreConversion.$conversion(),
), ),
@ -139,11 +139,11 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $ra == 0 { if $ra == 0 {
MOpRegNum::const_zero() MOpRegNum::const_zero().value
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra) MOpRegNum::power_isa_gpr_reg_imm($ra).value
}, },
MOpRegNum::power_isa_gpr_reg_imm($rb), MOpRegNum::power_isa_gpr_reg_imm($rb).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -154,7 +154,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_temp_reg()], [MOpRegNum::power_isa_temp_reg().value],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.$conversion(), LoadStoreConversion.$conversion(),
), ),
@ -177,8 +177,8 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra), MOpRegNum::power_isa_gpr_reg_imm($ra).value,
MOpRegNum::power_isa_gpr_reg_imm($rb), MOpRegNum::power_isa_gpr_reg_imm($rb).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -189,7 +189,7 @@ pub fn test_cases_book_i_3_3_2_fixed_point_load(retval: &mut Vec<TestCase>) {
), ),
LoadMOp::load( LoadMOp::load(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm($ra)], [MOpRegNum::power_isa_gpr_reg_imm($ra).value],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.$conversion(), LoadStoreConversion.$conversion(),
), ),

10
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_logical.rs
View file

@ -34,7 +34,7 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
&[] &[]
}, },
), ),
[MOpRegNum::power_isa_gpr_reg_imm($src)], [MOpRegNum::power_isa_gpr_reg_imm($src).value],
(($imm as u32) << if $mnemonic.contains('s') { 16 } else { 0 }) (($imm as u32) << if $mnemonic.contains('s') { 16 } else { 0 })
.cast_to_static::<SInt<_>>(), .cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -108,8 +108,8 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
}, },
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src0), MOpRegNum::power_isa_gpr_reg_imm($src0).value,
MOpRegNum::power_isa_gpr_reg_imm($src1), MOpRegNum::power_isa_gpr_reg_imm($src1).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -159,7 +159,7 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(4)], [MOpRegNum::power_isa_gpr_reg_imm(4).value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -232,7 +232,7 @@ pub fn test_cases_book_i_3_3_13_fixed_point_logical(retval: &mut Vec<TestCase>)
&[] &[]
}, },
), ),
[MOpRegNum::power_isa_gpr_reg_imm($src)], [MOpRegNum::power_isa_gpr_reg_imm($src).value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.$OutputIntegerMode(), OutputIntegerMode.$OutputIntegerMode(),
Lut4::from_fn(|a, b| a | b), Lut4::from_fn(|a, b| a | b),

84
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_rotate_and_shift.rs
View file

@ -95,9 +95,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
src2, src2.value,
], ],
&imm, &imm,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -121,9 +121,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
src2, src2.value,
], ],
imm, imm,
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -156,9 +156,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::power_isa_gpr_reg_imm($amount), MOpRegNum::power_isa_gpr_reg_imm($amount).value,
], ],
rotate_imm(None, $rotated_output_start_and_len, false), rotate_imm(None, $rotated_output_start_and_len, false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -182,9 +182,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::power_isa_gpr_reg_imm($amount), MOpRegNum::power_isa_gpr_reg_imm($amount).value,
], ],
rotate_imm(None, $rotated_output_start_and_len, false), rotate_imm(None, $rotated_output_start_and_len, false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -739,9 +739,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::power_isa_gpr_reg_imm($amount), MOpRegNum::power_isa_gpr_reg_imm($amount).value,
], ],
shift_imm(None, false), shift_imm(None, false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -766,9 +766,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::power_isa_gpr_reg_imm($amount), MOpRegNum::power_isa_gpr_reg_imm($amount).value,
], ],
shift_imm(None, false), shift_imm(None, false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -798,9 +798,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[ [
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::power_isa_gpr_reg_imm($amount), MOpRegNum::power_isa_gpr_reg_imm($amount).value,
], ],
shift_imm(None, true), shift_imm(None, true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -825,9 +825,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::power_isa_gpr_reg_imm($amount), MOpRegNum::power_isa_gpr_reg_imm($amount).value,
], ],
shift_imm(None, true), shift_imm(None, true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -863,9 +863,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[], &[],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::power_isa_gpr_reg_imm($amount), MOpRegNum::power_isa_gpr_reg_imm($amount).value,
], ],
shift_imm(None, true), shift_imm(None, true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -893,9 +893,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::power_isa_gpr_reg_imm($amount), MOpRegNum::power_isa_gpr_reg_imm($amount).value,
], ],
shift_imm(None, true), shift_imm(None, true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -931,9 +931,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[], &[],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
shift_imm(Some($amount), true), shift_imm(Some($amount), true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -961,9 +961,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
shift_imm(Some($amount), true), shift_imm(Some($amount), true),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -1072,9 +1072,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
ShiftRotateMOp::shift_rotate( ShiftRotateMOp::shift_rotate(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
shift_imm(Some($amount), false), shift_imm(Some($amount), false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -1099,9 +1099,9 @@ pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<Te
&[MOpRegNum::POWER_ISA_CR_0_REG_NUM], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
), ),
[ [
MOpRegNum::power_isa_gpr_reg_imm($src), MOpRegNum::power_isa_gpr_reg_imm($src).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
shift_imm(Some($amount), false), shift_imm(Some($amount), false),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),

68
crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_store.rs
View file

@ -25,11 +25,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $r != 0 || $ra == 0 { if $r != 0 || $ra == 0 {
MOpRegNum::const_zero() MOpRegNum::const_zero().value
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra) MOpRegNum::power_isa_gpr_reg_imm($ra).value
}, },
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -41,8 +41,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg(), MOpRegNum::power_isa_temp_reg().value,
MOpRegNum::power_isa_gpr_reg_imm($rs), MOpRegNum::power_isa_gpr_reg_imm($rs).value,
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
@ -66,11 +66,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $ra == 0 { if $ra == 0 {
MOpRegNum::const_zero() MOpRegNum::const_zero().value
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra) MOpRegNum::power_isa_gpr_reg_imm($ra).value
}, },
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -82,8 +82,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg(), MOpRegNum::power_isa_temp_reg().value,
MOpRegNum::power_isa_gpr_reg_imm($rs), MOpRegNum::power_isa_gpr_reg_imm($rs).value,
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
@ -107,8 +107,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra), MOpRegNum::power_isa_gpr_reg_imm($ra).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -120,15 +120,15 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg(), MOpRegNum::power_isa_temp_reg().value,
MOpRegNum::power_isa_gpr_reg_imm($rs), MOpRegNum::power_isa_gpr_reg_imm($rs).value,
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
), ),
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[MOpRegNum::power_isa_temp_reg()], [MOpRegNum::power_isa_temp_reg().value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
], ],
@ -142,8 +142,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra), MOpRegNum::power_isa_gpr_reg_imm($ra).value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
], ],
($disp as i64).cast_to_static::<SInt<_>>(), ($disp as i64).cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -155,8 +155,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra), MOpRegNum::power_isa_gpr_reg_imm($ra).value,
MOpRegNum::power_isa_gpr_reg_imm($rs), MOpRegNum::power_isa_gpr_reg_imm($rs).value,
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
@ -181,11 +181,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
if $ra == 0 { if $ra == 0 {
MOpRegNum::const_zero() MOpRegNum::const_zero().value
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra) MOpRegNum::power_isa_gpr_reg_imm($ra).value
}, },
MOpRegNum::power_isa_gpr_reg_imm($rb), MOpRegNum::power_isa_gpr_reg_imm($rb).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -197,8 +197,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg(), MOpRegNum::power_isa_temp_reg().value,
MOpRegNum::power_isa_gpr_reg_imm($rs), MOpRegNum::power_isa_gpr_reg_imm($rs).value,
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
@ -222,8 +222,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TEMP_REG_NUM], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra), MOpRegNum::power_isa_gpr_reg_imm($ra).value,
MOpRegNum::power_isa_gpr_reg_imm($rb), MOpRegNum::power_isa_gpr_reg_imm($rb).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -235,15 +235,15 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_temp_reg(), MOpRegNum::power_isa_temp_reg().value,
MOpRegNum::power_isa_gpr_reg_imm($rs), MOpRegNum::power_isa_gpr_reg_imm($rs).value,
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),
), ),
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[MOpRegNum::power_isa_temp_reg()], [MOpRegNum::power_isa_temp_reg().value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
], ],
@ -258,11 +258,11 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($ra)], &[]),
[ [
if $ra == 0 { if $ra == 0 {
MOpRegNum::const_zero() MOpRegNum::const_zero().value
} else { } else {
MOpRegNum::power_isa_gpr_reg_imm($ra) MOpRegNum::power_isa_gpr_reg_imm($ra).value
}, },
MOpRegNum::power_isa_gpr_reg_imm($rb), MOpRegNum::power_isa_gpr_reg_imm($rb).value,
], ],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
OutputIntegerMode.Full64(), OutputIntegerMode.Full64(),
@ -274,8 +274,8 @@ pub fn test_cases_book_i_3_3_3_fixed_point_store(retval: &mut Vec<TestCase>) {
StoreMOp::store( StoreMOp::store(
MOpDestReg::new_sim(&[], &[]), MOpDestReg::new_sim(&[], &[]),
[ [
MOpRegNum::power_isa_gpr_reg_imm($ra), MOpRegNum::power_isa_gpr_reg_imm($ra).value,
MOpRegNum::power_isa_gpr_reg_imm($rs), MOpRegNum::power_isa_gpr_reg_imm($rs).value,
], ],
LoadStoreWidth.$width(), LoadStoreWidth.$width(),
LoadStoreConversion.ZeroExt(), LoadStoreConversion.ZeroExt(),

26
crates/cpu/tests/simple_power_isa_decoder/test_cases/move_to_from_system_register.rs
View file

@ -30,9 +30,9 @@ pub fn test_cases_book_i_3_3_19_move_to_from_system_register(retval: &mut Vec<Te
LogicalFlagsMOp::logical_flags( LogicalFlagsMOp::logical_flags(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_cr_reg_num(3)], &[]),
[ [
MOpRegNum::power_isa_xer_ca_ca32_reg(), MOpRegNum::power_isa_xer_ca_ca32_reg().value,
MOpRegNum::const_zero(), MOpRegNum::const_zero().value,
MOpRegNum::power_isa_xer_so_ov_ov32_reg(), MOpRegNum::power_isa_xer_so_ov_ov32_reg().value,
], ],
mcrxrx_imm(), mcrxrx_imm(),
Lut4::from_fn(|a, b| a | b), Lut4::from_fn(|a, b| a | b),
@ -48,7 +48,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_lr_reg()], [MOpRegNum::power_isa_lr_reg().value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -58,7 +58,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(3)], [MOpRegNum::power_isa_gpr_reg_imm(3).value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -68,7 +68,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_ctr_reg()], [MOpRegNum::power_isa_ctr_reg().value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -78,7 +78,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_CTR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_CTR_REG_NUM], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(3)], [MOpRegNum::power_isa_gpr_reg_imm(3).value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -88,7 +88,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::power_isa_tar_reg()], [MOpRegNum::power_isa_tar_reg().value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -98,7 +98,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
MoveRegMOp::move_reg( MoveRegMOp::move_reg(
MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TAR_REG_NUM], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TAR_REG_NUM], &[]),
[MOpRegNum::power_isa_gpr_reg_imm(3)], [MOpRegNum::power_isa_gpr_reg_imm(3).value],
0.cast_to_static::<SInt<_>>(), 0.cast_to_static::<SInt<_>>(),
), ),
)); ));
@ -109,7 +109,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
ReadSpecialMOp::read_special( ReadSpecialMOp::read_special(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero(); 0], [MOpRegNum::const_zero().value; 0],
ReadSpecialMOpImm.PowerIsaTimeBase(), ReadSpecialMOpImm.PowerIsaTimeBase(),
), ),
)); ));
@ -120,7 +120,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
ReadSpecialMOp::read_special( ReadSpecialMOp::read_special(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero(); 0], [MOpRegNum::const_zero().value; 0],
ReadSpecialMOpImm.PowerIsaTimeBaseU(), ReadSpecialMOpImm.PowerIsaTimeBaseU(),
), ),
)); ));
@ -131,7 +131,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
ReadSpecialMOp::read_special( ReadSpecialMOp::read_special(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero(); 0], [MOpRegNum::const_zero().value; 0],
ReadSpecialMOpImm.PowerIsaTimeBase(), ReadSpecialMOpImm.PowerIsaTimeBase(),
), ),
)); ));
@ -142,7 +142,7 @@ pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<T
None, None,
ReadSpecialMOp::read_special( ReadSpecialMOp::read_special(
MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]), MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
[MOpRegNum::const_zero(); 0], [MOpRegNum::const_zero().value; 0],
ReadSpecialMOpImm.PowerIsaTimeBaseU(), ReadSpecialMOpImm.PowerIsaTimeBaseU(),
), ),
)); ));