diff --git a/.forgejo/workflows/test.yml b/.forgejo/workflows/test.yml
index 88dda29..98b304b 100644
--- a/.forgejo/workflows/test.yml
+++ b/.forgejo/workflows/test.yml
@@ -16,4 +16,5 @@ jobs:
       - uses: https://git.libre-chip.org/mirrors/rust-cache@v2
         with:
           save-if: ${{ github.ref == 'refs/heads/master' }}
+      - run: rustup override set 1.93.0
       - run: cargo test
diff --git a/Cargo.lock b/Cargo.lock
index 29086a1..b805b2f 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -388,7 +388,7 @@ checksum = "e8c02a5121d4ea3eb16a80748c74f5549a5665e4c21333c6098f283870fbdea6"
 [[package]]
 name = "fayalite"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#c97b44d9d646a4aa64fcc046538fc2354bb708ee"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#1bc835803bf87643c6464eaca0932e30e5febb8c"
 dependencies = [
  "base64",
  "bitvec",
@@ -403,6 +403,7 @@ dependencies = [
  "jobslot",
  "num-bigint",
  "num-traits",
+ "once_cell",
  "ordered-float",
  "petgraph",
  "serde",
@@ -415,7 +416,7 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#c97b44d9d646a4aa64fcc046538fc2354bb708ee"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#1bc835803bf87643c6464eaca0932e30e5febb8c"
 dependencies = [
  "fayalite-proc-macros-impl",
 ]
@@ -423,7 +424,7 @@ dependencies = [
 [[package]]
 name = "fayalite-proc-macros-impl"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#c97b44d9d646a4aa64fcc046538fc2354bb708ee"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#1bc835803bf87643c6464eaca0932e30e5febb8c"
 dependencies = [
  "base16ct 0.2.0",
  "num-bigint",
@@ -438,7 +439,7 @@ dependencies = [
 [[package]]
 name = "fayalite-visit-gen"
 version = "0.3.0"
-source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#c97b44d9d646a4aa64fcc046538fc2354bb708ee"
+source = "git+https://git.libre-chip.org/libre-chip/fayalite.git?branch=master#1bc835803bf87643c6464eaca0932e30e5febb8c"
 dependencies = [
  "indexmap",
  "prettyplease",
@@ -739,9 +740,9 @@ dependencies = [
 
 [[package]]
 name = "once_cell"
-version = "1.20.2"
+version = "1.21.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1261fe7e33c73b354eab43b1273a57c8f967d0391e80353e51f764ac02cf6775"
+checksum = "42f5e15c9953c5e4ccceeb2e7382a716482c34515315f7b03532b8b4e8393d2d"
 
 [[package]]
 name = "ordered-float"
diff --git a/Cargo.toml b/Cargo.toml
index a3a9787..cc5e746 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -11,7 +11,7 @@ edition = "2024"
 repository = ""
 keywords = []
 categories = []
-rust-version = "1.89.0"
+rust-version = "1.93.0"
 
 [workspace.dependencies]
 base16ct = "1.0.0"
diff --git a/crates/cpu/src/decoder/simple_power_isa.rs b/crates/cpu/src/decoder/simple_power_isa.rs
index 5caf6a4..9bab75a 100644
--- a/crates/cpu/src/decoder/simple_power_isa.rs
+++ b/crates/cpu/src/decoder/simple_power_isa.rs
@@ -6,7 +6,9 @@ use crate::{
     instruction::{
         AddSubMOp, BranchMOp, CompareMOp, CompareMode, ConditionMode, LoadMOp, LoadStoreConversion,
         LoadStoreWidth, LogicalFlagsMOp, LogicalFlagsMOpImm, LogicalMOp, Lut4, MOp, MOpDestReg,
-        MOpRegNum, MoveRegMOp, OutputIntegerMode, StoreMOp,
+        MOpRegNum, MoveRegMOp, OutputIntegerMode, ReadSpecialMOp, ReadSpecialMOpImm,
+        ShiftRotateDestLogicOp, ShiftRotateMOp, ShiftRotateMOpImm, ShiftRotateMode, StoreMOp,
+        power_isa::PowerIsaSprEnum,
     },
     powerisa_instructions_xml::{
         InstructionBitFieldName, InstructionBitFieldsInner, Instructions, TextLineItem,
@@ -14,15 +16,16 @@ use crate::{
     register::{
         PRegFlags, PRegFlagsPowerISA, PRegFlagsPowerISAView, PRegFlagsViewTrait, ViewUnused,
     },
-    util::array_vec::{ArrayVec, Length},
+    util::{
+        Rotate,
+        array_vec::{ArrayVec, Length},
+    },
 };
-use fayalite::{
-    int::{BoolOrIntType, UIntInRange},
-    module::wire_with_loc,
-    prelude::*,
-    ty::StaticType,
+use fayalite::{int::UIntInRange, module::wire_with_loc, prelude::*, ty::StaticType};
+use std::{
+    collections::{BTreeMap, HashMap, hash_map::Entry},
+    ops::RangeInclusive,
 };
-use std::{collections::BTreeMap, ops::RangeInclusive};
 
 #[rustfmt::skip]
 const FP_MNEMONICS: &[&str] = &[
@@ -129,7 +132,7 @@ const VSX_MNEMONICS: &[&str] = &[
 ];
 
 #[derive(Debug)]
-struct DecodeState {
+struct DecodeState<'a> {
     mnemonic: &'static str,
     arguments: Option<&'static str>,
     conditions: Option<&'static str>,
@@ -140,6 +143,7 @@ struct DecodeState {
     first_input: Expr<UInt<32>>,
     second_input: Expr<HdlOption<UInt<32>>>,
     second_input_used: Expr<Bool>,
+    field_wires: &'a mut HashMap<String, HashMap<Expr<UInt>, Expr<UInt>>>,
 }
 
 trait FieldSet {
@@ -218,12 +222,28 @@ impl_fields! {
     struct FieldDS(SInt<14>);
     #[name = "LI"]
     struct FieldLI(SInt<24>);
+    #[name = "MB"]
+    struct FieldMB(UInt<5>);
+    #[name = "mb"]
+    struct FieldMb(UInt<6>);
+    #[name = "ME"]
+    struct FieldME(UInt<5>);
+    #[name = "me"]
+    struct FieldMe(UInt<6>);
+    #[name = "SH"]
+    struct FieldSH(UInt<5>);
+    #[name = "sh"]
+    struct FieldSh(UInt<6>);
     #[name = "SI"]
     struct FieldSI(SInt<16>);
     #[name = "si0"]
     struct FieldSi0(SInt<18>);
     #[name = "si1"]
     struct FieldSi1(UInt<16>);
+    #[name = "spr"]
+    struct FieldSpr(UInt<10>);
+    #[name = "tbr"]
+    struct FieldTbr(UInt<10>);
     #[name = "UI"]
     struct FieldUI(UInt<16>);
     #[name = "d0"]
@@ -309,7 +329,7 @@ fn cr_bit_flag_index(
     (MOpRegNum::power_isa_cr_reg(field_num), flag_index)
 }
 
-impl DecodeState {
+impl DecodeState<'_> {
     fn form(&self) -> &'static str {
         let mut title_words = self
             .header
@@ -388,6 +408,26 @@ impl DecodeState {
             (var.trim(), value.trim())
         })
     }
+    fn get_field_wire(&mut self, value: Expr<UInt>, name: &str) -> Expr<UInt> {
+        let form = self.form();
+        let width = value.ty().width();
+        let wire_name =
+            format!("{form}_{name}_{width}").replace(|c: char| !c.is_ascii_alphanumeric(), "_");
+        match self
+            .field_wires
+            .entry(wire_name.clone())
+            .or_default()
+            .entry(value)
+        {
+            Entry::Vacant(entry) => {
+                let wire = wire_with_loc(&wire_name, SourceLocation::caller(), value.ty());
+                connect(wire, value);
+                entry.insert(wire);
+                wire
+            }
+            Entry::Occupied(entry) => *entry.get(),
+        }
+    }
     #[hdl]
     fn decode_word(
         &mut self,
@@ -397,6 +437,20 @@ impl DecodeState {
         fields_inner: &'static InstructionBitFieldsInner,
     ) {
         let mut last_start = word.ty().width();
+        struct FieldPieces {
+            filled_pieces: Vec<Expr<UInt>>,
+            piece_count: usize,
+        }
+        let mut fields_pieces = BTreeMap::new();
+        for bit_field in fields_inner.fields() {
+            fields_pieces
+                .entry(Self::bit_field_name(bit_field.name()))
+                .or_insert_with(|| FieldPieces {
+                    filled_pieces: Vec::with_capacity(1),
+                    piece_count: 0,
+                })
+                .piece_count += 1;
+        }
         for bit_field in fields_inner.fields().iter().rev() {
             let bit_number_text = match bit_field.bit_number().text() {
                 "3031" => "30 31",
@@ -436,6 +490,10 @@ impl DecodeState {
             if name.contains(char::is_alphabetic) {
                 for (cond_name, cond_value) in self.conditions() {
                     if name == cond_name {
+                        assert_eq!(
+                            fields_pieces[name].piece_count, 1,
+                            "can't apply conditions to a field with more than one piece: name {name:?}",
+                        );
                         name = cond_value;
                         break;
                     }
@@ -444,15 +502,25 @@ impl DecodeState {
             if name == "any value*" || name.bytes().all(|b| b == b'/') {
                 // wildcard
             } else if name.contains(char::is_alphabetic) {
-                let wire = wire_with_loc(
-                    &format!("{}_{name}", self.mnemonic)
-                        .replace(|c: char| !c.is_ascii_alphanumeric(), "_"),
-                    SourceLocation::caller(),
-                    field.ty(),
-                );
-                connect(wire, field);
-                if fields.insert(name, wire).is_some() {
-                    panic!("duplicate field name: {name:?}\nheader: {:#?}", self.header);
+                let Some(field_pieces) = fields_pieces.get_mut(name) else {
+                    unreachable!();
+                };
+                field_pieces.filled_pieces.push(field);
+                if field_pieces.filled_pieces.len() == field_pieces.piece_count {
+                    let filled_pieces = std::mem::take(&mut field_pieces.filled_pieces);
+                    // filled_pieces are in lsb to msb order
+                    let mut filled_pieces = filled_pieces.into_iter();
+                    let Some(mut value) = filled_pieces.next() else {
+                        unreachable!();
+                    };
+                    let mut value_width = value.ty().width();
+                    for next_value in filled_pieces {
+                        value = value | (next_value << value_width);
+                        value_width += next_value.ty().width();
+                    }
+                    value = value.cast_to(UInt[value_width]);
+                    let wire = self.get_field_wire(value, name);
+                    fields.insert(name, wire);
                 }
             } else {
                 let value: u32 = name.parse().expect("bit field name must have at least one letter, be all `/`, or be a valid decimal number");
@@ -476,8 +544,8 @@ impl DecodeState {
         let mut f = Some(f);
         #[hdl]
         #[track_caller]
-        fn run<FS: FieldSet, F: FnOnce(&mut DecodeState, FS)>(
-            this: &mut DecodeState,
+        fn run<'a, FS: FieldSet, F: FnOnce(&mut DecodeState<'a>, FS)>(
+            this: &mut DecodeState<'a>,
             matches: Expr<Bool>,
             fields: &mut BTreeMap<&str, Expr<UInt>>,
             f: &mut Option<F>,
@@ -1856,6 +1924,510 @@ impl DecodeState {
             );
         });
     }
+    #[hdl]
+    fn rotate_dest_logic_op(
+        &mut self,
+        msb0_mask_begin_: Expr<UInt<6>>,
+        msb0_mask_end_: Expr<UInt<6>>,
+        fallback_is_src2: bool,
+    ) -> Expr<HdlOption<ShiftRotateDestLogicOp>> {
+        #[hdl]
+        let msb0_mask_begin = wire();
+        connect(msb0_mask_begin, msb0_mask_begin_);
+        #[hdl]
+        let msb0_mask_end = wire();
+        connect(msb0_mask_end, msb0_mask_end_);
+        #[hdl]
+        let rotated_output_start: UInt<6> = wire();
+        #[hdl]
+        let rotated_output_len: UInt<6> = wire();
+
+        // gives the correct value modulo 2^6 even when `msb0_mask_begin > msb0_mask_end`
+        connect_any(
+            rotated_output_len,
+            msb0_mask_end - msb0_mask_begin + 1_hdl_u6,
+        );
+
+        // account for lsb0 vs. msb0
+        connect(rotated_output_start, !msb0_mask_end);
+
+        #[hdl]
+        let rotate_dest_logic_op = wire();
+
+        #[hdl]
+        if rotated_output_len.cmp_eq(0_hdl_u6) {
+            // it's really 64, it wrapped around to 0
+            connect(rotate_dest_logic_op, HdlNone());
+        } else {
+            connect(
+                rotate_dest_logic_op,
+                HdlSome(
+                    #[hdl]
+                    ShiftRotateDestLogicOp {
+                        rotated_output_start,
+                        rotated_output_len,
+                        fallback_is_src2,
+                    },
+                ),
+            );
+        }
+        rotate_dest_logic_op
+    }
+    #[hdl]
+    fn rotate_helper(
+        &mut self,
+        is_32bit: bool,
+        msb0_mask_begin: Expr<UInt<6>>,
+        msb0_mask_end: Expr<UInt<6>>,
+        ra: FieldRA,
+        rs: FieldRS,
+        rb: FieldRB,
+        rc: FieldRc,
+    ) {
+        // TODO: handle SO propagation
+        connect(
+            ArrayVec::len(self.output),
+            1usize.cast_to_static::<Length<_>>(),
+        );
+        let dest_logic_op = self.rotate_dest_logic_op(msb0_mask_begin, msb0_mask_end, false);
+        connect(
+            self.output[0],
+            ShiftRotateMOp::shift_rotate(
+                MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]),
+                [gpr(rs.0).value, gpr(rs.0).value, gpr(rb.0).value],
+                #[hdl]
+                ShiftRotateMOpImm {
+                    shift_rotate_amount: HdlNone(),
+                    shift_rotate_right: false,
+                    dest_logic_op,
+                },
+                OutputIntegerMode.Full64(),
+                if is_32bit {
+                    ShiftRotateMode.FunnelShift2x32Bit()
+                } else {
+                    ShiftRotateMode.FunnelShift2x64Bit()
+                },
+            ),
+        );
+    }
+    #[hdl]
+    fn rotate_imm_helper(
+        &mut self,
+        is_32bit: bool,
+        fallback_is_src2: bool,
+        msb0_mask_begin: Expr<UInt<6>>,
+        msb0_mask_end: Expr<UInt<6>>,
+        rotate_amount: Expr<UInt<6>>,
+        ra: FieldRA,
+        rs: FieldRS,
+        rc: FieldRc,
+    ) {
+        // TODO: handle SO propagation
+        connect(
+            ArrayVec::len(self.output),
+            1usize.cast_to_static::<Length<_>>(),
+        );
+        let dest_logic_op =
+            self.rotate_dest_logic_op(msb0_mask_begin, msb0_mask_end, fallback_is_src2);
+        #[hdl]
+        let rotate_imm_src2 = wire();
+        connect(rotate_imm_src2, MOpRegNum::const_zero().value);
+        // if dest_logic_op is HdlNone, we don't need to read from src2
+        #[hdl]
+        if let HdlSome(dest_logic_op) = dest_logic_op {
+            #[hdl]
+            if dest_logic_op.fallback_is_src2 {
+                connect(rotate_imm_src2, gpr(ra.0).value);
+            }
+        }
+        connect(
+            self.output[0],
+            ShiftRotateMOp::shift_rotate(
+                MOpDestReg::new([gpr(ra.0)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc.0)]),
+                [gpr(rs.0).value, gpr(rs.0).value, rotate_imm_src2],
+                #[hdl]
+                ShiftRotateMOpImm {
+                    shift_rotate_amount: HdlSome(rotate_amount),
+                    shift_rotate_right: false,
+                    dest_logic_op,
+                },
+                OutputIntegerMode.Full64(),
+                if is_32bit {
+                    ShiftRotateMode.FunnelShift2x32Bit()
+                } else {
+                    ShiftRotateMode.FunnelShift2x64Bit()
+                },
+            ),
+        );
+    }
+    /// for `rlwinm[.]/rlwnm[.]/rlwimi[.]/rldicl[.]/rldicr[.]/rldic[.]/rldcl[.]/rldcr[.]/rldimi[.]`
+    #[hdl]
+    fn decode_rotate(&mut self) {
+        match self.mnemonic.trim_end_matches('.') {
+            "rlwinm" => self.decode_scope(
+                |this, (ra, rs, FieldSH(sh), FieldMB(mb), FieldME(me), rc)| {
+                    this.rotate_imm_helper(
+                        true,
+                        false,
+                        (mb + 32u8).cast_to_static::<UInt<_>>(),
+                        (me + 32u8).cast_to_static::<UInt<_>>(),
+                        sh.cast_to_static::<UInt<_>>(),
+                        ra,
+                        rs,
+                        rc,
+                    );
+                },
+            ),
+            "rlwnm" => self.decode_scope(|this, (ra, rs, rb, FieldMB(mb), FieldME(me), rc)| {
+                this.rotate_helper(
+                    true,
+                    (mb + 32u8).cast_to_static::<UInt<_>>(),
+                    (me + 32u8).cast_to_static::<UInt<_>>(),
+                    ra,
+                    rs,
+                    rb,
+                    rc,
+                );
+            }),
+            "rlwimi" => self.decode_scope(
+                |this, (ra, rs, FieldSH(sh), FieldMB(mb), FieldME(me), rc)| {
+                    this.rotate_imm_helper(
+                        true,
+                        true,
+                        (mb + 32u8).cast_to_static::<UInt<_>>(),
+                        (me + 32u8).cast_to_static::<UInt<_>>(),
+                        sh.cast_to_static::<UInt<_>>(),
+                        ra,
+                        rs,
+                        rc,
+                    );
+                },
+            ),
+            "rldicl" => self.decode_scope(|this, (ra, rs, FieldSh(sh), FieldMb(mb), rc)| {
+                this.rotate_imm_helper(
+                    false,
+                    false,
+                    mb.rotate_right(1),
+                    63_hdl_u6,
+                    sh.rotate_right(1),
+                    ra,
+                    rs,
+                    rc,
+                );
+            }),
+            "rldicr" => self.decode_scope(|this, (ra, rs, FieldSh(sh), FieldMe(me), rc)| {
+                this.rotate_imm_helper(
+                    false,
+                    false,
+                    0_hdl_u6,
+                    me.rotate_right(1),
+                    sh.rotate_right(1),
+                    ra,
+                    rs,
+                    rc,
+                );
+            }),
+            "rldic" => self.decode_scope(|this, (ra, rs, FieldSh(sh), FieldMb(mb), rc)| {
+                this.rotate_imm_helper(
+                    false,
+                    false,
+                    mb.rotate_right(1),
+                    !sh.rotate_right(1),
+                    sh.rotate_right(1),
+                    ra,
+                    rs,
+                    rc,
+                );
+            }),
+            "rldcl" => self.decode_scope(|this, (ra, rs, rb, FieldMb(mb), rc)| {
+                this.rotate_helper(false, mb.rotate_right(1), 63_hdl_u6, ra, rs, rb, rc);
+            }),
+            "rldcr" => self.decode_scope(|this, (ra, rs, rb, FieldMe(me), rc)| {
+                this.rotate_helper(false, 0_hdl_u6, me.rotate_right(1), ra, rs, rb, rc);
+            }),
+            "rldimi" => self.decode_scope(|this, (ra, rs, FieldSh(sh), FieldMb(mb), rc)| {
+                this.rotate_imm_helper(
+                    false,
+                    true,
+                    mb.rotate_right(1),
+                    !sh.rotate_right(1),
+                    sh.rotate_right(1),
+                    ra,
+                    rs,
+                    rc,
+                );
+            }),
+            _ => unreachable!("{:?}", self.mnemonic),
+        }
+    }
+    /// for `slw[.]/srw[.]/srawi[.]/sraw[.]/sld[.]/sradi[.]/srd[.]/srad[.]`
+    #[hdl]
+    fn decode_shift(&mut self) {
+        let (is_32bit, is_signed, is_right_shift, is_immediate) =
+            match self.mnemonic.trim_end_matches('.') {
+                "slw" => (true, false, false, false),
+                "srw" => (true, false, true, false),
+                "srawi" => (true, true, true, true),
+                "sraw" => (true, true, true, false),
+                "sld" => (false, false, false, false),
+                "sradi" => (false, true, true, true),
+                "srd" => (false, false, true, false),
+                "srad" => (false, true, true, false),
+                _ => unreachable!("{:?}", self.mnemonic),
+            };
+        if is_immediate {
+            assert!(is_signed);
+            assert!(is_right_shift);
+            assert_eq!(self.arguments, Some("RA,RS,SH"));
+            if is_32bit {
+                self.decode_scope(
+                    |this, (FieldRA(ra), FieldRS(rs), FieldSH(sh), FieldRc(rc))| {
+                        // TODO: handle SO propagation
+                        connect(
+                            ArrayVec::len(this.output),
+                            1usize.cast_to_static::<Length<_>>(),
+                        );
+                        connect(
+                            this.output[0],
+                            ShiftRotateMOp::shift_rotate(
+                                MOpDestReg::new(
+                                    [gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()],
+                                    [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
+                                ),
+                                [
+                                    gpr(rs).value,
+                                    MOpRegNum::const_zero().value,
+                                    MOpRegNum::const_zero().value,
+                                ],
+                                #[hdl]
+                                ShiftRotateMOpImm {
+                                    shift_rotate_amount: HdlSome(sh.cast_to_static::<UInt<_>>()),
+                                    shift_rotate_right: true,
+                                    dest_logic_op: HdlNone(),
+                                },
+                                OutputIntegerMode.Full64(),
+                                ShiftRotateMode.SignExt32To64BitThenShift(),
+                            ),
+                        );
+                    },
+                );
+            } else {
+                self.decode_scope(
+                    |this, (FieldRA(ra), FieldRS(rs), FieldSh(sh), FieldRc(rc))| {
+                        // TODO: handle SO propagation
+                        connect(
+                            ArrayVec::len(this.output),
+                            1usize.cast_to_static::<Length<_>>(),
+                        );
+                        connect(
+                            this.output[0],
+                            ShiftRotateMOp::shift_rotate(
+                                MOpDestReg::new(
+                                    [gpr(ra), MOpRegNum::power_isa_xer_ca_ca32_reg()],
+                                    [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
+                                ),
+                                [
+                                    gpr(rs).value,
+                                    MOpRegNum::const_zero().value,
+                                    MOpRegNum::const_zero().value,
+                                ],
+                                #[hdl]
+                                ShiftRotateMOpImm {
+                                    shift_rotate_amount: HdlSome(sh.rotate_right(1)),
+                                    shift_rotate_right: true,
+                                    dest_logic_op: HdlNone(),
+                                },
+                                OutputIntegerMode.Full64(),
+                                ShiftRotateMode.ShiftSigned64(),
+                            ),
+                        );
+                    },
+                );
+            }
+        } else {
+            assert_eq!(self.arguments, Some("RA,RS,RB"));
+            self.decode_scope(
+                |this, (FieldRA(ra), FieldRS(rs), FieldRB(rb), FieldRc(rc))| {
+                    // TODO: handle SO propagation
+                    connect(
+                        ArrayVec::len(this.output),
+                        1usize.cast_to_static::<Length<_>>(),
+                    );
+                    connect(
+                        this.output[0],
+                        ShiftRotateMOp::shift_rotate(
+                            MOpDestReg::new(
+                                [
+                                    gpr(ra),
+                                    if is_signed && is_right_shift {
+                                        MOpRegNum::power_isa_xer_ca_ca32_reg()
+                                    } else {
+                                        MOpRegNum::const_zero()
+                                    },
+                                ],
+                                [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)],
+                            ),
+                            if !is_signed && is_right_shift {
+                                [MOpRegNum::const_zero().value, gpr(rs).value, gpr(rb).value]
+                            } else {
+                                [gpr(rs).value, MOpRegNum::const_zero().value, gpr(rb).value]
+                            },
+                            #[hdl]
+                            ShiftRotateMOpImm {
+                                shift_rotate_amount: HdlNone(),
+                                shift_rotate_right: is_right_shift,
+                                dest_logic_op: HdlNone(),
+                            },
+                            OutputIntegerMode.Full64(),
+                            match (is_32bit, is_signed, is_right_shift) {
+                                (false, _, false) => ShiftRotateMode.FunnelShift2x64Bit(),
+                                (false, false, true) => ShiftRotateMode.FunnelShift2x64Bit(),
+                                (false, true, true) => ShiftRotateMode.ShiftSigned64(),
+                                (true, _, false) => ShiftRotateMode.FunnelShift2x32Bit(),
+                                (true, false, true) => ShiftRotateMode.FunnelShift2x32Bit(),
+                                (true, true, true) => ShiftRotateMode.SignExt32To64BitThenShift(),
+                            },
+                        ),
+                    );
+                },
+            );
+        }
+    }
+    /// for `extswsli[.]`
+    #[hdl]
+    fn decode_extswsli(&mut self) {
+        self.decode_scope(
+            |this, (FieldRA(ra), FieldRS(rs), FieldSh(sh), FieldRc(rc))| {
+                connect(
+                    ArrayVec::len(this.output),
+                    1usize.cast_to_static::<Length<_>>(),
+                );
+                connect(
+                    this.output[0],
+                    ShiftRotateMOp::shift_rotate(
+                        MOpDestReg::new([gpr(ra)], [(MOpRegNum::POWER_ISA_CR_0_REG_NUM, rc)]),
+                        [
+                            gpr(rs).value,
+                            MOpRegNum::const_zero().value,
+                            MOpRegNum::const_zero().value,
+                        ],
+                        #[hdl]
+                        ShiftRotateMOpImm {
+                            shift_rotate_amount: HdlSome(sh.rotate_right(1)),
+                            shift_rotate_right: false,
+                            dest_logic_op: HdlNone(),
+                        },
+                        OutputIntegerMode.Full64(),
+                        ShiftRotateMode.SignExt32To64BitThenShift(),
+                    ),
+                );
+            },
+        );
+    }
+    fn read_write_spr(
+        &mut self,
+        spr: PowerIsaSprEnum,
+        reg: Expr<FieldGpr>,
+        is_write_to_spr: bool,
+    ) -> Result<(), ()> {
+        let normal_move = |spr: Expr<MOpRegNum>| {
+            connect(
+                ArrayVec::len(self.output),
+                1usize.cast_to_static::<Length<_>>(),
+            );
+            if is_write_to_spr {
+                connect(
+                    self.output[0],
+                    MoveRegMOp::move_reg(
+                        MOpDestReg::new([spr], []),
+                        [gpr(reg).value],
+                        0.cast_to_static::<SInt<_>>(),
+                    ),
+                );
+            } else {
+                connect(
+                    self.output[0],
+                    MoveRegMOp::move_reg(
+                        MOpDestReg::new([gpr(reg)], []),
+                        [spr.value],
+                        0.cast_to_static::<SInt<_>>(),
+                    ),
+                );
+            }
+            Ok(())
+        };
+        let read_special = |imm: Expr<ReadSpecialMOpImm>| {
+            connect(
+                ArrayVec::len(self.output),
+                1usize.cast_to_static::<Length<_>>(),
+            );
+            connect(
+                self.output[0],
+                ReadSpecialMOp::read_special(
+                    MOpDestReg::new([gpr(reg)], []),
+                    [MOpRegNum::const_zero().value; 0],
+                    imm,
+                ),
+            );
+            Ok(())
+        };
+        match spr {
+            // PowerIsaSprEnum::Xer => todo!(),
+            PowerIsaSprEnum::Lr => normal_move(MOpRegNum::power_isa_lr_reg()),
+            PowerIsaSprEnum::Ctr => normal_move(MOpRegNum::power_isa_ctr_reg()),
+            PowerIsaSprEnum::Tar => normal_move(MOpRegNum::power_isa_tar_reg()),
+            PowerIsaSprEnum::Tb if !is_write_to_spr => {
+                read_special(ReadSpecialMOpImm.PowerIsaTimeBase())
+            }
+            PowerIsaSprEnum::Tbu if !is_write_to_spr => {
+                read_special(ReadSpecialMOpImm.PowerIsaTimeBaseU())
+            }
+            _ => {
+                Err(()) // allow emulation
+            }
+        }
+    }
+    /// for `mtspr/mfspr/mftb`
+    fn decode_mtspr_mfspr_mftb(&mut self) {
+        #[hdl]
+        fn do_read_write_spr(
+            this: &mut DecodeState<'_>,
+            spr_field: Expr<UInt<10>>,
+            reg: Expr<FieldGpr>,
+            is_write_to_spr: bool,
+        ) {
+            #[hdl]
+            let spr_num = wire();
+            connect(spr_num, spr_field.rotate_left(5));
+            connect(this.is_illegal, true); // trap and/or allow emulation
+            for &spr in PowerIsaSprEnum::VARIANTS {
+                let num = spr.to_expr().num;
+                #[hdl]
+                if spr_num.cmp_eq(num) {
+                    match this.read_write_spr(spr, reg, is_write_to_spr) {
+                        Ok(()) => {
+                            connect(this.is_illegal, false);
+                        }
+                        Err(()) => {
+                            // self.is_illegal is already set to true
+                        }
+                    }
+                }
+            }
+        }
+        match self.mnemonic {
+            "mtspr" => self.decode_scope(|this, (FieldSpr(spr), FieldRS(rs))| {
+                do_read_write_spr(this, spr, rs, true)
+            }),
+            "mfspr" => self.decode_scope(|this, (FieldRT(rt), FieldSpr(spr))| {
+                do_read_write_spr(this, spr, rt, false)
+            }),
+            "mftb" => self.decode_scope(|this, (FieldRT(rt), FieldTbr(tbr))| {
+                do_read_write_spr(this, tbr, rt, false)
+            }),
+            _ => unreachable!(),
+        }
+    }
     /// for `mcrxrx`
     #[hdl]
     fn decode_mcrxrx(&mut self) {
@@ -1902,23 +2474,25 @@ impl DecodeState {
     }
 }
 
-type DecodeFn = fn(&mut DecodeState);
+type DecodeFn = fn(&mut DecodeState<'_>);
 
 const DECODE_FNS: &[(&[&str], DecodeFn)] = &[
-    (&["b", "ba", "bl", "bla"], DecodeState::decode_b_ba_bl_bla),
+    (&["b", "ba", "bl", "bla"], |state| {
+        DecodeState::decode_b_ba_bl_bla(state)
+    }),
     (
         &[
             "bc", "bca", "bcl", "bcla", "bclr", "bclrl", "bcctr", "bcctrl", "bctar", "bctarl",
         ],
-        DecodeState::decode_bc_bclr_bcctr_bctar,
+        |state| DecodeState::decode_bc_bclr_bcctr_bctar(state),
     ),
     (
         &[
             "crand", "crnand", "cror", "crxor", "crnor", "creqv", "crandc", "crorc",
         ],
-        DecodeState::decode_crand_crnand_cror_crxor_crnor_creqv_crandc_crorc,
+        |state| DecodeState::decode_crand_crnand_cror_crxor_crnor_creqv_crandc_crorc(state),
     ),
-    (&["mcrf"], DecodeState::decode_mcrf),
+    (&["mcrf"], |state| DecodeState::decode_mcrf(state)),
     (&["sc", "scv"], |_state| {
         // TODO
     }),
@@ -1928,14 +2502,14 @@ const DECODE_FNS: &[(&[&str], DecodeFn)] = &[
             "plha", "lhax", "lhau", "lhaux", "lwz", "plwz", "lwzx", "lwzu", "lwzux", "lwa", "plwa",
             "lwax", "lwaux", "ld", "pld", "ldx", "ldu", "ldux",
         ],
-        DecodeState::decode_load_8_16_32_64_bit,
+        |state| DecodeState::decode_load_8_16_32_64_bit(state),
     ),
     (
         &[
             "stb", "pstb", "stbx", "stbu", "stbux", "sth", "psth", "sthx", "sthu", "sthux", "stw",
             "pstw", "stwx", "stwu", "stwux", "std", "pstd", "stdx", "stdu", "stdux",
         ],
-        DecodeState::decode_store_8_16_32_64_bit,
+        |state| DecodeState::decode_store_8_16_32_64_bit(state),
     ),
     (&["lq", "plq", "stq", "pstq"], |_state| {
         // TODO
@@ -1952,43 +2526,46 @@ const DECODE_FNS: &[(&[&str], DecodeFn)] = &[
     (&["lswi", "lswx", "stswi", "stswx"], |_state| {
         // load/store string are intentionally not implemented
     }),
-    (&["addi", "paddi"], DecodeState::decode_addi_paddi),
-    (&["addis"], DecodeState::decode_addis),
-    (&["addpcis"], DecodeState::decode_addpcis),
-    (&["add", "add.", "addo", "addo."], DecodeState::decode_add),
-    (&["addic", "addic."], DecodeState::decode_addic),
-    (
-        &["subf", "subf.", "subfo", "subfo."],
-        DecodeState::decode_subf_subfc,
-    ),
-    (&["subfic"], DecodeState::decode_subfic),
-    (
-        &["addc", "addc.", "addco", "addco."],
-        DecodeState::decode_addc,
-    ),
-    (
-        &["subfc", "subfc.", "subfco", "subfco."],
-        DecodeState::decode_subf_subfc,
-    ),
-    (
-        &["adde", "adde.", "addeo", "addeo."],
-        DecodeState::decode_adde,
-    ),
-    (
-        &["subfe", "subfe.", "subfeo", "subfeo."],
-        DecodeState::decode_subfe,
-    ),
+    (&["addi", "paddi"], |state| {
+        DecodeState::decode_addi_paddi(state)
+    }),
+    (&["addis"], |state| DecodeState::decode_addis(state)),
+    (&["addpcis"], |state| DecodeState::decode_addpcis(state)),
+    (&["add", "add.", "addo", "addo."], |state| {
+        DecodeState::decode_add(state)
+    }),
+    (&["addic", "addic."], |state| {
+        DecodeState::decode_addic(state)
+    }),
+    (&["subf", "subf.", "subfo", "subfo."], |state| {
+        DecodeState::decode_subf_subfc(state)
+    }),
+    (&["subfic"], |state| DecodeState::decode_subfic(state)),
+    (&["addc", "addc.", "addco", "addco."], |state| {
+        DecodeState::decode_addc(state)
+    }),
+    (&["subfc", "subfc.", "subfco", "subfco."], |state| {
+        DecodeState::decode_subf_subfc(state)
+    }),
+    (&["adde", "adde.", "addeo", "addeo."], |state| {
+        DecodeState::decode_adde(state)
+    }),
+    (&["subfe", "subfe.", "subfeo", "subfeo."], |state| {
+        DecodeState::decode_subfe(state)
+    }),
     (
         &[
             "addme", "addme.", "addmeo", "addmeo.", "addze", "addze.", "addzeo", "addzeo.",
             "subfme", "subfme.", "subfmeo", "subfmeo.", "subfze", "subfze.", "subfzeo", "subfzeo.",
         ],
-        DecodeState::decode_addme_subfme_addze_subfze,
+        |state| DecodeState::decode_addme_subfme_addze_subfze(state),
     ),
     (&["addex"], |_state| {
         // TODO
     }),
-    (&["neg", "neg.", "nego", "nego."], DecodeState::decode_neg),
+    (&["neg", "neg.", "nego", "nego."], |state| {
+        DecodeState::decode_neg(state)
+    }),
     (
         &[
             "mulli", "mullw", "mullw.", "mullwo", "mullwo.", "mulhw", "mulhw.", "mulhwu", "mulhwu.",
@@ -2029,12 +2606,12 @@ const DECODE_FNS: &[(&[&str], DecodeFn)] = &[
             // TODO
         },
     ),
-    (&["cmpi"], DecodeState::decode_cmpi),
-    (&["cmp"], DecodeState::decode_cmp),
-    (&["cmpli"], DecodeState::decode_cmpli),
-    (&["cmpl"], DecodeState::decode_cmpl),
-    (&["cmprb"], DecodeState::decode_cmprb),
-    (&["cmpeqb"], DecodeState::decode_cmpeqb),
+    (&["cmpi"], |state| DecodeState::decode_cmpi(state)),
+    (&["cmp"], |state| DecodeState::decode_cmp(state)),
+    (&["cmpli"], |state| DecodeState::decode_cmpli(state)),
+    (&["cmpl"], |state| DecodeState::decode_cmpl(state)),
+    (&["cmprb"], |state| DecodeState::decode_cmprb(state)),
+    (&["cmpeqb"], |state| DecodeState::decode_cmpeqb(state)),
     (&["twi", "tw", "tdi", "td"], |_state| {
         // TODO
     }),
@@ -2043,18 +2620,18 @@ const DECODE_FNS: &[(&[&str], DecodeFn)] = &[
     }),
     (
         &["andi.", "andis.", "ori", "oris", "xori", "xoris"],
-        DecodeState::decode_andis_oris_xoris,
+        |state| DecodeState::decode_andis_oris_xoris(state),
     ),
     (
         &[
             "and", "and.", "xor", "xor.", "nand", "nand.", "or", "or.", "orc", "orc.", "nor",
             "nor.", "eqv", "eqv.", "andc", "andc.",
         ],
-        DecodeState::decode_and_xor_nand_or_orc_nor_eqv_andc,
+        |state| DecodeState::decode_and_xor_nand_or_orc_nor_eqv_andc(state),
     ),
     (
         &["extsb", "extsb.", "extsh", "extsh.", "extsw", "extsw."],
-        DecodeState::decode_extsb_extsh_extsw,
+        |state| DecodeState::decode_extsb_extsh_extsw(state),
     ),
     (&["cmpb"], |_state| {
         // TODO
@@ -2075,21 +2652,17 @@ const DECODE_FNS: &[(&[&str], DecodeFn)] = &[
             "rldicr", "rldicr.", "rldic", "rldic.", "rldcl", "rldcl.", "rldcr", "rldcr.", "rldimi",
             "rldimi.",
         ],
-        |_state| {
-            // TODO
-        },
+        |state| DecodeState::decode_rotate(state),
     ),
     (
         &[
             "slw", "slw.", "srw", "srw.", "srawi", "srawi.", "sraw", "sraw.", "sld", "sld.",
             "sradi", "sradi.", "srd", "srd.", "srad", "srad.",
         ],
-        |_state| {
-            // TODO
-        },
+        |state| DecodeState::decode_shift(state),
     ),
-    (&["extswsli", "extswsli."], |_state| {
-        // TODO
+    (&["extswsli", "extswsli."], |state| {
+        DecodeState::decode_extswsli(state)
     }),
     (&["cdtbcd", "cbcdtd", "addg6s"], |_state| {
         // TODO
@@ -2108,13 +2681,13 @@ const DECODE_FNS: &[(&[&str], DecodeFn)] = &[
             // TODO(FP) -- mostly intentionally not implemented
         },
     ),
-    (
-        &["mtspr", "mfspr", "mftb", "mtmsr", "mtmsrd", "mfmsr"],
-        |_state| {
-            // TODO
-        },
-    ),
-    (&["mcrxrx"], DecodeState::decode_mcrxrx),
+    (&["mtspr", "mfspr", "mftb"], |state| {
+        DecodeState::decode_mtspr_mfspr_mftb(state)
+    }),
+    (&["mtmsr", "mtmsrd", "mfmsr"], |_state| {
+        // TODO
+    }),
+    (&["mcrxrx"], |state| DecodeState::decode_mcrxrx(state)),
     (
         &[
             "mtocrf", "mtcrf", "mfocrf", "mfcr", "setb", "setbc", "setbcr", "setnbc", "setnbcr",
@@ -2123,7 +2696,7 @@ const DECODE_FNS: &[(&[&str], DecodeFn)] = &[
             // TODO
         },
     ),
-    (&["pnop"], DecodeState::decode_pnop),
+    (&["pnop"], |state| DecodeState::decode_pnop(state)),
     (FP_MNEMONICS, |_state| {
         // TODO(FP)
     }),
@@ -2217,6 +2790,7 @@ pub fn decode_one_insn() {
             assert!(!duplicate, "duplicate mnemonic in DECODE_FNS: {mnemonic:?}");
         }
     }
+    let mut field_wires = Default::default();
     for insn in Instructions::get().instructions() {
         for header in insn.header() {
             for mnemonic_line in header.mnemonics().lines() {
@@ -2260,6 +2834,7 @@ pub fn decode_one_insn() {
                     first_input,
                     second_input,
                     second_input_used,
+                    field_wires: &mut field_wires,
                 });
             }
         }
diff --git a/crates/cpu/src/instruction.rs b/crates/cpu/src/instruction.rs
index c889610..1f9f5ae 100644
--- a/crates/cpu/src/instruction.rs
+++ b/crates/cpu/src/instruction.rs
@@ -11,7 +11,7 @@ use fayalite::{
     intern::Interned,
     module::wire_with_loc,
     prelude::*,
-    ty::StaticType,
+    ty::{StaticType, TypeProperties},
     util::ConstBool,
 };
 use std::{
@@ -130,32 +130,54 @@ pub trait MOpTrait: Type {
 pub trait CommonMOpTrait: MOpTrait {
     type PrefixPad: KnownSize;
     type SrcCount: KnownSize;
+    type Imm: Type;
     type CommonMOpTraitMapped<NewDestReg: Type, NewSrcRegWidth: Size>: CommonMOpTrait<
             DestReg = NewDestReg,
             SrcRegWidth = NewSrcRegWidth,
             PrefixPad = Self::PrefixPad,
             SrcCount = Self::SrcCount,
+            Imm = Self::Imm,
         >;
     type CommonMOpTraitDestReg: Type;
     type CommonMOpTraitSrcRegWidth: Size;
     fn common_mop_ty(
         self,
-    ) -> CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount>;
+    ) -> CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount, Self::Imm>;
     fn common_mop(
         input: impl ToExpr<Type = Self>,
-    ) -> Expr<CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount>>;
+    ) -> Expr<CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount, Self::Imm>>;
     fn with_common_mop_ty<NewDestReg: Type, NewSrcRegWidth: Size>(
         self,
-        new_common_mop_ty: CommonMOp<Self::PrefixPad, NewDestReg, NewSrcRegWidth, Self::SrcCount>,
+        new_common_mop_ty: CommonMOp<
+            Self::PrefixPad,
+            NewDestReg,
+            NewSrcRegWidth,
+            Self::SrcCount,
+            Self::Imm,
+        >,
     ) -> Self::Mapped<NewDestReg, NewSrcRegWidth>;
     fn with_common_mop<NewDestReg: Type, NewSrcRegWidth: Size>(
         input: impl ToExpr<Type = Self>,
         new_common_mop: impl ToExpr<
-            Type = CommonMOp<Self::PrefixPad, NewDestReg, NewSrcRegWidth, Self::SrcCount>,
+            Type = CommonMOp<
+                Self::PrefixPad,
+                NewDestReg,
+                NewSrcRegWidth,
+                Self::SrcCount,
+                Self::Imm,
+            >,
         >,
     ) -> Expr<Self::Mapped<NewDestReg, NewSrcRegWidth>>;
 }
 
+pub type CommonMOpFor<T> = CommonMOp<
+    <T as CommonMOpTrait>::PrefixPad,
+    <T as CommonMOpTrait>::CommonMOpTraitDestReg,
+    <T as CommonMOpTrait>::CommonMOpTraitSrcRegWidth,
+    <T as CommonMOpTrait>::SrcCount,
+    <T as CommonMOpTrait>::Imm,
+>;
+
 impl<T: CommonMOpTrait> MOpTrait for T {
     type Mapped<NewDestReg: Type, NewSrcRegWidth: Size> =
         T::CommonMOpTraitMapped<NewDestReg, NewSrcRegWidth>;
@@ -185,10 +207,15 @@ impl<T: CommonMOpTrait> MOpTrait for T {
         new_dest_reg: NewDestReg,
         new_src_reg_width: NewSrcRegWidth::SizeType,
     ) -> Self::Mapped<NewDestReg, NewSrcRegWidth> {
-        self.with_common_mop_ty(
-            CommonMOp[T::PrefixPad::SIZE][new_dest_reg][new_src_reg_width][T::SrcCount::SIZE],
-        )
+        let common_mop_ty = self.common_mop_ty();
+        self.with_common_mop_ty(CommonMOp {
+            prefix_pad: common_mop_ty.prefix_pad,
+            dest: new_dest_reg,
+            src: ArrayType[UIntType[new_src_reg_width]][T::SrcCount::SIZE],
+            imm: common_mop_ty.imm,
+        })
     }
+    #[hdl]
     fn map_regs<NewDestReg: Type, NewSrcRegWidth: Size>(
         input: impl ToExpr<Type = Self>,
         new_dest: impl ToExpr<Type = NewDestReg>,
@@ -200,22 +227,21 @@ impl<T: CommonMOpTrait> MOpTrait for T {
     ) -> Expr<Self::Mapped<NewDestReg, NewSrcRegWidth>> {
         let input = input.to_expr();
         let common = T::common_mop(input);
-        let new_dest = new_dest.to_expr();
         T::with_common_mop(
             input,
-            CommonMOp::new(
-                common.prefix_pad,
-                new_dest,
-                ArrayLiteral::new(
+            #[hdl]
+            CommonMOp {
+                prefix_pad: common.prefix_pad,
+                dest: new_dest,
+                src: ArrayLiteral::new(
                     UIntType[new_src_reg_width],
                     Interned::from_iter(
                         (0..T::SrcCount::VALUE)
                             .map(|index| Expr::canonical(map_src(common.src[index], index))),
                     ),
-                )
-                .to_expr(),
-                CommonMOp::imm(common),
-            ),
+                ),
+                imm: common.imm,
+            },
         )
     }
 }
@@ -281,173 +307,269 @@ pub const MOP_IMM_WIDTH: usize = 34;
 pub const MOP_MIN_REG_WIDTH: usize = 8;
 pub const COMMON_MOP_SRC_LEN: usize = 3;
 pub const COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM: usize = 2;
-pub const COMMON_MOP_IMM_LOW_WIDTH: usize = CommonMOpWithMaxSrcCount::IMM_WIDTH - 1;
 
-#[hdl(cmp_eq)]
-pub struct CommonMOp<PrefixPad: KnownSize, DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> {
-    pub prefix_pad: UIntType<PrefixPad>,
-    pub dest: DestReg,
-    pub src: Array<UIntType<SrcRegWidth>, { COMMON_MOP_SRC_LEN }>,
-    pub imm_low: UInt<{ COMMON_MOP_IMM_LOW_WIDTH }>,
-    pub imm_sign: SInt<1>,
-    pub _phantom: PhantomData<SrcCount>,
+pub const fn common_mop_max_imm_size(src_count: usize) -> usize {
+    assert!(src_count <= COMMON_MOP_SRC_LEN, "too many sources");
+    assert!(COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM <= COMMON_MOP_SRC_LEN);
+    let sources_that_reduce_imm = src_count.saturating_sub(COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM);
+    MOP_IMM_WIDTH - sources_that_reduce_imm * MOP_MIN_REG_WIDTH
 }
 
-impl<PrefixPad: KnownSize, DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> CommonMOpTrait
-    for CommonMOp<PrefixPad, DestReg, SrcRegWidth, SrcCount>
+#[derive(Copy, Clone, PartialEq, Eq, Hash, Default)]
+pub struct CommonMOpDefaultImm<SrcCount: KnownSize> {
+    _phantom: PhantomData<SrcCount>,
+}
+
+#[doc(hidden)]
+pub struct CommonMOpDefaultImmNoGenerics(());
+
+#[expect(non_upper_case_globals)]
+pub const CommonMOpDefaultImm: CommonMOpDefaultImmNoGenerics = CommonMOpDefaultImmNoGenerics(());
+
+impl<SrcCount: fayalite::int::SizeType<Size: KnownSize>> std::ops::Index<SrcCount>
+    for CommonMOpDefaultImmNoGenerics
+{
+    type Output = CommonMOpDefaultImm<SrcCount::Size>;
+
+    fn index(&self, _src_count: SrcCount) -> &Self::Output {
+        const {
+            // check generics for validity
+            let _ = Self::Output::UNDERLYING_TYPE;
+            &CommonMOpDefaultImm {
+                _phantom: PhantomData,
+            }
+        }
+    }
+}
+
+impl<SrcCount: KnownSize> fmt::Debug for CommonMOpDefaultImm<SrcCount> {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(
+            f,
+            "CommonMOpDefaultImm<ConstUsize<{}>>({:?})",
+            SrcCount::VALUE,
+            Self::UNDERLYING_TYPE
+        )
+    }
+}
+
+impl<SrcCount: KnownSize> CommonMOpDefaultImm<SrcCount> {
+    pub const UNDERLYING_TYPE: SInt = SInt::new_dyn(common_mop_max_imm_size(SrcCount::VALUE));
+    pub fn as_sint<S: Size>(this: impl ToExpr<Type = Self>) -> Expr<SIntType<S>> {
+        Expr::from_canonical(Expr::canonical(this.to_expr()))
+    }
+    pub fn as_sint_dyn(this: impl ToExpr<Type = Self>) -> Expr<SInt> {
+        Expr::from_canonical(Expr::canonical(this.to_expr()))
+    }
+    pub fn from_sint<S: Size>(v: impl ToExpr<Type = SIntType<S>>) -> Expr<Self> {
+        Expr::from_canonical(Expr::canonical(v.to_expr()))
+    }
+    pub fn cast_from_sint<S: Size>(v: impl ToExpr<Type = SIntType<S>>) -> Expr<Self> {
+        Expr::from_canonical(Expr::canonical(v.to_expr().cast_to(Self::UNDERLYING_TYPE)))
+    }
+    pub fn zero(self) -> SimValue<Self> {
+        SimValue::from_value(self, Self::UNDERLYING_TYPE.zero())
+    }
+}
+
+impl<SrcCount: KnownSize> ToSimValueWithType<CommonMOpDefaultImm<SrcCount>> for SIntValue {
+    fn to_sim_value_with_type(
+        &self,
+        ty: CommonMOpDefaultImm<SrcCount>,
+    ) -> SimValue<CommonMOpDefaultImm<SrcCount>> {
+        SimValue::from_value(ty, self.clone())
+    }
+    fn into_sim_value_with_type(
+        self,
+        ty: CommonMOpDefaultImm<SrcCount>,
+    ) -> SimValue<CommonMOpDefaultImm<SrcCount>> {
+        SimValue::from_value(ty, self)
+    }
+}
+
+impl<SrcCount: KnownSize> Type for CommonMOpDefaultImm<SrcCount> {
+    type BaseType = SInt;
+    type MaskType = <Self::BaseType as Type>::MaskType;
+    type SimValue = <Self::BaseType as Type>::SimValue;
+    type MatchVariant = <Self::BaseType as Type>::MatchVariant;
+    type MatchActiveScope = <Self::BaseType as Type>::MatchActiveScope;
+    type MatchVariantAndInactiveScope = <Self::BaseType as Type>::MatchVariantAndInactiveScope;
+    type MatchVariantsIter = <Self::BaseType as Type>::MatchVariantsIter;
+
+    fn match_variants(
+        this: Expr<Self>,
+        source_location: SourceLocation,
+    ) -> Self::MatchVariantsIter {
+        Self::BaseType::match_variants(Expr::from_canonical(Expr::canonical(this)), source_location)
+    }
+
+    fn mask_type(&self) -> Self::MaskType {
+        Self::UNDERLYING_TYPE.mask_type()
+    }
+
+    fn canonical(&self) -> CanonicalType {
+        Self::UNDERLYING_TYPE.canonical()
+    }
+
+    fn from_canonical(canonical_type: CanonicalType) -> Self {
+        let underlying_type = Self::BaseType::from_canonical(canonical_type);
+        assert_eq!(underlying_type, Self::UNDERLYING_TYPE);
+        Self {
+            _phantom: PhantomData,
+        }
+    }
+
+    fn source_location() -> SourceLocation {
+        SourceLocation::caller()
+    }
+
+    fn sim_value_from_opaque(
+        &self,
+        opaque: fayalite::ty::OpaqueSimValueSlice<'_>,
+    ) -> Self::SimValue {
+        Self::UNDERLYING_TYPE.sim_value_from_opaque(opaque)
+    }
+
+    fn sim_value_clone_from_opaque(
+        &self,
+        value: &mut Self::SimValue,
+        opaque: fayalite::ty::OpaqueSimValueSlice<'_>,
+    ) {
+        Self::UNDERLYING_TYPE.sim_value_clone_from_opaque(value, opaque)
+    }
+
+    fn sim_value_to_opaque<'w>(
+        &self,
+        value: &Self::SimValue,
+        writer: fayalite::ty::OpaqueSimValueWriter<'w>,
+    ) -> fayalite::ty::OpaqueSimValueWritten<'w> {
+        Self::UNDERLYING_TYPE.sim_value_to_opaque(value, writer)
+    }
+}
+
+impl<SrcCount: KnownSize> StaticType for CommonMOpDefaultImm<SrcCount> {
+    const TYPE: Self = Self {
+        _phantom: PhantomData,
+    };
+    const MASK_TYPE: Self::MaskType = Self::MaskType::TYPE;
+    const TYPE_PROPERTIES: TypeProperties = Self::UNDERLYING_TYPE.type_properties_dyn();
+    const MASK_TYPE_PROPERTIES: TypeProperties = Self::MaskType::TYPE_PROPERTIES;
+}
+
+impl<SrcCount: KnownSize> HdlPartialEqImpl<Self> for CommonMOpDefaultImm<SrcCount> {
+    #[track_caller]
+    fn cmp_value_eq(
+        _lhs: Self,
+        lhs_value: Cow<'_, Self::SimValue>,
+        _rhs: Self,
+        rhs_value: Cow<'_, Self::SimValue>,
+    ) -> bool {
+        *lhs_value == *rhs_value
+    }
+
+    #[track_caller]
+    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
+    }
+
+    #[track_caller]
+    fn cmp_expr_ne(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        lhs.cast_to_bits().cmp_ne(rhs.cast_to_bits())
+    }
+}
+
+#[hdl(cmp_eq)]
+pub struct CommonMOp<
+    PrefixPad: KnownSize,
+    DestReg: Type,
+    SrcRegWidth: Size,
+    SrcCount: KnownSize,
+    Imm: Type,
+> {
+    pub prefix_pad: UIntType<PrefixPad>,
+    pub dest: DestReg,
+    pub src: ArrayType<UIntType<SrcRegWidth>, SrcCount>,
+    pub imm: Imm,
+}
+
+impl<PrefixPad: KnownSize, DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize, Imm: Type>
+    CommonMOp<PrefixPad, DestReg, SrcRegWidth, SrcCount, Imm>
+{
+    pub fn validate(self) {
+        let imm_type_properties = self.imm.canonical().type_properties();
+        assert!(
+            imm_type_properties.bit_width <= common_mop_max_imm_size(SrcCount::VALUE),
+            "{self:#?}",
+        );
+        // TODO: reg_alloc tests don't respect the min reg width,
+        // we should probably add padding to `CommonMOp` after `src` to compensate
+        // assert!(self.src.element().width() >= MOP_MIN_REG_WIDTH, "{self:#?}");
+    }
+}
+
+impl<PrefixPad: KnownSize, DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize, Imm: Type>
+    CommonMOpTrait for CommonMOp<PrefixPad, DestReg, SrcRegWidth, SrcCount, Imm>
 {
     type PrefixPad = PrefixPad;
     type SrcCount = SrcCount;
+    type Imm = Imm;
     type CommonMOpTraitMapped<NewDestReg: Type, NewSrcRegWidth: Size> =
-        CommonMOp<PrefixPad, NewDestReg, NewSrcRegWidth, SrcCount>;
+        CommonMOp<PrefixPad, NewDestReg, NewSrcRegWidth, SrcCount, Imm>;
     type CommonMOpTraitDestReg = DestReg;
     type CommonMOpTraitSrcRegWidth = SrcRegWidth;
     fn common_mop_ty(
         self,
-    ) -> CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount> {
+    ) -> CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount, Self::Imm>
+    {
+        self.validate();
         self
     }
     fn common_mop(
         input: impl ToExpr<Type = Self>,
-    ) -> Expr<CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount>> {
-        input.to_expr()
+    ) -> Expr<CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount, Self::Imm>>
+    {
+        let input = input.to_expr();
+        input.ty().validate();
+        input
     }
     fn with_common_mop_ty<NewDestReg: Type, NewSrcRegWidth: Size>(
         self,
-        new_common_mop_ty: CommonMOp<Self::PrefixPad, NewDestReg, NewSrcRegWidth, Self::SrcCount>,
+        new_common_mop_ty: CommonMOp<
+            Self::PrefixPad,
+            NewDestReg,
+            NewSrcRegWidth,
+            Self::SrcCount,
+            Self::Imm,
+        >,
     ) -> Self::Mapped<NewDestReg, NewSrcRegWidth> {
+        self.validate();
+        new_common_mop_ty.validate();
         new_common_mop_ty
     }
     fn with_common_mop<NewDestReg: Type, NewSrcRegWidth: Size>(
         input: impl ToExpr<Type = Self>,
         new_common_mop: impl ToExpr<
-            Type = CommonMOp<Self::PrefixPad, NewDestReg, NewSrcRegWidth, Self::SrcCount>,
+            Type = CommonMOp<
+                Self::PrefixPad,
+                NewDestReg,
+                NewSrcRegWidth,
+                Self::SrcCount,
+                Self::Imm,
+            >,
         >,
     ) -> Expr<Self::Mapped<NewDestReg, NewSrcRegWidth>> {
-        let _ = input.to_expr();
-        new_common_mop.to_expr()
+        let input = input.to_expr();
+        let new_common_mop = new_common_mop.to_expr();
+        input.ty().validate();
+        new_common_mop.ty().validate();
+        new_common_mop
     }
 }
 
-#[hdl(cmp_eq)]
-pub struct CommonMOpImmParts<ImmInSrcCount: Size> {
-    // fields must be in this exact order
-    pub imm_low: UInt<{ COMMON_MOP_IMM_LOW_WIDTH }>,
-    pub reversed_src: ArrayType<UInt<{ MOP_MIN_REG_WIDTH }>, ImmInSrcCount>,
-    pub imm_sign: SInt<1>,
-}
-
-type CommonMOpWithMaxSrcCount = CommonMOpForImm<{ COMMON_MOP_SRC_LEN }>;
-
-type CommonMOpForImm<const SRC_COUNT: usize> =
-    CommonMOp<ConstUsize<0>, (), ConstUsize<{ MOP_MIN_REG_WIDTH }>, ConstUsize<SRC_COUNT>>;
-
-pub const COMMON_MOP_0_IMM_WIDTH: usize = CommonMOpForImm::<0>::IMM_WIDTH;
-pub const COMMON_MOP_1_IMM_WIDTH: usize = CommonMOpForImm::<1>::IMM_WIDTH;
-pub const COMMON_MOP_2_IMM_WIDTH: usize = CommonMOpForImm::<2>::IMM_WIDTH;
-pub const COMMON_MOP_3_IMM_WIDTH: usize = CommonMOpForImm::<3>::IMM_WIDTH;
-const COMMON_MOP_0_IMM_IN_SRC_COUNT: usize = CommonMOpForImm::<0>::IMM_IN_SRC_COUNT;
-
-impl<PrefixPad: KnownSize, DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize>
-    CommonMOp<PrefixPad, DestReg, SrcRegWidth, SrcCount>
-{
-    pub const IMM_IN_SRC_COUNT: usize = {
-        assert!(SrcCount::VALUE <= COMMON_MOP_SRC_LEN, "too many sources");
-        const _: () = assert!(COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM <= COMMON_MOP_SRC_LEN);
-        (COMMON_MOP_SRC_LEN - COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM)
-            - SrcCount::VALUE.saturating_sub(COMMON_MOP_MIN_SRC_LEN_WITH_FULL_IMM)
-    };
-    pub const IMM_IN_SRC_RANGE: Range<usize> =
-        (COMMON_MOP_SRC_LEN - Self::IMM_IN_SRC_COUNT)..COMMON_MOP_SRC_LEN;
-    pub const IMM_WIDTH: usize = {
-        MOP_IMM_WIDTH - (COMMON_MOP_0_IMM_IN_SRC_COUNT - Self::IMM_IN_SRC_COUNT) * MOP_MIN_REG_WIDTH
-    };
-    pub fn imm_ty() -> SInt {
-        SInt::new(Self::IMM_WIDTH)
-    }
-    pub fn imm_parts_ty() -> CommonMOpImmParts<DynSize> {
-        let retval = CommonMOpImmParts[Self::IMM_IN_SRC_COUNT];
-        assert_eq!(
-            retval.canonical().bit_width(),
-            Self::IMM_WIDTH,
-            "{retval:#?}"
-        );
-        retval
-    }
-    #[hdl]
-    pub fn new(
-        prefix_pad: impl ToExpr<Type = UIntType<PrefixPad>>,
-        dest: impl ToExpr<Type = DestReg>,
-        src: impl ToExpr<Type = ArrayType<UIntType<SrcRegWidth>, SrcCount>>,
-        imm: impl ToExpr<Type = SInt>,
-    ) -> Expr<Self> {
-        let prefix_pad = prefix_pad.to_expr();
-        let dest = dest.to_expr();
-        let src_in = src.to_expr();
-        let imm = imm.to_expr();
-        assert_eq!(imm.ty(), Self::imm_ty());
-        let src_reg_ty = src_in.ty().element();
-        let imm_parts = imm.cast_to_bits().cast_bits_to(Self::imm_parts_ty());
-        let mut src = [0_hdl_u0.cast_to(src_reg_ty); COMMON_MOP_SRC_LEN];
-        for i in 0..SrcCount::VALUE {
-            src[i] = src_in[i];
-        }
-        for (reversed_src_index, src_index) in Self::IMM_IN_SRC_RANGE.rev().enumerate() {
-            src[src_index] = imm_parts.reversed_src[reversed_src_index].cast_to(src_reg_ty);
-        }
-        #[hdl]
-        Self {
-            prefix_pad,
-            dest,
-            src: ArrayLiteral::new(
-                src_reg_ty,
-                Interned::from_iter(src.iter().map(|v| Expr::canonical(*v))),
-            )
-            .to_expr(),
-            imm_low: Expr::from_dyn_int(imm[..COMMON_MOP_IMM_LOW_WIDTH]),
-            imm_sign: Expr::from_dyn_int(imm >> (Self::IMM_WIDTH - 1)),
-            _phantom: PhantomData,
-        }
-    }
-    #[hdl]
-    pub fn imm(expr: impl ToExpr<Type = Self>) -> Expr<SInt> {
-        let expr = expr.to_expr();
-        let reversed_src = Vec::from_iter(
-            Self::IMM_IN_SRC_RANGE
-                .rev()
-                .map(|src_index| expr.src[src_index].cast_to_static()),
-        );
-        let imm_parts = {
-            #[hdl]
-            CommonMOpImmParts {
-                imm_low: expr.imm_low,
-                reversed_src,
-                imm_sign: expr.imm_sign,
-            }
-        };
-        imm_parts.cast_to_bits().cast_bits_to(Self::imm_ty())
-    }
-    #[hdl]
-    pub fn connect_to_imm(expr: impl ToExpr<Type = Self>, imm: impl ToExpr<Type = SInt>) {
-        let expr = expr.to_expr();
-        let src_reg_ty = expr.ty().src.element();
-        let imm = imm.to_expr();
-        assert_eq!(imm.ty(), Self::imm_ty());
-        let imm_parts = imm.cast_to_bits().cast_bits_to(Self::imm_parts_ty());
-        let mut src = [Some(0_hdl_u0.cast_to(src_reg_ty)); COMMON_MOP_SRC_LEN];
-        for i in 0..SrcCount::VALUE {
-            src[i] = None;
-        }
-        for (reversed_src_index, src_index) in Self::IMM_IN_SRC_RANGE.rev().enumerate() {
-            src[src_index] = Some(imm_parts.reversed_src[reversed_src_index].cast_to(src_reg_ty));
-        }
-        for i in 0..COMMON_MOP_SRC_LEN {
-            if let Some(v) = src[i] {
-                connect(expr.src[i], v);
-            }
-        }
-    }
-}
+pub const COMMON_MOP_0_IMM_WIDTH: usize = common_mop_max_imm_size(0);
+pub const COMMON_MOP_1_IMM_WIDTH: usize = common_mop_max_imm_size(1);
+pub const COMMON_MOP_2_IMM_WIDTH: usize = common_mop_max_imm_size(2);
+pub const COMMON_MOP_3_IMM_WIDTH: usize = common_mop_max_imm_size(3);
 
 macro_rules! common_mop_struct {
     (
@@ -476,23 +598,24 @@ macro_rules! common_mop_struct {
         impl<$($Generic: $GenericBound),*> CommonMOpTrait for $MOp<$($Generic),*> {
             type PrefixPad = <$common_ty as CommonMOpTrait>::PrefixPad;
             type SrcCount = <$common_ty as CommonMOpTrait>::SrcCount;
+            type Imm = <$common_ty as CommonMOpTrait>::Imm;
             type CommonMOpTraitMapped<$NewDestReg: Type, $SrcRegWidth: Size> = $mapped_ty;
             type CommonMOpTraitDestReg = <$common_ty as CommonMOpTrait>::CommonMOpTraitDestReg;
             type CommonMOpTraitSrcRegWidth = <$common_ty as CommonMOpTrait>::CommonMOpTraitSrcRegWidth;
 
             fn common_mop_ty(
                 self,
-            ) -> CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount> {
+            ) -> CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount, Self::Imm> {
                 CommonMOpTrait::common_mop_ty(self.$common)
             }
             fn common_mop(
                 input: impl ToExpr<Type = Self>,
-            ) -> Expr<CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount>> {
+            ) -> Expr<CommonMOp<Self::PrefixPad, Self::DestReg, Self::SrcRegWidth, Self::SrcCount, Self::Imm>> {
                 CommonMOpTrait::common_mop(input.to_expr().$common)
             }
             fn with_common_mop_ty<NewDestReg: Type, NewSrcRegWidth: Size>(
                 self,
-                new_common_mop_ty: CommonMOp<Self::PrefixPad, NewDestReg, NewSrcRegWidth, Self::SrcCount>,
+                new_common_mop_ty: CommonMOp<Self::PrefixPad, NewDestReg, NewSrcRegWidth, Self::SrcCount, Self::Imm>,
             ) -> Self::Mapped<NewDestReg, NewSrcRegWidth> {
                 $MOp {
                     $common: CommonMOpTrait::with_common_mop_ty(self.$common, new_common_mop_ty),
@@ -503,7 +626,7 @@ macro_rules! common_mop_struct {
             fn with_common_mop<NewDestReg: Type, NewSrcRegWidth: Size>(
                 input: impl ToExpr<Type = Self>,
                 new_common_mop: impl ToExpr<
-                    Type = CommonMOp<Self::PrefixPad, NewDestReg, NewSrcRegWidth, Self::SrcCount>,
+                    Type = CommonMOp<Self::PrefixPad, NewDestReg, NewSrcRegWidth, Self::SrcCount, Self::Imm>,
                 >,
             ) -> Expr<Self::Mapped<NewDestReg, NewSrcRegWidth>> {
                 let input = input.to_expr();
@@ -811,11 +934,11 @@ macro_rules! mop_enum {
 pub(crate) use mop_enum;
 
 common_mop_struct! {
-    #[mapped(<NewDestReg, NewSrcRegWidth> AluCommonMOp<NewDestReg, NewSrcRegWidth, SrcCount>)]
+    #[mapped(<NewDestReg, NewSrcRegWidth> AluCommonMOp<NewDestReg, NewSrcRegWidth, SrcCount, Imm>)]
     #[hdl(cmp_eq)]
-    pub struct AluCommonMOp<DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> {
+    pub struct AluCommonMOp<DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize, Imm: Type> {
         #[common]
-        pub common: CommonMOp<ConstUsize<0>, DestReg, SrcRegWidth, SrcCount>,
+        pub common: CommonMOp<ConstUsize<0>, DestReg, SrcRegWidth, SrcCount, Imm>,
         pub output_integer_mode: OutputIntegerMode,
     }
 }
@@ -825,7 +948,7 @@ common_mop_struct! {
     #[hdl(cmp_eq)]
     pub struct AddSubMOp<DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> {
         #[common]
-        pub alu_common: AluCommonMOp<DestReg, SrcRegWidth, SrcCount>,
+        pub alu_common: AluCommonMOp<DestReg, SrcRegWidth, SrcCount, CommonMOpDefaultImm<SrcCount>>,
         pub invert_src0: Bool,
         /// * if this is `true`, use `alu_common.src[1]`'s [`PRegFlagsPowerISA::xer_ca`] as a carry-in/borrow-in
         /// * else, use `alu_common.src[1]` as a normal addend
@@ -855,7 +978,13 @@ impl<DestReg: Type, SrcRegWidth: Size> AddSubMOp<DestReg, SrcRegWidth, ConstUsiz
             AddSubMOp {
                 alu_common: #[hdl]
                 AluCommonMOp {
-                    common: CommonMOp::new(0_hdl_u0, dest, src, Expr::as_dyn_int(imm.to_expr())),
+                    common: #[hdl]
+                    CommonMOp {
+                        prefix_pad: 0_hdl_u0,
+                        dest,
+                        src,
+                        imm: CommonMOpDefaultImm::from_sint(imm.to_expr()),
+                    },
                     output_integer_mode,
                 },
                 invert_src0,
@@ -887,7 +1016,13 @@ impl<DestReg: Type, SrcRegWidth: Size> AddSubMOp<DestReg, SrcRegWidth, ConstUsiz
             AddSubMOp {
                 alu_common: #[hdl]
                 AluCommonMOp {
-                    common: CommonMOp::new(0_hdl_u0, dest, src, Expr::as_dyn_int(imm.to_expr())),
+                    common: #[hdl]
+                    CommonMOp {
+                        prefix_pad: 0_hdl_u0,
+                        dest,
+                        src,
+                        imm: CommonMOpDefaultImm::from_sint(imm.to_expr()),
+                    },
                     output_integer_mode,
                 },
                 invert_src0,
@@ -980,18 +1115,6 @@ pub struct LogicalFlagsMOpImm {
     pub dest_count: UIntInRangeInclusive<0, { PRegFlags::FLAG_COUNT }>,
 }
 
-#[cfg(test)]
-#[test]
-fn test_logical_flags_mop_imm_fits() {
-    let needed_width = LogicalFlagsMOpImm.canonical().bit_width();
-    type TheMOpCommon = LogicalFlagsMOpCommon<MOpDestReg, ConstUsize<{ MOpRegNum::WIDTH }>>;
-    let imm_width = TheMOpCommon::IMM_WIDTH;
-    assert!(
-        needed_width <= imm_width,
-        "needed_width={needed_width} imm_width={imm_width}",
-    );
-}
-
 /// intentionally not publicly constructable
 #[derive(Copy, Clone)]
 pub struct LogicalFlagsMOpImmFromSwizzleFnSrc<const SRC: usize> {
@@ -1080,20 +1203,6 @@ impl std::error::Error for LogicalFlagsMopImmTryFromSwizzleFnError {}
 
 impl LogicalFlagsMOpImm {
     pub const SWIZZLE_CAPACITY: usize = 4;
-    #[track_caller]
-    pub fn from_imm(imm: impl ToExpr<Type = SInt>) -> Expr<Self> {
-        let imm_ty =
-            LogicalFlagsMOpCommon::<MOpDestReg, ConstUsize<{ MOpRegNum::WIDTH }>>::imm_ty();
-        let imm = imm.to_expr();
-        assert_eq!(imm_ty, imm.ty(), "imm must have the correct width");
-        imm.cast_to(UInt[LogicalFlagsMOpImm.canonical().bit_width()])
-            .cast_bits_to(LogicalFlagsMOpImm)
-    }
-    pub fn to_imm(this: impl ToExpr<Type = Self>) -> Expr<SInt> {
-        let imm_ty =
-            LogicalFlagsMOpCommon::<MOpDestReg, ConstUsize<{ MOpRegNum::WIDTH }>>::imm_ty();
-        this.to_expr().cast_to_bits().cast_to(imm_ty)
-    }
     fn flags_operation_impl<Flags, I, IU, C, CU, Lut, U, B, AF>(
         src0_start: I,
         src1_start: I,
@@ -1384,10 +1493,6 @@ impl LogicalFlagsMOpImm {
     }
 }
 
-#[hdl]
-type LogicalFlagsMOpCommon<DestReg: Type, SrcRegWidth: Size> =
-    CommonMOp<ConstUsize<0>, DestReg, SrcRegWidth, ConstUsize<3>>;
-
 common_mop_struct! {
     #[mapped(<NewDestReg, NewSrcRegWidth> LogicalFlagsMOp<NewDestReg, NewSrcRegWidth>)]
     #[hdl(cmp_eq)]
@@ -1461,7 +1566,7 @@ common_mop_struct! {
     /// ```
     pub struct LogicalFlagsMOp<DestReg: Type, SrcRegWidth: Size> {
         #[common]
-        pub common: LogicalFlagsMOpCommon<DestReg, SrcRegWidth>,
+        pub common: CommonMOp<ConstUsize<0>, DestReg, SrcRegWidth, ConstUsize<3>, LogicalFlagsMOpImm>,
         pub lut: Lut4,
     }
 }
@@ -1474,7 +1579,7 @@ impl<DestReg: Type, SrcRegWidth: Size> LogicalFlagsMOp<DestReg, SrcRegWidth> {
     ) -> Expr<PRegValue> {
         let this = this.to_expr();
         let flags = LogicalFlagsMOpImm::flags_operation(
-            Self::imm(this),
+            this.common.imm,
             this.lut,
             src.to_expr().map(|v| v.flags),
         );
@@ -1493,10 +1598,18 @@ impl<DestReg: Type, SrcRegWidth: Size> LogicalFlagsMOp<DestReg, SrcRegWidth> {
         this: impl ToSimValue<Type = Self>,
         src: impl ToSimValue<Type = Array<PRegValue, 3>>,
     ) -> SimValue<PRegValue> {
-        let this = this.into_sim_value();
+        #[hdl(sim)]
+        let Self { common, lut } = this.into_sim_value();
+        #[hdl(sim)]
+        let CommonMOp::<_, _, _, _, _> {
+            prefix_pad: _,
+            dest: _,
+            src: _,
+            imm,
+        } = common;
         let flags = LogicalFlagsMOpImm::flags_operation_sim(
-            Self::imm(&this),
-            SimValue::into_value(this).lut,
+            imm,
+            lut,
             SimValue::into_value(src.into_sim_value()).map(|v| SimValue::into_value(v).flags),
         );
         #[hdl(sim)]
@@ -1510,12 +1623,6 @@ impl<DestReg: Type, SrcRegWidth: Size> LogicalFlagsMOp<DestReg, SrcRegWidth> {
         }
     }
     #[hdl]
-    pub fn imm(this: impl ToExpr<Type = Self>) -> Expr<LogicalFlagsMOpImm> {
-        LogicalFlagsMOpImm::from_imm(LogicalFlagsMOpCommon::<DestReg, SrcRegWidth>::imm(
-            this.to_expr().common,
-        ))
-    }
-    #[hdl]
     pub fn logical_flags<Target: MOpTrait>(
         dest: impl ToExpr<Type = DestReg>,
         src: impl ToExpr<Type = Array<UIntType<SrcRegWidth>, 3>>,
@@ -1528,12 +1635,13 @@ impl<DestReg: Type, SrcRegWidth: Size> LogicalFlagsMOp<DestReg, SrcRegWidth> {
         MOpInto::mop_into(
             #[hdl]
             LogicalFlagsMOp {
-                common: CommonMOp::new(
-                    0_hdl_u0,
+                common: #[hdl]
+                CommonMOp {
+                    prefix_pad: 0_hdl_u0,
                     dest,
                     src,
-                    LogicalFlagsMOpImm::to_imm(imm.to_expr()),
-                ),
+                    imm,
+                },
                 lut,
             },
         )
@@ -1545,7 +1653,7 @@ common_mop_struct! {
     #[hdl(cmp_eq)]
     pub struct LogicalMOp<DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> {
         #[common]
-        pub alu_common: AluCommonMOp<DestReg, SrcRegWidth, SrcCount>,
+        pub alu_common: AluCommonMOp<DestReg, SrcRegWidth, SrcCount, CommonMOpDefaultImm<SrcCount>>,
         pub lut: Lut4,
     }
 }
@@ -1567,7 +1675,13 @@ impl<DestReg: Type, SrcRegWidth: Size> LogicalMOp<DestReg, SrcRegWidth, ConstUsi
             LogicalMOp {
                 alu_common: #[hdl]
                 AluCommonMOp {
-                    common: CommonMOp::new(0_hdl_u0, dest, src, Expr::as_dyn_int(imm.to_expr())),
+                    common: #[hdl]
+                    CommonMOp {
+                        prefix_pad: 0_hdl_u0,
+                        dest,
+                        src,
+                        imm: CommonMOpDefaultImm::from_sint(imm.to_expr()),
+                    },
                     output_integer_mode,
                 },
                 lut,
@@ -1593,7 +1707,13 @@ impl<DestReg: Type, SrcRegWidth: Size> LogicalMOp<DestReg, SrcRegWidth, ConstUsi
             LogicalMOp {
                 alu_common: #[hdl]
                 AluCommonMOp {
-                    common: CommonMOp::new(0_hdl_u0, dest, src, Expr::as_dyn_int(imm.to_expr())),
+                    common: #[hdl]
+                    CommonMOp {
+                        prefix_pad: 0_hdl_u0,
+                        dest,
+                        src,
+                        imm: CommonMOpDefaultImm::from_sint(imm.to_expr()),
+                    },
                     output_integer_mode,
                 },
                 lut,
@@ -1602,6 +1722,193 @@ impl<DestReg: Type, SrcRegWidth: Size> LogicalMOp<DestReg, SrcRegWidth, ConstUsi
     }
 }
 
+#[hdl]
+pub enum ShiftRotateMode {
+    /// like `llvm.fsh[lr].i8(src0, src1, shift_rotate_amount.unwrap_or(src2))`
+    FunnelShift2x8Bit,
+    /// like `llvm.fsh[lr].i16(src0, src1, shift_rotate_amount.unwrap_or(src2))`
+    FunnelShift2x16Bit,
+    /// like `llvm.fsh[lr].i32(src0, src1, shift_rotate_amount.unwrap_or(src2))`
+    FunnelShift2x32Bit,
+    /// like `llvm.fsh[lr].i64(src0, src1, shift_rotate_amount.unwrap_or(src2))`
+    FunnelShift2x64Bit,
+    /// `shift(src0 as i8 as i64, shift_rotate_amount.unwrap_or(src2))`
+    SignExt8To64BitThenShift,
+    /// `shift(src0 as i16 as i64, shift_rotate_amount.unwrap_or(src2))`
+    SignExt16To64BitThenShift,
+    /// `shift(src0 as i32 as i64, shift_rotate_amount.unwrap_or(src2))`
+    SignExt32To64BitThenShift,
+    /// `shift(src0 as i64, shift_rotate_amount.unwrap_or(src2))`
+    ShiftSigned64,
+}
+
+impl HdlPartialEqImpl<Self> for ShiftRotateMode {
+    #[track_caller]
+    fn cmp_value_eq(
+        lhs: Self,
+        lhs_value: Cow<'_, Self::SimValue>,
+        rhs: Self,
+        rhs_value: Cow<'_, Self::SimValue>,
+    ) -> bool {
+        SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned()))
+            == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned()))
+    }
+
+    #[track_caller]
+    fn cmp_sim_value_eq(
+        lhs: Cow<'_, SimValue<Self>>,
+        rhs: Cow<'_, SimValue<Self>>,
+    ) -> SimValue<Bool> {
+        (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value()
+    }
+
+    #[track_caller]
+    fn cmp_sim_value_ne(
+        lhs: Cow<'_, SimValue<Self>>,
+        rhs: Cow<'_, SimValue<Self>>,
+    ) -> SimValue<Bool> {
+        (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value()
+    }
+
+    #[track_caller]
+    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
+    }
+}
+
+#[hdl(cmp_eq)]
+pub struct ShiftRotateDestLogicOp {
+    pub rotated_output_start: UInt<6>,
+    pub rotated_output_len: UInt<6>,
+    /// `false` for fallback is zeros, `true` for fallback is `src2`
+    pub fallback_is_src2: Bool,
+}
+
+impl ShiftRotateDestLogicOp {
+    #[hdl]
+    fn operation_impl<U64, U6, U, B, S1>(
+        rotated_output_start: U6,
+        rotated_output_len: U6,
+        fallback_is_src2: B,
+        rotated_output: U64,
+        src2: U64,
+    ) -> U64
+    where
+        U64: ValueType<Type = UInt<64>>
+            + Rotate<U6, Output = U64>
+            + std::ops::BitAnd<Output = U>
+            + std::ops::Not<Output = U64>
+            + Clone,
+        U: CastTo<Type = UInt, Output<UInt<64>> = U64>
+            + std::ops::BitAnd<U64, Output = U>
+            + std::ops::BitOr<Output = U>,
+        U6: ValueType<Type = UInt<6>>,
+        B: CastTo<Type = Bool, Output<SInt<1>> = S1>,
+        S1: CastTo<Type = SInt<1>, Output<UInt<64>> = U64>,
+        u8: std::ops::Shl<
+                U6,
+                Output: std::ops::Sub<u8, Output: CastTo<Type = UInt, Output<UInt<64>> = U64>>,
+            >,
+    {
+        let unrotated_mask = ((1u8 << rotated_output_len) - 1u8).cast_to_static::<UInt<64>>();
+        let mask = unrotated_mask.rotate_left(rotated_output_start);
+        let src1_mask = fallback_is_src2
+            .cast_to_static::<SInt<1>>()
+            .cast_to_static::<UInt<64>>();
+        ((rotated_output & mask.clone()) | (src1_mask & src2 & !mask)).cast_to_static::<UInt<64>>()
+    }
+    pub fn operation(
+        this: impl ToExpr<Type = Self>,
+        rotated_output: impl ToExpr<Type = UInt<64>>,
+        src2: impl ToExpr<Type = UInt<64>>,
+    ) -> Expr<UInt<64>> {
+        let this = this.to_expr();
+        let rotated_output = rotated_output.to_expr();
+        let src2 = src2.to_expr();
+        Self::operation_impl(
+            this.rotated_output_start,
+            this.rotated_output_len,
+            this.fallback_is_src2,
+            rotated_output,
+            src2,
+        )
+    }
+    #[hdl]
+    pub fn operation_sim(
+        this: impl ToSimValue<Type = Self>,
+        rotated_output: impl ToSimValue<Type = UInt<64>>,
+        src2: impl ToSimValue<Type = UInt<64>>,
+    ) -> SimValue<UInt<64>> {
+        #[hdl(sim)]
+        let Self {
+            rotated_output_start,
+            rotated_output_len,
+            fallback_is_src2,
+        } = this.into_sim_value();
+        let rotated_output = rotated_output.into_sim_value();
+        let src2 = src2.into_sim_value();
+        Self::operation_impl(
+            rotated_output_start,
+            rotated_output_len,
+            fallback_is_src2,
+            rotated_output,
+            src2,
+        )
+    }
+}
+
+/// immediate values for [`ShiftRotateMOp`].
+#[hdl(cmp_eq)]
+pub struct ShiftRotateMOpImm {
+    /// taken from `src2` if this is [`HdlNone`]
+    pub shift_rotate_amount: HdlOption<UInt<6>>,
+    /// `false` for shift/rotate left, `true` for shift/rotate right
+    pub shift_rotate_right: Bool,
+    pub dest_logic_op: HdlOption<ShiftRotateDestLogicOp>,
+}
+
+common_mop_struct! {
+    #[mapped(<NewDestReg, NewSrcRegWidth> ShiftRotateMOp<NewDestReg, NewSrcRegWidth>)]
+    #[hdl(cmp_eq)]
+    pub struct ShiftRotateMOp<DestReg: Type, SrcRegWidth: Size> {
+        #[common]
+        pub alu_common: AluCommonMOp<DestReg, SrcRegWidth, ConstUsize<3>, ShiftRotateMOpImm>,
+        pub mode: ShiftRotateMode,
+    }
+}
+
+impl<DestReg: Type, SrcRegWidth: Size> ShiftRotateMOp<DestReg, SrcRegWidth> {
+    #[hdl]
+    pub fn shift_rotate<Target: MOpTrait>(
+        dest: impl ToExpr<Type = DestReg>,
+        src: impl ToExpr<Type = Array<UIntType<SrcRegWidth>, 3>>,
+        imm: impl ToExpr<Type = ShiftRotateMOpImm>,
+        output_integer_mode: impl ToExpr<Type = OutputIntegerMode>,
+        mode: impl ToExpr<Type = ShiftRotateMode>,
+    ) -> Expr<Target>
+    where
+        Self: MOpInto<Target>,
+    {
+        MOpInto::mop_into(
+            #[hdl]
+            ShiftRotateMOp {
+                alu_common: #[hdl]
+                AluCommonMOp {
+                    common: #[hdl]
+                    CommonMOp {
+                        prefix_pad: 0_hdl_u0,
+                        dest,
+                        src,
+                        imm,
+                    },
+                    output_integer_mode,
+                },
+                mode,
+            },
+        )
+    }
+}
+
 #[hdl]
 pub enum CompareMode {
     U64,
@@ -1659,7 +1966,7 @@ common_mop_struct! {
     #[hdl(cmp_eq)]
     pub struct CompareMOp<DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> {
         #[common]
-        pub alu_common: AluCommonMOp<DestReg, SrcRegWidth, SrcCount>,
+        pub alu_common: AluCommonMOp<DestReg, SrcRegWidth, SrcCount, CommonMOpDefaultImm<SrcCount>>,
         pub compare_mode: CompareMode,
     }
 }
@@ -1681,7 +1988,13 @@ impl<DestReg: Type, SrcRegWidth: Size> CompareMOp<DestReg, SrcRegWidth, ConstUsi
             CompareMOp {
                 alu_common: #[hdl]
                 AluCommonMOp {
-                    common: CommonMOp::new(0_hdl_u0, dest, src, Expr::as_dyn_int(imm.to_expr())),
+                    common: #[hdl]
+                    CommonMOp {
+                        prefix_pad: 0_hdl_u0,
+                        dest,
+                        src,
+                        imm: CommonMOpDefaultImm::from_sint(imm.to_expr()),
+                    },
                     output_integer_mode,
                 },
                 compare_mode,
@@ -1707,7 +2020,13 @@ impl<DestReg: Type, SrcRegWidth: Size> CompareMOp<DestReg, SrcRegWidth, ConstUsi
             CompareMOp {
                 alu_common: #[hdl]
                 AluCommonMOp {
-                    common: CommonMOp::new(0_hdl_u0, dest, src, Expr::as_dyn_int(imm.to_expr())),
+                    common: #[hdl]
+                    CommonMOp {
+                        prefix_pad: 0_hdl_u0,
+                        dest,
+                        src,
+                        imm: CommonMOpDefaultImm::from_sint(imm.to_expr()),
+                    },
                     output_integer_mode,
                 },
                 compare_mode,
@@ -1772,7 +2091,7 @@ common_mop_struct! {
     /// The output value is the next instruction's address used for a return address when this is a call.
     pub struct BranchMOp<DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> {
         #[common]
-        pub common: CommonMOp<ConstUsize<0>, DestReg, SrcRegWidth, SrcCount>,
+        pub common: CommonMOp<ConstUsize<0>, DestReg, SrcRegWidth, SrcCount, CommonMOpDefaultImm<SrcCount>>,
         pub invert_src0_cond: Bool,
         pub src0_cond_mode: ConditionMode,
         /// `src2`'s condition passes if `src2`'s value `== 0`.
@@ -1802,7 +2121,13 @@ impl<DestReg: Type, SrcRegWidth: Size> BranchMOp<DestReg, SrcRegWidth, ConstUsiz
         MOpInto::mop_into(
             #[hdl]
             BranchMOp {
-                common: CommonMOp::new(0_hdl_u0, dest, src, Expr::as_dyn_int(imm.to_expr())),
+                common: #[hdl]
+                CommonMOp {
+                    prefix_pad: 0_hdl_u0,
+                    dest,
+                    src,
+                    imm: CommonMOpDefaultImm::from_sint(imm.to_expr()),
+                },
                 invert_src0_cond,
                 src0_cond_mode,
                 invert_src2_eq_zero: false,
@@ -1863,7 +2188,13 @@ impl<DestReg: Type, SrcRegWidth: Size> BranchMOp<DestReg, SrcRegWidth, ConstUsiz
         MOpInto::mop_into(
             #[hdl]
             BranchMOp {
-                common: CommonMOp::new(0_hdl_u0, dest, src, Expr::as_dyn_int(imm.to_expr())),
+                common: #[hdl]
+                CommonMOp {
+                    prefix_pad: 0_hdl_u0,
+                    dest,
+                    src,
+                    imm: CommonMOpDefaultImm::from_sint(imm.to_expr()),
+                },
                 invert_src0_cond,
                 src0_cond_mode,
                 invert_src2_eq_zero,
@@ -1908,6 +2239,80 @@ impl<DestReg: Type, SrcRegWidth: Size> BranchMOp<DestReg, SrcRegWidth, ConstUsiz
     }
 }
 
+#[hdl]
+pub enum ReadSpecialMOpImm {
+    PowerIsaTimeBase,
+    PowerIsaTimeBaseU,
+}
+
+impl HdlPartialEqImpl<Self> for ReadSpecialMOpImm {
+    #[track_caller]
+    fn cmp_value_eq(
+        lhs: Self,
+        lhs_value: Cow<'_, Self::SimValue>,
+        rhs: Self,
+        rhs_value: Cow<'_, Self::SimValue>,
+    ) -> bool {
+        SimValue::opaque(&SimValue::from_value(lhs, lhs_value.into_owned()))
+            == SimValue::opaque(&SimValue::from_value(rhs, rhs_value.into_owned()))
+    }
+
+    #[track_caller]
+    fn cmp_sim_value_eq(
+        lhs: Cow<'_, SimValue<Self>>,
+        rhs: Cow<'_, SimValue<Self>>,
+    ) -> SimValue<Bool> {
+        (SimValue::opaque(&lhs) == SimValue::opaque(&rhs)).to_sim_value()
+    }
+
+    #[track_caller]
+    fn cmp_sim_value_ne(
+        lhs: Cow<'_, SimValue<Self>>,
+        rhs: Cow<'_, SimValue<Self>>,
+    ) -> SimValue<Bool> {
+        (SimValue::opaque(&lhs) != SimValue::opaque(&rhs)).to_sim_value()
+    }
+
+    #[track_caller]
+    fn cmp_expr_eq(lhs: Expr<Self>, rhs: Expr<Self>) -> Expr<Bool> {
+        lhs.cast_to_bits().cmp_eq(rhs.cast_to_bits())
+    }
+}
+
+common_mop_struct! {
+    #[mapped(<NewDestReg, NewSrcRegWidth> ReadSpecialMOp<NewDestReg, NewSrcRegWidth>)]
+    #[hdl(cmp_eq)]
+    pub struct ReadSpecialMOp<DestReg: Type, SrcRegWidth: Size> {
+        #[common]
+        pub common: CommonMOp<ConstUsize<0>, DestReg, SrcRegWidth, ConstUsize<0>, ReadSpecialMOpImm>,
+    }
+}
+
+impl<DestReg: Type, SrcRegWidth: Size> ReadSpecialMOp<DestReg, SrcRegWidth> {
+    #[hdl]
+    pub fn read_special<Target: MOpTrait>(
+        dest: impl ToExpr<Type = DestReg>,
+        src: impl ToExpr<Type = Array<UIntType<SrcRegWidth>, 0>>,
+        imm: impl ToExpr<Type = ReadSpecialMOpImm>,
+    ) -> Expr<Target>
+    where
+        Self: MOpInto<Target>,
+    {
+        MOpInto::mop_into(
+            #[hdl]
+            ReadSpecialMOp {
+                common: #[hdl]
+                CommonMOp {
+                    prefix_pad: 0_hdl_u0,
+                    dest,
+                    src,
+                    imm,
+                },
+            },
+        )
+    }
+}
+
 mop_enum! {
     #[impl_mop_into = true]
     #[hdl]
@@ -1917,10 +2322,12 @@ mop_enum! {
         LogicalFlags(LogicalFlagsMOp<DestReg, SrcRegWidth>),
         Logical(LogicalMOp<DestReg, SrcRegWidth, ConstUsize<2>>),
         LogicalI(LogicalMOp<DestReg, SrcRegWidth, ConstUsize<1>>),
+        ShiftRotate(ShiftRotateMOp<DestReg, SrcRegWidth>),
         Compare(CompareMOp<DestReg, SrcRegWidth, ConstUsize<2>>),
         CompareI(CompareMOp<DestReg, SrcRegWidth, ConstUsize<1>>),
         Branch(BranchMOp<DestReg, SrcRegWidth, ConstUsize<3>>),
         BranchI(BranchMOp<DestReg, SrcRegWidth, ConstUsize<2>>),
+        ReadSpecial(ReadSpecialMOp<DestReg, SrcRegWidth>),
     }
 }
 
@@ -1929,7 +2336,7 @@ common_mop_struct! {
     #[hdl(cmp_eq)]
     pub struct ReadL2RegMOp<DestReg: Type, SrcRegWidth: Size> {
         #[common]
-        pub common: CommonMOp<ConstUsize<3>, DestReg, SrcRegWidth, ConstUsize<0>>,
+        pub common: CommonMOp<ConstUsize<3>, DestReg, SrcRegWidth, ConstUsize<0>, CommonMOpDefaultImm<ConstUsize<0>>>,
     }
 }
 
@@ -1938,7 +2345,7 @@ common_mop_struct! {
     #[hdl(cmp_eq)]
     pub struct WriteL2RegMOp<DestReg: Type, SrcRegWidth: Size> {
         #[common]
-        pub common: CommonMOp<ConstUsize<3>, DestReg, SrcRegWidth, ConstUsize<1>>,
+        pub common: CommonMOp<ConstUsize<3>, DestReg, SrcRegWidth, ConstUsize<1>, CommonMOpDefaultImm<ConstUsize<1>>>,
     }
 }
 
@@ -2040,7 +2447,7 @@ common_mop_struct! {
     /// `src0` is always the address to load from or store to.
     pub struct LoadStoreCommonMOp<DestReg: Type, SrcRegWidth: Size, SrcCount: KnownSize> {
         #[common]
-        pub common: CommonMOp<ConstUsize<3>, DestReg, SrcRegWidth, SrcCount>,
+        pub common: CommonMOp<ConstUsize<3>, DestReg, SrcRegWidth, SrcCount, CommonMOpDefaultImm<SrcCount>>,
         pub width: LoadStoreWidth,
         pub conversion: LoadStoreConversion,
     }
@@ -2071,12 +2478,13 @@ impl<DestReg: Type, SrcRegWidth: Size> LoadMOp<DestReg, SrcRegWidth> {
             LoadMOp {
                 load_store_common: #[hdl]
                 LoadStoreCommonMOp {
-                    common: CommonMOp::new(
-                        0.cast_to_static::<UInt<_>>(),
+                    common: #[hdl]
+                    CommonMOp {
+                        prefix_pad: UInt::TYPE.zero(),
                         dest,
                         src,
-                        SInt[COMMON_MOP_1_IMM_WIDTH].zero(),
-                    ),
+                        imm: CommonMOpDefaultImm::TYPE.zero(),
+                    },
                     width,
                     conversion,
                 },
@@ -2111,12 +2519,13 @@ impl<DestReg: Type, SrcRegWidth: Size> StoreMOp<DestReg, SrcRegWidth> {
             StoreMOp {
                 load_store_common: #[hdl]
                 LoadStoreCommonMOp {
-                    common: CommonMOp::new(
-                        0.cast_to_static::<UInt<_>>(),
+                    common: #[hdl]
+                    CommonMOp {
+                        prefix_pad: UInt::TYPE.zero(),
                         dest,
                         src,
-                        SInt[COMMON_MOP_2_IMM_WIDTH].zero(),
-                    ),
+                        imm: CommonMOpDefaultImm::TYPE.zero(),
+                    },
                     width,
                     conversion,
                 },
@@ -2139,7 +2548,7 @@ common_mop_struct! {
     #[hdl(cmp_eq)]
     pub struct MoveRegMOp<DestReg: Type, SrcRegWidth: Size> {
         #[common]
-        pub common: CommonMOp<ConstUsize<4>, DestReg, SrcRegWidth, ConstUsize<1>>,
+        pub common: CommonMOp<ConstUsize<4>, DestReg, SrcRegWidth, ConstUsize<1>, CommonMOpDefaultImm<ConstUsize<1>>>,
     }
 }
 
@@ -2174,12 +2583,13 @@ impl<DestReg: Type, SrcRegWidth: Size> MoveRegMOp<DestReg, SrcRegWidth> {
         MOpInto::mop_into(
             #[hdl]
             MoveRegMOp {
-                common: CommonMOp::new(
-                    0.cast_to_static::<UInt<_>>(),
+                common: #[hdl]
+                CommonMOp {
+                    prefix_pad: UInt::TYPE.zero(),
                     dest,
                     src,
-                    Expr::as_dyn_int(imm.to_expr()),
-                ),
+                    imm: CommonMOpDefaultImm::from_sint(imm),
+                },
             },
         )
     }
diff --git a/crates/cpu/src/instruction/power_isa.rs b/crates/cpu/src/instruction/power_isa.rs
index d751ae5..496ed51 100644
--- a/crates/cpu/src/instruction/power_isa.rs
+++ b/crates/cpu/src/instruction/power_isa.rs
@@ -221,3 +221,238 @@ impl MOpRegNum {
         }
     }
 }
+
+#[hdl(cmp_eq)]
+pub struct PowerIsaSpr {
+    pub num: UInt<10>,
+}
+
+macro_rules! make_spr_enum {
+    (
+        $(#[$enum_meta:meta])*
+        $enum_vis:vis enum $PowerIsaSprEnum:ident {
+            $($enum_body:tt)*
+        }
+    ) => {
+        $(#[$enum_meta])*
+        $enum_vis enum $PowerIsaSprEnum {
+            $($enum_body)*
+            Unknown(u16),
+        }
+
+        make_spr_enum! {
+            @impl
+            $enum_vis enum $PowerIsaSprEnum {
+                $($enum_body)*
+            }
+        }
+    };
+    (
+        @impl
+        $enum_vis:vis enum $PowerIsaSprEnum:ident {
+            $(
+                $(#[$variant_meta:meta])*
+                $Variant:ident = $value:literal,
+            )+
+        }
+    ) => {
+        impl $PowerIsaSprEnum {
+            pub const VARIANTS: &[Self; 1 << 10] = &{
+                let mut retval = [Self::Unknown(0); 1 << 10];
+                let mut i = 0;
+                while i < retval.len() {
+                    retval[i] = Self::Unknown(i as u16);
+                    i += 1;
+                }
+                let mut last_value = None;
+                #[track_caller]
+                const fn add_variant(
+                    values: &mut [$PowerIsaSprEnum; 1 << 10],
+                    last_value: &mut Option<u16>,
+                    variant: $PowerIsaSprEnum,
+                    value: u16,
+                ) {
+                    assert!(value < 1 << 10, "variant value out of range");
+                    if let Some(last_value) = *last_value {
+                        assert!(last_value < value, "variants must be in ascending order with no duplicates");
+                    }
+                    *last_value = Some(value);
+                    values[value as usize] = variant;
+                }
+                $(add_variant(&mut retval, &mut last_value, Self::$Variant, $value);)+
+                retval
+            };
+            pub const fn value(self) -> u16 {
+                match self {
+                    $(Self::$Variant => $value,)+
+                    Self::Unknown(v) => v,
+                }
+            }
+        }
+    };
+}
+
+make_spr_enum! {
+    #[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
+    #[repr(u16)]
+    pub enum PowerIsaSprEnum {
+        Xer = 1,
+        UserDscr = 3,
+        Lr = 8,
+        Ctr = 9,
+        UserAmr = 13,
+        Dscr = 17,
+        Dsisr = 18,
+        Dar = 19,
+        Dec = 22,
+        Srr0 = 26,
+        Srr1 = 27,
+        Cfar = 28,
+        Amr = 29,
+        Pidr = 48,
+        Iamr = 61,
+        ReadCtrl = 136,
+        WriteCtrl = 152,
+        Fscr = 153,
+        Uamor = 157,
+        Pspb = 159,
+        Dpdes = 176,
+        Dawr0 = 180,
+        Dawr1 = 181,
+        Rpr = 186,
+        Ciabr = 187,
+        Dawrx0 = 188,
+        Dawrx1 = 189,
+        Hfscr = 190,
+        Vrsave = 256,
+        UserSprg3 = 259,
+        Tb = 268,
+        Tbu = 269,
+        Sprg0 = 272,
+        Sprg1 = 273,
+        Sprg2 = 274,
+        Sprg3 = 275,
+        Tbl = 284,
+        WriteTbu = 285,
+        Tbu40 = 286,
+        Pvr = 287,
+        Hsprg0 = 304,
+        Hsprg1 = 305,
+        Hdsisr = 306,
+        Hdar = 307,
+        Spurr = 308,
+        Purr = 309,
+        Hdec = 310,
+        Hrmor = 313,
+        Hsrr0 = 314,
+        Hsrr1 = 315,
+        Lpcr = 318,
+        Lpidr = 319,
+        Hmer = 336,
+        Hmeer = 337,
+        Pcr = 338,
+        Heir = 339,
+        Amor = 349,
+        Tir = 446,
+        UserHdexcr = 455,
+        Ptcr = 464,
+        Hashkeyr = 468,
+        Hashpkeyr = 469,
+        Hdexcr = 471,
+        Usprg0 = 496,
+        Usprg1 = 497,
+        Urmor = 505,
+        Usrr0 = 506,
+        Usrr1 = 507,
+        Smfctrl = 511,
+        UserSier2 = 736,
+        UserSier3 = 737,
+        UserMmcr3 = 738,
+        Sier2 = 752,
+        Sier3 = 753,
+        Mmcr3 = 754,
+        UserSier = 768,
+        Mmcr2 = 769,
+        Mmcra = 770,
+        Pmc1 = 771,
+        Pmc2 = 772,
+        Pmc3 = 773,
+        Pmc4 = 774,
+        Pmc5 = 775,
+        Pmc6 = 776,
+        Mmcr0 = 779,
+        Siar = 780,
+        Sdar = 781,
+        Mmcr1 = 782,
+        Sier = 784,
+        PrivMmcr2 = 785,
+        PrivMmcra = 786,
+        PrivPmc1 = 787,
+        PrivPmc2 = 788,
+        PrivPmc3 = 789,
+        PrivPmc4 = 790,
+        PrivPmc5 = 791,
+        PrivPmc6 = 792,
+        PrivMmcr0 = 795,
+        PrivSiar = 796,
+        PrivSdar = 797,
+        PrivMmcr1 = 798,
+        Bescrs15 = 800,
+        Bescrsu16 = 801,
+        Bescrr15 = 802,
+        Bescrru16 = 803,
+        Ebbhr = 804,
+        Ebbrr = 805,
+        Bescr = 806,
+        Reserved808 = 808,
+        Reserved809 = 809,
+        Reserved810 = 810,
+        Reserved811 = 811,
+        UserDexcr = 812,
+        Tar = 815,
+        Asdr = 816,
+        Psscr = 823,
+        Dexcr = 828,
+        Ic = 848,
+        Vtb = 849,
+        HyperPsscr = 855,
+        Ppr = 896,
+        Ppr32 = 898,
+        Pir = 1023,
+    }
+}
+
+impl ValueType for PowerIsaSprEnum {
+    type Type = PowerIsaSpr;
+    type ValueCategory = fayalite::expr::value_category::ValueCategoryValue;
+
+    fn ty(&self) -> Self::Type {
+        PowerIsaSpr
+    }
+}
+
+impl ToExpr for PowerIsaSprEnum {
+    #[hdl]
+    fn to_expr(&self) -> Expr<Self::Type> {
+        #[hdl]
+        PowerIsaSpr {
+            num: self.value().cast_to_static::<UInt<_>>(),
+        }
+    }
+}
+
+impl ToSimValueWithType<PowerIsaSpr> for PowerIsaSprEnum {
+    fn to_sim_value_with_type(&self, _ty: PowerIsaSpr) -> SimValue<PowerIsaSpr> {
+        self.to_sim_value()
+    }
+}
+
+impl ToSimValue for PowerIsaSprEnum {
+    #[hdl]
+    fn to_sim_value(&self) -> SimValue<Self::Type> {
+        #[hdl(sim)]
+        PowerIsaSpr {
+            num: self.value().cast_to_static::<UInt<_>>(),
+        }
+    }
+}
diff --git a/crates/cpu/src/unit/alu_branch.rs b/crates/cpu/src/unit/alu_branch.rs
index 90d7b32..6815ae6 100644
--- a/crates/cpu/src/unit/alu_branch.rs
+++ b/crates/cpu/src/unit/alu_branch.rs
@@ -4,9 +4,9 @@
 use crate::{
     config::CpuConfig,
     instruction::{
-        AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOp,
-        CompareMOp, LogicalFlagsMOp, LogicalMOp, MOpTrait, OutputIntegerMode, RenamedMOp,
-        UnitOutRegNum,
+        AddSubMOp, AluBranchMOp, AluCommonMOp, BranchMOp, COMMON_MOP_SRC_LEN, CommonMOpDefaultImm,
+        CompareMOp, LogicalFlagsMOp, LogicalMOp, MOpTrait, OutputIntegerMode, ReadSpecialMOp,
+        RenamedMOp, ShiftRotateMOp, UnitOutRegNum,
     },
     register::{
         FlagsMode, PRegFlagsPowerISA, PRegFlagsPowerISAView, PRegFlagsViewTrait, PRegFlagsX86,
@@ -42,11 +42,11 @@ fn add_sub<SrcCount: KnownSize>(
         add_pc,
     } = mop;
     #[hdl]
-    let AluCommonMOp::<_, _, _> {
+    let AluCommonMOp::<_, _, _, _> {
         common,
         output_integer_mode,
     } = alu_common;
-    let imm: Expr<UInt<64>> = CommonMOp::imm(common).cast_to_static();
+    let imm = CommonMOpDefaultImm::as_sint_dyn(common.imm).cast_to_static::<UInt<64>>();
     #[hdl]
     let carry_in_before_inversion = wire();
     connect(carry_in_before_inversion, false);
@@ -285,6 +285,20 @@ fn logical_i(
     }
 }
 
+#[hdl]
+fn shift_rotate(
+    mop: Expr<ShiftRotateMOp<UnitOutRegNum<DynSize>, DynSize>>,
+    flags_mode: Expr<FlagsMode>,
+    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<UnitResultCompleted<()>> {
+    // TODO: finish
+    #[hdl]
+    UnitResultCompleted::<_> {
+        value: PRegValue::zeroed(),
+        extra_out: (),
+    }
+}
+
 #[hdl]
 fn compare<SrcCount: KnownSize>(
     mop: Expr<CompareMOp<UnitOutRegNum<DynSize>, DynSize, SrcCount>>,
@@ -314,6 +328,21 @@ fn branch<SrcCount: KnownSize>(
     }
 }
 
+#[hdl]
+fn read_special(
+    mop: Expr<ReadSpecialMOp<UnitOutRegNum<DynSize>, DynSize>>,
+    pc: Expr<UInt<64>>,
+    flags_mode: Expr<FlagsMode>,
+    src_values: Expr<Array<PRegValue, { COMMON_MOP_SRC_LEN }>>,
+) -> Expr<UnitResultCompleted<()>> {
+    // TODO: finish
+    #[hdl]
+    UnitResultCompleted::<_> {
+        value: PRegValue::zeroed(),
+        extra_out: (),
+    }
+}
+
 #[hdl_module]
 pub fn alu_branch(config: &CpuConfig, unit_index: usize) {
     #[hdl]
@@ -440,6 +469,23 @@ pub fn alu_branch(config: &CpuConfig, unit_index: usize) {
                     },
                 ),
             ),
+            AluBranchMOp::<_, _>::ShiftRotate(mop) => connect(
+                unit_base.execute_end,
+                HdlSome(
+                    #[hdl]
+                    ExecuteEnd::<_, _> {
+                        unit_output: #[hdl]
+                        UnitOutput::<_, _> {
+                            which: MOpTrait::dest_reg(mop),
+                            result: UnitResult[()].Completed(shift_rotate(
+                                mop,
+                                global_state.flags_mode,
+                                src_values,
+                            )),
+                        },
+                    },
+                ),
+            ),
             AluBranchMOp::<_, _>::Compare(mop) => connect(
                 unit_base.execute_end,
                 HdlSome(
@@ -510,6 +556,24 @@ pub fn alu_branch(config: &CpuConfig, unit_index: usize) {
                     },
                 ),
             ),
+            AluBranchMOp::<_, _>::ReadSpecial(mop) => connect(
+                unit_base.execute_end,
+                HdlSome(
+                    #[hdl]
+                    ExecuteEnd::<_, _> {
+                        unit_output: #[hdl]
+                        UnitOutput::<_, _> {
+                            which: MOpTrait::dest_reg(mop),
+                            result: UnitResult[()].Completed(read_special(
+                                mop,
+                                pc,
+                                global_state.flags_mode,
+                                src_values,
+                            )),
+                        },
+                    },
+                ),
+            ),
         }
     }
 }
diff --git a/crates/cpu/src/util.rs b/crates/cpu/src/util.rs
index ec9e17f..4e8f946 100644
--- a/crates/cpu/src/util.rs
+++ b/crates/cpu/src/util.rs
@@ -38,6 +38,54 @@ pub trait Rotate<Amount> {
     fn rotate_right(&self, amount: Amount) -> Self::Output;
 }
 
+impl<VSz: Size> Rotate<usize> for Expr<UIntType<VSz>> {
+    type Output = Self;
+    /// like [`usize::rotate_left`]
+    fn rotate_left(&self, amount: usize) -> Self::Output {
+        if self.ty().width() == 0 {
+            return *self;
+        }
+        let amount = amount % self.ty().width();
+        let l = *self << amount;
+        let r = *self >> (self.ty().width() - amount);
+        (l | r).cast_to(self.ty())
+    }
+    /// like [`usize::rotate_right`]
+    fn rotate_right(&self, amount: usize) -> Self::Output {
+        if self.ty().width() == 0 {
+            return *self;
+        }
+        let amount = amount % self.ty().width();
+        let l = *self << (self.ty().width() - amount);
+        let r = *self >> amount;
+        (l | r).cast_to(self.ty())
+    }
+}
+
+impl<VSz: Size> Rotate<usize> for SimValue<UIntType<VSz>> {
+    type Output = Self;
+    /// like [`usize::rotate_left`]
+    fn rotate_left(&self, amount: usize) -> Self::Output {
+        if self.ty().width() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().width();
+        let l = self << amount;
+        let r = self >> (self.ty().width() - amount);
+        (l | r).cast_to(self.ty())
+    }
+    /// like [`usize::rotate_right`]
+    fn rotate_right(&self, amount: usize) -> Self::Output {
+        if self.ty().width() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().width();
+        let l = self << (self.ty().width() - amount);
+        let r = self >> amount;
+        (l | r).cast_to(self.ty())
+    }
+}
+
 impl<VSz: Size, ASz: Size> Rotate<Expr<UIntType<ASz>>> for Expr<UIntType<VSz>> {
     type Output = Self;
     /// like [`usize::rotate_left`]
@@ -176,3 +224,59 @@ impl<T: Type, N: Size, AmountSize: Size> Rotate<SimValue<UIntType<AmountSize>>>
         retval
     }
 }
+
+impl<T: Type, N: Size> Rotate<usize> for Expr<ArrayType<T, N>> {
+    type Output = Self;
+    /// like [`<[T]>::rotate_left`](slice::rotate_left)
+    fn rotate_left(&self, amount: usize) -> Self::Output {
+        if self.ty().len() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().len();
+        let mut retval = Vec::from_iter(*self);
+        retval.rotate_left(amount);
+        ArrayLiteral::new(
+            self.ty().element(),
+            retval.into_iter().map(Expr::canonical).collect(),
+        )
+        .to_expr()
+    }
+    /// like [`<[T]>::rotate_right`](slice::rotate_right)
+    fn rotate_right(&self, amount: usize) -> Self::Output {
+        if self.ty().len() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().len();
+        let mut retval = Vec::from_iter(*self);
+        retval.rotate_right(amount);
+        ArrayLiteral::new(
+            self.ty().element(),
+            retval.into_iter().map(Expr::canonical).collect(),
+        )
+        .to_expr()
+    }
+}
+
+impl<T: Type, N: Size> Rotate<usize> for SimValue<ArrayType<T, N>> {
+    type Output = Self;
+    /// like [`<[T]>::rotate_left`](slice::rotate_left)
+    fn rotate_left(&self, amount: usize) -> Self::Output {
+        if self.ty().len() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().len();
+        let mut retval = self.clone();
+        AsMut::<[SimValue<T>]>::as_mut(&mut SimValue::value_mut(&mut retval)).rotate_left(amount);
+        retval
+    }
+    /// like [`<[T]>::rotate_right`](slice::rotate_right)
+    fn rotate_right(&self, amount: usize) -> Self::Output {
+        if self.ty().len() == 0 {
+            return self.clone();
+        }
+        let amount = amount % self.ty().len();
+        let mut retval = self.clone();
+        AsMut::<[SimValue<T>]>::as_mut(&mut SimValue::value_mut(&mut retval)).rotate_right(amount);
+        retval
+    }
+}
diff --git a/crates/cpu/tests/expected/reg_alloc.vcd b/crates/cpu/tests/expected/reg_alloc.vcd
index 79bbcf7..20250f5 100644
--- a/crates/cpu/tests/expected/reg_alloc.vcd
+++ b/crates/cpu/tests/expected/reg_alloc.vcd
@@ -45,187 +45,189 @@ $var wire 8 + \[0] $end
 $var wire 8 , \[1] $end
 $var wire 8 - \[2] $end
 $upscope $end
-$var wire 25 . imm_low $end
-$var wire 1 / imm_sign $end
-$scope struct _phantom $end
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-$upscope $end
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-$var wire 1 2 src1_is_carry_in $end
-$var wire 1 3 invert_carry_in $end
-$var wire 1 4 add_pc $end
+$var wire 1 0 invert_src0 $end
+$var wire 1 1 src1_is_carry_in $end
+$var wire 1 2 invert_carry_in $end
+$var wire 1 3 add_pc $end
 $upscope $end
 $scope struct AddSubI $end
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 $scope struct common $end
-$var string 0 5 prefix_pad $end
+$var string 0 4 prefix_pad $end
 $scope struct dest $end
 $scope struct normal_regs $end
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-$var wire 8 6 value $end
+$var wire 8 5 value $end
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+$var wire 8 6 value $end
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-$var string 1 ? output_integer_mode $end
-$upscope $end
-$var wire 1 @ invert_src0 $end
-$var wire 1 A src1_is_carry_in $end
-$var wire 1 B invert_carry_in $end
-$var wire 1 C add_pc $end
+$var wire 1 = invert_src0 $end
+$var wire 1 > src1_is_carry_in $end
+$var wire 1 ? invert_carry_in $end
+$var wire 1 @ add_pc $end
 $upscope $end
 $scope struct LogicalFlags $end
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-$var string 0 D prefix_pad $end
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+$scope struct src0_start $end
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-$var wire 1 ] \[0] $end
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@@ -238,7 +240,7 @@ $var wire 1 o \[3] $end
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@@ -269,221 +271,241 @@ $var wire 8 u \[0] $end
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@@ -509,339 +531,344 @@ $upscope $end
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@@ -3700,101 +3764,77 @@ $scope struct unit_out_reg $end
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@@ -3805,76 +3845,100 @@ $scope struct unit_out_reg $end
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@@ -3895,7 +3959,7 @@ $var wire 1 b% value $end
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@@ -3916,7 +3980,7 @@ $var wire 1 i% value $end
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@@ -3928,76 +3992,76 @@ $scope struct unit_out_reg $end
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@@ -4124,57 +4230,57 @@ $upscope $end
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@@ -4182,15 +4288,15 @@ $upscope $end
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@@ -4200,31 +4306,31 @@ $upscope $end
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@@ -4232,37 +4338,37 @@ $upscope $end
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@@ -4270,57 +4376,57 @@ $upscope $end
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@@ -4328,15 +4434,15 @@ $upscope $end
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@@ -4349,76 +4455,6 @@ $scope struct renamed_insn $end
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@@ -4449,7 +4485,7 @@ $upscope $end
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@@ -4484,7 +4520,7 @@ $upscope $end
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@@ -4519,7 +4555,7 @@ $upscope $end
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@@ -4554,7 +4590,7 @@ $upscope $end
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@@ -4589,7 +4625,7 @@ $upscope $end
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@@ -4624,7 +4660,7 @@ $upscope $end
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@@ -4659,7 +4695,7 @@ $upscope $end
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@@ -4694,7 +4730,7 @@ $upscope $end
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@@ -4729,7 +4765,7 @@ $upscope $end
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 $upscope $end
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@@ -4764,7 +4800,7 @@ $upscope $end
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 $upscope $end
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@@ -4799,7 +4835,7 @@ $upscope $end
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@@ -4834,7 +4870,7 @@ $upscope $end
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@@ -4869,7 +4905,7 @@ $upscope $end
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@@ -4904,7 +4940,7 @@ $upscope $end
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@@ -4939,7 +4975,7 @@ $upscope $end
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@@ -4974,7 +5010,7 @@ $upscope $end
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@@ -5009,7 +5045,7 @@ $upscope $end
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@@ -5044,31 +5080,101 @@ $upscope $end
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@@ -5076,36 +5182,36 @@ $upscope $end
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@@ -5113,120 +5219,87 @@ $upscope $end
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@@ -6297,20 +6430,20 @@ $upscope $end
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@@ -6319,238 +6452,237 @@ $upscope $end
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@@ -7254,20 +7431,20 @@ $upscope $end
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@@ -7276,48 +7453,48 @@ $upscope $end
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@@ -7326,20 +7503,20 @@ $upscope $end
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@@ -7348,61 +7525,61 @@ $upscope $end
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@@ -7411,20 +7588,20 @@ $upscope $end
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@@ -7433,48 +7610,48 @@ $upscope $end
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@@ -7483,20 +7660,20 @@ $upscope $end
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@@ -7505,61 +7682,61 @@ $upscope $end
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@@ -7568,20 +7745,20 @@ $upscope $end
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@@ -7590,48 +7767,48 @@ $upscope $end
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@@ -7640,20 +7817,20 @@ $upscope $end
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@@ -7662,54 +7839,33 @@ $upscope $end
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@@ -7729,8 +7885,8 @@ $var wire 1 c3 value $end
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@@ -7750,8 +7906,8 @@ $var wire 1 j3 value $end
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@@ -7771,7 +7927,7 @@ $var wire 1 q3 value $end
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@@ -7792,7 +7948,7 @@ $var wire 1 x3 value $end
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@@ -7813,109 +7969,113 @@ $var wire 1 !4 value $end
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@@ -7926,7 +8086,7 @@ $var wire 1 V4 \[3] $end
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@@ -7936,224 +8096,228 @@ $upscope $end
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@@ -8173,7 +8337,7 @@ $upscope $end
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@@ -8195,182 +8359,197 @@ $upscope $end
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@@ -8379,21 +8558,30 @@ $upscope $end
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@@ -8404,293 +8592,305 @@ $var wire 6 `6 \[0] $end
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@@ -9120,15 +9350,15 @@ $upscope $end
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@@ -9137,50 +9367,50 @@ $upscope $end
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@@ -9188,15 +9418,15 @@ $upscope $end
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@@ -9205,261 +9435,290 @@ $upscope $end
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@@ -9473,7 +9732,7 @@ $upscope $end
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@@ -9483,50 +9742,50 @@ $upscope $end
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@@ -9534,15 +9793,15 @@ $upscope $end
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@@ -9551,261 +9810,290 @@ $upscope $end
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@@ -10467,50 +10813,50 @@ $upscope $end
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@@ -10518,15 +10864,15 @@ $upscope $end
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@@ -10535,261 +10881,290 @@ $upscope $end
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@@ -10803,60 +11178,13 @@ $upscope $end
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@@ -10866,21 +11194,16 @@ $var wire 6 e= \[0] $end
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@@ -10890,208 +11213,289 @@ $upscope $end
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 $scope struct common $end
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 $scope struct src_values $end
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 $scope struct \[1] $end
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+$var wire 1 )? pwr_cr_lt_x86_sf $end
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 $upscope $end
 $scope struct \[2] $end
-$var wire 64 g> int_fp $end
+$var wire 64 *? int_fp $end
 $scope struct flags $end
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+$var wire 1 ,? pwr_ca_x86_cf $end
+$var wire 1 -? pwr_ov32_x86_df $end
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+$var wire 1 0? pwr_cr_eq_x86_zf $end
+$var wire 1 1? pwr_cr_gt_x86_pf $end
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-$var wire 1 p> ready $end
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-$var string 1 q> \$tag $end
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 $scope struct unit_output $end
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-$var wire 4 r> value $end
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 $scope struct result $end
-$var string 1 s> \$tag $end
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 $scope struct Completed $end
 $scope struct value $end
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 $scope struct flags $end
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+$var wire 1 ?? pwr_cr_lt_x86_sf $end
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 $upscope $end
 $scope struct extra_out $end
@@ -11106,487 +11510,438 @@ $upscope $end
 $scope struct unit_0_output_regs_valid $end
 $scope struct contents $end
 $scope struct \[0] $end
-$var reg 1 P>" unit_0_output_regs_valid $end
+$var reg 1 PD" unit_0_output_regs_valid $end
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+$var reg 1 QD" unit_0_output_regs_valid $end
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+$var reg 1 UD" unit_0_output_regs_valid $end
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+$var reg 1 WD" unit_0_output_regs_valid $end
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+$var reg 1 YD" unit_0_output_regs_valid $end
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+$var reg 1 ZD" unit_0_output_regs_valid $end
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 $scope struct r1 $end
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-$var wire 4 +? addr $end
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 $upscope $end
 $scope struct r1 $end
-$var wire 4 9? addr $end
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 $upscope $end
 $scope struct r2 $end
-$var wire 4 =? addr $end
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 $upscope $end
 $scope struct w3 $end
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 $scope struct w4 $end
-$var wire 4 F? addr $end
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 $upscope $end
 $upscope $end
 $scope struct unit_0_output_regs $end
 $scope struct contents $end
 $scope struct \[0] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 p>" int_fp $end
+$var reg 64 pD" int_fp $end
 $scope struct flags $end
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-$var reg 1 $@" pwr_cr_gt_x86_pf $end
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+$var reg 1 "E" pwr_ca32_x86_af $end
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 $scope struct \[1] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 q>" int_fp $end
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 $scope struct flags $end
-$var reg 1 #?" pwr_ca32_x86_af $end
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-$var reg 1 S?" pwr_ov_x86_of $end
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+$var reg 1 #E" pwr_ca32_x86_af $end
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+$var reg 1 %F" pwr_cr_gt_x86_pf $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[2] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 r>" int_fp $end
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 $scope struct flags $end
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+$var reg 1 $E" pwr_ca32_x86_af $end
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+$var reg 1 6F" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[3] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 s>" int_fp $end
+$var reg 64 sD" int_fp $end
 $scope struct flags $end
-$var reg 1 %?" pwr_ca32_x86_af $end
-$var reg 1 5?" pwr_ca_x86_cf $end
-$var reg 1 E?" pwr_ov32_x86_df $end
-$var reg 1 U?" pwr_ov_x86_of $end
-$var reg 1 e?" pwr_so $end
-$var reg 1 u?" pwr_cr_eq_x86_zf $end
-$var reg 1 '@" pwr_cr_gt_x86_pf $end
-$var reg 1 7@" pwr_cr_lt_x86_sf $end
+$var reg 1 %E" pwr_ca32_x86_af $end
+$var reg 1 5E" pwr_ca_x86_cf $end
+$var reg 1 EE" pwr_ov32_x86_df $end
+$var reg 1 UE" pwr_ov_x86_of $end
+$var reg 1 eE" pwr_so $end
+$var reg 1 uE" pwr_cr_eq_x86_zf $end
+$var reg 1 'F" pwr_cr_gt_x86_pf $end
+$var reg 1 7F" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[4] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 t>" int_fp $end
+$var reg 64 tD" int_fp $end
 $scope struct flags $end
-$var reg 1 &?" pwr_ca32_x86_af $end
-$var reg 1 6?" pwr_ca_x86_cf $end
-$var reg 1 F?" pwr_ov32_x86_df $end
-$var reg 1 V?" pwr_ov_x86_of $end
-$var reg 1 f?" pwr_so $end
-$var reg 1 v?" pwr_cr_eq_x86_zf $end
-$var reg 1 (@" pwr_cr_gt_x86_pf $end
-$var reg 1 8@" pwr_cr_lt_x86_sf $end
+$var reg 1 &E" pwr_ca32_x86_af $end
+$var reg 1 6E" pwr_ca_x86_cf $end
+$var reg 1 FE" pwr_ov32_x86_df $end
+$var reg 1 VE" pwr_ov_x86_of $end
+$var reg 1 fE" pwr_so $end
+$var reg 1 vE" pwr_cr_eq_x86_zf $end
+$var reg 1 (F" pwr_cr_gt_x86_pf $end
+$var reg 1 8F" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[5] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 u>" int_fp $end
+$var reg 64 uD" int_fp $end
 $scope struct flags $end
-$var reg 1 '?" pwr_ca32_x86_af $end
-$var reg 1 7?" pwr_ca_x86_cf $end
-$var reg 1 G?" pwr_ov32_x86_df $end
-$var reg 1 W?" pwr_ov_x86_of $end
-$var reg 1 g?" pwr_so $end
-$var reg 1 w?" pwr_cr_eq_x86_zf $end
-$var reg 1 )@" pwr_cr_gt_x86_pf $end
-$var reg 1 9@" pwr_cr_lt_x86_sf $end
+$var reg 1 'E" pwr_ca32_x86_af $end
+$var reg 1 7E" pwr_ca_x86_cf $end
+$var reg 1 GE" pwr_ov32_x86_df $end
+$var reg 1 WE" pwr_ov_x86_of $end
+$var reg 1 gE" pwr_so $end
+$var reg 1 wE" pwr_cr_eq_x86_zf $end
+$var reg 1 )F" pwr_cr_gt_x86_pf $end
+$var reg 1 9F" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[6] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 v>" int_fp $end
+$var reg 64 vD" int_fp $end
 $scope struct flags $end
-$var reg 1 (?" pwr_ca32_x86_af $end
-$var reg 1 8?" pwr_ca_x86_cf $end
-$var reg 1 H?" pwr_ov32_x86_df $end
-$var reg 1 X?" pwr_ov_x86_of $end
-$var reg 1 h?" pwr_so $end
-$var reg 1 x?" pwr_cr_eq_x86_zf $end
-$var reg 1 *@" pwr_cr_gt_x86_pf $end
-$var reg 1 :@" pwr_cr_lt_x86_sf $end
+$var reg 1 (E" pwr_ca32_x86_af $end
+$var reg 1 8E" pwr_ca_x86_cf $end
+$var reg 1 HE" pwr_ov32_x86_df $end
+$var reg 1 XE" pwr_ov_x86_of $end
+$var reg 1 hE" pwr_so $end
+$var reg 1 xE" pwr_cr_eq_x86_zf $end
+$var reg 1 *F" pwr_cr_gt_x86_pf $end
+$var reg 1 :F" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[7] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 w>" int_fp $end
+$var reg 64 wD" int_fp $end
 $scope struct flags $end
-$var reg 1 )?" pwr_ca32_x86_af $end
-$var reg 1 9?" pwr_ca_x86_cf $end
-$var reg 1 I?" pwr_ov32_x86_df $end
-$var reg 1 Y?" pwr_ov_x86_of $end
-$var reg 1 i?" pwr_so $end
-$var reg 1 y?" pwr_cr_eq_x86_zf $end
-$var reg 1 +@" pwr_cr_gt_x86_pf $end
-$var reg 1 ;@" pwr_cr_lt_x86_sf $end
+$var reg 1 )E" pwr_ca32_x86_af $end
+$var reg 1 9E" pwr_ca_x86_cf $end
+$var reg 1 IE" pwr_ov32_x86_df $end
+$var reg 1 YE" pwr_ov_x86_of $end
+$var reg 1 iE" pwr_so $end
+$var reg 1 yE" pwr_cr_eq_x86_zf $end
+$var reg 1 +F" pwr_cr_gt_x86_pf $end
+$var reg 1 ;F" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[8] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 x>" int_fp $end
+$var reg 64 xD" int_fp $end
 $scope struct flags $end
-$var reg 1 *?" pwr_ca32_x86_af $end
-$var reg 1 :?" pwr_ca_x86_cf $end
-$var reg 1 J?" pwr_ov32_x86_df $end
-$var reg 1 Z?" pwr_ov_x86_of $end
-$var reg 1 j?" pwr_so $end
-$var reg 1 z?" pwr_cr_eq_x86_zf $end
-$var reg 1 ,@" pwr_cr_gt_x86_pf $end
-$var reg 1 <@" pwr_cr_lt_x86_sf $end
+$var reg 1 *E" pwr_ca32_x86_af $end
+$var reg 1 :E" pwr_ca_x86_cf $end
+$var reg 1 JE" pwr_ov32_x86_df $end
+$var reg 1 ZE" pwr_ov_x86_of $end
+$var reg 1 jE" pwr_so $end
+$var reg 1 zE" pwr_cr_eq_x86_zf $end
+$var reg 1 ,F" pwr_cr_gt_x86_pf $end
+$var reg 1 <F" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[9] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 y>" int_fp $end
+$var reg 64 yD" int_fp $end
 $scope struct flags $end
-$var reg 1 +?" pwr_ca32_x86_af $end
-$var reg 1 ;?" pwr_ca_x86_cf $end
-$var reg 1 K?" pwr_ov32_x86_df $end
-$var reg 1 [?" pwr_ov_x86_of $end
-$var reg 1 k?" pwr_so $end
-$var reg 1 {?" pwr_cr_eq_x86_zf $end
-$var reg 1 -@" pwr_cr_gt_x86_pf $end
-$var reg 1 =@" pwr_cr_lt_x86_sf $end
+$var reg 1 +E" pwr_ca32_x86_af $end
+$var reg 1 ;E" pwr_ca_x86_cf $end
+$var reg 1 KE" pwr_ov32_x86_df $end
+$var reg 1 [E" pwr_ov_x86_of $end
+$var reg 1 kE" pwr_so $end
+$var reg 1 {E" pwr_cr_eq_x86_zf $end
+$var reg 1 -F" pwr_cr_gt_x86_pf $end
+$var reg 1 =F" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[10] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 z>" int_fp $end
+$var reg 64 zD" int_fp $end
 $scope struct flags $end
-$var reg 1 ,?" pwr_ca32_x86_af $end
-$var reg 1 <?" pwr_ca_x86_cf $end
-$var reg 1 L?" pwr_ov32_x86_df $end
-$var reg 1 \?" pwr_ov_x86_of $end
-$var reg 1 l?" pwr_so $end
-$var reg 1 |?" pwr_cr_eq_x86_zf $end
-$var reg 1 .@" pwr_cr_gt_x86_pf $end
-$var reg 1 >@" pwr_cr_lt_x86_sf $end
+$var reg 1 ,E" pwr_ca32_x86_af $end
+$var reg 1 <E" pwr_ca_x86_cf $end
+$var reg 1 LE" pwr_ov32_x86_df $end
+$var reg 1 \E" pwr_ov_x86_of $end
+$var reg 1 lE" pwr_so $end
+$var reg 1 |E" pwr_cr_eq_x86_zf $end
+$var reg 1 .F" pwr_cr_gt_x86_pf $end
+$var reg 1 >F" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[11] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 {>" int_fp $end
+$var reg 64 {D" int_fp $end
 $scope struct flags $end
-$var reg 1 -?" pwr_ca32_x86_af $end
-$var reg 1 =?" pwr_ca_x86_cf $end
-$var reg 1 M?" pwr_ov32_x86_df $end
-$var reg 1 ]?" pwr_ov_x86_of $end
-$var reg 1 m?" pwr_so $end
-$var reg 1 }?" pwr_cr_eq_x86_zf $end
-$var reg 1 /@" pwr_cr_gt_x86_pf $end
-$var reg 1 ?@" pwr_cr_lt_x86_sf $end
+$var reg 1 -E" pwr_ca32_x86_af $end
+$var reg 1 =E" pwr_ca_x86_cf $end
+$var reg 1 ME" pwr_ov32_x86_df $end
+$var reg 1 ]E" pwr_ov_x86_of $end
+$var reg 1 mE" pwr_so $end
+$var reg 1 }E" pwr_cr_eq_x86_zf $end
+$var reg 1 /F" pwr_cr_gt_x86_pf $end
+$var reg 1 ?F" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[12] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 |>" int_fp $end
+$var reg 64 |D" int_fp $end
 $scope struct flags $end
-$var reg 1 .?" pwr_ca32_x86_af $end
-$var reg 1 >?" pwr_ca_x86_cf $end
-$var reg 1 N?" pwr_ov32_x86_df $end
-$var reg 1 ^?" pwr_ov_x86_of $end
-$var reg 1 n?" pwr_so $end
-$var reg 1 ~?" pwr_cr_eq_x86_zf $end
-$var reg 1 0@" pwr_cr_gt_x86_pf $end
-$var reg 1 @@" pwr_cr_lt_x86_sf $end
+$var reg 1 .E" pwr_ca32_x86_af $end
+$var reg 1 >E" pwr_ca_x86_cf $end
+$var reg 1 NE" pwr_ov32_x86_df $end
+$var reg 1 ^E" pwr_ov_x86_of $end
+$var reg 1 nE" pwr_so $end
+$var reg 1 ~E" pwr_cr_eq_x86_zf $end
+$var reg 1 0F" pwr_cr_gt_x86_pf $end
+$var reg 1 @F" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[13] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 }>" int_fp $end
+$var reg 64 }D" int_fp $end
 $scope struct flags $end
-$var reg 1 /?" pwr_ca32_x86_af $end
-$var reg 1 ??" pwr_ca_x86_cf $end
-$var reg 1 O?" pwr_ov32_x86_df $end
-$var reg 1 _?" pwr_ov_x86_of $end
-$var reg 1 o?" pwr_so $end
-$var reg 1 !@" pwr_cr_eq_x86_zf $end
-$var reg 1 1@" pwr_cr_gt_x86_pf $end
-$var reg 1 A@" pwr_cr_lt_x86_sf $end
+$var reg 1 /E" pwr_ca32_x86_af $end
+$var reg 1 ?E" pwr_ca_x86_cf $end
+$var reg 1 OE" pwr_ov32_x86_df $end
+$var reg 1 _E" pwr_ov_x86_of $end
+$var reg 1 oE" pwr_so $end
+$var reg 1 !F" pwr_cr_eq_x86_zf $end
+$var reg 1 1F" pwr_cr_gt_x86_pf $end
+$var reg 1 AF" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[14] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 ~>" int_fp $end
+$var reg 64 ~D" int_fp $end
 $scope struct flags $end
-$var reg 1 0?" pwr_ca32_x86_af $end
-$var reg 1 @?" pwr_ca_x86_cf $end
-$var reg 1 P?" pwr_ov32_x86_df $end
-$var reg 1 `?" pwr_ov_x86_of $end
-$var reg 1 p?" pwr_so $end
-$var reg 1 "@" pwr_cr_eq_x86_zf $end
-$var reg 1 2@" pwr_cr_gt_x86_pf $end
-$var reg 1 B@" pwr_cr_lt_x86_sf $end
+$var reg 1 0E" pwr_ca32_x86_af $end
+$var reg 1 @E" pwr_ca_x86_cf $end
+$var reg 1 PE" pwr_ov32_x86_df $end
+$var reg 1 `E" pwr_ov_x86_of $end
+$var reg 1 pE" pwr_so $end
+$var reg 1 "F" pwr_cr_eq_x86_zf $end
+$var reg 1 2F" pwr_cr_gt_x86_pf $end
+$var reg 1 BF" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[15] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 !?" int_fp $end
+$var reg 64 !E" int_fp $end
 $scope struct flags $end
-$var reg 1 1?" pwr_ca32_x86_af $end
-$var reg 1 A?" pwr_ca_x86_cf $end
-$var reg 1 Q?" pwr_ov32_x86_df $end
-$var reg 1 a?" pwr_ov_x86_of $end
-$var reg 1 q?" pwr_so $end
-$var reg 1 #@" pwr_cr_eq_x86_zf $end
-$var reg 1 3@" pwr_cr_gt_x86_pf $end
-$var reg 1 C@" pwr_cr_lt_x86_sf $end
+$var reg 1 1E" pwr_ca32_x86_af $end
+$var reg 1 AE" pwr_ca_x86_cf $end
+$var reg 1 QE" pwr_ov32_x86_df $end
+$var reg 1 aE" pwr_ov_x86_of $end
+$var reg 1 qE" pwr_so $end
+$var reg 1 #F" pwr_cr_eq_x86_zf $end
+$var reg 1 3F" pwr_cr_gt_x86_pf $end
+$var reg 1 CF" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r0 $end
-$var wire 4 K? addr $end
-$var wire 1 L? en $end
-$var wire 1 M? clk $end
+$var wire 4 l? addr $end
+$var wire 1 m? en $end
+$var wire 1 n? clk $end
 $scope struct data $end
-$var wire 64 N? int_fp $end
+$var wire 64 o? int_fp $end
 $scope struct flags $end
-$var wire 1 O? pwr_ca32_x86_af $end
-$var wire 1 P? pwr_ca_x86_cf $end
-$var wire 1 Q? pwr_ov32_x86_df $end
-$var wire 1 R? pwr_ov_x86_of $end
-$var wire 1 S? pwr_so $end
-$var wire 1 T? pwr_cr_eq_x86_zf $end
-$var wire 1 U? pwr_cr_gt_x86_pf $end
-$var wire 1 V? pwr_cr_lt_x86_sf $end
+$var wire 1 p? pwr_ca32_x86_af $end
+$var wire 1 q? pwr_ca_x86_cf $end
+$var wire 1 r? pwr_ov32_x86_df $end
+$var wire 1 s? pwr_ov_x86_of $end
+$var wire 1 t? pwr_so $end
+$var wire 1 u? pwr_cr_eq_x86_zf $end
+$var wire 1 v? pwr_cr_gt_x86_pf $end
+$var wire 1 w? pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r1 $end
-$var wire 4 W? addr $end
-$var wire 1 X? en $end
-$var wire 1 Y? clk $end
+$var wire 4 x? addr $end
+$var wire 1 y? en $end
+$var wire 1 z? clk $end
 $scope struct data $end
-$var wire 64 Z? int_fp $end
-$scope struct flags $end
-$var wire 1 [? pwr_ca32_x86_af $end
-$var wire 1 \? pwr_ca_x86_cf $end
-$var wire 1 ]? pwr_ov32_x86_df $end
-$var wire 1 ^? pwr_ov_x86_of $end
-$var wire 1 _? pwr_so $end
-$var wire 1 `? pwr_cr_eq_x86_zf $end
-$var wire 1 a? pwr_cr_gt_x86_pf $end
-$var wire 1 b? pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct r2 $end
-$var wire 4 c? addr $end
-$var wire 1 d? en $end
-$var wire 1 e? clk $end
-$scope struct data $end
-$var wire 64 f? int_fp $end
-$scope struct flags $end
-$var wire 1 g? pwr_ca32_x86_af $end
-$var wire 1 h? pwr_ca_x86_cf $end
-$var wire 1 i? pwr_ov32_x86_df $end
-$var wire 1 j? pwr_ov_x86_of $end
-$var wire 1 k? pwr_so $end
-$var wire 1 l? pwr_cr_eq_x86_zf $end
-$var wire 1 m? pwr_cr_gt_x86_pf $end
-$var wire 1 n? pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct w3 $end
-$var wire 4 o? addr $end
-$var wire 1 p? en $end
-$var wire 1 q? clk $end
-$scope struct data $end
-$var wire 64 r? int_fp $end
-$scope struct flags $end
-$var wire 1 s? pwr_ca32_x86_af $end
-$var wire 1 t? pwr_ca_x86_cf $end
-$var wire 1 u? pwr_ov32_x86_df $end
-$var wire 1 v? pwr_ov_x86_of $end
-$var wire 1 w? pwr_so $end
-$var wire 1 x? pwr_cr_eq_x86_zf $end
-$var wire 1 y? pwr_cr_gt_x86_pf $end
-$var wire 1 z? pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$scope struct mask $end
-$var wire 1 {? int_fp $end
+$var wire 64 {? int_fp $end
 $scope struct flags $end
 $var wire 1 |? pwr_ca32_x86_af $end
 $var wire 1 }? pwr_ca_x86_cf $end
@@ -11599,251 +11954,7 @@ $var wire 1 %@ pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
-$upscope $end
-$scope struct unit_1_output_regs $end
-$scope struct contents $end
-$scope struct \[0] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 D@" int_fp $end
-$scope struct flags $end
-$var reg 1 T@" pwr_ca32_x86_af $end
-$var reg 1 d@" pwr_ca_x86_cf $end
-$var reg 1 t@" pwr_ov32_x86_df $end
-$var reg 1 &A" pwr_ov_x86_of $end
-$var reg 1 6A" pwr_so $end
-$var reg 1 FA" pwr_cr_eq_x86_zf $end
-$var reg 1 VA" pwr_cr_gt_x86_pf $end
-$var reg 1 fA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[1] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 E@" int_fp $end
-$scope struct flags $end
-$var reg 1 U@" pwr_ca32_x86_af $end
-$var reg 1 e@" pwr_ca_x86_cf $end
-$var reg 1 u@" pwr_ov32_x86_df $end
-$var reg 1 'A" pwr_ov_x86_of $end
-$var reg 1 7A" pwr_so $end
-$var reg 1 GA" pwr_cr_eq_x86_zf $end
-$var reg 1 WA" pwr_cr_gt_x86_pf $end
-$var reg 1 gA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[2] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 F@" int_fp $end
-$scope struct flags $end
-$var reg 1 V@" pwr_ca32_x86_af $end
-$var reg 1 f@" pwr_ca_x86_cf $end
-$var reg 1 v@" pwr_ov32_x86_df $end
-$var reg 1 (A" pwr_ov_x86_of $end
-$var reg 1 8A" pwr_so $end
-$var reg 1 HA" pwr_cr_eq_x86_zf $end
-$var reg 1 XA" pwr_cr_gt_x86_pf $end
-$var reg 1 hA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[3] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 G@" int_fp $end
-$scope struct flags $end
-$var reg 1 W@" pwr_ca32_x86_af $end
-$var reg 1 g@" pwr_ca_x86_cf $end
-$var reg 1 w@" pwr_ov32_x86_df $end
-$var reg 1 )A" pwr_ov_x86_of $end
-$var reg 1 9A" pwr_so $end
-$var reg 1 IA" pwr_cr_eq_x86_zf $end
-$var reg 1 YA" pwr_cr_gt_x86_pf $end
-$var reg 1 iA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[4] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 H@" int_fp $end
-$scope struct flags $end
-$var reg 1 X@" pwr_ca32_x86_af $end
-$var reg 1 h@" pwr_ca_x86_cf $end
-$var reg 1 x@" pwr_ov32_x86_df $end
-$var reg 1 *A" pwr_ov_x86_of $end
-$var reg 1 :A" pwr_so $end
-$var reg 1 JA" pwr_cr_eq_x86_zf $end
-$var reg 1 ZA" pwr_cr_gt_x86_pf $end
-$var reg 1 jA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[5] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 I@" int_fp $end
-$scope struct flags $end
-$var reg 1 Y@" pwr_ca32_x86_af $end
-$var reg 1 i@" pwr_ca_x86_cf $end
-$var reg 1 y@" pwr_ov32_x86_df $end
-$var reg 1 +A" pwr_ov_x86_of $end
-$var reg 1 ;A" pwr_so $end
-$var reg 1 KA" pwr_cr_eq_x86_zf $end
-$var reg 1 [A" pwr_cr_gt_x86_pf $end
-$var reg 1 kA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[6] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 J@" int_fp $end
-$scope struct flags $end
-$var reg 1 Z@" pwr_ca32_x86_af $end
-$var reg 1 j@" pwr_ca_x86_cf $end
-$var reg 1 z@" pwr_ov32_x86_df $end
-$var reg 1 ,A" pwr_ov_x86_of $end
-$var reg 1 <A" pwr_so $end
-$var reg 1 LA" pwr_cr_eq_x86_zf $end
-$var reg 1 \A" pwr_cr_gt_x86_pf $end
-$var reg 1 lA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[7] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 K@" int_fp $end
-$scope struct flags $end
-$var reg 1 [@" pwr_ca32_x86_af $end
-$var reg 1 k@" pwr_ca_x86_cf $end
-$var reg 1 {@" pwr_ov32_x86_df $end
-$var reg 1 -A" pwr_ov_x86_of $end
-$var reg 1 =A" pwr_so $end
-$var reg 1 MA" pwr_cr_eq_x86_zf $end
-$var reg 1 ]A" pwr_cr_gt_x86_pf $end
-$var reg 1 mA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[8] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 L@" int_fp $end
-$scope struct flags $end
-$var reg 1 \@" pwr_ca32_x86_af $end
-$var reg 1 l@" pwr_ca_x86_cf $end
-$var reg 1 |@" pwr_ov32_x86_df $end
-$var reg 1 .A" pwr_ov_x86_of $end
-$var reg 1 >A" pwr_so $end
-$var reg 1 NA" pwr_cr_eq_x86_zf $end
-$var reg 1 ^A" pwr_cr_gt_x86_pf $end
-$var reg 1 nA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[9] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 M@" int_fp $end
-$scope struct flags $end
-$var reg 1 ]@" pwr_ca32_x86_af $end
-$var reg 1 m@" pwr_ca_x86_cf $end
-$var reg 1 }@" pwr_ov32_x86_df $end
-$var reg 1 /A" pwr_ov_x86_of $end
-$var reg 1 ?A" pwr_so $end
-$var reg 1 OA" pwr_cr_eq_x86_zf $end
-$var reg 1 _A" pwr_cr_gt_x86_pf $end
-$var reg 1 oA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[10] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 N@" int_fp $end
-$scope struct flags $end
-$var reg 1 ^@" pwr_ca32_x86_af $end
-$var reg 1 n@" pwr_ca_x86_cf $end
-$var reg 1 ~@" pwr_ov32_x86_df $end
-$var reg 1 0A" pwr_ov_x86_of $end
-$var reg 1 @A" pwr_so $end
-$var reg 1 PA" pwr_cr_eq_x86_zf $end
-$var reg 1 `A" pwr_cr_gt_x86_pf $end
-$var reg 1 pA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
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-$scope struct unit_1_output_regs $end
-$var reg 64 O@" int_fp $end
-$scope struct flags $end
-$var reg 1 _@" pwr_ca32_x86_af $end
-$var reg 1 o@" pwr_ca_x86_cf $end
-$var reg 1 !A" pwr_ov32_x86_df $end
-$var reg 1 1A" pwr_ov_x86_of $end
-$var reg 1 AA" pwr_so $end
-$var reg 1 QA" pwr_cr_eq_x86_zf $end
-$var reg 1 aA" pwr_cr_gt_x86_pf $end
-$var reg 1 qA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[12] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 P@" int_fp $end
-$scope struct flags $end
-$var reg 1 `@" pwr_ca32_x86_af $end
-$var reg 1 p@" pwr_ca_x86_cf $end
-$var reg 1 "A" pwr_ov32_x86_df $end
-$var reg 1 2A" pwr_ov_x86_of $end
-$var reg 1 BA" pwr_so $end
-$var reg 1 RA" pwr_cr_eq_x86_zf $end
-$var reg 1 bA" pwr_cr_gt_x86_pf $end
-$var reg 1 rA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[13] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 Q@" int_fp $end
-$scope struct flags $end
-$var reg 1 a@" pwr_ca32_x86_af $end
-$var reg 1 q@" pwr_ca_x86_cf $end
-$var reg 1 #A" pwr_ov32_x86_df $end
-$var reg 1 3A" pwr_ov_x86_of $end
-$var reg 1 CA" pwr_so $end
-$var reg 1 SA" pwr_cr_eq_x86_zf $end
-$var reg 1 cA" pwr_cr_gt_x86_pf $end
-$var reg 1 sA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[14] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 R@" int_fp $end
-$scope struct flags $end
-$var reg 1 b@" pwr_ca32_x86_af $end
-$var reg 1 r@" pwr_ca_x86_cf $end
-$var reg 1 $A" pwr_ov32_x86_df $end
-$var reg 1 4A" pwr_ov_x86_of $end
-$var reg 1 DA" pwr_so $end
-$var reg 1 TA" pwr_cr_eq_x86_zf $end
-$var reg 1 dA" pwr_cr_gt_x86_pf $end
-$var reg 1 tA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct \[15] $end
-$scope struct unit_1_output_regs $end
-$var reg 64 S@" int_fp $end
-$scope struct flags $end
-$var reg 1 c@" pwr_ca32_x86_af $end
-$var reg 1 s@" pwr_ca_x86_cf $end
-$var reg 1 %A" pwr_ov32_x86_df $end
-$var reg 1 5A" pwr_ov_x86_of $end
-$var reg 1 EA" pwr_so $end
-$var reg 1 UA" pwr_cr_eq_x86_zf $end
-$var reg 1 eA" pwr_cr_gt_x86_pf $end
-$var reg 1 uA" pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct r0 $end
+$scope struct r2 $end
 $var wire 4 &@ addr $end
 $var wire 1 '@ en $end
 $var wire 1 (@ clk $end
@@ -11861,7 +11972,7 @@ $var wire 1 1@ pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
-$scope struct r1 $end
+$scope struct w3 $end
 $var wire 4 2@ addr $end
 $var wire 1 3@ en $end
 $var wire 1 4@ clk $end
@@ -11878,44 +11989,288 @@ $var wire 1 <@ pwr_cr_gt_x86_pf $end
 $var wire 1 =@ pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
-$upscope $end
-$scope struct r2 $end
-$var wire 4 >@ addr $end
-$var wire 1 ?@ en $end
-$var wire 1 @@ clk $end
-$scope struct data $end
-$var wire 64 A@ int_fp $end
-$scope struct flags $end
-$var wire 1 B@ pwr_ca32_x86_af $end
-$var wire 1 C@ pwr_ca_x86_cf $end
-$var wire 1 D@ pwr_ov32_x86_df $end
-$var wire 1 E@ pwr_ov_x86_of $end
-$var wire 1 F@ pwr_so $end
-$var wire 1 G@ pwr_cr_eq_x86_zf $end
-$var wire 1 H@ pwr_cr_gt_x86_pf $end
-$var wire 1 I@ pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
-$upscope $end
-$scope struct w3 $end
-$var wire 4 J@ addr $end
-$var wire 1 K@ en $end
-$var wire 1 L@ clk $end
-$scope struct data $end
-$var wire 64 M@ int_fp $end
-$scope struct flags $end
-$var wire 1 N@ pwr_ca32_x86_af $end
-$var wire 1 O@ pwr_ca_x86_cf $end
-$var wire 1 P@ pwr_ov32_x86_df $end
-$var wire 1 Q@ pwr_ov_x86_of $end
-$var wire 1 R@ pwr_so $end
-$var wire 1 S@ pwr_cr_eq_x86_zf $end
-$var wire 1 T@ pwr_cr_gt_x86_pf $end
-$var wire 1 U@ pwr_cr_lt_x86_sf $end
-$upscope $end
-$upscope $end
 $scope struct mask $end
-$var wire 1 V@ int_fp $end
+$var wire 1 >@ int_fp $end
+$scope struct flags $end
+$var wire 1 ?@ pwr_ca32_x86_af $end
+$var wire 1 @@ pwr_ca_x86_cf $end
+$var wire 1 A@ pwr_ov32_x86_df $end
+$var wire 1 B@ pwr_ov_x86_of $end
+$var wire 1 C@ pwr_so $end
+$var wire 1 D@ pwr_cr_eq_x86_zf $end
+$var wire 1 E@ pwr_cr_gt_x86_pf $end
+$var wire 1 F@ pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct unit_1_output_regs $end
+$scope struct contents $end
+$scope struct \[0] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 DF" int_fp $end
+$scope struct flags $end
+$var reg 1 TF" pwr_ca32_x86_af $end
+$var reg 1 dF" pwr_ca_x86_cf $end
+$var reg 1 tF" pwr_ov32_x86_df $end
+$var reg 1 &G" pwr_ov_x86_of $end
+$var reg 1 6G" pwr_so $end
+$var reg 1 FG" pwr_cr_eq_x86_zf $end
+$var reg 1 VG" pwr_cr_gt_x86_pf $end
+$var reg 1 fG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[1] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 EF" int_fp $end
+$scope struct flags $end
+$var reg 1 UF" pwr_ca32_x86_af $end
+$var reg 1 eF" pwr_ca_x86_cf $end
+$var reg 1 uF" pwr_ov32_x86_df $end
+$var reg 1 'G" pwr_ov_x86_of $end
+$var reg 1 7G" pwr_so $end
+$var reg 1 GG" pwr_cr_eq_x86_zf $end
+$var reg 1 WG" pwr_cr_gt_x86_pf $end
+$var reg 1 gG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[2] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 FF" int_fp $end
+$scope struct flags $end
+$var reg 1 VF" pwr_ca32_x86_af $end
+$var reg 1 fF" pwr_ca_x86_cf $end
+$var reg 1 vF" pwr_ov32_x86_df $end
+$var reg 1 (G" pwr_ov_x86_of $end
+$var reg 1 8G" pwr_so $end
+$var reg 1 HG" pwr_cr_eq_x86_zf $end
+$var reg 1 XG" pwr_cr_gt_x86_pf $end
+$var reg 1 hG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[3] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 GF" int_fp $end
+$scope struct flags $end
+$var reg 1 WF" pwr_ca32_x86_af $end
+$var reg 1 gF" pwr_ca_x86_cf $end
+$var reg 1 wF" pwr_ov32_x86_df $end
+$var reg 1 )G" pwr_ov_x86_of $end
+$var reg 1 9G" pwr_so $end
+$var reg 1 IG" pwr_cr_eq_x86_zf $end
+$var reg 1 YG" pwr_cr_gt_x86_pf $end
+$var reg 1 iG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[4] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 HF" int_fp $end
+$scope struct flags $end
+$var reg 1 XF" pwr_ca32_x86_af $end
+$var reg 1 hF" pwr_ca_x86_cf $end
+$var reg 1 xF" pwr_ov32_x86_df $end
+$var reg 1 *G" pwr_ov_x86_of $end
+$var reg 1 :G" pwr_so $end
+$var reg 1 JG" pwr_cr_eq_x86_zf $end
+$var reg 1 ZG" pwr_cr_gt_x86_pf $end
+$var reg 1 jG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[5] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 IF" int_fp $end
+$scope struct flags $end
+$var reg 1 YF" pwr_ca32_x86_af $end
+$var reg 1 iF" pwr_ca_x86_cf $end
+$var reg 1 yF" pwr_ov32_x86_df $end
+$var reg 1 +G" pwr_ov_x86_of $end
+$var reg 1 ;G" pwr_so $end
+$var reg 1 KG" pwr_cr_eq_x86_zf $end
+$var reg 1 [G" pwr_cr_gt_x86_pf $end
+$var reg 1 kG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[6] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 JF" int_fp $end
+$scope struct flags $end
+$var reg 1 ZF" pwr_ca32_x86_af $end
+$var reg 1 jF" pwr_ca_x86_cf $end
+$var reg 1 zF" pwr_ov32_x86_df $end
+$var reg 1 ,G" pwr_ov_x86_of $end
+$var reg 1 <G" pwr_so $end
+$var reg 1 LG" pwr_cr_eq_x86_zf $end
+$var reg 1 \G" pwr_cr_gt_x86_pf $end
+$var reg 1 lG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[7] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 KF" int_fp $end
+$scope struct flags $end
+$var reg 1 [F" pwr_ca32_x86_af $end
+$var reg 1 kF" pwr_ca_x86_cf $end
+$var reg 1 {F" pwr_ov32_x86_df $end
+$var reg 1 -G" pwr_ov_x86_of $end
+$var reg 1 =G" pwr_so $end
+$var reg 1 MG" pwr_cr_eq_x86_zf $end
+$var reg 1 ]G" pwr_cr_gt_x86_pf $end
+$var reg 1 mG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[8] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 LF" int_fp $end
+$scope struct flags $end
+$var reg 1 \F" pwr_ca32_x86_af $end
+$var reg 1 lF" pwr_ca_x86_cf $end
+$var reg 1 |F" pwr_ov32_x86_df $end
+$var reg 1 .G" pwr_ov_x86_of $end
+$var reg 1 >G" pwr_so $end
+$var reg 1 NG" pwr_cr_eq_x86_zf $end
+$var reg 1 ^G" pwr_cr_gt_x86_pf $end
+$var reg 1 nG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[9] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 MF" int_fp $end
+$scope struct flags $end
+$var reg 1 ]F" pwr_ca32_x86_af $end
+$var reg 1 mF" pwr_ca_x86_cf $end
+$var reg 1 }F" pwr_ov32_x86_df $end
+$var reg 1 /G" pwr_ov_x86_of $end
+$var reg 1 ?G" pwr_so $end
+$var reg 1 OG" pwr_cr_eq_x86_zf $end
+$var reg 1 _G" pwr_cr_gt_x86_pf $end
+$var reg 1 oG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[10] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 NF" int_fp $end
+$scope struct flags $end
+$var reg 1 ^F" pwr_ca32_x86_af $end
+$var reg 1 nF" pwr_ca_x86_cf $end
+$var reg 1 ~F" pwr_ov32_x86_df $end
+$var reg 1 0G" pwr_ov_x86_of $end
+$var reg 1 @G" pwr_so $end
+$var reg 1 PG" pwr_cr_eq_x86_zf $end
+$var reg 1 `G" pwr_cr_gt_x86_pf $end
+$var reg 1 pG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[11] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 OF" int_fp $end
+$scope struct flags $end
+$var reg 1 _F" pwr_ca32_x86_af $end
+$var reg 1 oF" pwr_ca_x86_cf $end
+$var reg 1 !G" pwr_ov32_x86_df $end
+$var reg 1 1G" pwr_ov_x86_of $end
+$var reg 1 AG" pwr_so $end
+$var reg 1 QG" pwr_cr_eq_x86_zf $end
+$var reg 1 aG" pwr_cr_gt_x86_pf $end
+$var reg 1 qG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[12] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 PF" int_fp $end
+$scope struct flags $end
+$var reg 1 `F" pwr_ca32_x86_af $end
+$var reg 1 pF" pwr_ca_x86_cf $end
+$var reg 1 "G" pwr_ov32_x86_df $end
+$var reg 1 2G" pwr_ov_x86_of $end
+$var reg 1 BG" pwr_so $end
+$var reg 1 RG" pwr_cr_eq_x86_zf $end
+$var reg 1 bG" pwr_cr_gt_x86_pf $end
+$var reg 1 rG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[13] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 QF" int_fp $end
+$scope struct flags $end
+$var reg 1 aF" pwr_ca32_x86_af $end
+$var reg 1 qF" pwr_ca_x86_cf $end
+$var reg 1 #G" pwr_ov32_x86_df $end
+$var reg 1 3G" pwr_ov_x86_of $end
+$var reg 1 CG" pwr_so $end
+$var reg 1 SG" pwr_cr_eq_x86_zf $end
+$var reg 1 cG" pwr_cr_gt_x86_pf $end
+$var reg 1 sG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[14] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 RF" int_fp $end
+$scope struct flags $end
+$var reg 1 bF" pwr_ca32_x86_af $end
+$var reg 1 rF" pwr_ca_x86_cf $end
+$var reg 1 $G" pwr_ov32_x86_df $end
+$var reg 1 4G" pwr_ov_x86_of $end
+$var reg 1 DG" pwr_so $end
+$var reg 1 TG" pwr_cr_eq_x86_zf $end
+$var reg 1 dG" pwr_cr_gt_x86_pf $end
+$var reg 1 tG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct \[15] $end
+$scope struct unit_1_output_regs $end
+$var reg 64 SF" int_fp $end
+$scope struct flags $end
+$var reg 1 cF" pwr_ca32_x86_af $end
+$var reg 1 sF" pwr_ca_x86_cf $end
+$var reg 1 %G" pwr_ov32_x86_df $end
+$var reg 1 5G" pwr_ov_x86_of $end
+$var reg 1 EG" pwr_so $end
+$var reg 1 UG" pwr_cr_eq_x86_zf $end
+$var reg 1 eG" pwr_cr_gt_x86_pf $end
+$var reg 1 uG" pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct r0 $end
+$var wire 4 G@ addr $end
+$var wire 1 H@ en $end
+$var wire 1 I@ clk $end
+$scope struct data $end
+$var wire 64 J@ int_fp $end
+$scope struct flags $end
+$var wire 1 K@ pwr_ca32_x86_af $end
+$var wire 1 L@ pwr_ca_x86_cf $end
+$var wire 1 M@ pwr_ov32_x86_df $end
+$var wire 1 N@ pwr_ov_x86_of $end
+$var wire 1 O@ pwr_so $end
+$var wire 1 P@ pwr_cr_eq_x86_zf $end
+$var wire 1 Q@ pwr_cr_gt_x86_pf $end
+$var wire 1 R@ pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct r1 $end
+$var wire 4 S@ addr $end
+$var wire 1 T@ en $end
+$var wire 1 U@ clk $end
+$scope struct data $end
+$var wire 64 V@ int_fp $end
 $scope struct flags $end
 $var wire 1 W@ pwr_ca32_x86_af $end
 $var wire 1 X@ pwr_ca_x86_cf $end
@@ -11928,711 +12283,717 @@ $var wire 1 ^@ pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
+$scope struct r2 $end
+$var wire 4 _@ addr $end
+$var wire 1 `@ en $end
+$var wire 1 a@ clk $end
+$scope struct data $end
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+$scope struct flags $end
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+$var wire 1 d@ pwr_ca_x86_cf $end
+$var wire 1 e@ pwr_ov32_x86_df $end
+$var wire 1 f@ pwr_ov_x86_of $end
+$var wire 1 g@ pwr_so $end
+$var wire 1 h@ pwr_cr_eq_x86_zf $end
+$var wire 1 i@ pwr_cr_gt_x86_pf $end
+$var wire 1 j@ pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct w3 $end
+$var wire 4 k@ addr $end
+$var wire 1 l@ en $end
+$var wire 1 m@ clk $end
+$scope struct data $end
+$var wire 64 n@ int_fp $end
+$scope struct flags $end
+$var wire 1 o@ pwr_ca32_x86_af $end
+$var wire 1 p@ pwr_ca_x86_cf $end
+$var wire 1 q@ pwr_ov32_x86_df $end
+$var wire 1 r@ pwr_ov_x86_of $end
+$var wire 1 s@ pwr_so $end
+$var wire 1 t@ pwr_cr_eq_x86_zf $end
+$var wire 1 u@ pwr_cr_gt_x86_pf $end
+$var wire 1 v@ pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$scope struct mask $end
+$var wire 1 w@ int_fp $end
+$scope struct flags $end
+$var wire 1 x@ pwr_ca32_x86_af $end
+$var wire 1 y@ pwr_ca_x86_cf $end
+$var wire 1 z@ pwr_ov32_x86_df $end
+$var wire 1 {@ pwr_ov_x86_of $end
+$var wire 1 |@ pwr_so $end
+$var wire 1 }@ pwr_cr_eq_x86_zf $end
+$var wire 1 ~@ pwr_cr_gt_x86_pf $end
+$var wire 1 !A pwr_cr_lt_x86_sf $end
+$upscope $end
+$upscope $end
+$upscope $end
 $upscope $end
 $scope struct in_flight_ops $end
 $scope struct \[0] $end
-$var string 1 _@ \$tag $end
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 $scope struct HdlSome $end
-$var string 1 `@ state $end
+$var string 1 #A state $end
 $scope struct mop $end
-$var string 1 a@ \$tag $end
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 $scope struct AddSub $end
 $scope struct alu_common $end
 $scope struct common $end
-$var string 0 b@ prefix_pad $end
+$var string 0 %A prefix_pad $end
 $scope struct dest $end
-$var reg 4 c@ value $end
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 $upscope $end
 $scope struct src $end
-$var reg 6 d@ \[0] $end
-$var reg 6 e@ \[1] $end
-$var reg 6 f@ \[2] $end
+$var reg 6 'A \[0] $end
+$var reg 6 (A \[1] $end
+$var reg 6 )A \[2] $end
 $upscope $end
-$var reg 25 g@ imm_low $end
-$var reg 1 h@ imm_sign $end
-$scope struct _phantom $end
+$var reg 26 *A imm $end
 $upscope $end
+$var string 1 +A output_integer_mode $end
 $upscope $end
-$var string 1 i@ output_integer_mode $end
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@@ -15330,99 +15795,103 @@ $upscope $end
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@@ -15441,651 +15910,667 @@ $upscope $end
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@@ -16096,7 +16581,7 @@ $var wire 1 >V \[3] $end
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@@ -16106,300 +16591,308 @@ $upscope $end
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@@ -16407,299 +16900,308 @@ $upscope $end
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 $upscope $end
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 $scope struct common $end
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 $scope struct src_values $end
 $scope struct \[0] $end
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 $upscope $end
 $upscope $end
 $scope struct \[1] $end
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 $scope struct flags $end
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 $upscope $end
 $upscope $end
 $scope struct \[2] $end
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 $scope struct flags $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
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 $scope struct flags $end
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 $upscope $end
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 $scope struct flags_2 $end
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 $upscope $end
 $upscope $end
 $scope struct unit_0_free_regs_tracker $end
 $scope struct cd $end
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 $scope struct \[0] $end
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 $upscope $end
 $upscope $end
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 $scope struct \[0] $end
 $scope struct data $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope module unit_free_regs_tracker $end
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 $upscope $end
 $scope struct free_in $end
 $scope struct \[0] $end
 $scope struct data $end
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 $upscope $end
 $upscope $end
 $scope struct alloc_out $end
 $scope struct \[0] $end
 $scope struct data $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $scope struct allocated_reg $end
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 $upscope $end
 $scope struct firing_data $end
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 $upscope $end
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-$var wire 1 ?a reduced_count_overflowed_0_2 $end
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 $scope struct reduced_alloc_nums_0_2 $end
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 $upscope $end
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 $scope struct reduced_alloc_nums_2_4 $end
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 $upscope $end
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 $scope struct reduced_alloc_nums_0_4 $end
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 $upscope $end
-$var wire 1 Ga reduced_count_4_6 $end
-$var wire 1 Ha reduced_count_overflowed_4_6 $end
+$var wire 1 rc reduced_count_4_6 $end
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 $scope struct reduced_alloc_nums_4_6 $end
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 $upscope $end
-$var wire 1 Ja reduced_count_6_8 $end
-$var wire 1 Ka reduced_count_overflowed_6_8 $end
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 $scope struct reduced_alloc_nums_6_8 $end
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 $scope struct reduced_alloc_nums_0_8 $end
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@@ -17875,7 +18334,7 @@ $var wire 1 kd \[3] $end
 $upscope $end
 $upscope $end
 $upscope $end
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 $scope struct alu_common $end
 $scope struct common $end
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@@ -17885,94 +18344,110 @@ $upscope $end
 $scope struct src $end
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 $upscope $end
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@@ -18337,836 +18811,504 @@ $var wire 6 'g \[0] $end
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@@ -19177,893 +19319,241 @@ $var wire 6 Pi \[0] $end
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@@ -20072,8 +19562,7 @@ $var wire 1 `j src1_is_carry_in $end
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@@ -20084,136 +19573,145 @@ $var wire 6 ej \[0] $end
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@@ -20230,75 +19728,1154 @@ $var wire 6 Hk \[0] $end
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@@ -20312,295 +20889,1021 @@ $upscope $end
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 $upscope $end
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@@ -20615,496 +21918,496 @@ $upscope $end
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 $scope struct flags $end
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 $scope struct unit_0_output_regs $end
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 $scope struct flags $end
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-$var reg 1 zB" pwr_ov_x86_of $end
-$var reg 1 ,C" pwr_so $end
-$var reg 1 <C" pwr_cr_eq_x86_zf $end
-$var reg 1 LC" pwr_cr_gt_x86_pf $end
-$var reg 1 \C" pwr_cr_lt_x86_sf $end
+$var reg 1 JH" pwr_ca32_x86_af $end
+$var reg 1 ZH" pwr_ca_x86_cf $end
+$var reg 1 jH" pwr_ov32_x86_df $end
+$var reg 1 zH" pwr_ov_x86_of $end
+$var reg 1 ,I" pwr_so $end
+$var reg 1 <I" pwr_cr_eq_x86_zf $end
+$var reg 1 LI" pwr_cr_gt_x86_pf $end
+$var reg 1 \I" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[3] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 ;B" int_fp $end
+$var reg 64 ;H" int_fp $end
 $scope struct flags $end
-$var reg 1 KB" pwr_ca32_x86_af $end
-$var reg 1 [B" pwr_ca_x86_cf $end
-$var reg 1 kB" pwr_ov32_x86_df $end
-$var reg 1 {B" pwr_ov_x86_of $end
-$var reg 1 -C" pwr_so $end
-$var reg 1 =C" pwr_cr_eq_x86_zf $end
-$var reg 1 MC" pwr_cr_gt_x86_pf $end
-$var reg 1 ]C" pwr_cr_lt_x86_sf $end
+$var reg 1 KH" pwr_ca32_x86_af $end
+$var reg 1 [H" pwr_ca_x86_cf $end
+$var reg 1 kH" pwr_ov32_x86_df $end
+$var reg 1 {H" pwr_ov_x86_of $end
+$var reg 1 -I" pwr_so $end
+$var reg 1 =I" pwr_cr_eq_x86_zf $end
+$var reg 1 MI" pwr_cr_gt_x86_pf $end
+$var reg 1 ]I" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[4] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 <B" int_fp $end
+$var reg 64 <H" int_fp $end
 $scope struct flags $end
-$var reg 1 LB" pwr_ca32_x86_af $end
-$var reg 1 \B" pwr_ca_x86_cf $end
-$var reg 1 lB" pwr_ov32_x86_df $end
-$var reg 1 |B" pwr_ov_x86_of $end
-$var reg 1 .C" pwr_so $end
-$var reg 1 >C" pwr_cr_eq_x86_zf $end
-$var reg 1 NC" pwr_cr_gt_x86_pf $end
-$var reg 1 ^C" pwr_cr_lt_x86_sf $end
+$var reg 1 LH" pwr_ca32_x86_af $end
+$var reg 1 \H" pwr_ca_x86_cf $end
+$var reg 1 lH" pwr_ov32_x86_df $end
+$var reg 1 |H" pwr_ov_x86_of $end
+$var reg 1 .I" pwr_so $end
+$var reg 1 >I" pwr_cr_eq_x86_zf $end
+$var reg 1 NI" pwr_cr_gt_x86_pf $end
+$var reg 1 ^I" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[5] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 =B" int_fp $end
+$var reg 64 =H" int_fp $end
 $scope struct flags $end
-$var reg 1 MB" pwr_ca32_x86_af $end
-$var reg 1 ]B" pwr_ca_x86_cf $end
-$var reg 1 mB" pwr_ov32_x86_df $end
-$var reg 1 }B" pwr_ov_x86_of $end
-$var reg 1 /C" pwr_so $end
-$var reg 1 ?C" pwr_cr_eq_x86_zf $end
-$var reg 1 OC" pwr_cr_gt_x86_pf $end
-$var reg 1 _C" pwr_cr_lt_x86_sf $end
+$var reg 1 MH" pwr_ca32_x86_af $end
+$var reg 1 ]H" pwr_ca_x86_cf $end
+$var reg 1 mH" pwr_ov32_x86_df $end
+$var reg 1 }H" pwr_ov_x86_of $end
+$var reg 1 /I" pwr_so $end
+$var reg 1 ?I" pwr_cr_eq_x86_zf $end
+$var reg 1 OI" pwr_cr_gt_x86_pf $end
+$var reg 1 _I" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[6] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 >B" int_fp $end
+$var reg 64 >H" int_fp $end
 $scope struct flags $end
-$var reg 1 NB" pwr_ca32_x86_af $end
-$var reg 1 ^B" pwr_ca_x86_cf $end
-$var reg 1 nB" pwr_ov32_x86_df $end
-$var reg 1 ~B" pwr_ov_x86_of $end
-$var reg 1 0C" pwr_so $end
-$var reg 1 @C" pwr_cr_eq_x86_zf $end
-$var reg 1 PC" pwr_cr_gt_x86_pf $end
-$var reg 1 `C" pwr_cr_lt_x86_sf $end
+$var reg 1 NH" pwr_ca32_x86_af $end
+$var reg 1 ^H" pwr_ca_x86_cf $end
+$var reg 1 nH" pwr_ov32_x86_df $end
+$var reg 1 ~H" pwr_ov_x86_of $end
+$var reg 1 0I" pwr_so $end
+$var reg 1 @I" pwr_cr_eq_x86_zf $end
+$var reg 1 PI" pwr_cr_gt_x86_pf $end
+$var reg 1 `I" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[7] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 ?B" int_fp $end
+$var reg 64 ?H" int_fp $end
 $scope struct flags $end
-$var reg 1 OB" pwr_ca32_x86_af $end
-$var reg 1 _B" pwr_ca_x86_cf $end
-$var reg 1 oB" pwr_ov32_x86_df $end
-$var reg 1 !C" pwr_ov_x86_of $end
-$var reg 1 1C" pwr_so $end
-$var reg 1 AC" pwr_cr_eq_x86_zf $end
-$var reg 1 QC" pwr_cr_gt_x86_pf $end
-$var reg 1 aC" pwr_cr_lt_x86_sf $end
+$var reg 1 OH" pwr_ca32_x86_af $end
+$var reg 1 _H" pwr_ca_x86_cf $end
+$var reg 1 oH" pwr_ov32_x86_df $end
+$var reg 1 !I" pwr_ov_x86_of $end
+$var reg 1 1I" pwr_so $end
+$var reg 1 AI" pwr_cr_eq_x86_zf $end
+$var reg 1 QI" pwr_cr_gt_x86_pf $end
+$var reg 1 aI" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[8] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 @B" int_fp $end
+$var reg 64 @H" int_fp $end
 $scope struct flags $end
-$var reg 1 PB" pwr_ca32_x86_af $end
-$var reg 1 `B" pwr_ca_x86_cf $end
-$var reg 1 pB" pwr_ov32_x86_df $end
-$var reg 1 "C" pwr_ov_x86_of $end
-$var reg 1 2C" pwr_so $end
-$var reg 1 BC" pwr_cr_eq_x86_zf $end
-$var reg 1 RC" pwr_cr_gt_x86_pf $end
-$var reg 1 bC" pwr_cr_lt_x86_sf $end
+$var reg 1 PH" pwr_ca32_x86_af $end
+$var reg 1 `H" pwr_ca_x86_cf $end
+$var reg 1 pH" pwr_ov32_x86_df $end
+$var reg 1 "I" pwr_ov_x86_of $end
+$var reg 1 2I" pwr_so $end
+$var reg 1 BI" pwr_cr_eq_x86_zf $end
+$var reg 1 RI" pwr_cr_gt_x86_pf $end
+$var reg 1 bI" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[9] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 AB" int_fp $end
+$var reg 64 AH" int_fp $end
 $scope struct flags $end
-$var reg 1 QB" pwr_ca32_x86_af $end
-$var reg 1 aB" pwr_ca_x86_cf $end
-$var reg 1 qB" pwr_ov32_x86_df $end
-$var reg 1 #C" pwr_ov_x86_of $end
-$var reg 1 3C" pwr_so $end
-$var reg 1 CC" pwr_cr_eq_x86_zf $end
-$var reg 1 SC" pwr_cr_gt_x86_pf $end
-$var reg 1 cC" pwr_cr_lt_x86_sf $end
+$var reg 1 QH" pwr_ca32_x86_af $end
+$var reg 1 aH" pwr_ca_x86_cf $end
+$var reg 1 qH" pwr_ov32_x86_df $end
+$var reg 1 #I" pwr_ov_x86_of $end
+$var reg 1 3I" pwr_so $end
+$var reg 1 CI" pwr_cr_eq_x86_zf $end
+$var reg 1 SI" pwr_cr_gt_x86_pf $end
+$var reg 1 cI" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[10] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 BB" int_fp $end
+$var reg 64 BH" int_fp $end
 $scope struct flags $end
-$var reg 1 RB" pwr_ca32_x86_af $end
-$var reg 1 bB" pwr_ca_x86_cf $end
-$var reg 1 rB" pwr_ov32_x86_df $end
-$var reg 1 $C" pwr_ov_x86_of $end
-$var reg 1 4C" pwr_so $end
-$var reg 1 DC" pwr_cr_eq_x86_zf $end
-$var reg 1 TC" pwr_cr_gt_x86_pf $end
-$var reg 1 dC" pwr_cr_lt_x86_sf $end
+$var reg 1 RH" pwr_ca32_x86_af $end
+$var reg 1 bH" pwr_ca_x86_cf $end
+$var reg 1 rH" pwr_ov32_x86_df $end
+$var reg 1 $I" pwr_ov_x86_of $end
+$var reg 1 4I" pwr_so $end
+$var reg 1 DI" pwr_cr_eq_x86_zf $end
+$var reg 1 TI" pwr_cr_gt_x86_pf $end
+$var reg 1 dI" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[11] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 CB" int_fp $end
+$var reg 64 CH" int_fp $end
 $scope struct flags $end
-$var reg 1 SB" pwr_ca32_x86_af $end
-$var reg 1 cB" pwr_ca_x86_cf $end
-$var reg 1 sB" pwr_ov32_x86_df $end
-$var reg 1 %C" pwr_ov_x86_of $end
-$var reg 1 5C" pwr_so $end
-$var reg 1 EC" pwr_cr_eq_x86_zf $end
-$var reg 1 UC" pwr_cr_gt_x86_pf $end
-$var reg 1 eC" pwr_cr_lt_x86_sf $end
+$var reg 1 SH" pwr_ca32_x86_af $end
+$var reg 1 cH" pwr_ca_x86_cf $end
+$var reg 1 sH" pwr_ov32_x86_df $end
+$var reg 1 %I" pwr_ov_x86_of $end
+$var reg 1 5I" pwr_so $end
+$var reg 1 EI" pwr_cr_eq_x86_zf $end
+$var reg 1 UI" pwr_cr_gt_x86_pf $end
+$var reg 1 eI" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[12] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 DB" int_fp $end
+$var reg 64 DH" int_fp $end
 $scope struct flags $end
-$var reg 1 TB" pwr_ca32_x86_af $end
-$var reg 1 dB" pwr_ca_x86_cf $end
-$var reg 1 tB" pwr_ov32_x86_df $end
-$var reg 1 &C" pwr_ov_x86_of $end
-$var reg 1 6C" pwr_so $end
-$var reg 1 FC" pwr_cr_eq_x86_zf $end
-$var reg 1 VC" pwr_cr_gt_x86_pf $end
-$var reg 1 fC" pwr_cr_lt_x86_sf $end
+$var reg 1 TH" pwr_ca32_x86_af $end
+$var reg 1 dH" pwr_ca_x86_cf $end
+$var reg 1 tH" pwr_ov32_x86_df $end
+$var reg 1 &I" pwr_ov_x86_of $end
+$var reg 1 6I" pwr_so $end
+$var reg 1 FI" pwr_cr_eq_x86_zf $end
+$var reg 1 VI" pwr_cr_gt_x86_pf $end
+$var reg 1 fI" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[13] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 EB" int_fp $end
+$var reg 64 EH" int_fp $end
 $scope struct flags $end
-$var reg 1 UB" pwr_ca32_x86_af $end
-$var reg 1 eB" pwr_ca_x86_cf $end
-$var reg 1 uB" pwr_ov32_x86_df $end
-$var reg 1 'C" pwr_ov_x86_of $end
-$var reg 1 7C" pwr_so $end
-$var reg 1 GC" pwr_cr_eq_x86_zf $end
-$var reg 1 WC" pwr_cr_gt_x86_pf $end
-$var reg 1 gC" pwr_cr_lt_x86_sf $end
+$var reg 1 UH" pwr_ca32_x86_af $end
+$var reg 1 eH" pwr_ca_x86_cf $end
+$var reg 1 uH" pwr_ov32_x86_df $end
+$var reg 1 'I" pwr_ov_x86_of $end
+$var reg 1 7I" pwr_so $end
+$var reg 1 GI" pwr_cr_eq_x86_zf $end
+$var reg 1 WI" pwr_cr_gt_x86_pf $end
+$var reg 1 gI" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[14] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 FB" int_fp $end
+$var reg 64 FH" int_fp $end
 $scope struct flags $end
-$var reg 1 VB" pwr_ca32_x86_af $end
-$var reg 1 fB" pwr_ca_x86_cf $end
-$var reg 1 vB" pwr_ov32_x86_df $end
-$var reg 1 (C" pwr_ov_x86_of $end
-$var reg 1 8C" pwr_so $end
-$var reg 1 HC" pwr_cr_eq_x86_zf $end
-$var reg 1 XC" pwr_cr_gt_x86_pf $end
-$var reg 1 hC" pwr_cr_lt_x86_sf $end
+$var reg 1 VH" pwr_ca32_x86_af $end
+$var reg 1 fH" pwr_ca_x86_cf $end
+$var reg 1 vH" pwr_ov32_x86_df $end
+$var reg 1 (I" pwr_ov_x86_of $end
+$var reg 1 8I" pwr_so $end
+$var reg 1 HI" pwr_cr_eq_x86_zf $end
+$var reg 1 XI" pwr_cr_gt_x86_pf $end
+$var reg 1 hI" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[15] $end
 $scope struct unit_0_output_regs $end
-$var reg 64 GB" int_fp $end
+$var reg 64 GH" int_fp $end
 $scope struct flags $end
-$var reg 1 WB" pwr_ca32_x86_af $end
-$var reg 1 gB" pwr_ca_x86_cf $end
-$var reg 1 wB" pwr_ov32_x86_df $end
-$var reg 1 )C" pwr_ov_x86_of $end
-$var reg 1 9C" pwr_so $end
-$var reg 1 IC" pwr_cr_eq_x86_zf $end
-$var reg 1 YC" pwr_cr_gt_x86_pf $end
-$var reg 1 iC" pwr_cr_lt_x86_sf $end
+$var reg 1 WH" pwr_ca32_x86_af $end
+$var reg 1 gH" pwr_ca_x86_cf $end
+$var reg 1 wH" pwr_ov32_x86_df $end
+$var reg 1 )I" pwr_ov_x86_of $end
+$var reg 1 9I" pwr_so $end
+$var reg 1 II" pwr_cr_eq_x86_zf $end
+$var reg 1 YI" pwr_cr_gt_x86_pf $end
+$var reg 1 iI" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r0 $end
-$var wire 4 rm addr $end
-$var wire 1 sm en $end
-$var wire 1 tm clk $end
+$var wire 4 2q addr $end
+$var wire 1 3q en $end
+$var wire 1 4q clk $end
 $scope struct data $end
-$var wire 64 um int_fp $end
+$var wire 64 5q int_fp $end
 $scope struct flags $end
-$var wire 1 vm pwr_ca32_x86_af $end
-$var wire 1 wm pwr_ca_x86_cf $end
-$var wire 1 xm pwr_ov32_x86_df $end
-$var wire 1 ym pwr_ov_x86_of $end
-$var wire 1 zm pwr_so $end
-$var wire 1 {m pwr_cr_eq_x86_zf $end
-$var wire 1 |m pwr_cr_gt_x86_pf $end
-$var wire 1 }m pwr_cr_lt_x86_sf $end
+$var wire 1 6q pwr_ca32_x86_af $end
+$var wire 1 7q pwr_ca_x86_cf $end
+$var wire 1 8q pwr_ov32_x86_df $end
+$var wire 1 9q pwr_ov_x86_of $end
+$var wire 1 :q pwr_so $end
+$var wire 1 ;q pwr_cr_eq_x86_zf $end
+$var wire 1 <q pwr_cr_gt_x86_pf $end
+$var wire 1 =q pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r1 $end
-$var wire 4 ~m addr $end
-$var wire 1 !n en $end
-$var wire 1 "n clk $end
+$var wire 4 >q addr $end
+$var wire 1 ?q en $end
+$var wire 1 @q clk $end
 $scope struct data $end
-$var wire 64 #n int_fp $end
+$var wire 64 Aq int_fp $end
 $scope struct flags $end
-$var wire 1 $n pwr_ca32_x86_af $end
-$var wire 1 %n pwr_ca_x86_cf $end
-$var wire 1 &n pwr_ov32_x86_df $end
-$var wire 1 'n pwr_ov_x86_of $end
-$var wire 1 (n pwr_so $end
-$var wire 1 )n pwr_cr_eq_x86_zf $end
-$var wire 1 *n pwr_cr_gt_x86_pf $end
-$var wire 1 +n pwr_cr_lt_x86_sf $end
+$var wire 1 Bq pwr_ca32_x86_af $end
+$var wire 1 Cq pwr_ca_x86_cf $end
+$var wire 1 Dq pwr_ov32_x86_df $end
+$var wire 1 Eq pwr_ov_x86_of $end
+$var wire 1 Fq pwr_so $end
+$var wire 1 Gq pwr_cr_eq_x86_zf $end
+$var wire 1 Hq pwr_cr_gt_x86_pf $end
+$var wire 1 Iq pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r2 $end
-$var wire 4 ,n addr $end
-$var wire 1 -n en $end
-$var wire 1 .n clk $end
+$var wire 4 Jq addr $end
+$var wire 1 Kq en $end
+$var wire 1 Lq clk $end
 $scope struct data $end
-$var wire 64 /n int_fp $end
+$var wire 64 Mq int_fp $end
 $scope struct flags $end
-$var wire 1 0n pwr_ca32_x86_af $end
-$var wire 1 1n pwr_ca_x86_cf $end
-$var wire 1 2n pwr_ov32_x86_df $end
-$var wire 1 3n pwr_ov_x86_of $end
-$var wire 1 4n pwr_so $end
-$var wire 1 5n pwr_cr_eq_x86_zf $end
-$var wire 1 6n pwr_cr_gt_x86_pf $end
-$var wire 1 7n pwr_cr_lt_x86_sf $end
+$var wire 1 Nq pwr_ca32_x86_af $end
+$var wire 1 Oq pwr_ca_x86_cf $end
+$var wire 1 Pq pwr_ov32_x86_df $end
+$var wire 1 Qq pwr_ov_x86_of $end
+$var wire 1 Rq pwr_so $end
+$var wire 1 Sq pwr_cr_eq_x86_zf $end
+$var wire 1 Tq pwr_cr_gt_x86_pf $end
+$var wire 1 Uq pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct w3 $end
-$var wire 4 8n addr $end
-$var wire 1 9n en $end
-$var wire 1 :n clk $end
+$var wire 4 Vq addr $end
+$var wire 1 Wq en $end
+$var wire 1 Xq clk $end
 $scope struct data $end
-$var wire 64 ;n int_fp $end
+$var wire 64 Yq int_fp $end
 $scope struct flags $end
-$var wire 1 <n pwr_ca32_x86_af $end
-$var wire 1 =n pwr_ca_x86_cf $end
-$var wire 1 >n pwr_ov32_x86_df $end
-$var wire 1 ?n pwr_ov_x86_of $end
-$var wire 1 @n pwr_so $end
-$var wire 1 An pwr_cr_eq_x86_zf $end
-$var wire 1 Bn pwr_cr_gt_x86_pf $end
-$var wire 1 Cn pwr_cr_lt_x86_sf $end
+$var wire 1 Zq pwr_ca32_x86_af $end
+$var wire 1 [q pwr_ca_x86_cf $end
+$var wire 1 \q pwr_ov32_x86_df $end
+$var wire 1 ]q pwr_ov_x86_of $end
+$var wire 1 ^q pwr_so $end
+$var wire 1 _q pwr_cr_eq_x86_zf $end
+$var wire 1 `q pwr_cr_gt_x86_pf $end
+$var wire 1 aq pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $scope struct mask $end
-$var wire 1 Dn int_fp $end
+$var wire 1 bq int_fp $end
 $scope struct flags $end
-$var wire 1 En pwr_ca32_x86_af $end
-$var wire 1 Fn pwr_ca_x86_cf $end
-$var wire 1 Gn pwr_ov32_x86_df $end
-$var wire 1 Hn pwr_ov_x86_of $end
-$var wire 1 In pwr_so $end
-$var wire 1 Jn pwr_cr_eq_x86_zf $end
-$var wire 1 Kn pwr_cr_gt_x86_pf $end
-$var wire 1 Ln pwr_cr_lt_x86_sf $end
+$var wire 1 cq pwr_ca32_x86_af $end
+$var wire 1 dq pwr_ca_x86_cf $end
+$var wire 1 eq pwr_ov32_x86_df $end
+$var wire 1 fq pwr_ov_x86_of $end
+$var wire 1 gq pwr_so $end
+$var wire 1 hq pwr_cr_eq_x86_zf $end
+$var wire 1 iq pwr_cr_gt_x86_pf $end
+$var wire 1 jq pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -21113,1186 +22416,535 @@ $scope struct unit_1_output_regs $end
 $scope struct contents $end
 $scope struct \[0] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 jC" int_fp $end
+$var reg 64 jI" int_fp $end
 $scope struct flags $end
-$var reg 1 zC" pwr_ca32_x86_af $end
-$var reg 1 ,D" pwr_ca_x86_cf $end
-$var reg 1 <D" pwr_ov32_x86_df $end
-$var reg 1 LD" pwr_ov_x86_of $end
-$var reg 1 \D" pwr_so $end
-$var reg 1 lD" pwr_cr_eq_x86_zf $end
-$var reg 1 |D" pwr_cr_gt_x86_pf $end
-$var reg 1 .E" pwr_cr_lt_x86_sf $end
+$var reg 1 zI" pwr_ca32_x86_af $end
+$var reg 1 ,J" pwr_ca_x86_cf $end
+$var reg 1 <J" pwr_ov32_x86_df $end
+$var reg 1 LJ" pwr_ov_x86_of $end
+$var reg 1 \J" pwr_so $end
+$var reg 1 lJ" pwr_cr_eq_x86_zf $end
+$var reg 1 |J" pwr_cr_gt_x86_pf $end
+$var reg 1 .K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 kC" int_fp $end
+$var reg 64 kI" int_fp $end
 $scope struct flags $end
-$var reg 1 {C" pwr_ca32_x86_af $end
-$var reg 1 -D" pwr_ca_x86_cf $end
-$var reg 1 =D" pwr_ov32_x86_df $end
-$var reg 1 MD" pwr_ov_x86_of $end
-$var reg 1 ]D" pwr_so $end
-$var reg 1 mD" pwr_cr_eq_x86_zf $end
-$var reg 1 }D" pwr_cr_gt_x86_pf $end
-$var reg 1 /E" pwr_cr_lt_x86_sf $end
+$var reg 1 {I" pwr_ca32_x86_af $end
+$var reg 1 -J" pwr_ca_x86_cf $end
+$var reg 1 =J" pwr_ov32_x86_df $end
+$var reg 1 MJ" pwr_ov_x86_of $end
+$var reg 1 ]J" pwr_so $end
+$var reg 1 mJ" pwr_cr_eq_x86_zf $end
+$var reg 1 }J" pwr_cr_gt_x86_pf $end
+$var reg 1 /K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[2] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 lC" int_fp $end
+$var reg 64 lI" int_fp $end
 $scope struct flags $end
-$var reg 1 |C" pwr_ca32_x86_af $end
-$var reg 1 .D" pwr_ca_x86_cf $end
-$var reg 1 >D" pwr_ov32_x86_df $end
-$var reg 1 ND" pwr_ov_x86_of $end
-$var reg 1 ^D" pwr_so $end
-$var reg 1 nD" pwr_cr_eq_x86_zf $end
-$var reg 1 ~D" pwr_cr_gt_x86_pf $end
-$var reg 1 0E" pwr_cr_lt_x86_sf $end
+$var reg 1 |I" pwr_ca32_x86_af $end
+$var reg 1 .J" pwr_ca_x86_cf $end
+$var reg 1 >J" pwr_ov32_x86_df $end
+$var reg 1 NJ" pwr_ov_x86_of $end
+$var reg 1 ^J" pwr_so $end
+$var reg 1 nJ" pwr_cr_eq_x86_zf $end
+$var reg 1 ~J" pwr_cr_gt_x86_pf $end
+$var reg 1 0K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[3] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 mC" int_fp $end
+$var reg 64 mI" int_fp $end
 $scope struct flags $end
-$var reg 1 }C" pwr_ca32_x86_af $end
-$var reg 1 /D" pwr_ca_x86_cf $end
-$var reg 1 ?D" pwr_ov32_x86_df $end
-$var reg 1 OD" pwr_ov_x86_of $end
-$var reg 1 _D" pwr_so $end
-$var reg 1 oD" pwr_cr_eq_x86_zf $end
-$var reg 1 !E" pwr_cr_gt_x86_pf $end
-$var reg 1 1E" pwr_cr_lt_x86_sf $end
+$var reg 1 }I" pwr_ca32_x86_af $end
+$var reg 1 /J" pwr_ca_x86_cf $end
+$var reg 1 ?J" pwr_ov32_x86_df $end
+$var reg 1 OJ" pwr_ov_x86_of $end
+$var reg 1 _J" pwr_so $end
+$var reg 1 oJ" pwr_cr_eq_x86_zf $end
+$var reg 1 !K" pwr_cr_gt_x86_pf $end
+$var reg 1 1K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[4] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 nC" int_fp $end
+$var reg 64 nI" int_fp $end
 $scope struct flags $end
-$var reg 1 ~C" pwr_ca32_x86_af $end
-$var reg 1 0D" pwr_ca_x86_cf $end
-$var reg 1 @D" pwr_ov32_x86_df $end
-$var reg 1 PD" pwr_ov_x86_of $end
-$var reg 1 `D" pwr_so $end
-$var reg 1 pD" pwr_cr_eq_x86_zf $end
-$var reg 1 "E" pwr_cr_gt_x86_pf $end
-$var reg 1 2E" pwr_cr_lt_x86_sf $end
+$var reg 1 ~I" pwr_ca32_x86_af $end
+$var reg 1 0J" pwr_ca_x86_cf $end
+$var reg 1 @J" pwr_ov32_x86_df $end
+$var reg 1 PJ" pwr_ov_x86_of $end
+$var reg 1 `J" pwr_so $end
+$var reg 1 pJ" pwr_cr_eq_x86_zf $end
+$var reg 1 "K" pwr_cr_gt_x86_pf $end
+$var reg 1 2K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[5] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 oC" int_fp $end
+$var reg 64 oI" int_fp $end
 $scope struct flags $end
-$var reg 1 !D" pwr_ca32_x86_af $end
-$var reg 1 1D" pwr_ca_x86_cf $end
-$var reg 1 AD" pwr_ov32_x86_df $end
-$var reg 1 QD" pwr_ov_x86_of $end
-$var reg 1 aD" pwr_so $end
-$var reg 1 qD" pwr_cr_eq_x86_zf $end
-$var reg 1 #E" pwr_cr_gt_x86_pf $end
-$var reg 1 3E" pwr_cr_lt_x86_sf $end
+$var reg 1 !J" pwr_ca32_x86_af $end
+$var reg 1 1J" pwr_ca_x86_cf $end
+$var reg 1 AJ" pwr_ov32_x86_df $end
+$var reg 1 QJ" pwr_ov_x86_of $end
+$var reg 1 aJ" pwr_so $end
+$var reg 1 qJ" pwr_cr_eq_x86_zf $end
+$var reg 1 #K" pwr_cr_gt_x86_pf $end
+$var reg 1 3K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[6] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 pC" int_fp $end
+$var reg 64 pI" int_fp $end
 $scope struct flags $end
-$var reg 1 "D" pwr_ca32_x86_af $end
-$var reg 1 2D" pwr_ca_x86_cf $end
-$var reg 1 BD" pwr_ov32_x86_df $end
-$var reg 1 RD" pwr_ov_x86_of $end
-$var reg 1 bD" pwr_so $end
-$var reg 1 rD" pwr_cr_eq_x86_zf $end
-$var reg 1 $E" pwr_cr_gt_x86_pf $end
-$var reg 1 4E" pwr_cr_lt_x86_sf $end
+$var reg 1 "J" pwr_ca32_x86_af $end
+$var reg 1 2J" pwr_ca_x86_cf $end
+$var reg 1 BJ" pwr_ov32_x86_df $end
+$var reg 1 RJ" pwr_ov_x86_of $end
+$var reg 1 bJ" pwr_so $end
+$var reg 1 rJ" pwr_cr_eq_x86_zf $end
+$var reg 1 $K" pwr_cr_gt_x86_pf $end
+$var reg 1 4K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[7] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 qC" int_fp $end
+$var reg 64 qI" int_fp $end
 $scope struct flags $end
-$var reg 1 #D" pwr_ca32_x86_af $end
-$var reg 1 3D" pwr_ca_x86_cf $end
-$var reg 1 CD" pwr_ov32_x86_df $end
-$var reg 1 SD" pwr_ov_x86_of $end
-$var reg 1 cD" pwr_so $end
-$var reg 1 sD" pwr_cr_eq_x86_zf $end
-$var reg 1 %E" pwr_cr_gt_x86_pf $end
-$var reg 1 5E" pwr_cr_lt_x86_sf $end
+$var reg 1 #J" pwr_ca32_x86_af $end
+$var reg 1 3J" pwr_ca_x86_cf $end
+$var reg 1 CJ" pwr_ov32_x86_df $end
+$var reg 1 SJ" pwr_ov_x86_of $end
+$var reg 1 cJ" pwr_so $end
+$var reg 1 sJ" pwr_cr_eq_x86_zf $end
+$var reg 1 %K" pwr_cr_gt_x86_pf $end
+$var reg 1 5K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[8] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 rC" int_fp $end
+$var reg 64 rI" int_fp $end
 $scope struct flags $end
-$var reg 1 $D" pwr_ca32_x86_af $end
-$var reg 1 4D" pwr_ca_x86_cf $end
-$var reg 1 DD" pwr_ov32_x86_df $end
-$var reg 1 TD" pwr_ov_x86_of $end
-$var reg 1 dD" pwr_so $end
-$var reg 1 tD" pwr_cr_eq_x86_zf $end
-$var reg 1 &E" pwr_cr_gt_x86_pf $end
-$var reg 1 6E" pwr_cr_lt_x86_sf $end
+$var reg 1 $J" pwr_ca32_x86_af $end
+$var reg 1 4J" pwr_ca_x86_cf $end
+$var reg 1 DJ" pwr_ov32_x86_df $end
+$var reg 1 TJ" pwr_ov_x86_of $end
+$var reg 1 dJ" pwr_so $end
+$var reg 1 tJ" pwr_cr_eq_x86_zf $end
+$var reg 1 &K" pwr_cr_gt_x86_pf $end
+$var reg 1 6K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[9] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 sC" int_fp $end
+$var reg 64 sI" int_fp $end
 $scope struct flags $end
-$var reg 1 %D" pwr_ca32_x86_af $end
-$var reg 1 5D" pwr_ca_x86_cf $end
-$var reg 1 ED" pwr_ov32_x86_df $end
-$var reg 1 UD" pwr_ov_x86_of $end
-$var reg 1 eD" pwr_so $end
-$var reg 1 uD" pwr_cr_eq_x86_zf $end
-$var reg 1 'E" pwr_cr_gt_x86_pf $end
-$var reg 1 7E" pwr_cr_lt_x86_sf $end
+$var reg 1 %J" pwr_ca32_x86_af $end
+$var reg 1 5J" pwr_ca_x86_cf $end
+$var reg 1 EJ" pwr_ov32_x86_df $end
+$var reg 1 UJ" pwr_ov_x86_of $end
+$var reg 1 eJ" pwr_so $end
+$var reg 1 uJ" pwr_cr_eq_x86_zf $end
+$var reg 1 'K" pwr_cr_gt_x86_pf $end
+$var reg 1 7K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[10] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 tC" int_fp $end
+$var reg 64 tI" int_fp $end
 $scope struct flags $end
-$var reg 1 &D" pwr_ca32_x86_af $end
-$var reg 1 6D" pwr_ca_x86_cf $end
-$var reg 1 FD" pwr_ov32_x86_df $end
-$var reg 1 VD" pwr_ov_x86_of $end
-$var reg 1 fD" pwr_so $end
-$var reg 1 vD" pwr_cr_eq_x86_zf $end
-$var reg 1 (E" pwr_cr_gt_x86_pf $end
-$var reg 1 8E" pwr_cr_lt_x86_sf $end
+$var reg 1 &J" pwr_ca32_x86_af $end
+$var reg 1 6J" pwr_ca_x86_cf $end
+$var reg 1 FJ" pwr_ov32_x86_df $end
+$var reg 1 VJ" pwr_ov_x86_of $end
+$var reg 1 fJ" pwr_so $end
+$var reg 1 vJ" pwr_cr_eq_x86_zf $end
+$var reg 1 (K" pwr_cr_gt_x86_pf $end
+$var reg 1 8K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[11] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 uC" int_fp $end
+$var reg 64 uI" int_fp $end
 $scope struct flags $end
-$var reg 1 'D" pwr_ca32_x86_af $end
-$var reg 1 7D" pwr_ca_x86_cf $end
-$var reg 1 GD" pwr_ov32_x86_df $end
-$var reg 1 WD" pwr_ov_x86_of $end
-$var reg 1 gD" pwr_so $end
-$var reg 1 wD" pwr_cr_eq_x86_zf $end
-$var reg 1 )E" pwr_cr_gt_x86_pf $end
-$var reg 1 9E" pwr_cr_lt_x86_sf $end
+$var reg 1 'J" pwr_ca32_x86_af $end
+$var reg 1 7J" pwr_ca_x86_cf $end
+$var reg 1 GJ" pwr_ov32_x86_df $end
+$var reg 1 WJ" pwr_ov_x86_of $end
+$var reg 1 gJ" pwr_so $end
+$var reg 1 wJ" pwr_cr_eq_x86_zf $end
+$var reg 1 )K" pwr_cr_gt_x86_pf $end
+$var reg 1 9K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[12] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 vC" int_fp $end
+$var reg 64 vI" int_fp $end
 $scope struct flags $end
-$var reg 1 (D" pwr_ca32_x86_af $end
-$var reg 1 8D" pwr_ca_x86_cf $end
-$var reg 1 HD" pwr_ov32_x86_df $end
-$var reg 1 XD" pwr_ov_x86_of $end
-$var reg 1 hD" pwr_so $end
-$var reg 1 xD" pwr_cr_eq_x86_zf $end
-$var reg 1 *E" pwr_cr_gt_x86_pf $end
-$var reg 1 :E" pwr_cr_lt_x86_sf $end
+$var reg 1 (J" pwr_ca32_x86_af $end
+$var reg 1 8J" pwr_ca_x86_cf $end
+$var reg 1 HJ" pwr_ov32_x86_df $end
+$var reg 1 XJ" pwr_ov_x86_of $end
+$var reg 1 hJ" pwr_so $end
+$var reg 1 xJ" pwr_cr_eq_x86_zf $end
+$var reg 1 *K" pwr_cr_gt_x86_pf $end
+$var reg 1 :K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[13] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 wC" int_fp $end
+$var reg 64 wI" int_fp $end
 $scope struct flags $end
-$var reg 1 )D" pwr_ca32_x86_af $end
-$var reg 1 9D" pwr_ca_x86_cf $end
-$var reg 1 ID" pwr_ov32_x86_df $end
-$var reg 1 YD" pwr_ov_x86_of $end
-$var reg 1 iD" pwr_so $end
-$var reg 1 yD" pwr_cr_eq_x86_zf $end
-$var reg 1 +E" pwr_cr_gt_x86_pf $end
-$var reg 1 ;E" pwr_cr_lt_x86_sf $end
+$var reg 1 )J" pwr_ca32_x86_af $end
+$var reg 1 9J" pwr_ca_x86_cf $end
+$var reg 1 IJ" pwr_ov32_x86_df $end
+$var reg 1 YJ" pwr_ov_x86_of $end
+$var reg 1 iJ" pwr_so $end
+$var reg 1 yJ" pwr_cr_eq_x86_zf $end
+$var reg 1 +K" pwr_cr_gt_x86_pf $end
+$var reg 1 ;K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[14] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 xC" int_fp $end
+$var reg 64 xI" int_fp $end
 $scope struct flags $end
-$var reg 1 *D" pwr_ca32_x86_af $end
-$var reg 1 :D" pwr_ca_x86_cf $end
-$var reg 1 JD" pwr_ov32_x86_df $end
-$var reg 1 ZD" pwr_ov_x86_of $end
-$var reg 1 jD" pwr_so $end
-$var reg 1 zD" pwr_cr_eq_x86_zf $end
-$var reg 1 ,E" pwr_cr_gt_x86_pf $end
-$var reg 1 <E" pwr_cr_lt_x86_sf $end
+$var reg 1 *J" pwr_ca32_x86_af $end
+$var reg 1 :J" pwr_ca_x86_cf $end
+$var reg 1 JJ" pwr_ov32_x86_df $end
+$var reg 1 ZJ" pwr_ov_x86_of $end
+$var reg 1 jJ" pwr_so $end
+$var reg 1 zJ" pwr_cr_eq_x86_zf $end
+$var reg 1 ,K" pwr_cr_gt_x86_pf $end
+$var reg 1 <K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct \[15] $end
 $scope struct unit_1_output_regs $end
-$var reg 64 yC" int_fp $end
+$var reg 64 yI" int_fp $end
 $scope struct flags $end
-$var reg 1 +D" pwr_ca32_x86_af $end
-$var reg 1 ;D" pwr_ca_x86_cf $end
-$var reg 1 KD" pwr_ov32_x86_df $end
-$var reg 1 [D" pwr_ov_x86_of $end
-$var reg 1 kD" pwr_so $end
-$var reg 1 {D" pwr_cr_eq_x86_zf $end
-$var reg 1 -E" pwr_cr_gt_x86_pf $end
-$var reg 1 =E" pwr_cr_lt_x86_sf $end
+$var reg 1 +J" pwr_ca32_x86_af $end
+$var reg 1 ;J" pwr_ca_x86_cf $end
+$var reg 1 KJ" pwr_ov32_x86_df $end
+$var reg 1 [J" pwr_ov_x86_of $end
+$var reg 1 kJ" pwr_so $end
+$var reg 1 {J" pwr_cr_eq_x86_zf $end
+$var reg 1 -K" pwr_cr_gt_x86_pf $end
+$var reg 1 =K" pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r0 $end
-$var wire 4 Mn addr $end
-$var wire 1 Nn en $end
-$var wire 1 On clk $end
+$var wire 4 kq addr $end
+$var wire 1 lq en $end
+$var wire 1 mq clk $end
 $scope struct data $end
-$var wire 64 Pn int_fp $end
+$var wire 64 nq int_fp $end
 $scope struct flags $end
-$var wire 1 Qn pwr_ca32_x86_af $end
-$var wire 1 Rn pwr_ca_x86_cf $end
-$var wire 1 Sn pwr_ov32_x86_df $end
-$var wire 1 Tn pwr_ov_x86_of $end
-$var wire 1 Un pwr_so $end
-$var wire 1 Vn pwr_cr_eq_x86_zf $end
-$var wire 1 Wn pwr_cr_gt_x86_pf $end
-$var wire 1 Xn pwr_cr_lt_x86_sf $end
+$var wire 1 oq pwr_ca32_x86_af $end
+$var wire 1 pq pwr_ca_x86_cf $end
+$var wire 1 qq pwr_ov32_x86_df $end
+$var wire 1 rq pwr_ov_x86_of $end
+$var wire 1 sq pwr_so $end
+$var wire 1 tq pwr_cr_eq_x86_zf $end
+$var wire 1 uq pwr_cr_gt_x86_pf $end
+$var wire 1 vq pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r1 $end
-$var wire 4 Yn addr $end
-$var wire 1 Zn en $end
-$var wire 1 [n clk $end
+$var wire 4 wq addr $end
+$var wire 1 xq en $end
+$var wire 1 yq clk $end
 $scope struct data $end
-$var wire 64 \n int_fp $end
+$var wire 64 zq int_fp $end
 $scope struct flags $end
-$var wire 1 ]n pwr_ca32_x86_af $end
-$var wire 1 ^n pwr_ca_x86_cf $end
-$var wire 1 _n pwr_ov32_x86_df $end
-$var wire 1 `n pwr_ov_x86_of $end
-$var wire 1 an pwr_so $end
-$var wire 1 bn pwr_cr_eq_x86_zf $end
-$var wire 1 cn pwr_cr_gt_x86_pf $end
-$var wire 1 dn pwr_cr_lt_x86_sf $end
+$var wire 1 {q pwr_ca32_x86_af $end
+$var wire 1 |q pwr_ca_x86_cf $end
+$var wire 1 }q pwr_ov32_x86_df $end
+$var wire 1 ~q pwr_ov_x86_of $end
+$var wire 1 !r pwr_so $end
+$var wire 1 "r pwr_cr_eq_x86_zf $end
+$var wire 1 #r pwr_cr_gt_x86_pf $end
+$var wire 1 $r pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct r2 $end
-$var wire 4 en addr $end
-$var wire 1 fn en $end
-$var wire 1 gn clk $end
+$var wire 4 %r addr $end
+$var wire 1 &r en $end
+$var wire 1 'r clk $end
 $scope struct data $end
-$var wire 64 hn int_fp $end
+$var wire 64 (r int_fp $end
 $scope struct flags $end
-$var wire 1 in pwr_ca32_x86_af $end
-$var wire 1 jn pwr_ca_x86_cf $end
-$var wire 1 kn pwr_ov32_x86_df $end
-$var wire 1 ln pwr_ov_x86_of $end
-$var wire 1 mn pwr_so $end
-$var wire 1 nn pwr_cr_eq_x86_zf $end
-$var wire 1 on pwr_cr_gt_x86_pf $end
-$var wire 1 pn pwr_cr_lt_x86_sf $end
+$var wire 1 )r pwr_ca32_x86_af $end
+$var wire 1 *r pwr_ca_x86_cf $end
+$var wire 1 +r pwr_ov32_x86_df $end
+$var wire 1 ,r pwr_ov_x86_of $end
+$var wire 1 -r pwr_so $end
+$var wire 1 .r pwr_cr_eq_x86_zf $end
+$var wire 1 /r pwr_cr_gt_x86_pf $end
+$var wire 1 0r pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct w3 $end
-$var wire 4 qn addr $end
-$var wire 1 rn en $end
-$var wire 1 sn clk $end
+$var wire 4 1r addr $end
+$var wire 1 2r en $end
+$var wire 1 3r clk $end
 $scope struct data $end
-$var wire 64 tn int_fp $end
+$var wire 64 4r int_fp $end
 $scope struct flags $end
-$var wire 1 un pwr_ca32_x86_af $end
-$var wire 1 vn pwr_ca_x86_cf $end
-$var wire 1 wn pwr_ov32_x86_df $end
-$var wire 1 xn pwr_ov_x86_of $end
-$var wire 1 yn pwr_so $end
-$var wire 1 zn pwr_cr_eq_x86_zf $end
-$var wire 1 {n pwr_cr_gt_x86_pf $end
-$var wire 1 |n pwr_cr_lt_x86_sf $end
+$var wire 1 5r pwr_ca32_x86_af $end
+$var wire 1 6r pwr_ca_x86_cf $end
+$var wire 1 7r pwr_ov32_x86_df $end
+$var wire 1 8r pwr_ov_x86_of $end
+$var wire 1 9r pwr_so $end
+$var wire 1 :r pwr_cr_eq_x86_zf $end
+$var wire 1 ;r pwr_cr_gt_x86_pf $end
+$var wire 1 <r pwr_cr_lt_x86_sf $end
 $upscope $end
 $upscope $end
 $scope struct mask $end
-$var wire 1 }n int_fp $end
+$var wire 1 =r int_fp $end
 $scope struct flags $end
-$var wire 1 ~n pwr_ca32_x86_af $end
-$var wire 1 !o pwr_ca_x86_cf $end
-$var wire 1 "o pwr_ov32_x86_df $end
-$var wire 1 #o pwr_ov_x86_of $end
-$var wire 1 $o pwr_so $end
-$var wire 1 %o pwr_cr_eq_x86_zf $end
-$var wire 1 &o pwr_cr_gt_x86_pf $end
-$var wire 1 'o pwr_cr_lt_x86_sf $end
+$var wire 1 >r pwr_ca32_x86_af $end
+$var wire 1 ?r pwr_ca_x86_cf $end
+$var wire 1 @r pwr_ov32_x86_df $end
+$var wire 1 Ar pwr_ov_x86_of $end
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@@ -24413,145 +25197,136 @@ $upscope $end
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@@ -24561,513 +25336,536 @@ $var wire 6 -!" \[0] $end
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@@ -25078,65 +25876,62 @@ $var wire 6 s#" \[0] $end
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@@ -25149,7 +25944,7 @@ $var wire 1 >$" pwr_cr_gt_x86_pf $end
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 $upscope $end
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@@ -25162,56 +25957,60 @@ $var wire 1 G$" pwr_cr_gt_x86_pf $end
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 $upscope $end
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@@ -25220,8 +26019,7 @@ $var wire 1 d$" src1_is_carry_in $end
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@@ -25232,136 +26030,145 @@ $var wire 6 i$" \[0] $end
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@@ -25378,40 +26185,44 @@ $var wire 6 L%" \[0] $end
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@@ -25458,20 +26269,20 @@ $upscope $end
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@@ -25488,111 +26299,113 @@ $var wire 6 -&" \[0] $end
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@@ -25605,7 +26418,7 @@ $var wire 1 e&" \[3] $end
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@@ -25617,99 +26430,113 @@ $var wire 6 h&" \[0] $end
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@@ -25722,7 +26549,7 @@ $var wire 1 E'" pwr_cr_gt_x86_pf $end
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@@ -25885,7 +26704,7 @@ $var wire 1 5(" \[3] $end
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@@ -25894,19 +26713,21 @@ $var wire 4 7(" value $end
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@@ -25918,91 +26739,113 @@ $var wire 6 A(" \[0] $end
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@@ -26015,199 +26858,186 @@ $var wire 1 |(" pwr_cr_gt_x86_pf $end
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 $scope struct flags $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $scope struct unit_1_free_regs_tracker $end
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 $scope struct \[0] $end
 $scope struct data $end
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 $upscope $end
 $upscope $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $upscope $end
 $scope module unit_free_regs_tracker_2 $end
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 $scope struct data $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $scope struct alloc_out $end
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 $scope struct data $end
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 $upscope $end
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 $upscope $end
 $upscope $end
 $scope struct allocated_reg $end
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-$var reg 1 Y1" \[6] $end
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 $upscope $end
 $scope struct firing_data $end
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 $upscope $end
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 $scope struct reduced_alloc_nums_0_2 $end
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 $upscope $end
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 $scope struct reduced_alloc_nums_2_4 $end
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 $upscope $end
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 $scope struct reduced_alloc_nums_0_4 $end
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 $upscope $end
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 $scope struct reduced_alloc_nums_4_6 $end
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 $upscope $end
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 $scope struct reduced_alloc_nums_6_8 $end
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 $upscope $end
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 $scope struct reduced_alloc_nums_4_8 $end
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 $upscope $end
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 $scope struct reduced_alloc_nums_0_8 $end
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 $upscope $end
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-$var wire 1 {1" reduced_count_overflowed_8_10 $end
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 $scope struct reduced_alloc_nums_8_10 $end
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 $upscope $end
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+$var wire 1 H7" reduced_count_overflowed_10_12 $end
 $scope struct reduced_alloc_nums_10_12 $end
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 $upscope $end
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+$var wire 1 J7" reduced_count_8_12 $end
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 $scope struct reduced_alloc_nums_8_12 $end
-$var wire 2 $2" \[0] $end
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 $upscope $end
-$var wire 1 %2" reduced_count_12_14 $end
-$var wire 1 &2" reduced_count_overflowed_12_14 $end
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 0!
 1"
 sHdlSome\x20(1) #
@@ -29318,69 +31346,69 @@ sHdlSome\x20(1) )
 sHdlNone\x20(0) *
 b0 +
 b0 ,
-b1001 -
-b1101000101011001111000 .
-0/
-sDupLow32\x20(1) 0
+b1111000 -
+b100100011010001010110 .
+sDupLow32\x20(1) /
+00
 01
 02
 03
-04
-s0 5
-b1 6
-b0 7
-sHdlSome\x20(1) 8
-sHdlNone\x20(0) 9
+s0 4
+b1 5
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+sHdlSome\x20(1) 7
+sHdlNone\x20(0) 8
+b0 9
 b0 :
-b0 ;
-b1001 <
-b1101000101011001111000 =
+b10010001101000101011001111000 ;
+sDupLow32\x20(1) <
+0=
 0>
-sDupLow32\x20(1) ?
+0?
 0@
-0A
-0B
-0C
-s0 D
-b1 E
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 b0 F
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-0[
-sDupLow32\x20(1) \
-0]
-0^
-0_
+b0 G
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+sPhantomConst(\"0..8\") J
+b10 K
+sPhantomConst(\"0..8\") L
+b1 M
+sPhantomConst(\"0..8\") N
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+sPhantomConst(\"0..8\") P
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+0S
+1T
+0U
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+sHdlSome\x20(1) Z
+sHdlNone\x20(0) [
+b0 \
+b0 ]
+b10010001101000101011001111000 ^
+sDupLow32\x20(1) _
 0`
-s0 a
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-sHdlNone\x20(0) e
+0a
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-0j
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+sHdlSome\x20(1) g
+sHdlNone\x20(0) h
+b0 i
+b1000110100010101100111100000000000 j
+sZeroExt16\x20(4) k
 0l
 0m
 0n
@@ -29392,194 +31420,194 @@ sHdlSome\x20(1) s
 sHdlNone\x20(0) t
 b0 u
 b0 v
-b1001 w
-b1101000101011001111000 x
-0y
-sDupLow32\x20(1) z
-sU64\x20(0) {
-s0 |
-b1 }
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-sHdlSome\x20(1) !"
-sHdlNone\x20(0) ""
-b0 #"
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-b1101000101011001111000 &"
-0'"
-sDupLow32\x20(1) ("
-sU64\x20(0) )"
-s0 *"
-b1 +"
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-sHdlSome\x20(1) -"
-sHdlNone\x20(0) ."
+b1111000 w
+sHdlNone\x20(0) x
+b101011 y
+0z
+sHdlNone\x20(0) {
+b11010 |
+b100100 }
+0~
+sFull64\x20(0) !"
+sFunnelShift2x32Bit\x20(2) ""
+s0 #"
+b1 $"
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+sHdlSome\x20(1) &"
+sHdlNone\x20(0) '"
+b0 ("
+b0 )"
+b10010001101000101011001111000 *"
+sDupLow32\x20(1) +"
+sU64\x20(0) ,"
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+b1 ."
 b0 /"
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-b1101000101011001111000 2"
-03"
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-06"
-07"
-08"
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-s0 :"
-b1 ;"
+sHdlSome\x20(1) 0"
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+sHdlSome\x20(1) 9"
+sHdlNone\x20(0) :"
+b0 ;"
 b0 <"
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-b0 ?"
-b0 @"
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+b100100011010001010110 >"
+1?"
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 b0 ["
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-b1101000101011001111000 ]"
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+sHdlSome\x20(1) \"
+sHdlNone\x20(0) ]"
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-0/#
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 041
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 061
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 0f3
 b0 g3
 b0 h3
 1i3
 1j3
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@@ -31080,167 +33108,167 @@ b0 o3
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 1q3
 0r3
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 0T4
 0U4
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 s0 W4
 b0 X4
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 b0 Z4
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 0]4
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 0-5
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@@ -31842,175 +33870,175 @@ b0 t;
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 b0 g=
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@@ -32020,211 +34048,211 @@ b0 o=
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-0F>
-s0 G>
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 0:?
 0;?
 0<?
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 0>?
 0??
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 0G?
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@@ -33961,8 +35989,8 @@ b0 IR
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@@ -33970,22 +35998,22 @@ b0 RR
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@@ -35741,150 +37769,150 @@ s0 He
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 0Ji
 0Ki
@@ -36123,112 +38151,112 @@ s0 Ni
 b0 Oi
 b0 Pi
 b0 Qi
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-1QW
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-0O,
-0V,
-b1000010010000 ..
-0X3
+09&
+0@&
+0I&
+0Z(
+0;,
+0B,
+0I,
+0P,
+0W,
+0^,
+b1000010010000 3.
 0_3
 0f3
 0m3
 0t3
 0{3
-b1000010010100 S5
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+0$4
+b1000010010100 W5
+0>:
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 0(@
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-0^m
-0bm
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-0jm
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-0"n
-0.n
-0:n
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-0[n
-0gn
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-0O*"
-0q/"
-0K1"
-062"
+0I@
+0U@
+0a@
+0m@
+0/\
+0la
+0Oc
+0:d
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+0Em
+0fp
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+0rp
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+04q
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+0'r
+03r
+0S/"
+025"
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+0^7"
 #19500000
 1!
-1e$
-1j$
-1o$
-1t$
-1{$
+1s$
+1x$
+1}$
 1$%
-1)%
-1.%
-13%
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+1+%
+12%
+17%
+1<%
 1A%
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 1^%
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 1+&
 12&
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+1Z(
+1;,
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 1_3
 1f3
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 #20000000
diff --git a/crates/cpu/tests/simple_power_isa_decoder/expected/decode_one_insn.vcd b/crates/cpu/tests/simple_power_isa_decoder/expected/decode_one_insn.vcd
index 243c00e..c5f2870 100644
--- a/crates/cpu/tests/simple_power_isa_decoder/expected/decode_one_insn.vcd
+++ b/crates/cpu/tests/simple_power_isa_decoder/expected/decode_one_insn.vcd
@@ -37,187 +37,189 @@ $var wire 8 ( \[0] $end
 $var wire 8 ) \[1] $end
 $var wire 8 * \[2] $end
 $upscope $end
-$var wire 25 + imm_low $end
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-$scope struct _phantom $end
+$var wire 26 + imm $end
 $upscope $end
+$var string 1 , output_integer_mode $end
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-$var string 1 - output_integer_mode $end
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-$var wire 1 . invert_src0 $end
-$var wire 1 / src1_is_carry_in $end
-$var wire 1 0 invert_carry_in $end
-$var wire 1 1 add_pc $end
+$var wire 1 - invert_src0 $end
+$var wire 1 . src1_is_carry_in $end
+$var wire 1 / invert_carry_in $end
+$var wire 1 0 add_pc $end
 $upscope $end
 $scope struct AddSubI $end
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 $scope struct common $end
-$var string 0 2 prefix_pad $end
+$var string 0 1 prefix_pad $end
 $scope struct dest $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 3 value $end
+$var wire 8 2 value $end
 $upscope $end
 $scope struct \[1] $end
-$var wire 8 4 value $end
+$var wire 8 3 value $end
 $upscope $end
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 $var string 1 5 \$tag $end
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-$var wire 25 : imm_low $end
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+$var wire 34 8 imm $end
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+$var string 1 9 output_integer_mode $end
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-$var string 1 < output_integer_mode $end
-$upscope $end
-$var wire 1 = invert_src0 $end
-$var wire 1 > src1_is_carry_in $end
-$var wire 1 ? invert_carry_in $end
-$var wire 1 @ add_pc $end
+$var wire 1 : invert_src0 $end
+$var wire 1 ; src1_is_carry_in $end
+$var wire 1 < invert_carry_in $end
+$var wire 1 = add_pc $end
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-$var string 0 A prefix_pad $end
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-$var wire 8 B value $end
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-$var wire 8 C value $end
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-$var string 1 D \$tag $end
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-$var string 1 E \$tag $end
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-$var wire 8 F \[0] $end
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+$upscope $end
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+$var string 1 G range $end
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+$scope struct src1_start $end
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-$var wire 1 K \[0] $end
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-$var string 0 O prefix_pad $end
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-$var wire 8 P value $end
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-$var string 0 ^ prefix_pad $end
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@@ -230,7 +232,7 @@ $var wire 1 l \[3] $end
 $upscope $end
 $upscope $end
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-$scope struct Compare $end
+$scope struct ShiftRotate $end
 $scope struct alu_common $end
 $scope struct common $end
 $var string 0 m prefix_pad $end
@@ -261,221 +263,241 @@ $var wire 8 r \[0] $end
 $var wire 8 s \[1] $end
 $var wire 8 t \[2] $end
 $upscope $end
-$var wire 25 u imm_low $end
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+$upscope $end
+$var wire 1 w shift_rotate_right $end
+$scope struct dest_logic_op $end
+$var string 1 x \$tag $end
+$scope struct HdlSome $end
+$var wire 6 y rotated_output_start $end
+$var wire 6 z rotated_output_len $end
+$var wire 1 { fallback_is_src2 $end
 $upscope $end
 $upscope $end
-$var string 1 w output_integer_mode $end
 $upscope $end
-$var string 1 x compare_mode $end
+$upscope $end
+$var string 1 | output_integer_mode $end
+$upscope $end
+$var string 1 } mode $end
+$upscope $end
+$scope struct Compare $end
+$scope struct alu_common $end
+$scope struct common $end
+$var string 0 ~ prefix_pad $end
+$scope struct dest $end
+$scope struct normal_regs $end
+$scope struct \[0] $end
+$var wire 8 !" value $end
+$upscope $end
+$scope struct \[1] $end
+$var wire 8 "" value $end
+$upscope $end
+$upscope $end
+$scope struct flag_regs $end
+$scope struct \[0] $end
+$var string 1 #" \$tag $end
+$scope struct HdlSome $end
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+$var string 1 $" \$tag $end
+$scope struct HdlSome $end
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+$upscope $end
+$upscope $end
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+$var wire 8 %" \[0] $end
+$var wire 8 &" \[1] $end
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+$var wire 34 '" imm $end
+$upscope $end
+$var string 1 (" output_integer_mode $end
+$upscope $end
+$var string 1 )" compare_mode $end
 $upscope $end
 $scope struct CompareI $end
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 $scope struct common $end
-$var string 0 y prefix_pad $end
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 $scope struct dest $end
 $scope struct normal_regs $end
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-$var wire 8 z value $end
+$var wire 8 +" value $end
 $upscope $end
 $scope struct \[1] $end
-$var wire 8 { value $end
+$var wire 8 ," value $end
 $upscope $end
 $upscope $end
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-$var string 1 | \$tag $end
+$var string 1 -" \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
-$var string 1 } \$tag $end
+$var string 1 ." \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct src $end
-$var wire 8 ~ \[0] $end
-$var wire 8 !" \[1] $end
-$var wire 8 "" \[2] $end
+$var wire 8 /" \[0] $end
 $upscope $end
-$var wire 25 #" imm_low $end
-$var wire 1 $" imm_sign $end
-$scope struct _phantom $end
+$var wire 34 0" imm $end
 $upscope $end
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 $upscope $end
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-$upscope $end
-$var string 1 &" compare_mode $end
+$var string 1 2" compare_mode $end
 $upscope $end
 $scope struct Branch $end
 $scope struct common $end
-$var string 0 '" prefix_pad $end
+$var string 0 3" prefix_pad $end
 $scope struct dest $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 (" value $end
+$var wire 8 4" value $end
 $upscope $end
 $scope struct \[1] $end
-$var wire 8 )" value $end
+$var wire 8 5" value $end
 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 *" \$tag $end
+$var string 1 6" \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
-$var string 1 +" \$tag $end
+$var string 1 7" \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct src $end
-$var wire 8 ," \[0] $end
-$var wire 8 -" \[1] $end
-$var wire 8 ." \[2] $end
+$var wire 8 8" \[0] $end
+$var wire 8 9" \[1] $end
+$var wire 8 :" \[2] $end
 $upscope $end
-$var wire 25 /" imm_low $end
-$var wire 1 0" imm_sign $end
-$scope struct _phantom $end
+$var wire 26 ;" imm $end
 $upscope $end
-$upscope $end
-$var wire 1 1" invert_src0_cond $end
-$var string 1 2" src0_cond_mode $end
-$var wire 1 3" invert_src2_eq_zero $end
-$var wire 1 4" pc_relative $end
-$var wire 1 5" is_call $end
-$var wire 1 6" is_ret $end
+$var wire 1 <" invert_src0_cond $end
+$var string 1 =" src0_cond_mode $end
+$var wire 1 >" invert_src2_eq_zero $end
+$var wire 1 ?" pc_relative $end
+$var wire 1 @" is_call $end
+$var wire 1 A" is_ret $end
 $upscope $end
 $scope struct BranchI $end
 $scope struct common $end
-$var string 0 7" prefix_pad $end
+$var string 0 B" prefix_pad $end
 $scope struct dest $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 8" value $end
+$var wire 8 C" value $end
 $upscope $end
 $scope struct \[1] $end
-$var wire 8 9" value $end
+$var wire 8 D" value $end
 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 :" \$tag $end
+$var string 1 E" \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
-$var string 1 ;" \$tag $end
+$var string 1 F" \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct src $end
-$var wire 8 <" \[0] $end
-$var wire 8 =" \[1] $end
-$var wire 8 >" \[2] $end
+$var wire 8 G" \[0] $end
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 $upscope $end
-$var wire 25 ?" imm_low $end
-$var wire 1 @" imm_sign $end
-$scope struct _phantom $end
+$var wire 34 I" imm $end
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+$var wire 1 J" invert_src0_cond $end
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+$var wire 1 N" is_call $end
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+$upscope $end
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+$var wire 8 Q" value $end
+$upscope $end
+$scope struct \[1] $end
+$var wire 8 R" value $end
 $upscope $end
 $upscope $end
-$var wire 1 A" invert_src0_cond $end
-$var string 1 B" src0_cond_mode $end
-$var wire 1 C" invert_src2_eq_zero $end
-$var wire 1 D" pc_relative $end
-$var wire 1 E" is_call $end
-$var wire 1 F" is_ret $end
+$scope struct flag_regs $end
+$scope struct \[0] $end
+$var string 1 S" \$tag $end
+$scope struct HdlSome $end
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+$upscope $end
+$scope struct \[1] $end
+$var string 1 T" \$tag $end
+$scope struct HdlSome $end
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+$upscope $end
+$upscope $end
+$upscope $end
+$scope struct src $end
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+$var string 1 U" imm $end
+$upscope $end
 $upscope $end
 $upscope $end
 $scope struct TransformedMove $end
 $scope struct common $end
-$var wire 4 G" prefix_pad $end
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 $scope struct dest $end
 $scope struct normal_regs $end
 $scope struct \[0] $end
-$var wire 8 H" value $end
+$var wire 8 W" value $end
 $upscope $end
 $scope struct \[1] $end
-$var wire 8 I" value $end
+$var wire 8 X" value $end
 $upscope $end
 $upscope $end
 $scope struct flag_regs $end
 $scope struct \[0] $end
-$var string 1 J" \$tag $end
+$var string 1 Y" \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct \[1] $end
-$var string 1 K" \$tag $end
+$var string 1 Z" \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope struct src $end
-$var wire 8 L" \[0] $end
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-$upscope $end
-$var wire 25 O" imm_low $end
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-$scope struct _phantom $end
+$var wire 8 [" \[0] $end
 $upscope $end
+$var wire 34 \" imm $end
 $upscope $end
 $upscope $end
 $scope struct LoadStore $end
-$var string 1 Q" \$tag $end
+$var string 1 ]" \$tag $end
 $scope struct Load $end
 $scope struct load_store_common $end
 $scope struct common $end
-$var wire 3 R" prefix_pad $end
-$scope struct dest $end
-$scope struct normal_regs $end
-$scope struct \[0] $end
-$var wire 8 S" value $end
-$upscope $end
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-$upscope $end
-$upscope $end
-$scope struct flag_regs $end
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-$upscope $end
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-$scope struct src $end
-$var wire 8 W" \[0] $end
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-$upscope $end
-$var wire 25 Z" imm_low $end
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-$var string 1 \" width $end
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-$scope struct load_store_common $end
-$scope struct common $end
 $var wire 3 ^" prefix_pad $end
 $scope struct dest $end
 $scope struct normal_regs $end
@@ -501,329 +523,334 @@ $upscope $end
 $upscope $end
 $scope struct src $end
 $var wire 8 c" \[0] $end
-$var wire 8 d" \[1] $end
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 $upscope $end
-$var wire 25 f" imm_low $end
-$var wire 1 g" imm_sign $end
-$scope struct _phantom $end
+$var wire 34 d" imm $end
+$upscope $end
+$var string 1 e" width $end
+$var string 1 f" conversion $end
 $upscope $end
 $upscope $end
-$var string 1 h" width $end
-$var string 1 i" conversion $end
-$upscope $end
-$upscope $end
-$upscope $end
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@@ -851,658 +878,694 @@ $upscope $end
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@@ -1526,1670 +1589,1819 @@ $upscope $end
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@@ -3215,21 +3427,30 @@ $upscope $end
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 $upscope $end
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 $scope struct common $end
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@@ -3259,21 +3480,16 @@ $var wire 8 G, \[0] $end
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@@ -3302,639 +3518,659 @@ $upscope $end
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@@ -3961,852 +4197,939 @@ $upscope $end
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@@ -4832,70 +5155,69 @@ $upscope $end
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@@ -4924,631 +5246,656 @@ $upscope $end
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@@ -5575,244 +5922,262 @@ $upscope $end
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@@ -5838,2291 +6203,2638 @@ $upscope $end
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 $scope struct power_isa_cr_reg_11 $end
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 $scope struct power_isa_cr_reg_12 $end
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 $scope struct power_isa_cr_reg_13 $end
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-$var wire 8 69 value $end
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 $var wire 8 X9 value $end
 $upscope $end
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 $var wire 8 \9 value $end
 $upscope $end
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-$scope struct power_isa_gpr_or_zero_reg_6 $end
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 $var wire 8 `9 value $end
 $upscope $end
-$var wire 18 a9 plhz_d0 $end
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+$var wire 8 a9 value $end
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 $var wire 8 f9 value $end
 $upscope $end
-$var wire 5 g9 lhzx_RB $end
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 $var wire 8 j9 value $end
 $upscope $end
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-$scope struct power_isa_gpr_or_zero_reg_9 $end
-$var wire 8 n9 value $end
+$scope struct power_isa_cr_reg_32 $end
+$var wire 8 k9 value $end
 $upscope $end
-$var wire 5 o9 lhzux_RB $end
-$var wire 5 p9 lhzux_RA $end
-$var wire 5 q9 lhzux_RT $end
-$scope struct power_isa_gpr_or_zero_reg_10 $end
-$var wire 8 r9 value $end
+$scope struct power_isa_cr_reg_33 $end
+$var wire 8 l9 value $end
 $upscope $end
-$var wire 16 s9 lha_D $end
-$var wire 5 t9 lha_RA $end
-$var wire 5 u9 lha_RT $end
-$scope struct power_isa_gpr_or_zero_reg_11 $end
-$var wire 8 v9 value $end
+$scope struct power_isa_cr_reg_34 $end
+$var wire 8 m9 value $end
 $upscope $end
-$var wire 18 w9 plha_d0 $end
-$var wire 1 x9 plha_R $end
-$var wire 16 y9 plha_d1 $end
-$var wire 5 z9 plha_RA $end
-$var wire 5 {9 plha_RT $end
-$scope struct power_isa_gpr_or_zero_reg_12 $end
-$var wire 8 |9 value $end
+$var wire 3 n9 XL_BFA_3 $end
+$var wire 3 o9 XL_BF_3 $end
+$scope struct power_isa_cr_reg_35 $end
+$var wire 8 p9 value $end
 $upscope $end
-$var wire 5 }9 lhax_RB $end
-$var wire 5 ~9 lhax_RA $end
-$var wire 5 !: lhax_RT $end
-$scope struct power_isa_gpr_or_zero_reg_13 $end
+$scope struct power_isa_cr_reg_36 $end
+$var wire 8 q9 value $end
+$upscope $end
+$var wire 16 r9 D_D_16 $end
+$var wire 5 s9 D_RA_5 $end
+$var wire 5 t9 D_RT_5 $end
+$scope struct power_isa_gpr_or_zero_reg $end
+$var wire 8 u9 value $end
+$upscope $end
+$var wire 18 v9 MLS_D_d0_18 $end
+$var wire 1 w9 MLS_D_R_1 $end
+$var wire 16 x9 MLS_D_d1_16 $end
+$var wire 5 y9 MLS_D_RA_5 $end
+$var wire 5 z9 MLS_D_RT_5 $end
+$scope struct power_isa_gpr_or_zero_reg_2 $end
+$var wire 8 {9 value $end
+$upscope $end
+$var wire 5 |9 X_RB_5 $end
+$var wire 5 }9 X_RA_5 $end
+$var wire 5 ~9 X_RT_5 $end
+$scope struct power_isa_gpr_or_zero_reg_3 $end
+$var wire 8 !: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_4 $end
 $var wire 8 ": value $end
 $upscope $end
-$var wire 16 #: lhau_D $end
-$var wire 5 $: lhau_RA $end
-$var wire 5 %: lhau_RT $end
-$scope struct power_isa_gpr_or_zero_reg_14 $end
+$scope struct power_isa_gpr_or_zero_reg_5 $end
+$var wire 8 #: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_6 $end
+$var wire 8 $: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_7 $end
+$var wire 8 %: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_8 $end
 $var wire 8 &: value $end
 $upscope $end
-$var wire 5 ': lhaux_RB $end
-$var wire 5 (: lhaux_RA $end
-$var wire 5 ): lhaux_RT $end
-$scope struct power_isa_gpr_or_zero_reg_15 $end
+$scope struct power_isa_gpr_or_zero_reg_9 $end
+$var wire 8 ': value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_10 $end
+$var wire 8 (: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_11 $end
+$var wire 8 ): value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_12 $end
 $var wire 8 *: value $end
 $upscope $end
-$var wire 16 +: lwz_D $end
-$var wire 5 ,: lwz_RA $end
-$var wire 5 -: lwz_RT $end
+$scope struct power_isa_gpr_or_zero_reg_13 $end
+$var wire 8 +: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_14 $end
+$var wire 8 ,: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_15 $end
+$var wire 8 -: value $end
+$upscope $end
 $scope struct power_isa_gpr_or_zero_reg_16 $end
 $var wire 8 .: value $end
 $upscope $end
-$var wire 18 /: plwz_d0 $end
-$var wire 1 0: plwz_R $end
-$var wire 16 1: plwz_d1 $end
-$var wire 5 2: plwz_RA $end
-$var wire 5 3: plwz_RT $end
 $scope struct power_isa_gpr_or_zero_reg_17 $end
-$var wire 8 4: value $end
+$var wire 8 /: value $end
 $upscope $end
-$var wire 5 5: lwzx_RB $end
-$var wire 5 6: lwzx_RA $end
-$var wire 5 7: lwzx_RT $end
 $scope struct power_isa_gpr_or_zero_reg_18 $end
-$var wire 8 8: value $end
+$var wire 8 0: value $end
 $upscope $end
-$var wire 16 9: lwzu_D $end
-$var wire 5 :: lwzu_RA $end
-$var wire 5 ;: lwzu_RT $end
 $scope struct power_isa_gpr_or_zero_reg_19 $end
+$var wire 8 1: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_20 $end
+$var wire 8 2: value $end
+$upscope $end
+$var wire 14 3: DS_DS_14 $end
+$var wire 5 4: DS_RA_5 $end
+$var wire 5 5: DS_RT_5 $end
+$scope struct power_isa_gpr_or_zero_reg_21 $end
+$var wire 8 6: value $end
+$upscope $end
+$var wire 18 7: \8LS_D_d0_18 $end
+$var wire 1 8: \8LS_D_R_1 $end
+$var wire 16 9: \8LS_D_d1_16 $end
+$var wire 5 :: \8LS_D_RA_5 $end
+$var wire 5 ;: \8LS_D_RT_5 $end
+$scope struct power_isa_gpr_or_zero_reg_22 $end
 $var wire 8 <: value $end
 $upscope $end
-$var wire 5 =: lwzux_RB $end
-$var wire 5 >: lwzux_RA $end
-$var wire 5 ?: lwzux_RT $end
-$scope struct power_isa_gpr_or_zero_reg_20 $end
+$scope struct power_isa_gpr_or_zero_reg_23 $end
+$var wire 8 =: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_24 $end
+$var wire 8 >: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_25 $end
+$var wire 8 ?: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_26 $end
 $var wire 8 @: value $end
 $upscope $end
-$var wire 14 A: lwa_DS $end
-$var wire 5 B: lwa_RA $end
-$var wire 5 C: lwa_RT $end
-$scope struct power_isa_gpr_or_zero_reg_21 $end
-$var wire 8 D: value $end
+$scope struct power_isa_gpr_or_zero_reg_27 $end
+$var wire 8 A: value $end
 $upscope $end
-$var wire 18 E: plwa_d0 $end
-$var wire 1 F: plwa_R $end
-$var wire 16 G: plwa_d1 $end
-$var wire 5 H: plwa_RA $end
-$var wire 5 I: plwa_RT $end
-$scope struct power_isa_gpr_or_zero_reg_22 $end
+$scope struct power_isa_gpr_or_zero_reg_28 $end
+$var wire 8 B: value $end
+$upscope $end
+$scope struct power_isa_gpr_or_zero_reg_29 $end
+$var wire 8 C: value $end
+$upscope $end
+$var wire 5 D: D_RS_5 $end
+$scope struct power_isa_gpr_or_zero_reg_30 $end
+$var wire 8 E: value $end
+$upscope $end
+$var wire 5 F: MLS_D_RS_5 $end
+$scope struct power_isa_gpr_or_zero_reg_31 $end
+$var wire 8 G: value $end
+$upscope $end
+$var wire 5 H: X_RS_5 $end
+$scope struct power_isa_gpr_or_zero_reg_32 $end
+$var wire 8 I: value $end
+$upscope $end
+$scope struct stbu_ea_reg $end
 $var wire 8 J: value $end
 $upscope $end
-$var wire 5 K: lwax_RB $end
-$var wire 5 L: lwax_RA $end
-$var wire 5 M: lwax_RT $end
-$scope struct power_isa_gpr_or_zero_reg_23 $end
-$var wire 8 N: value $end
-$upscope $end
-$var wire 5 O: lwaux_RB $end
-$var wire 5 P: lwaux_RA $end
-$var wire 5 Q: lwaux_RT $end
-$scope struct power_isa_gpr_or_zero_reg_24 $end
-$var wire 8 R: value $end
-$upscope $end
-$var wire 14 S: ld_DS $end
-$var wire 5 T: ld_RA $end
-$var wire 5 U: ld_RT $end
-$scope struct power_isa_gpr_or_zero_reg_25 $end
-$var wire 8 V: value $end
-$upscope $end
-$var wire 18 W: pld_d0 $end
-$var wire 1 X: pld_R $end
-$var wire 16 Y: pld_d1 $end
-$var wire 5 Z: pld_RA $end
-$var wire 5 [: pld_RT $end
-$scope struct power_isa_gpr_or_zero_reg_26 $end
-$var wire 8 \: value $end
-$upscope $end
-$var wire 5 ]: ldx_RB $end
-$var wire 5 ^: ldx_RA $end
-$var wire 5 _: ldx_RT $end
-$scope struct power_isa_gpr_or_zero_reg_27 $end
-$var wire 8 `: value $end
-$upscope $end
-$var wire 14 a: ldu_DS $end
-$var wire 5 b: ldu_RA $end
-$var wire 5 c: ldu_RT $end
-$scope struct power_isa_gpr_or_zero_reg_28 $end
-$var wire 8 d: value $end
-$upscope $end
-$var wire 5 e: ldux_RB $end
-$var wire 5 f: ldux_RA $end
-$var wire 5 g: ldux_RT $end
-$scope struct power_isa_gpr_or_zero_reg_29 $end
-$var wire 8 h: value $end
-$upscope $end
-$var wire 16 i: stb_D $end
-$var wire 5 j: stb_RA $end
-$var wire 5 k: stb_RS $end
-$scope struct power_isa_gpr_or_zero_reg_30 $end
-$var wire 8 l: value $end
-$upscope $end
-$var wire 18 m: pstb_d0 $end
-$var wire 1 n: pstb_R $end
-$var wire 16 o: pstb_d1 $end
-$var wire 5 p: pstb_RA $end
-$var wire 5 q: pstb_RS $end
-$scope struct power_isa_gpr_or_zero_reg_31 $end
-$var wire 8 r: value $end
-$upscope $end
-$var wire 5 s: stbx_RB $end
-$var wire 5 t: stbx_RA $end
-$var wire 5 u: stbx_RS $end
-$scope struct power_isa_gpr_or_zero_reg_32 $end
-$var wire 8 v: value $end
-$upscope $end
-$var wire 16 w: stbu_D $end
-$var wire 5 x: stbu_RA $end
-$var wire 5 y: stbu_RS $end
-$scope struct stbu_ea_reg $end
-$var wire 8 z: value $end
-$upscope $end
 $scope struct power_isa_gpr_or_zero_reg_33 $end
-$var wire 8 {: value $end
+$var wire 8 K: value $end
 $upscope $end
-$var wire 5 |: stbux_RB $end
-$var wire 5 }: stbux_RA $end
-$var wire 5 ~: stbux_RS $end
 $scope struct stbux_ea_reg $end
-$var wire 8 !; value $end
+$var wire 8 L: value $end
 $upscope $end
 $scope struct power_isa_gpr_or_zero_reg_34 $end
-$var wire 8 "; value $end
+$var wire 8 M: value $end
 $upscope $end
-$var wire 16 #; sth_D $end
-$var wire 5 $; sth_RA $end
-$var wire 5 %; sth_RS $end
 $scope struct power_isa_gpr_or_zero_reg_35 $end
-$var wire 8 &; value $end
+$var wire 8 N: value $end
 $upscope $end
-$var wire 18 '; psth_d0 $end
-$var wire 1 (; psth_R $end
-$var wire 16 ); psth_d1 $end
-$var wire 5 *; psth_RA $end
-$var wire 5 +; psth_RS $end
 $scope struct power_isa_gpr_or_zero_reg_36 $end
-$var wire 8 ,; value $end
+$var wire 8 O: value $end
 $upscope $end
-$var wire 5 -; sthx_RB $end
-$var wire 5 .; sthx_RA $end
-$var wire 5 /; sthx_RS $end
 $scope struct power_isa_gpr_or_zero_reg_37 $end
-$var wire 8 0; value $end
+$var wire 8 P: value $end
 $upscope $end
-$var wire 16 1; sthu_D $end
-$var wire 5 2; sthu_RA $end
-$var wire 5 3; sthu_RS $end
 $scope struct sthu_ea_reg $end
-$var wire 8 4; value $end
+$var wire 8 Q: value $end
 $upscope $end
 $scope struct power_isa_gpr_or_zero_reg_38 $end
-$var wire 8 5; value $end
+$var wire 8 R: value $end
 $upscope $end
-$var wire 5 6; sthux_RB $end
-$var wire 5 7; sthux_RA $end
-$var wire 5 8; sthux_RS $end
 $scope struct sthux_ea_reg $end
-$var wire 8 9; value $end
+$var wire 8 S: value $end
 $upscope $end
 $scope struct power_isa_gpr_or_zero_reg_39 $end
-$var wire 8 :; value $end
+$var wire 8 T: value $end
 $upscope $end
-$var wire 16 ;; stw_D $end
-$var wire 5 <; stw_RA $end
-$var wire 5 =; stw_RS $end
 $scope struct power_isa_gpr_or_zero_reg_40 $end
-$var wire 8 >; value $end
+$var wire 8 U: value $end
 $upscope $end
-$var wire 18 ?; pstw_d0 $end
-$var wire 1 @; pstw_R $end
-$var wire 16 A; pstw_d1 $end
-$var wire 5 B; pstw_RA $end
-$var wire 5 C; pstw_RS $end
 $scope struct power_isa_gpr_or_zero_reg_41 $end
-$var wire 8 D; value $end
+$var wire 8 V: value $end
 $upscope $end
-$var wire 5 E; stwx_RB $end
-$var wire 5 F; stwx_RA $end
-$var wire 5 G; stwx_RS $end
 $scope struct power_isa_gpr_or_zero_reg_42 $end
-$var wire 8 H; value $end
+$var wire 8 W: value $end
 $upscope $end
-$var wire 16 I; stwu_D $end
-$var wire 5 J; stwu_RA $end
-$var wire 5 K; stwu_RS $end
 $scope struct stwu_ea_reg $end
-$var wire 8 L; value $end
+$var wire 8 X: value $end
 $upscope $end
 $scope struct power_isa_gpr_or_zero_reg_43 $end
-$var wire 8 M; value $end
+$var wire 8 Y: value $end
 $upscope $end
-$var wire 5 N; stwux_RB $end
-$var wire 5 O; stwux_RA $end
-$var wire 5 P; stwux_RS $end
 $scope struct stwux_ea_reg $end
-$var wire 8 Q; value $end
+$var wire 8 Z: value $end
 $upscope $end
 $scope struct power_isa_gpr_or_zero_reg_44 $end
-$var wire 8 R; value $end
+$var wire 8 [: value $end
 $upscope $end
-$var wire 14 S; std_DS $end
-$var wire 5 T; std_RA $end
-$var wire 5 U; std_RS $end
+$var wire 5 \: DS_RS_5 $end
 $scope struct power_isa_gpr_or_zero_reg_45 $end
-$var wire 8 V; value $end
+$var wire 8 ]: value $end
 $upscope $end
-$var wire 18 W; pstd_d0 $end
-$var wire 1 X; pstd_R $end
-$var wire 16 Y; pstd_d1 $end
-$var wire 5 Z; pstd_RA $end
-$var wire 5 [; pstd_RS $end
+$var wire 5 ^: \8LS_D_RS_5 $end
 $scope struct power_isa_gpr_or_zero_reg_46 $end
-$var wire 8 \; value $end
+$var wire 8 _: value $end
 $upscope $end
-$var wire 5 ]; stdx_RB $end
-$var wire 5 ^; stdx_RA $end
-$var wire 5 _; stdx_RS $end
 $scope struct power_isa_gpr_or_zero_reg_47 $end
-$var wire 8 `; value $end
+$var wire 8 `: value $end
 $upscope $end
-$var wire 14 a; stdu_DS $end
-$var wire 5 b; stdu_RA $end
-$var wire 5 c; stdu_RS $end
 $scope struct stdu_ea_reg $end
-$var wire 8 d; value $end
+$var wire 8 a: value $end
 $upscope $end
 $scope struct power_isa_gpr_or_zero_reg_48 $end
-$var wire 8 e; value $end
+$var wire 8 b: value $end
 $upscope $end
-$var wire 5 f; stdux_RB $end
-$var wire 5 g; stdux_RA $end
-$var wire 5 h; stdux_RS $end
 $scope struct stdux_ea_reg $end
-$var wire 8 i; value $end
+$var wire 8 c: value $end
 $upscope $end
 $scope struct power_isa_gpr_or_zero_reg_49 $end
-$var wire 8 j; value $end
+$var wire 8 d: value $end
 $upscope $end
-$var wire 16 k; addi_SI $end
-$var wire 5 l; addi_RA $end
-$var wire 5 m; addi_RT $end
+$var wire 16 e: D_SI_16 $end
 $scope struct power_isa_gpr_or_zero_reg_50 $end
-$var wire 8 n; value $end
+$var wire 8 f: value $end
 $upscope $end
-$var wire 18 o; paddi_si0 $end
-$var wire 1 p; paddi_R $end
-$var wire 16 q; paddi_si1 $end
-$var wire 5 r; paddi_RA $end
-$var wire 5 s; paddi_RT $end
+$var wire 18 g: MLS_D_si0_18 $end
+$var wire 16 h: MLS_D_si1_16 $end
 $scope struct power_isa_gpr_or_zero_reg_51 $end
-$var wire 8 t; value $end
+$var wire 8 i: value $end
 $upscope $end
-$var wire 16 u; addis_SI $end
-$var wire 5 v; addis_RA $end
-$var wire 5 w; addis_RT $end
 $scope struct power_isa_gpr_or_zero_reg_52 $end
-$var wire 8 x; value $end
+$var wire 8 j: value $end
 $upscope $end
-$var wire 1 y; addpcis_d2 $end
-$var wire 10 z; addpcis_d0 $end
-$var wire 5 {; addpcis_d1 $end
-$var wire 5 |; addpcis_RT $end
-$var wire 5 }; add_RB $end
-$var wire 5 ~; add_RA $end
-$var wire 5 !< add_RT $end
+$var wire 1 k: DX_d2_1 $end
+$var wire 10 l: DX_d0_10 $end
+$var wire 5 m: DX_d1_5 $end
+$var wire 5 n: DX_RT_5 $end
+$var wire 5 o: XO_RB_5 $end
+$var wire 5 p: XO_RA_5 $end
+$var wire 5 q: XO_RT_5 $end
 $scope struct flag_reg_0 $end
-$var string 1 "< \$tag $end
+$var string 1 r: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1 $end
-$var string 1 #< \$tag $end
+$var string 1 s: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 $< add__RB $end
-$var wire 5 %< add__RA $end
-$var wire 5 &< add__RT $end
 $scope struct flag_reg_0_2 $end
-$var string 1 '< \$tag $end
+$var string 1 t: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_2 $end
-$var string 1 (< \$tag $end
+$var string 1 u: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 )< addo_RB $end
-$var wire 5 *< addo_RA $end
-$var wire 5 +< addo_RT $end
 $scope struct flag_reg_0_3 $end
-$var string 1 ,< \$tag $end
+$var string 1 v: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_3 $end
-$var string 1 -< \$tag $end
+$var string 1 w: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 .< addo__RB $end
-$var wire 5 /< addo__RA $end
-$var wire 5 0< addo__RT $end
 $scope struct flag_reg_0_4 $end
-$var string 1 1< \$tag $end
+$var string 1 x: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_4 $end
-$var string 1 2< \$tag $end
+$var string 1 y: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 16 3< addic_SI $end
-$var wire 5 4< addic_RA $end
-$var wire 5 5< addic_RT $end
 $scope struct flag_reg_1_5 $end
-$var string 1 6< \$tag $end
+$var string 1 z: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 16 7< addic__SI $end
-$var wire 5 8< addic__RA $end
-$var wire 5 9< addic__RT $end
 $scope struct flag_reg_1_6 $end
-$var string 1 :< \$tag $end
+$var string 1 {: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 ;< subf_RB $end
-$var wire 5 << subf_RA $end
-$var wire 5 =< subf_RT $end
 $scope struct flag_reg_0_5 $end
-$var string 1 >< \$tag $end
+$var string 1 |: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_7 $end
-$var string 1 ?< \$tag $end
+$var string 1 }: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 @< subf__RB $end
-$var wire 5 A< subf__RA $end
-$var wire 5 B< subf__RT $end
 $scope struct flag_reg_0_6 $end
-$var string 1 C< \$tag $end
+$var string 1 ~: \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_8 $end
-$var string 1 D< \$tag $end
+$var string 1 !; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 E< subfo_RB $end
-$var wire 5 F< subfo_RA $end
-$var wire 5 G< subfo_RT $end
 $scope struct flag_reg_0_7 $end
-$var string 1 H< \$tag $end
+$var string 1 "; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_9 $end
-$var string 1 I< \$tag $end
+$var string 1 #; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 J< subfo__RB $end
-$var wire 5 K< subfo__RA $end
-$var wire 5 L< subfo__RT $end
 $scope struct flag_reg_0_8 $end
-$var string 1 M< \$tag $end
+$var string 1 $; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_10 $end
-$var string 1 N< \$tag $end
+$var string 1 %; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 16 O< subfic_SI $end
-$var wire 5 P< subfic_RA $end
-$var wire 5 Q< subfic_RT $end
 $scope struct flag_reg_1_11 $end
-$var string 1 R< \$tag $end
+$var string 1 &; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 S< addc_RB $end
-$var wire 5 T< addc_RA $end
-$var wire 5 U< addc_RT $end
 $scope struct flag_reg_0_9 $end
-$var string 1 V< \$tag $end
+$var string 1 '; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_12 $end
-$var string 1 W< \$tag $end
+$var string 1 (; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 X< addc__RB $end
-$var wire 5 Y< addc__RA $end
-$var wire 5 Z< addc__RT $end
 $scope struct flag_reg_0_10 $end
-$var string 1 [< \$tag $end
+$var string 1 ); \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_13 $end
-$var string 1 \< \$tag $end
+$var string 1 *; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 ]< addco_RB $end
-$var wire 5 ^< addco_RA $end
-$var wire 5 _< addco_RT $end
 $scope struct flag_reg_0_11 $end
-$var string 1 `< \$tag $end
+$var string 1 +; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_14 $end
-$var string 1 a< \$tag $end
+$var string 1 ,; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 b< addco__RB $end
-$var wire 5 c< addco__RA $end
-$var wire 5 d< addco__RT $end
 $scope struct flag_reg_0_12 $end
-$var string 1 e< \$tag $end
+$var string 1 -; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_15 $end
-$var string 1 f< \$tag $end
+$var string 1 .; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 g< subfc_RB $end
-$var wire 5 h< subfc_RA $end
-$var wire 5 i< subfc_RT $end
 $scope struct flag_reg_0_13 $end
-$var string 1 j< \$tag $end
+$var string 1 /; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_16 $end
-$var string 1 k< \$tag $end
+$var string 1 0; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 l< subfc__RB $end
-$var wire 5 m< subfc__RA $end
-$var wire 5 n< subfc__RT $end
 $scope struct flag_reg_0_14 $end
-$var string 1 o< \$tag $end
+$var string 1 1; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_17 $end
-$var string 1 p< \$tag $end
+$var string 1 2; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 q< subfco_RB $end
-$var wire 5 r< subfco_RA $end
-$var wire 5 s< subfco_RT $end
 $scope struct flag_reg_0_15 $end
-$var string 1 t< \$tag $end
+$var string 1 3; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_18 $end
-$var string 1 u< \$tag $end
+$var string 1 4; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 v< subfco__RB $end
-$var wire 5 w< subfco__RA $end
-$var wire 5 x< subfco__RT $end
 $scope struct flag_reg_0_16 $end
-$var string 1 y< \$tag $end
+$var string 1 5; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_19 $end
-$var string 1 z< \$tag $end
+$var string 1 6; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 {< adde_RB $end
-$var wire 5 |< adde_RA $end
-$var wire 5 }< adde_RT $end
 $scope struct flag_reg_0_17 $end
-$var string 1 ~< \$tag $end
+$var string 1 7; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_20 $end
-$var string 1 != \$tag $end
+$var string 1 8; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 "= adde__RB $end
-$var wire 5 #= adde__RA $end
-$var wire 5 $= adde__RT $end
 $scope struct flag_reg_0_18 $end
-$var string 1 %= \$tag $end
+$var string 1 9; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_21 $end
-$var string 1 &= \$tag $end
+$var string 1 :; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 '= addeo_RB $end
-$var wire 5 (= addeo_RA $end
-$var wire 5 )= addeo_RT $end
 $scope struct flag_reg_0_19 $end
-$var string 1 *= \$tag $end
+$var string 1 ;; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_22 $end
-$var string 1 += \$tag $end
+$var string 1 <; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 ,= addeo__RB $end
-$var wire 5 -= addeo__RA $end
-$var wire 5 .= addeo__RT $end
 $scope struct flag_reg_0_20 $end
-$var string 1 /= \$tag $end
+$var string 1 =; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_23 $end
-$var string 1 0= \$tag $end
+$var string 1 >; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 1= subfe_RB $end
-$var wire 5 2= subfe_RA $end
-$var wire 5 3= subfe_RT $end
 $scope struct flag_reg_0_21 $end
-$var string 1 4= \$tag $end
+$var string 1 ?; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_24 $end
-$var string 1 5= \$tag $end
+$var string 1 @; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 6= subfe__RB $end
-$var wire 5 7= subfe__RA $end
-$var wire 5 8= subfe__RT $end
 $scope struct flag_reg_0_22 $end
-$var string 1 9= \$tag $end
+$var string 1 A; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_25 $end
-$var string 1 := \$tag $end
+$var string 1 B; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 ;= subfeo_RB $end
-$var wire 5 <= subfeo_RA $end
-$var wire 5 == subfeo_RT $end
 $scope struct flag_reg_0_23 $end
-$var string 1 >= \$tag $end
+$var string 1 C; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_26 $end
-$var string 1 ?= \$tag $end
+$var string 1 D; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 @= subfeo__RB $end
-$var wire 5 A= subfeo__RA $end
-$var wire 5 B= subfeo__RT $end
 $scope struct flag_reg_0_24 $end
-$var string 1 C= \$tag $end
+$var string 1 E; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_27 $end
-$var string 1 D= \$tag $end
+$var string 1 F; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 E= addme_RA $end
-$var wire 5 F= addme_RT $end
 $scope struct flag_reg_0_25 $end
-$var string 1 G= \$tag $end
+$var string 1 G; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_28 $end
-$var string 1 H= \$tag $end
+$var string 1 H; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 I= addme__RA $end
-$var wire 5 J= addme__RT $end
 $scope struct flag_reg_0_26 $end
-$var string 1 K= \$tag $end
+$var string 1 I; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_29 $end
-$var string 1 L= \$tag $end
+$var string 1 J; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 M= addmeo_RA $end
-$var wire 5 N= addmeo_RT $end
 $scope struct flag_reg_0_27 $end
-$var string 1 O= \$tag $end
+$var string 1 K; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_30 $end
-$var string 1 P= \$tag $end
+$var string 1 L; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 Q= addmeo__RA $end
-$var wire 5 R= addmeo__RT $end
 $scope struct flag_reg_0_28 $end
-$var string 1 S= \$tag $end
+$var string 1 M; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_31 $end
-$var string 1 T= \$tag $end
+$var string 1 N; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 U= addze_RA $end
-$var wire 5 V= addze_RT $end
 $scope struct flag_reg_0_29 $end
-$var string 1 W= \$tag $end
+$var string 1 O; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_32 $end
-$var string 1 X= \$tag $end
+$var string 1 P; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 Y= addze__RA $end
-$var wire 5 Z= addze__RT $end
 $scope struct flag_reg_0_30 $end
-$var string 1 [= \$tag $end
+$var string 1 Q; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_33 $end
-$var string 1 \= \$tag $end
+$var string 1 R; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 ]= addzeo_RA $end
-$var wire 5 ^= addzeo_RT $end
 $scope struct flag_reg_0_31 $end
-$var string 1 _= \$tag $end
+$var string 1 S; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_34 $end
-$var string 1 `= \$tag $end
+$var string 1 T; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 a= addzeo__RA $end
-$var wire 5 b= addzeo__RT $end
 $scope struct flag_reg_0_32 $end
-$var string 1 c= \$tag $end
+$var string 1 U; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_35 $end
-$var string 1 d= \$tag $end
+$var string 1 V; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 e= subfme_RA $end
-$var wire 5 f= subfme_RT $end
 $scope struct flag_reg_0_33 $end
-$var string 1 g= \$tag $end
+$var string 1 W; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_36 $end
-$var string 1 h= \$tag $end
+$var string 1 X; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 i= subfme__RA $end
-$var wire 5 j= subfme__RT $end
 $scope struct flag_reg_0_34 $end
-$var string 1 k= \$tag $end
+$var string 1 Y; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_37 $end
-$var string 1 l= \$tag $end
+$var string 1 Z; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 m= subfmeo_RA $end
-$var wire 5 n= subfmeo_RT $end
 $scope struct flag_reg_0_35 $end
-$var string 1 o= \$tag $end
+$var string 1 [; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_38 $end
-$var string 1 p= \$tag $end
+$var string 1 \; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 q= subfmeo__RA $end
-$var wire 5 r= subfmeo__RT $end
 $scope struct flag_reg_0_36 $end
-$var string 1 s= \$tag $end
+$var string 1 ]; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_39 $end
-$var string 1 t= \$tag $end
+$var string 1 ^; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 u= subfze_RA $end
-$var wire 5 v= subfze_RT $end
 $scope struct flag_reg_0_37 $end
-$var string 1 w= \$tag $end
+$var string 1 _; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_40 $end
-$var string 1 x= \$tag $end
+$var string 1 `; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 y= subfze__RA $end
-$var wire 5 z= subfze__RT $end
 $scope struct flag_reg_0_38 $end
-$var string 1 {= \$tag $end
+$var string 1 a; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_41 $end
-$var string 1 |= \$tag $end
+$var string 1 b; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 }= subfzeo_RA $end
-$var wire 5 ~= subfzeo_RT $end
 $scope struct flag_reg_0_39 $end
-$var string 1 !> \$tag $end
+$var string 1 c; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_42 $end
-$var string 1 "> \$tag $end
+$var string 1 d; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 #> subfzeo__RA $end
-$var wire 5 $> subfzeo__RT $end
 $scope struct flag_reg_0_40 $end
-$var string 1 %> \$tag $end
+$var string 1 e; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_43 $end
-$var string 1 &> \$tag $end
+$var string 1 f; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 '> neg_RA $end
-$var wire 5 (> neg_RT $end
 $scope struct flag_reg_0_41 $end
-$var string 1 )> \$tag $end
+$var string 1 g; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_44 $end
-$var string 1 *> \$tag $end
+$var string 1 h; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 +> neg__RA $end
-$var wire 5 ,> neg__RT $end
 $scope struct flag_reg_0_42 $end
-$var string 1 -> \$tag $end
+$var string 1 i; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_45 $end
-$var string 1 .> \$tag $end
+$var string 1 j; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 /> nego_RA $end
-$var wire 5 0> nego_RT $end
 $scope struct flag_reg_0_43 $end
-$var string 1 1> \$tag $end
+$var string 1 k; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_46 $end
-$var string 1 2> \$tag $end
+$var string 1 l; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 3> nego__RA $end
-$var wire 5 4> nego__RT $end
 $scope struct flag_reg_0_44 $end
-$var string 1 5> \$tag $end
+$var string 1 m; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
 $scope struct flag_reg_1_47 $end
-$var string 1 6> \$tag $end
+$var string 1 n; \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 16 7> cmpi_SI $end
-$var wire 5 8> cmpi_RA $end
-$var wire 1 9> cmpi_L $end
-$var wire 3 :> cmpi_BF $end
-$var string 1 ;> compare_mode $end
+$var wire 1 o; D_L_1 $end
+$var wire 3 p; D_BF_3 $end
+$var string 1 q; compare_mode $end
 $scope struct power_isa_cr_reg_37 $end
-$var wire 8 <> value $end
+$var wire 8 r; value $end
 $upscope $end
-$var wire 5 => cmp_RB $end
-$var wire 5 >> cmp_RA $end
-$var wire 1 ?> cmp_L $end
-$var wire 3 @> cmp_BF $end
-$var string 1 A> compare_mode_2 $end
+$var wire 1 s; X_L_1 $end
+$var wire 3 t; X_BF_3 $end
+$var string 1 u; compare_mode_2 $end
 $scope struct power_isa_cr_reg_38 $end
-$var wire 8 B> value $end
+$var wire 8 v; value $end
 $upscope $end
-$var wire 16 C> cmpli_UI $end
-$var wire 5 D> cmpli_RA $end
-$var wire 1 E> cmpli_L $end
-$var wire 3 F> cmpli_BF $end
-$var string 1 G> compare_mode_3 $end
+$var wire 16 w; D_UI_16 $end
+$var string 1 x; compare_mode_3 $end
 $scope struct power_isa_cr_reg_39 $end
-$var wire 8 H> value $end
+$var wire 8 y; value $end
 $upscope $end
-$var wire 5 I> cmpl_RB $end
-$var wire 5 J> cmpl_RA $end
-$var wire 1 K> cmpl_L $end
-$var wire 3 L> cmpl_BF $end
-$var string 1 M> compare_mode_4 $end
+$var string 1 z; compare_mode_4 $end
 $scope struct power_isa_cr_reg_40 $end
-$var wire 8 N> value $end
+$var wire 8 {; value $end
 $upscope $end
-$var wire 5 O> cmprb_RB $end
-$var wire 5 P> cmprb_RA $end
-$var wire 1 Q> cmprb_L $end
-$var wire 3 R> cmprb_BF $end
-$var string 1 S> compare_mode_5 $end
+$var string 1 |; compare_mode_5 $end
 $scope struct power_isa_cr_reg_41 $end
-$var wire 8 T> value $end
+$var wire 8 }; value $end
 $upscope $end
-$var wire 5 U> cmpeqb_RB $end
-$var wire 5 V> cmpeqb_RA $end
-$var wire 3 W> cmpeqb_BF $end
 $scope struct power_isa_cr_reg_42 $end
-$var wire 8 X> value $end
+$var wire 8 ~; value $end
 $upscope $end
-$var wire 16 Y> andi__UI $end
-$var wire 5 Z> andi__RA $end
-$var wire 5 [> andi__RS $end
 $scope struct flag_reg_1_48 $end
-$var string 1 \> \$tag $end
+$var string 1 !< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 16 ]> andis__UI $end
-$var wire 5 ^> andis__RA $end
-$var wire 5 _> andis__RS $end
 $scope struct flag_reg_1_49 $end
-$var string 1 `> \$tag $end
+$var string 1 "< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 16 a> ori_UI $end
-$var wire 5 b> ori_RA $end
-$var wire 5 c> ori_RS $end
 $scope struct flag_reg_1_50 $end
-$var string 1 d> \$tag $end
+$var string 1 #< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 16 e> oris_UI $end
-$var wire 5 f> oris_RA $end
-$var wire 5 g> oris_RS $end
 $scope struct flag_reg_1_51 $end
-$var string 1 h> \$tag $end
+$var string 1 $< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 16 i> xori_UI $end
-$var wire 5 j> xori_RA $end
-$var wire 5 k> xori_RS $end
 $scope struct flag_reg_1_52 $end
-$var string 1 l> \$tag $end
+$var string 1 %< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 16 m> xoris_UI $end
-$var wire 5 n> xoris_RA $end
-$var wire 5 o> xoris_RS $end
 $scope struct flag_reg_1_53 $end
-$var string 1 p> \$tag $end
+$var string 1 &< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 q> and_RB $end
-$var wire 5 r> and_RA $end
-$var wire 5 s> and_RS $end
 $scope struct flag_reg_1_54 $end
-$var string 1 t> \$tag $end
+$var string 1 '< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 u> and__RB $end
-$var wire 5 v> and__RA $end
-$var wire 5 w> and__RS $end
 $scope struct flag_reg_1_55 $end
-$var string 1 x> \$tag $end
+$var string 1 (< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 y> xor_RB $end
-$var wire 5 z> xor_RA $end
-$var wire 5 {> xor_RS $end
 $scope struct flag_reg_1_56 $end
-$var string 1 |> \$tag $end
+$var string 1 )< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 }> xor__RB $end
-$var wire 5 ~> xor__RA $end
-$var wire 5 !? xor__RS $end
 $scope struct flag_reg_1_57 $end
-$var string 1 "? \$tag $end
+$var string 1 *< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 #? nand_RB $end
-$var wire 5 $? nand_RA $end
-$var wire 5 %? nand_RS $end
 $scope struct flag_reg_1_58 $end
-$var string 1 &? \$tag $end
+$var string 1 +< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 '? nand__RB $end
-$var wire 5 (? nand__RA $end
-$var wire 5 )? nand__RS $end
 $scope struct flag_reg_1_59 $end
-$var string 1 *? \$tag $end
+$var string 1 ,< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 +? or_RB $end
-$var wire 5 ,? or_RA $end
-$var wire 5 -? or_RS $end
 $scope struct flag_reg_1_60 $end
-$var string 1 .? \$tag $end
+$var string 1 -< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 /? or__RB $end
-$var wire 5 0? or__RA $end
-$var wire 5 1? or__RS $end
 $scope struct flag_reg_1_61 $end
-$var string 1 2? \$tag $end
+$var string 1 .< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 3? orc_RB $end
-$var wire 5 4? orc_RA $end
-$var wire 5 5? orc_RS $end
 $scope struct flag_reg_1_62 $end
-$var string 1 6? \$tag $end
+$var string 1 /< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 7? orc__RB $end
-$var wire 5 8? orc__RA $end
-$var wire 5 9? orc__RS $end
 $scope struct flag_reg_1_63 $end
-$var string 1 :? \$tag $end
+$var string 1 0< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 ;? nor_RB $end
-$var wire 5 <? nor_RA $end
-$var wire 5 =? nor_RS $end
 $scope struct flag_reg_1_64 $end
-$var string 1 >? \$tag $end
+$var string 1 1< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 ?? nor__RB $end
-$var wire 5 @? nor__RA $end
-$var wire 5 A? nor__RS $end
 $scope struct flag_reg_1_65 $end
-$var string 1 B? \$tag $end
+$var string 1 2< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 C? eqv_RB $end
-$var wire 5 D? eqv_RA $end
-$var wire 5 E? eqv_RS $end
 $scope struct flag_reg_1_66 $end
-$var string 1 F? \$tag $end
+$var string 1 3< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 G? eqv__RB $end
-$var wire 5 H? eqv__RA $end
-$var wire 5 I? eqv__RS $end
 $scope struct flag_reg_1_67 $end
-$var string 1 J? \$tag $end
+$var string 1 4< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 K? andc_RB $end
-$var wire 5 L? andc_RA $end
-$var wire 5 M? andc_RS $end
 $scope struct flag_reg_1_68 $end
-$var string 1 N? \$tag $end
+$var string 1 5< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 O? andc__RB $end
-$var wire 5 P? andc__RA $end
-$var wire 5 Q? andc__RS $end
 $scope struct flag_reg_1_69 $end
-$var string 1 R? \$tag $end
+$var string 1 6< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 S? extsb_RA $end
-$var wire 5 T? extsb_RS $end
 $scope struct flag_reg_1_70 $end
-$var string 1 U? \$tag $end
+$var string 1 7< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 V? extsb__RA $end
-$var wire 5 W? extsb__RS $end
 $scope struct flag_reg_1_71 $end
-$var string 1 X? \$tag $end
+$var string 1 8< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 Y? extsh_RA $end
-$var wire 5 Z? extsh_RS $end
 $scope struct flag_reg_1_72 $end
-$var string 1 [? \$tag $end
+$var string 1 9< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 \? extsh__RA $end
-$var wire 5 ]? extsh__RS $end
 $scope struct flag_reg_1_73 $end
-$var string 1 ^? \$tag $end
+$var string 1 :< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 _? extsw_RA $end
-$var wire 5 `? extsw_RS $end
 $scope struct flag_reg_1_74 $end
-$var string 1 a? \$tag $end
+$var string 1 ;< \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 5 b? extsw__RA $end
-$var wire 5 c? extsw__RS $end
 $scope struct flag_reg_1_75 $end
-$var string 1 d? \$tag $end
+$var string 1 << \$tag $end
 $scope struct HdlSome $end
 $upscope $end
 $upscope $end
-$var wire 3 e? mcrxrx_BF $end
-$scope struct power_isa_cr_reg_43 $end
-$var wire 8 f? value $end
+$var wire 5 =< M_ME_5 $end
+$var wire 5 >< M_MB_5 $end
+$var wire 5 ?< M_SH_5 $end
+$var wire 5 @< M_RA_5 $end
+$var wire 5 A< M_RS_5 $end
+$var wire 6 B< msb0_mask_begin $end
+$var wire 6 C< msb0_mask_end $end
+$var wire 6 D< rotated_output_start $end
+$var wire 6 E< rotated_output_len $end
+$scope struct rotate_dest_logic_op $end
+$var string 1 F< \$tag $end
+$scope struct HdlSome $end
+$var wire 6 G< rotated_output_start $end
+$var wire 6 H< rotated_output_len $end
+$var wire 1 I< fallback_is_src2 $end
 $upscope $end
 $upscope $end
+$var wire 8 J< rotate_imm_src2 $end
+$scope struct flag_reg_1_76 $end
+$var string 1 K< \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 L< msb0_mask_begin_2 $end
+$var wire 6 M< msb0_mask_end_2 $end
+$var wire 6 N< rotated_output_start_2 $end
+$var wire 6 O< rotated_output_len_2 $end
+$scope struct rotate_dest_logic_op_2 $end
+$var string 1 P< \$tag $end
+$scope struct HdlSome $end
+$var wire 6 Q< rotated_output_start $end
+$var wire 6 R< rotated_output_len $end
+$var wire 1 S< fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$var wire 8 T< rotate_imm_src2_2 $end
+$scope struct flag_reg_1_77 $end
+$var string 1 U< \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 5 V< M_RB_5 $end
+$var wire 6 W< msb0_mask_begin_3 $end
+$var wire 6 X< msb0_mask_end_3 $end
+$var wire 6 Y< rotated_output_start_3 $end
+$var wire 6 Z< rotated_output_len_3 $end
+$scope struct rotate_dest_logic_op_3 $end
+$var string 1 [< \$tag $end
+$scope struct HdlSome $end
+$var wire 6 \< rotated_output_start $end
+$var wire 6 ]< rotated_output_len $end
+$var wire 1 ^< fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_78 $end
+$var string 1 _< \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 `< msb0_mask_begin_4 $end
+$var wire 6 a< msb0_mask_end_4 $end
+$var wire 6 b< rotated_output_start_4 $end
+$var wire 6 c< rotated_output_len_4 $end
+$scope struct rotate_dest_logic_op_4 $end
+$var string 1 d< \$tag $end
+$scope struct HdlSome $end
+$var wire 6 e< rotated_output_start $end
+$var wire 6 f< rotated_output_len $end
+$var wire 1 g< fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_79 $end
+$var string 1 h< \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 i< msb0_mask_begin_5 $end
+$var wire 6 j< msb0_mask_end_5 $end
+$var wire 6 k< rotated_output_start_5 $end
+$var wire 6 l< rotated_output_len_5 $end
+$scope struct rotate_dest_logic_op_5 $end
+$var string 1 m< \$tag $end
+$scope struct HdlSome $end
+$var wire 6 n< rotated_output_start $end
+$var wire 6 o< rotated_output_len $end
+$var wire 1 p< fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$var wire 8 q< rotate_imm_src2_3 $end
+$scope struct flag_reg_1_80 $end
+$var string 1 r< \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 s< msb0_mask_begin_6 $end
+$var wire 6 t< msb0_mask_end_6 $end
+$var wire 6 u< rotated_output_start_6 $end
+$var wire 6 v< rotated_output_len_6 $end
+$scope struct rotate_dest_logic_op_6 $end
+$var string 1 w< \$tag $end
+$scope struct HdlSome $end
+$var wire 6 x< rotated_output_start $end
+$var wire 6 y< rotated_output_len $end
+$var wire 1 z< fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$var wire 8 {< rotate_imm_src2_4 $end
+$scope struct flag_reg_1_81 $end
+$var string 1 |< \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 }< MD_mb_6 $end
+$var wire 6 ~< MD_sh_6 $end
+$var wire 5 != MD_RA_5 $end
+$var wire 5 "= MD_RS_5 $end
+$var wire 6 #= msb0_mask_begin_7 $end
+$var wire 6 $= msb0_mask_end_7 $end
+$var wire 6 %= rotated_output_start_7 $end
+$var wire 6 &= rotated_output_len_7 $end
+$scope struct rotate_dest_logic_op_7 $end
+$var string 1 '= \$tag $end
+$scope struct HdlSome $end
+$var wire 6 (= rotated_output_start $end
+$var wire 6 )= rotated_output_len $end
+$var wire 1 *= fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$var wire 8 += rotate_imm_src2_5 $end
+$scope struct flag_reg_1_82 $end
+$var string 1 ,= \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 -= msb0_mask_begin_8 $end
+$var wire 6 .= msb0_mask_end_8 $end
+$var wire 6 /= rotated_output_start_8 $end
+$var wire 6 0= rotated_output_len_8 $end
+$scope struct rotate_dest_logic_op_8 $end
+$var string 1 1= \$tag $end
+$scope struct HdlSome $end
+$var wire 6 2= rotated_output_start $end
+$var wire 6 3= rotated_output_len $end
+$var wire 1 4= fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$var wire 8 5= rotate_imm_src2_6 $end
+$scope struct flag_reg_1_83 $end
+$var string 1 6= \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 7= MD_me_6 $end
+$var wire 6 8= msb0_mask_begin_9 $end
+$var wire 6 9= msb0_mask_end_9 $end
+$var wire 6 := rotated_output_start_9 $end
+$var wire 6 ;= rotated_output_len_9 $end
+$scope struct rotate_dest_logic_op_9 $end
+$var string 1 <= \$tag $end
+$scope struct HdlSome $end
+$var wire 6 == rotated_output_start $end
+$var wire 6 >= rotated_output_len $end
+$var wire 1 ?= fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$var wire 8 @= rotate_imm_src2_7 $end
+$scope struct flag_reg_1_84 $end
+$var string 1 A= \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 B= msb0_mask_begin_10 $end
+$var wire 6 C= msb0_mask_end_10 $end
+$var wire 6 D= rotated_output_start_10 $end
+$var wire 6 E= rotated_output_len_10 $end
+$scope struct rotate_dest_logic_op_10 $end
+$var string 1 F= \$tag $end
+$scope struct HdlSome $end
+$var wire 6 G= rotated_output_start $end
+$var wire 6 H= rotated_output_len $end
+$var wire 1 I= fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$var wire 8 J= rotate_imm_src2_8 $end
+$scope struct flag_reg_1_85 $end
+$var string 1 K= \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 L= msb0_mask_begin_11 $end
+$var wire 6 M= msb0_mask_end_11 $end
+$var wire 6 N= rotated_output_start_11 $end
+$var wire 6 O= rotated_output_len_11 $end
+$scope struct rotate_dest_logic_op_11 $end
+$var string 1 P= \$tag $end
+$scope struct HdlSome $end
+$var wire 6 Q= rotated_output_start $end
+$var wire 6 R= rotated_output_len $end
+$var wire 1 S= fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$var wire 8 T= rotate_imm_src2_9 $end
+$scope struct flag_reg_1_86 $end
+$var string 1 U= \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 V= msb0_mask_begin_12 $end
+$var wire 6 W= msb0_mask_end_12 $end
+$var wire 6 X= rotated_output_start_12 $end
+$var wire 6 Y= rotated_output_len_12 $end
+$scope struct rotate_dest_logic_op_12 $end
+$var string 1 Z= \$tag $end
+$scope struct HdlSome $end
+$var wire 6 [= rotated_output_start $end
+$var wire 6 \= rotated_output_len $end
+$var wire 1 ]= fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$var wire 8 ^= rotate_imm_src2_10 $end
+$scope struct flag_reg_1_87 $end
+$var string 1 _= \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 `= MDS_mb_6 $end
+$var wire 5 a= MDS_RB_5 $end
+$var wire 5 b= MDS_RA_5 $end
+$var wire 5 c= MDS_RS_5 $end
+$var wire 6 d= msb0_mask_begin_13 $end
+$var wire 6 e= msb0_mask_end_13 $end
+$var wire 6 f= rotated_output_start_13 $end
+$var wire 6 g= rotated_output_len_13 $end
+$scope struct rotate_dest_logic_op_13 $end
+$var string 1 h= \$tag $end
+$scope struct HdlSome $end
+$var wire 6 i= rotated_output_start $end
+$var wire 6 j= rotated_output_len $end
+$var wire 1 k= fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_88 $end
+$var string 1 l= \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 m= msb0_mask_begin_14 $end
+$var wire 6 n= msb0_mask_end_14 $end
+$var wire 6 o= rotated_output_start_14 $end
+$var wire 6 p= rotated_output_len_14 $end
+$scope struct rotate_dest_logic_op_14 $end
+$var string 1 q= \$tag $end
+$scope struct HdlSome $end
+$var wire 6 r= rotated_output_start $end
+$var wire 6 s= rotated_output_len $end
+$var wire 1 t= fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_89 $end
+$var string 1 u= \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 v= MDS_me_6 $end
+$var wire 6 w= msb0_mask_begin_15 $end
+$var wire 6 x= msb0_mask_end_15 $end
+$var wire 6 y= rotated_output_start_15 $end
+$var wire 6 z= rotated_output_len_15 $end
+$scope struct rotate_dest_logic_op_15 $end
+$var string 1 {= \$tag $end
+$scope struct HdlSome $end
+$var wire 6 |= rotated_output_start $end
+$var wire 6 }= rotated_output_len $end
+$var wire 1 ~= fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_90 $end
+$var string 1 !> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 "> msb0_mask_begin_16 $end
+$var wire 6 #> msb0_mask_end_16 $end
+$var wire 6 $> rotated_output_start_16 $end
+$var wire 6 %> rotated_output_len_16 $end
+$scope struct rotate_dest_logic_op_16 $end
+$var string 1 &> \$tag $end
+$scope struct HdlSome $end
+$var wire 6 '> rotated_output_start $end
+$var wire 6 (> rotated_output_len $end
+$var wire 1 )> fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_91 $end
+$var string 1 *> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 +> msb0_mask_begin_17 $end
+$var wire 6 ,> msb0_mask_end_17 $end
+$var wire 6 -> rotated_output_start_17 $end
+$var wire 6 .> rotated_output_len_17 $end
+$scope struct rotate_dest_logic_op_17 $end
+$var string 1 /> \$tag $end
+$scope struct HdlSome $end
+$var wire 6 0> rotated_output_start $end
+$var wire 6 1> rotated_output_len $end
+$var wire 1 2> fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$var wire 8 3> rotate_imm_src2_11 $end
+$scope struct flag_reg_1_92 $end
+$var string 1 4> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 5> msb0_mask_begin_18 $end
+$var wire 6 6> msb0_mask_end_18 $end
+$var wire 6 7> rotated_output_start_18 $end
+$var wire 6 8> rotated_output_len_18 $end
+$scope struct rotate_dest_logic_op_18 $end
+$var string 1 9> \$tag $end
+$scope struct HdlSome $end
+$var wire 6 :> rotated_output_start $end
+$var wire 6 ;> rotated_output_len $end
+$var wire 1 <> fallback_is_src2 $end
+$upscope $end
+$upscope $end
+$var wire 8 => rotate_imm_src2_12 $end
+$scope struct flag_reg_1_93 $end
+$var string 1 >> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_94 $end
+$var string 1 ?> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_95 $end
+$var string 1 @> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_96 $end
+$var string 1 A> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_97 $end
+$var string 1 B> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 5 C> X_SH_5 $end
+$scope struct flag_reg_1_98 $end
+$var string 1 D> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_99 $end
+$var string 1 E> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_100 $end
+$var string 1 F> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_101 $end
+$var string 1 G> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_102 $end
+$var string 1 H> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_103 $end
+$var string 1 I> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 6 J> XS_sh_6 $end
+$var wire 5 K> XS_RA_5 $end
+$var wire 5 L> XS_RS_5 $end
+$scope struct flag_reg_1_104 $end
+$var string 1 M> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_105 $end
+$var string 1 N> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_106 $end
+$var string 1 O> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_107 $end
+$var string 1 P> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_108 $end
+$var string 1 Q> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_109 $end
+$var string 1 R> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_110 $end
+$var string 1 S> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$scope struct flag_reg_1_111 $end
+$var string 1 T> \$tag $end
+$scope struct HdlSome $end
+$upscope $end
+$upscope $end
+$var wire 10 U> XFX_spr_10 $end
+$var wire 5 V> XFX_RS_5 $end
+$var wire 10 W> spr_num $end
+$var wire 5 X> XFX_RT_5 $end
+$var wire 10 Y> spr_num_2 $end
+$scope struct power_isa_cr_reg_43 $end
+$var wire 8 Z> value $end
+$upscope $end
+$var wire 10 [> XFX_tbr_10 $end
+$var wire 10 \> spr_num_3 $end
+$var wire 10 ]> spr_num_4 $end
+$var wire 10 ^> spr_num_5 $end
+$upscope $end
 $enddefinitions $end
 $dumpvars
 sAluBranch\x20(0) !
-sBranchI\x20(8) "
+sBranchI\x20(9) "
 s0 #
 b0 $
 b0 %
@@ -8130,72 +8842,72 @@ sHdlNone\x20(0) &
 sHdlNone\x20(0) '
 b0 (
 b0 )
-b0 *
-b1101000101011001111000 +
-0,
-sSignExt32\x20(3) -
+b1111000 *
+b11010001010110 +
+sSignExt32\x20(3) ,
+0-
 0.
-0/
-10
-01
-s0 2
+1/
+00
+s0 1
+b0 2
 b0 3
-b0 4
+sHdlNone\x20(0) 4
 sHdlNone\x20(0) 5
-sHdlNone\x20(0) 6
+b0 6
 b0 7
-b0 8
-b0 9
-b1101000101011001111000 :
+b1101000101011001111000 8
+sSignExt32\x20(3) 9
+0:
 0;
-sSignExt32\x20(3) <
+1<
 0=
-0>
-1?
-0@
-s0 A
-b0 B
+s0 >
+b0 ?
+b0 @
+sHdlNone\x20(0) A
+sHdlNone\x20(0) B
 b0 C
-sHdlNone\x20(0) D
-sHdlNone\x20(0) E
-b0 F
-b0 G
-b0 H
-b1101000101011001111000 I
-0J
-1K
-1L
-0M
-0N
-s0 O
-b0 P
-b0 Q
-sHdlNone\x20(0) R
-sHdlNone\x20(0) S
-b0 T
+b0 D
+b1111000 E
+b110 F
+sPhantomConst(\"0..8\") G
+b10 H
+sPhantomConst(\"0..8\") I
+b1 J
+sPhantomConst(\"0..8\") K
+b10 L
+sPhantomConst(\"0..8\") M
+b11 N
+sPhantomConst(\"0..=8\") O
+0P
+0Q
+0R
+0S
+s0 T
 b0 U
 b0 V
-b1101000101011001111000 W
-0X
-sSignExt32\x20(3) Y
-0Z
-0[
-1\
+sHdlNone\x20(0) W
+sHdlNone\x20(0) X
+b0 Y
+b0 Z
+b1101000101011001111000 [
+sSignExt32\x20(3) \
 0]
-s0 ^
-b0 _
-b0 `
-sHdlNone\x20(0) a
-sHdlNone\x20(0) b
+0^
+1_
+0`
+s0 a
+b0 b
 b0 c
-b0 d
-b0 e
-b1101000101011001111000 f
-0g
-sSignExt32\x20(3) h
+sHdlNone\x20(0) d
+sHdlNone\x20(0) e
+b0 f
+b110100010101100111100000000000 g
+sFull64\x20(0) h
 0i
 0j
-1k
+0k
 0l
 s0 m
 b0 n
@@ -8204,190 +8916,190 @@ sHdlNone\x20(0) p
 sHdlNone\x20(0) q
 b0 r
 b0 s
-b0 t
-b1101000101011001111000 u
-0v
-sSignExt32\x20(3) w
-sU16\x20(4) x
-s0 y
+b1111000 t
+sHdlNone\x20(0) u
+b101011 v
+0w
+sHdlNone\x20(0) x
+b11010 y
 b0 z
-b0 {
-sHdlNone\x20(0) |
-sHdlNone\x20(0) }
-b0 ~
+0{
+sFull64\x20(0) |
+sSignExt32To64BitThenShift\x20(6) }
+s0 ~
 b0 !"
 b0 ""
-b1101000101011001111000 #"
-0$"
-sSignExt32\x20(3) %"
-sU16\x20(4) &"
-s0 '"
-b0 ("
-b0 )"
-sHdlNone\x20(0) *"
-sHdlNone\x20(0) +"
+sHdlNone\x20(0) #"
+sHdlNone\x20(0) $"
+b0 %"
+b0 &"
+b1101000101011001111000 '"
+sSignExt32\x20(3) ("
+sU16\x20(4) )"
+s0 *"
+b0 +"
 b0 ,"
-b0 -"
-b0 ."
-b1101000101011001111000 /"
-00"
-11"
-sULt\x20(1) 2"
-03"
-14"
-05"
-06"
-s0 7"
+sHdlNone\x20(0) -"
+sHdlNone\x20(0) ."
+b0 /"
+b110100010101100111100000000000 0"
+sFull64\x20(0) 1"
+sU64\x20(0) 2"
+s0 3"
+b0 4"
+b0 5"
+sHdlNone\x20(0) 6"
+sHdlNone\x20(0) 7"
 b0 8"
 b0 9"
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 s0 B,
 b1 C,
 b0 D,
@@ -9197,11 +9909,11 @@ b1101 G,
 b0 H,
 b10 I,
 b101011001111000 J,
-0K,
-1L,
+sSignExt8\x20(7) K,
+0L,
 1M,
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+1O,
 s0 P,
 b1 Q,
 b0 R,
@@ -9209,214 +9921,214 @@ sHdlNone\x20(0) S,
 sHdlNone\x20(0) T,
 b1101 U,
 b0 V,
-b10 W,
-b101011001111000 X,
+b10101100111100000000010 W,
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+1X1
+0Y1
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+0[1
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 b0 l1
-0m1
-sSignExt8\x20(7) n1
-0o1
-1p1
-0q1
-0r1
-s0 s1
-b0 t1
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 b0 u1
 sHdlNone\x20(0) v1
 sHdlNone\x20(0) w1
 b1101 x1
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 b10 z1
-b0 {1
-0|1
-1}1
-1~1
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+sBranch\x20(8) #2
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 b0 %2
-sHdlNone\x20(0) &2
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 sHdlNone\x20(0) '2
-b1101 (2
-b10 )2
+sHdlNone\x20(0) (2
+b1101 )2
 b10 *2
-b0 +2
-0,2
+b10 +2
+b0 ,2
 sSignExt8\x20(7) -2
 0.2
 1/2
@@ -9744,210 +10456,210 @@ sHdlNone\x20(0) 62
 b1101 72
 b10 82
 b10 92
-b0 :2
+sSignExt8\x20(7) :2
 0;2
-sSignExt8\x20(7) <2
+1<2
 0=2
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-0@2
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-b0 C2
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-sHdlNone\x20(0) E2
-b1101 F2
-b10 G2
-b10 H2
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 b0 I2
-0J2
-sSignExt8\x20(7) K2
-sU32\x20(2) L2
-s0 M2
-b0 N2
+sPhantomConst(\"0..8\") J2
+b0 K2
+sPhantomConst(\"0..8\") L2
+b0 M2
+sPhantomConst(\"0..8\") N2
 b0 O2
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-sHdlNone\x20(0) Q2
-b1101 R2
-b10 S2
-b10 T2
-b0 U2
-0V2
-sSignExt8\x20(7) W2
-sU32\x20(2) X2
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-sHdlNone\x20(0) ]2
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-0b2
-1c2
-sSLt\x20(3) d2
-1e2
-0f2
-0g2
-0h2
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-b10 p2
-b0 q2
-0r2
-1s2
-sSLt\x20(3) t2
-1u2
-0v2
-0w2
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+0^2
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 0x2
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 b0 z2
 b0 {2
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-sWidth64Bit\x20(3) 03
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-b11 23
-b0 33
-b0 43
-sHdlNone\x20(0) 53
-sHdlNone\x20(0) 63
-b1101 73
-b10 83
-b10 93
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-sSignExt\x20(1) =3
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-sBranch\x20(7) E3
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-sHdlNone\x20(0) J3
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-b10 M3
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-sHdlNone\x20(0) Y3
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-0^3
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-b10 )4
-b10 *4
-b0 +4
-0,4
-sSignExt8\x20(7) -4
-0.4
-1/4
+0P3
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+1$4
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+sSignExt8\x20(7) /4
 004
 114
-s0 24
-b1 34
-b0 44
-sHdlNone\x20(0) 54
-sHdlNone\x20(0) 64
-b1101 74
-b10 84
-b10 94
-b0 :4
-0;4
-sSignExt8\x20(7) <4
-sCmpEqB\x20(10) =4
-s0 >4
-b1 ?4
+024
+134
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+b0 64
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+sHdlNone\x20(0) 84
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+sPhantomConst(\"0..8\") =4
+b0 >4
+sPhantomConst(\"0..8\") ?4
 b0 @4
-sHdlNone\x20(0) A4
-sHdlNone\x20(0) B4
-b1101 C4
-b10 D4
-b10 E4
-b0 F4
+sPhantomConst(\"0..8\") A4
+b0 B4
+sPhantomConst(\"0..8\") C4
+b0 D4
+sPhantomConst(\"0..=8\") E4
+0F4
 0G4
-sSignExt8\x20(7) H4
-sCmpEqB\x20(10) I4
+0H4
+0I4
 s0 J4
 b1 K4
 b0 L4
@@ -9956,118406 +10668,82620 @@ sHdlNone\x20(0) N4
 b1101 O4
 b10 P4
 b10 Q4
-b0 R4
+sSignExt8\x20(7) R4
 0S4
 1T4
-sSLt\x20(3) U4
+0U4
 1V4
-0W4
-1X4
-0Y4
-s0 Z4
-b1 [4
-b0 \4
-sHdlNone\x20(0) ]4
-sHdlNone\x20(0) ^4
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-b10 `4
-b10 a4
-b0 b4
-0c4
-1d4
-sSLt\x20(3) e4
-1f4
-0g4
-1h4
-0i4
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-b1 k4
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+b0 Y4
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 b0 l4
-sHdlNone\x20(0) m4
+0m4
 sHdlNone\x20(0) n4
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-b10 p4
-b10 q4
-b0 r4
-0s4
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-b1 v4
-b0 w4
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 sHdlNone\x20(0) x4
-sHdlNone\x20(0) y4
-b1101 z4
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 b10 {4
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-0~4
-sWidth64Bit\x20(3) !5
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-b10 )5
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-0,5
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+055
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-b1101 <5
-b11 =5
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 b10 >5
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-0B5
-1C5
-0D5
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 sHdlNone\x20(0) J5
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-b11 L5
-b10 M5
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 b0 N5
-0O5
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-0T5
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 b0 V5
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 sHdlNone\x20(0) X5
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 b0 76
-086
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-0D6
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 0H6
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+b0 }6
 b0 ~6
-b10 !7
-b10 "7
-b10100 #7
-b1 $7
-b1101 %7
-sAluBranch\x20(0) &7
-sBranch\x20(7) '7
-s0 (7
-b1 )7
-b0 *7
-sHdlNone\x20(0) +7
-sHdlNone\x20(0) ,7
-b1101 -7
-b11 .7
-b10 /7
-b0 07
-017
-sSignExt8\x20(7) 27
-037
-147
-057
-167
-s0 77
-b1 87
-b0 97
-sHdlNone\x20(0) :7
-sHdlNone\x20(0) ;7
-b1101 <7
-b11 =7
-b10 >7
-b0 ?7
-0@7
-sSignExt8\x20(7) A7
-0B7
-1C7
-0D7
-1E7
-s0 F7
-b1 G7
-b0 H7
-sHdlNone\x20(0) I7
-sHdlNone\x20(0) J7
-b1101 K7
-b11 L7
-b10 M7
-b0 N7
-0O7
-1P7
-1Q7
-1R7
-0S7
-s0 T7
-b1 U7
-b0 V7
-sHdlNone\x20(0) W7
-sHdlNone\x20(0) X7
-b1101 Y7
-b11 Z7
-b10 [7
+sHdlNone\x20(0) !7
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+1'7
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+1)7
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+0+7
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+157
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+177
+087
+097
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+b1000 A7
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+b1101 F7
+b1000000011 G7
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+b100 I7
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+b0 K7
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+b1101 N7
+b1000000011 O7
+sWidth8Bit\x20(0) P7
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+b100 R7
+b0 S7
+b0 T7
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+sHdlNone\x20(0) V7
+b1101 W7
+b11 X7
+b10 Y7
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+sSignExt\x20(1) [7
 b0 \7
-0]7
-sSignExt8\x20(7) ^7
-0_7
-1`7
-0a7
-1b7
-s0 c7
-b1 d7
-b0 e7
-sHdlNone\x20(0) f7
-sHdlNone\x20(0) g7
-b1101 h7
-b11 i7
-b10 j7
-b0 k7
-0l7
-sSignExt8\x20(7) m7
-0n7
-1o7
-0p7
-1q7
-s0 r7
-b1 s7
-b0 t7
-sHdlNone\x20(0) u7
-sHdlNone\x20(0) v7
-b1101 w7
-b11 x7
-b10 y7
-b0 z7
-0{7
-sSignExt8\x20(7) |7
-sCmpEqB\x20(10) }7
-s0 ~7
-b1 !8
-b0 "8
-sHdlNone\x20(0) #8
-sHdlNone\x20(0) $8
-b1101 %8
-b11 &8
-b10 '8
+b10 ]7
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+0x7
+1y7
+0z7
+1{7
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+b1101 #8
+b11 $8
+b10 %8
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+sPhantomConst(\"0..8\") '8
 b0 (8
-0)8
-sSignExt8\x20(7) *8
-sCmpEqB\x20(10) +8
-s0 ,8
-b1 -8
+sPhantomConst(\"0..8\") )8
+b0 *8
+sPhantomConst(\"0..8\") +8
+b0 ,8
+sPhantomConst(\"0..8\") -8
 b0 .8
-sHdlNone\x20(0) /8
-sHdlNone\x20(0) 08
-b1101 18
-b11 28
-b10 38
-b0 48
-058
-168
-sSLt\x20(3) 78
-188
-098
-1:8
-0;8
-s0 <8
-b1 =8
-b0 >8
-sHdlNone\x20(0) ?8
-sHdlNone\x20(0) @8
-b1101 A8
-b11 B8
-b10 C8
-b0 D8
-0E8
-1F8
-sSLt\x20(3) G8
-1H8
+sPhantomConst(\"0..=8\") /8
+008
+018
+028
+038
+s0 48
+b1 58
+b0 68
+sHdlNone\x20(0) 78
+sHdlNone\x20(0) 88
+b1101 98
+b11 :8
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+0=8
+1>8
+0?8
+1@8
+s0 A8
+b1 B8
+b0 C8
+sHdlNone\x20(0) D8
+sHdlNone\x20(0) E8
+b1101 F8
+b1000000011 G8
+sFull64\x20(0) H8
 0I8
-1J8
+0J8
 0K8
-b111 L8
-b1 M8
-b0 N8
-sHdlNone\x20(0) O8
+0L8
+s0 M8
+b1 N8
+b0 O8
 sHdlNone\x20(0) P8
-b1101 Q8
-b11 R8
-b10 S8
-b0 T8
-0U8
-sStore\x20(1) V8
-b11 W8
-b1 X8
+sHdlNone\x20(0) Q8
+b1101 R8
+b11 S8
+b10 T8
+sHdlNone\x20(0) U8
+b0 V8
+0W8
+sHdlNone\x20(0) X8
 b0 Y8
-sHdlNone\x20(0) Z8
-sHdlNone\x20(0) [8
-b1101 \8
-b11 ]8
-b10 ^8
-b0 _8
-0`8
-sWidth64Bit\x20(3) a8
-sSignExt\x20(1) b8
-b11 c8
-b1 d8
-b0 e8
-sHdlNone\x20(0) f8
-sHdlNone\x20(0) g8
-b1101 h8
-b11 i8
-b10 j8
-b0 k8
-0l8
-sWidth64Bit\x20(3) m8
-sSignExt\x20(1) n8
-b1 o8
-b10 p8
-b1010 q8
-b10100 r8
-b1 s8
-b11111111 t8
-b1101 u8
-b1010 v8
-b1010 w8
-b10100 x8
-b1 y8
-b11111111 z8
-b1101 {8
-b1010 |8
-b1010 }8
-b10100 ~8
-b1 !9
-b11111111 "9
-b1101 #9
-b1010 $9
-b1010 %9
-b10100 &9
-b1 '9
-b11111111 (9
-b1101 )9
-b1010 *9
-b1010 +9
-b10100 ,9
-b1 -9
-b11111111 .9
-b1101 /9
-b1010 09
-b1010 19
-b10100 29
-b1 39
-b11111111 49
-b1101 59
-b1010 69
-b1010 79
-b10100 89
-b1 99
-b11111111 :9
+b0 Z8
+0[8
+sFull64\x20(0) \8
+sSignExt32To64BitThenShift\x20(6) ]8
+s0 ^8
+b1 _8
+b0 `8
+sHdlNone\x20(0) a8
+sHdlNone\x20(0) b8
+b1101 c8
+b11 d8
+b10 e8
+sSignExt8\x20(7) f8
+sCmpEqB\x20(10) g8
+s0 h8
+b1 i8
+b0 j8
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+sHdlNone\x20(0) l8
+b1101 m8
+b1000000011 n8
+sFull64\x20(0) o8
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+s0 q8
+b1 r8
+b0 s8
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+b11 w8
+b10 x8
+b0 y8
+1z8
+sSLt\x20(3) {8
+1|8
+0}8
+1~8
+0!9
+s0 "9
+b1 #9
+b0 $9
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+b1101 '9
+b11 (9
+b10 )9
+1*9
+sSLt\x20(3) +9
+1,9
+0-9
+1.9
+0/9
+s0 09
+b1 19
+b0 29
+sHdlNone\x20(0) 39
+sHdlNone\x20(0) 49
+sPowerIsaTimeBaseU\x20(1) 59
+b1000 69
+b1 79
+b0 89
+sHdlNone\x20(0) 99
+sHdlNone\x20(0) :9
 b1101 ;9
-b1010 <9
-b1010 =9
-b10100 >9
+b1000000011 <9
+sLoad\x20(0) =9
+b100 >9
 b1 ?9
-b11111111 @9
-b1101 A9
-b1010 B9
-b101 C9
-b0 D9
-b11111111 E9
-b1101 F9
-b101011001111000 G9
-b10100 H9
-b1 I9
-b110100 J9
-b101011001111000 K9
-1L9
-b0 M9
-b0 N9
-b0 O9
-b0 P9
-b1010 Q9
-b10100 R9
-b1 S9
-b110100 T9
-b101011001111000 U9
-b10100 V9
-b1 W9
-b110100 X9
-b1010 Y9
-b10100 Z9
-b1 [9
-b110100 \9
-b101011001111000 ]9
-b10100 ^9
-b1 _9
-b110100 `9
-b101011001111000 a9
-1b9
-b0 c9
-b0 d9
-b0 e9
-b0 f9
+b0 @9
+sHdlNone\x20(0) A9
+sHdlNone\x20(0) B9
+b1101 C9
+b1000000011 D9
+sWidth8Bit\x20(0) E9
+sZeroExt\x20(0) F9
+b100 G9
+b1 H9
+b0 I9
+sHdlNone\x20(0) J9
+sHdlNone\x20(0) K9
+b1101 L9
+b11 M9
+b10 N9
+sWidth64Bit\x20(3) O9
+sSignExt\x20(1) P9
+b1 Q9
+b10 R9
+b1010 S9
+b10100 T9
+b1 U9
+b11111111 V9
+b1101 W9
+b1010 X9
+b11111111 Y9
+b1101 Z9
+b1010 [9
+b11111111 \9
+b1101 ]9
+b1010 ^9
+b11111111 _9
+b1101 `9
+b1010 a9
+b11111111 b9
+b1101 c9
+b1010 d9
+b11111111 e9
+b1101 f9
 b1010 g9
-b10100 h9
-b1 i9
-b110100 j9
-b101011001111000 k9
-b10100 l9
-b1 m9
-b110100 n9
-b1010 o9
-b10100 p9
-b1 q9
-b110100 r9
-b101011001111000 s9
-b10100 t9
-b1 u9
-b110100 v9
-b101011001111000 w9
-1x9
+b11111111 h9
+b1101 i9
+b1010 j9
+b11111111 k9
+b1101 l9
+b1010 m9
+b101 n9
+b0 o9
+b11111111 p9
+b1101 q9
+b101011001111000 r9
+b10100 s9
+b1 t9
+b110100 u9
+b101011001111000 v9
+1w9
+b0 x9
 b0 y9
 b0 z9
 b0 {9
-b0 |9
-b1010 }9
-b10100 ~9
-b1 !:
+b1010 |9
+b10100 }9
+b1 ~9
+b110100 !:
 b110100 ":
-b101011001111000 #:
-b10100 $:
-b1 %:
+b110100 #:
+b110100 $:
+b0 %:
 b110100 &:
-b1010 ':
-b10100 (:
-b1 ):
-b110100 *:
-b101011001111000 +:
-b10100 ,:
-b1 -:
+b110100 ':
+b110100 (:
+b110100 ):
+b0 *:
+b110100 +:
+b110100 ,:
+b110100 -:
 b110100 .:
-b101011001111000 /:
-10:
-b0 1:
-b0 2:
-b0 3:
-b0 4:
-b1010 5:
-b10100 6:
-b1 7:
-b110100 8:
-b101011001111000 9:
-b10100 ::
-b1 ;:
-b110100 <:
-b1010 =:
-b10100 >:
-b1 ?:
-b110100 @:
-b1010110011110 A:
-b10100 B:
-b1 C:
-b110100 D:
-b101011001111000 E:
-1F:
+b0 /:
+b110100 0:
+b110100 1:
+b110100 2:
+b1010110011110 3:
+b10100 4:
+b1 5:
+b110100 6:
+b101011001111000 7:
+18:
+b0 9:
+b0 ::
+b0 ;:
+b0 <:
+b110100 =:
+b110100 >:
+b110100 ?:
+b0 @:
+b110100 A:
+b110100 B:
+b110100 C:
+b1 D:
+b110100 E:
+b0 F:
 b0 G:
-b0 H:
-b0 I:
-b0 J:
-b1010 K:
-b10100 L:
-b1 M:
+b1 H:
+b110100 I:
+b110100 J:
+b110100 K:
+b110100 L:
+b110100 M:
 b110100 N:
-b1010 O:
-b10100 P:
-b1 Q:
+b0 O:
+b110100 P:
+b110100 Q:
 b110100 R:
-b1010110011110 S:
-b10100 T:
-b1 U:
-b110100 V:
-b101011001111000 W:
-1X:
-b0 Y:
-b0 Z:
-b0 [:
-b0 \:
-b1010 ]:
-b10100 ^:
-b1 _:
+b110100 S:
+b110100 T:
+b110100 U:
+b0 V:
+b110100 W:
+b110100 X:
+b110100 Y:
+b110100 Z:
+b110100 [:
+b1 \:
+b110100 ]:
+b0 ^:
+b0 _:
 b110100 `:
-b1010110011110 a:
-b10100 b:
-b1 c:
+b110100 a:
+b110100 b:
+b110100 c:
 b110100 d:
-b1010 e:
-b10100 f:
-b1 g:
-b110100 h:
-b101011001111000 i:
-b10100 j:
-b1 k:
-b110100 l:
-b101011001111000 m:
-1n:
-b0 o:
-b0 p:
-b0 q:
-b0 r:
-b1010 s:
-b10100 t:
-b1 u:
-b110100 v:
-b101011001111000 w:
-b10100 x:
-b1 y:
-b110100 z:
-b110100 {:
-b1010 |:
-b10100 }:
-b1 ~:
-b110100 !;
-b110100 ";
-b101011001111000 #;
-b10100 $;
-b1 %;
-b110100 &;
-b101011001111000 ';
-1(;
-b0 );
-b0 *;
-b0 +;
-b0 ,;
-b1010 -;
-b10100 .;
-b1 /;
-b110100 0;
-b101011001111000 1;
-b10100 2;
-b1 3;
-b110100 4;
-b110100 5;
-b1010 6;
-b10100 7;
-b1 8;
-b110100 9;
-b110100 :;
-b101011001111000 ;;
-b10100 <;
-b1 =;
-b110100 >;
-b101011001111000 ?;
-1@;
-b0 A;
-b0 B;
-b0 C;
-b0 D;
-b1010 E;
-b10100 F;
-b1 G;
-b110100 H;
-b101011001111000 I;
-b10100 J;
-b1 K;
-b110100 L;
-b110100 M;
-b1010 N;
-b10100 O;
-b1 P;
-b110100 Q;
-b110100 R;
-b1010110011110 S;
-b10100 T;
-b1 U;
-b110100 V;
-b101011001111000 W;
-1X;
-b0 Y;
-b0 Z;
-b0 [;
-b0 \;
-b1010 ];
-b10100 ^;
-b1 _;
-b110100 `;
-b1010110011110 a;
-b10100 b;
-b1 c;
-b110100 d;
-b110100 e;
-b1010 f;
-b10100 g;
-b1 h;
-b110100 i;
-b110100 j;
-b101011001111000 k;
-b10100 l;
-b1 m;
-b110100 n;
-b101011001111000 o;
-1p;
-b0 q;
-b0 r;
-b0 s;
+b101011001111000 e:
+b110100 f:
+b101011001111000 g:
+b0 h:
+b0 i:
+b110100 j:
+0k:
+b101011001 l:
+b10100 m:
+b1 n:
+b1010 o:
+b10100 p:
+b1 q:
+sHdlNone\x20(0) r:
+sHdlNone\x20(0) s:
+sHdlNone\x20(0) t:
+sHdlSome\x20(1) u:
+sHdlSome\x20(1) v:
+sHdlNone\x20(0) w:
+sHdlSome\x20(1) x:
+sHdlSome\x20(1) y:
+sHdlNone\x20(0) z:
+sHdlSome\x20(1) {:
+sHdlNone\x20(0) |:
+sHdlNone\x20(0) }:
+sHdlNone\x20(0) ~:
+sHdlSome\x20(1) !;
+sHdlSome\x20(1) ";
+sHdlNone\x20(0) #;
+sHdlSome\x20(1) $;
+sHdlSome\x20(1) %;
+sHdlNone\x20(0) &;
+sHdlNone\x20(0) ';
+sHdlNone\x20(0) (;
+sHdlNone\x20(0) );
+sHdlSome\x20(1) *;
+sHdlSome\x20(1) +;
+sHdlNone\x20(0) ,;
+sHdlSome\x20(1) -;
+sHdlSome\x20(1) .;
+sHdlNone\x20(0) /;
+sHdlNone\x20(0) 0;
+sHdlNone\x20(0) 1;
+sHdlSome\x20(1) 2;
+sHdlSome\x20(1) 3;
+sHdlNone\x20(0) 4;
+sHdlSome\x20(1) 5;
+sHdlSome\x20(1) 6;
+sHdlNone\x20(0) 7;
+sHdlNone\x20(0) 8;
+sHdlNone\x20(0) 9;
+sHdlSome\x20(1) :;
+sHdlSome\x20(1) ;;
+sHdlNone\x20(0) <;
+sHdlSome\x20(1) =;
+sHdlSome\x20(1) >;
+sHdlNone\x20(0) ?;
+sHdlNone\x20(0) @;
+sHdlNone\x20(0) A;
+sHdlSome\x20(1) B;
+sHdlSome\x20(1) C;
+sHdlNone\x20(0) D;
+sHdlSome\x20(1) E;
+sHdlSome\x20(1) F;
+sHdlNone\x20(0) G;
+sHdlNone\x20(0) H;
+sHdlNone\x20(0) I;
+sHdlSome\x20(1) J;
+sHdlSome\x20(1) K;
+sHdlNone\x20(0) L;
+sHdlSome\x20(1) M;
+sHdlSome\x20(1) N;
+sHdlNone\x20(0) O;
+sHdlNone\x20(0) P;
+sHdlNone\x20(0) Q;
+sHdlSome\x20(1) R;
+sHdlSome\x20(1) S;
+sHdlNone\x20(0) T;
+sHdlSome\x20(1) U;
+sHdlSome\x20(1) V;
+sHdlNone\x20(0) W;
+sHdlNone\x20(0) X;
+sHdlNone\x20(0) Y;
+sHdlSome\x20(1) Z;
+sHdlSome\x20(1) [;
+sHdlNone\x20(0) \;
+sHdlSome\x20(1) ];
+sHdlSome\x20(1) ^;
+sHdlNone\x20(0) _;
+sHdlNone\x20(0) `;
+sHdlNone\x20(0) a;
+sHdlSome\x20(1) b;
+sHdlSome\x20(1) c;
+sHdlNone\x20(0) d;
+sHdlSome\x20(1) e;
+sHdlSome\x20(1) f;
+sHdlNone\x20(0) g;
+sHdlNone\x20(0) h;
+sHdlNone\x20(0) i;
+sHdlSome\x20(1) j;
+sHdlSome\x20(1) k;
+sHdlNone\x20(0) l;
+sHdlSome\x20(1) m;
+sHdlSome\x20(1) n;
+1o;
+b0 p;
+sS64\x20(1) q;
+b11111111 r;
+1s;
 b0 t;
-b101011001111000 u;
-b10100 v;
-b1 w;
-b110100 x;
-0y;
-b101011001 z;
-b10100 {;
-b1 |;
-b1010 };
-b10100 ~;
-b1 !<
-sHdlNone\x20(0) "<
+sS64\x20(1) u;
+b11111111 v;
+b101011001111000 w;
+sU64\x20(0) x;
+b11111111 y;
+sU64\x20(0) z;
+b11111111 {;
+sCmpRBTwo\x20(9) |;
+b11111111 };
+b11111111 ~;
+sHdlSome\x20(1) !<
+sHdlSome\x20(1) "<
 sHdlNone\x20(0) #<
-b1010 $<
-b10100 %<
-b1 &<
+sHdlNone\x20(0) $<
+sHdlNone\x20(0) %<
+sHdlNone\x20(0) &<
 sHdlNone\x20(0) '<
 sHdlSome\x20(1) (<
-b1010 )<
-b10100 *<
-b1 +<
+sHdlNone\x20(0) )<
+sHdlSome\x20(1) *<
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 sHdlSome\x20(1) ,<
 sHdlNone\x20(0) -<
-b1010 .<
-b10100 /<
-b1 0<
-sHdlSome\x20(1) 1<
+sHdlSome\x20(1) .<
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+sHdlSome\x20(1) 0<
+sHdlNone\x20(0) 1<
 sHdlSome\x20(1) 2<
-b101011001111000 3<
-b10100 4<
-b1 5<
-sHdlNone\x20(0) 6<
-b101011001111000 7<
-b10100 8<
-b1 9<
+sHdlNone\x20(0) 3<
+sHdlSome\x20(1) 4<
+sHdlNone\x20(0) 5<
+sHdlSome\x20(1) 6<
+sHdlNone\x20(0) 7<
+sHdlSome\x20(1) 8<
+sHdlNone\x20(0) 9<
 sHdlSome\x20(1) :<
-b1010 ;<
-b10100 <<
-b1 =<
-sHdlNone\x20(0) ><
-sHdlNone\x20(0) ?<
-b1010 @<
-b10100 A<
-b1 B<
-sHdlNone\x20(0) C<
-sHdlSome\x20(1) D<
-b1010 E<
-b10100 F<
-b1 G<
-sHdlSome\x20(1) H<
-sHdlNone\x20(0) I<
-b1010 J<
-b10100 K<
-b1 L<
-sHdlSome\x20(1) M<
-sHdlSome\x20(1) N<
-b101011001111000 O<
-b10100 P<
-b1 Q<
-sHdlNone\x20(0) R<
-b1010 S<
-b10100 T<
-b1 U<
-sHdlNone\x20(0) V<
-sHdlNone\x20(0) W<
-b1010 X<
-b10100 Y<
-b1 Z<
-sHdlNone\x20(0) [<
-sHdlSome\x20(1) \<
-b1010 ]<
-b10100 ^<
-b1 _<
-sHdlSome\x20(1) `<
-sHdlNone\x20(0) a<
-b1010 b<
-b10100 c<
-b1 d<
-sHdlSome\x20(1) e<
-sHdlSome\x20(1) f<
-b1010 g<
-b10100 h<
-b1 i<
-sHdlNone\x20(0) j<
-sHdlNone\x20(0) k<
-b1010 l<
-b10100 m<
-b1 n<
-sHdlNone\x20(0) o<
-sHdlSome\x20(1) p<
-b1010 q<
-b10100 r<
-b1 s<
-sHdlSome\x20(1) t<
-sHdlNone\x20(0) u<
-b1010 v<
-b10100 w<
-b1 x<
-sHdlSome\x20(1) y<
-sHdlSome\x20(1) z<
-b1010 {<
-b10100 |<
-b1 }<
-sHdlNone\x20(0) ~<
-sHdlNone\x20(0) !=
-b1010 "=
-b10100 #=
-b1 $=
-sHdlNone\x20(0) %=
-sHdlSome\x20(1) &=
-b1010 '=
-b10100 (=
-b1 )=
-sHdlSome\x20(1) *=
-sHdlNone\x20(0) +=
-b1010 ,=
-b10100 -=
-b1 .=
-sHdlSome\x20(1) /=
-sHdlSome\x20(1) 0=
-b1010 1=
-b10100 2=
-b1 3=
-sHdlNone\x20(0) 4=
-sHdlNone\x20(0) 5=
-b1010 6=
-b10100 7=
-b1 8=
-sHdlNone\x20(0) 9=
-sHdlSome\x20(1) :=
-b1010 ;=
-b10100 <=
-b1 ==
-sHdlSome\x20(1) >=
-sHdlNone\x20(0) ?=
-b1010 @=
-b10100 A=
-b1 B=
-sHdlSome\x20(1) C=
-sHdlSome\x20(1) D=
-b10100 E=
-b1 F=
-sHdlNone\x20(0) G=
-sHdlNone\x20(0) H=
-b10100 I=
-b1 J=
-sHdlNone\x20(0) K=
-sHdlSome\x20(1) L=
-b10100 M=
-b1 N=
-sHdlSome\x20(1) O=
-sHdlNone\x20(0) P=
-b10100 Q=
-b1 R=
-sHdlSome\x20(1) S=
-sHdlSome\x20(1) T=
-b10100 U=
-b1 V=
-sHdlNone\x20(0) W=
-sHdlNone\x20(0) X=
-b10100 Y=
-b1 Z=
-sHdlNone\x20(0) [=
-sHdlSome\x20(1) \=
-b10100 ]=
-b1 ^=
+sHdlNone\x20(0) ;<
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+b1 A<
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+b11 D<
+b100 E<
+sHdlSome\x20(1) F<
+b11 G<
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+0I<
+b0 J<
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+b111001 L<
+b111100 M<
+b11 N<
+b100 O<
+sHdlSome\x20(1) P<
+b11 Q<
+b100 R<
+0S<
+b0 T<
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+b1010 V<
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+b100 Z<
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+b11 \<
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+0^<
+sHdlNone\x20(0) _<
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+b111100 a<
+b11 b<
+b100 c<
+sHdlSome\x20(1) d<
+b11 e<
+b100 f<
+0g<
+sHdlSome\x20(1) h<
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+1p<
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+b11 u<
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+sHdlSome\x20(1) w<
+b11 x<
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+1z<
+b110100 {<
+sHdlSome\x20(1) |<
+b110011 }<
+b10100 ~<
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+b1 "=
+b111001 #=
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+b0 %=
+b111 &=
+sHdlSome\x20(1) '=
+b0 (=
+b111 )=
+0*=
+b0 +=
+sHdlNone\x20(0) ,=
+b111001 -=
+b111111 .=
+b0 /=
+b111 0=
+sHdlSome\x20(1) 1=
+b0 2=
+b111 3=
+04=
+b0 5=
+sHdlSome\x20(1) 6=
+b110011 7=
+b0 8=
+b111001 9=
+b110 :=
+b111010 ;=
+sHdlSome\x20(1) <=
+b110 ==
+b111010 >=
+0?=
+b0 @=
+sHdlNone\x20(0) A=
+b0 B=
+b111001 C=
+b110 D=
+b111010 E=
+sHdlSome\x20(1) F=
+b110 G=
+b111010 H=
+0I=
+b0 J=
+sHdlSome\x20(1) K=
+b111001 L=
+b110101 M=
+b1010 N=
+b111101 O=
+sHdlSome\x20(1) P=
+b1010 Q=
+b111101 R=
+0S=
+b0 T=
+sHdlNone\x20(0) U=
+b111001 V=
+b110101 W=
+b1010 X=
+b111101 Y=
+sHdlSome\x20(1) Z=
+b1010 [=
+b111101 \=
+0]=
+b0 ^=
 sHdlSome\x20(1) _=
-sHdlNone\x20(0) `=
-b10100 a=
-b1 b=
-sHdlSome\x20(1) c=
-sHdlSome\x20(1) d=
-b10100 e=
-b1 f=
-sHdlNone\x20(0) g=
-sHdlNone\x20(0) h=
-b10100 i=
-b1 j=
-sHdlNone\x20(0) k=
-sHdlSome\x20(1) l=
-b10100 m=
-b1 n=
-sHdlSome\x20(1) o=
-sHdlNone\x20(0) p=
-b10100 q=
-b1 r=
-sHdlSome\x20(1) s=
-sHdlSome\x20(1) t=
-b10100 u=
-b1 v=
-sHdlNone\x20(0) w=
-sHdlNone\x20(0) x=
-b10100 y=
-b1 z=
-sHdlNone\x20(0) {=
-sHdlSome\x20(1) |=
-b10100 }=
-b1 ~=
-sHdlSome\x20(1) !>
-sHdlNone\x20(0) ">
-b10100 #>
-b1 $>
-sHdlSome\x20(1) %>
+b110011 `=
+b1010 a=
+b10100 b=
+b1 c=
+b111001 d=
+b111111 e=
+b0 f=
+b111 g=
+sHdlSome\x20(1) h=
+b0 i=
+b111 j=
+0k=
+sHdlNone\x20(0) l=
+b111001 m=
+b111111 n=
+b0 o=
+b111 p=
+sHdlSome\x20(1) q=
+b0 r=
+b111 s=
+0t=
+sHdlSome\x20(1) u=
+b110011 v=
+b0 w=
+b111001 x=
+b110 y=
+b111010 z=
+sHdlSome\x20(1) {=
+b110 |=
+b111010 }=
+0~=
+sHdlNone\x20(0) !>
+b0 ">
+b111001 #>
+b110 $>
+b111010 %>
 sHdlSome\x20(1) &>
-b10100 '>
-b1 (>
-sHdlNone\x20(0) )>
-sHdlNone\x20(0) *>
-b10100 +>
-b1 ,>
-sHdlNone\x20(0) ->
-sHdlSome\x20(1) .>
-b10100 />
-b1 0>
-sHdlSome\x20(1) 1>
-sHdlNone\x20(0) 2>
-b10100 3>
-b1 4>
-sHdlSome\x20(1) 5>
-sHdlSome\x20(1) 6>
-b101011001111000 7>
-b10100 8>
-19>
-b0 :>
-sS64\x20(1) ;>
-b11111111 <>
-b1010 =>
-b10100 >>
-1?>
-b0 @>
-sS64\x20(1) A>
-b11111111 B>
-b101011001111000 C>
-b10100 D>
-1E>
-b0 F>
-sU64\x20(0) G>
-b11111111 H>
-b1010 I>
+b110 '>
+b111010 (>
+0)>
+sHdlSome\x20(1) *>
+b111001 +>
+b110101 ,>
+b1010 ->
+b111101 .>
+sHdlSome\x20(1) />
+b1010 0>
+b111101 1>
+12>
+b110100 3>
+sHdlNone\x20(0) 4>
+b111001 5>
+b110101 6>
+b1010 7>
+b111101 8>
+sHdlSome\x20(1) 9>
+b1010 :>
+b111101 ;>
+1<>
+b110100 =>
+sHdlSome\x20(1) >>
+sHdlNone\x20(0) ?>
+sHdlSome\x20(1) @>
+sHdlNone\x20(0) A>
+sHdlSome\x20(1) B>
+b1010 C>
+sHdlNone\x20(0) D>
+sHdlSome\x20(1) E>
+sHdlNone\x20(0) F>
+sHdlSome\x20(1) G>
+sHdlNone\x20(0) H>
+sHdlSome\x20(1) I>
 b10100 J>
-1K>
-b0 L>
-sU64\x20(0) M>
-b11111111 N>
-b1010 O>
-b10100 P>
-1Q>
-b0 R>
-sCmpRBTwo\x20(9) S>
-b11111111 T>
-b1010 U>
-b10100 V>
-b0 W>
-b11111111 X>
-b101011001111000 Y>
-b10100 Z>
-b1 [>
-sHdlSome\x20(1) \>
-b101011001111000 ]>
-b10100 ^>
-b1 _>
-sHdlSome\x20(1) `>
-b101011001111000 a>
-b10100 b>
-b1 c>
-sHdlNone\x20(0) d>
-b101011001111000 e>
-b10100 f>
-b1 g>
-sHdlNone\x20(0) h>
-b101011001111000 i>
-b10100 j>
-b1 k>
-sHdlNone\x20(0) l>
-b101011001111000 m>
-b10100 n>
-b1 o>
-sHdlNone\x20(0) p>
-b1010 q>
-b10100 r>
-b1 s>
-sHdlNone\x20(0) t>
-b1010 u>
-b10100 v>
-b1 w>
-sHdlSome\x20(1) x>
-b1010 y>
-b10100 z>
-b1 {>
-sHdlNone\x20(0) |>
-b1010 }>
-b10100 ~>
-b1 !?
-sHdlSome\x20(1) "?
-b1010 #?
-b10100 $?
-b1 %?
-sHdlNone\x20(0) &?
-b1010 '?
-b10100 (?
-b1 )?
-sHdlSome\x20(1) *?
-b1010 +?
-b10100 ,?
-b1 -?
-sHdlNone\x20(0) .?
-b1010 /?
-b10100 0?
-b1 1?
-sHdlSome\x20(1) 2?
-b1010 3?
-b10100 4?
-b1 5?
-sHdlNone\x20(0) 6?
-b1010 7?
-b10100 8?
-b1 9?
-sHdlSome\x20(1) :?
-b1010 ;?
-b10100 <?
-b1 =?
-sHdlNone\x20(0) >?
-b1010 ??
-b10100 @?
-b1 A?
-sHdlSome\x20(1) B?
-b1010 C?
-b10100 D?
-b1 E?
-sHdlNone\x20(0) F?
-b1010 G?
-b10100 H?
-b1 I?
-sHdlSome\x20(1) J?
-b1010 K?
-b10100 L?
-b1 M?
-sHdlNone\x20(0) N?
-b1010 O?
-b10100 P?
-b1 Q?
-sHdlSome\x20(1) R?
-b10100 S?
-b1 T?
-sHdlNone\x20(0) U?
-b10100 V?
-b1 W?
-sHdlSome\x20(1) X?
-b10100 Y?
-b1 Z?
-sHdlNone\x20(0) [?
-b10100 \?
-b1 ]?
-sHdlSome\x20(1) ^?
-b10100 _?
-b1 `?
-sHdlNone\x20(0) a?
-b10100 b?
-b1 c?
-sHdlSome\x20(1) d?
-b0 e?
-b11111111 f?
+b10100 K>
+b1 L>
+sHdlNone\x20(0) M>
+sHdlSome\x20(1) N>
+sHdlNone\x20(0) O>
+sHdlSome\x20(1) P>
+sHdlNone\x20(0) Q>
+sHdlSome\x20(1) R>
+sHdlNone\x20(0) S>
+sHdlSome\x20(1) T>
+b1010001010 U>
+b1 V>
+b101010100 W>
+b1 X>
+b101010100 Y>
+b11111111 Z>
+b1010001010 [>
+b101010100 \>
+b101010100 ]>
+b101010100 ^>
 $end
 #1000000
-00
-0?
-0\
-0k
-sU64\x20(0) x
-sU64\x20(0) &"
-04"
-0D"
-b1001000001101000101011001111010 C&
-b101011001111010 G9
-b101011001111010 K9
-b101011001111010 U9
-b101011001111010 ]9
-b101011001111010 a9
-b101011001111010 k9
-b101011001111010 s9
-b101011001111010 w9
-b101011001111010 #:
-b101011001111010 +:
-b101011001111010 /:
-b101011001111010 9:
-b101011001111010 E:
-b101011001111010 W:
-b101011001111010 i:
-b101011001111010 m:
-b101011001111010 w:
-b101011001111010 #;
-b101011001111010 ';
-b101011001111010 1;
-b101011001111010 ;;
-b101011001111010 ?;
-b101011001111010 I;
-b101011001111010 W;
-b101011001111010 k;
-b101011001111010 o;
-b101011001111010 u;
-b101011001111010 3<
-b101011001111010 7<
-b101011001111010 O<
-b101011001111010 7>
-b101011001111010 C>
-b101011001111010 Y>
-b101011001111010 ]>
-b101011001111010 a>
-b101011001111010 e>
-b101011001111010 i>
-b101011001111010 m>
+0/
+0<
+0_
+sU64\x20(0) )"
+0?"
+0M"
+b1001000001101000101011001111010 X&
+b101011001111010 r9
+b101011001111010 v9
+b101011001111010 7:
+b101011001111010 e:
+b101011001111010 g:
+b101011001111010 w;
+b11101 =<
+b111101 C<
+b10 D<
+b101 E<
+b10 G<
+b101 H<
+b111101 M<
+b10 N<
+b101 O<
+b10 Q<
+b101 R<
+b111101 X<
+b10 Y<
+b101 Z<
+b10 \<
+b101 ]<
+b111101 a<
+b10 b<
+b101 c<
+b10 e<
+b101 f<
+b111101 j<
+b10 k<
+b101 l<
+b10 n<
+b101 o<
+b111101 t<
+b10 u<
+b101 v<
+b10 x<
+b101 y<
+b10101 ~<
+b10101 M=
+b101010 N=
+b11101 O=
+b101010 Q=
+b11101 R=
+b10101 W=
+b101010 X=
+b11101 Y=
+b101010 [=
+b11101 \=
+b10101 ,>
+b101010 ->
+b11101 .>
+b101010 0>
+b11101 1>
+b10101 6>
+b101010 7>
+b11101 8>
+b101010 :>
+b11101 ;>
+b10101 J>
 #2000000
 b1 $
+1/
 10
-11
-b1 3
-1?
-1@
-b1 B
-b1 P
-1\
-1]
-b1 _
-1k
-1l
+b1 2
+1<
+1=
+b1 ?
+b1 U
+1_
+1`
+b1 b
 b1 n
-s<invalid>\x20(12) x
-b1 z
-s<invalid>\x20(12) &"
-b1 ("
-14"
-15"
-b1 8"
-1D"
-1E"
-b1 H"
-b1 S"
+b1 !"
+s<invalid>\x20(12) )"
+b1 +"
+b1 4"
+1?"
+1@"
+b1 C"
+1M"
+1N"
+b1 Q"
+b1 W"
 b1 _"
-b1001000001101000101011001111001 C&
-b101011001111001 G9
-b101011001111001 K9
-b101011001111001 U9
-b101011001111001 ]9
-b101011001111001 a9
-b101011001111001 k9
-b101011001111001 s9
-b101011001111001 w9
-b101011001111001 #:
-b101011001111001 +:
-b101011001111001 /:
-b101011001111001 9:
-b101011001111001 E:
-b101011001111001 W:
-b101011001111001 i:
-b101011001111001 m:
-b101011001111001 w:
-b101011001111001 #;
-b101011001111001 ';
-b101011001111001 1;
-b101011001111001 ;;
-b101011001111001 ?;
-b101011001111001 I;
-b101011001111001 W;
-b101011001111001 k;
-b101011001111001 o;
-b101011001111001 u;
-1y;
-b101011001111001 3<
-b101011001111001 7<
-b101011001111001 O<
-b101011001111001 7>
-b101011001111001 C>
-b101011001111001 Y>
-b101011001111001 ]>
-b101011001111001 a>
-b101011001111001 e>
-b101011001111001 i>
-b101011001111001 m>
+b1 h"
+b1001000001101000101011001111001 X&
+b101011001111001 r9
+b101011001111001 v9
+b101011001111001 7:
+b101011001111001 e:
+b101011001111001 g:
+1k:
+b101011001111001 w;
+b11100 =<
+b111100 C<
+b11 D<
+b100 E<
+b11 G<
+b100 H<
+b111100 M<
+b11 N<
+b100 O<
+b11 Q<
+b100 R<
+b111100 X<
+b11 Y<
+b100 Z<
+b11 \<
+b100 ]<
+b111100 a<
+b11 b<
+b100 c<
+b11 e<
+b100 f<
+b111100 j<
+b11 k<
+b100 l<
+b11 n<
+b100 o<
+b111100 t<
+b11 u<
+b100 v<
+b11 x<
+b100 y<
+b10100 ~<
+b110101 M=
+b1010 N=
+b111101 O=
+b1010 Q=
+b111101 R=
+b110101 W=
+b1010 X=
+b111101 Y=
+b1010 [=
+b111101 \=
+b110101 ,>
+b1010 ->
+b111101 .>
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+b1010 :>
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-b101011001111011 K9
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 #4000000
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-b11111111 d*
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+b100 e,
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+b100100011010000000010 z,
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+b10010001101000000001000000000 (-
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+b0 5.
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-b11111111 x/
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-b11111111 70
-b11111111 F0
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-b11111111 }0
-b11111111 /1
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-b11111111 F1
-b0 P1
-b0 Q1
-b11111111 R1
-b11111111 Z1
-b11111111 i1
+b11111111 }.
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 b11111111 x1
-b11111111 (2
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+b11111111 )2
 b11111111 72
-b11111111 F2
-b11111111 R2
-b11111111 ^2
-b11111111 n2
-b11111111 ~2
-b11111111 +3
-b11111111 73
-b0 A3
-b0 B3
-b11111111 C3
-b11111111 K3
-b11111111 Z3
-b11111111 i3
-b11111111 w3
-b11111111 (4
-b11111111 74
-b11111111 C4
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 b11111111 O4
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-b11111111 o4
-b11111111 z4
-b11111111 (5
-b0 25
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 b11111111 ;9
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-b1001000110100 G9
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-b0 B:
-b0 C:
-b0 D:
-b1001000110100 E:
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-b10 K:
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-b0 M:
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-b0 R:
-b10010001101 S:
-b0 T:
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-b10 ]:
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-b1001000110100 #;
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-b0 38
-068
-sSGt\x20(4) 78
-b1001 A8
-b0 C8
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-sSGt\x20(4) G8
-b1001 Q8
-b0 S8
-b1001 \8
-b0 ^8
-sWidth8Bit\x20(0) a8
-b1001 h8
-b0 j8
-sWidth8Bit\x20(0) m8
-b0 p8
-b10100 q8
-b101 r8
-b1111 s8
-b1011 t8
-b1001 u8
-b1101 v8
-b10100 w8
-b101 x8
-b1111 y8
-b1011 z8
-b1001 {8
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-b10100 }8
-b101 ~8
-b1111 !9
-b1011 "9
-b1001 #9
-b1101 $9
-b10100 %9
-b101 &9
-b1111 '9
-b1011 (9
-b1001 )9
-b1101 *9
-b10100 +9
-b101 ,9
-b1111 -9
-b1011 .9
-b1001 /9
-b1101 09
-b10100 19
-b101 29
-b1111 39
-b1011 49
-b1001 59
-b1101 69
-b10100 79
-b101 89
-b1111 99
-b1011 :9
-b1001 ;9
-b1101 <9
-b10100 =9
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-b1111 ?9
-b1011 @9
-b1001 A9
-b1101 B9
-b1 C9
-b11 D9
-b1011 E9
-b1001 F9
-b1010001000000010 G9
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-b1111 I9
-b100101 J9
-b11010001000000010 K9
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-b101 R9
-b1111 S9
-b100101 T9
-b1010001000000010 U9
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-b1111 W9
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-b1010001000000010 +:
-b101 ,:
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-b100101 8:
-b1010001000000010 9:
-b101 ::
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-b100101 <:
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-b10100010000000 A:
-b101 B:
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-sDupLow32\x20(1) 96
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-b1001 18
-b0 38
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-b1001 59
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-b1001 M-
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-b1001 X-
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-sWidth8Bit\x20(0) ]-
-b1001 d-
-b0 f-
-b1111111111010001101000000 g-
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-sWidth8Bit\x20(0) i-
-b0 l-
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-b101 n-
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-sWidth8Bit\x20(0) Z/
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-b0 ^/
-b101 _/
-b1111 `/
-b1001 a/
-b1001 i/
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-b0 z/
-sFull64\x20(0) }/
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-b1001 )0
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-b1001 70
-b0 90
-sFull64\x20(0) <0
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-b1001 F0
-b0 H0
-sFull64\x20(0) K0
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-b1001 U0
-b0 W0
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-sCmpRBTwo\x20(9) [0
-b1001 a0
-b0 c0
-sFull64\x20(0) f0
-sCmpRBTwo\x20(9) g0
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-b0 !1
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-b1001 /1
-b0 11
-b1001 :1
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-sWidth8Bit\x20(0) ?1
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-sWidth8Bit\x20(0) K1
-b0 N1
-b0 O1
-b101 P1
-b1111 Q1
-b1001 R1
-b1001 Z1
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-sFull64\x20(0) <4
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-b1001 C4
-b0 E4
-sFull64\x20(0) H4
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-b1001 O4
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-sWidth8Bit\x20(0) !5
-b1001 (5
-b0 *5
-sWidth8Bit\x20(0) -5
-b0 05
-b0 15
-b101 25
-b1111 35
-b1001 45
-b1001 <5
-b0 >5
-sFull64\x20(0) A5
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-b1001 K5
-b0 M5
-sFull64\x20(0) P5
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-b1001 Z5
-b0 \5
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-b1001 h5
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-b1001 w5
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-sFull64\x20(0) |5
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-b1001 (6
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-sFull64\x20(0) -6
-sS64\x20(1) .6
-b1001 46
-b0 66
-sFull64\x20(0) 96
-sS64\x20(1) :6
-b1001 @6
-b0 B6
-0E6
-0G6
-b1001 P6
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-0U6
-0W6
-b1001 `6
-b0 b6
-b1001 k6
-b0 m6
-sWidth8Bit\x20(0) p6
-b1001 w6
-b0 y6
-sWidth8Bit\x20(0) |6
-b0 !7
-b0 "7
-b101 #7
-b1111 $7
-b1001 %7
-b1001 -7
-b0 /7
-sFull64\x20(0) 27
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-b1001 <7
-b0 >7
-sFull64\x20(0) A7
-0C7
-b1001 K7
-b0 M7
-0P7
-b1001 Y7
-b0 [7
-sFull64\x20(0) ^7
-0`7
-b1001 h7
-b0 j7
-sFull64\x20(0) m7
-0o7
-b1001 w7
-b0 y7
-sFull64\x20(0) |7
-sCmpRBTwo\x20(9) }7
-b1001 %8
-b0 '8
-sFull64\x20(0) *8
-sCmpRBTwo\x20(9) +8
-b1001 18
-b0 38
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-b1001 A8
-b0 C8
-0F8
-0H8
-b1001 Q8
-b0 S8
-b1001 \8
-b0 ^8
-sWidth8Bit\x20(0) a8
-b1001 h8
-b0 j8
-sWidth8Bit\x20(0) m8
-b0 p8
-b10100 q8
-b101 r8
-b1111 s8
-b1011 t8
-b1001 u8
-b1101 v8
-b10100 w8
-b101 x8
-b1111 y8
-b1011 z8
-b1001 {8
-b1101 |8
-b10100 }8
-b101 ~8
-b1111 !9
-b1011 "9
-b1001 #9
-b1101 $9
-b10100 %9
-b101 &9
-b1111 '9
-b1011 (9
-b1001 )9
-b1101 *9
-b10100 +9
-b101 ,9
-b1111 -9
-b1011 .9
-b1001 /9
-b1101 09
-b10100 19
-b101 29
-b1111 39
-b1011 49
-b1001 59
-b1101 69
-b10100 79
-b101 89
-b1111 99
-b1011 :9
-b1001 ;9
-b1101 <9
-b10100 =9
-b101 >9
-b1111 ?9
-b1011 @9
-b1001 A9
-b1101 B9
-b1 C9
-b11 D9
-b1011 E9
-b1001 F9
-b1010001101000010 G9
-b101 H9
-b1111 I9
-b100101 J9
-b11010001101000010 K9
-b10100 Q9
-b101 R9
-b1111 S9
-b100101 T9
-b1010001101000010 U9
-b101 V9
-b1111 W9
-b100101 X9
-b10100 Y9
-b101 Z9
-b1111 [9
-b100101 \9
-b1010001101000010 ]9
-b101 ^9
-b1111 _9
-b100101 `9
-b11010001101000010 a9
-b10100 g9
-b101 h9
-b1111 i9
-b100101 j9
-b1010001101000010 k9
-b101 l9
-b1111 m9
-b100101 n9
-b10100 o9
-b101 p9
-b1111 q9
-b100101 r9
-b1010001101000010 s9
-b101 t9
-b1111 u9
-b100101 v9
-b11010001101000010 w9
-b10100 }9
-b101 ~9
-b1111 !:
-b100101 ":
-b1010001101000010 #:
-b101 $:
-b1111 %:
-b100101 &:
-b10100 ':
-b101 (:
-b1111 ):
-b100101 *:
-b1010001101000010 +:
-b101 ,:
-b1111 -:
-b100101 .:
-b11010001101000010 /:
-b10100 5:
-b101 6:
-b1111 7:
-b100101 8:
-b1010001101000010 9:
-b101 ::
-b1111 ;:
-b100101 <:
-b10100 =:
-b101 >:
-b1111 ?:
-b100101 @:
-b10100011010000 A:
-b101 B:
-b1111 C:
-b100101 D:
-b11010001101000010 E:
-b10100 K:
-b101 L:
-b1111 M:
-b100101 N:
-b10100 O:
-b101 P:
-b1111 Q:
-b100101 R:
-b10100011010000 S:
-b101 T:
-b1111 U:
-b100101 V:
-b11010001101000010 W:
-b10100 ]:
-b101 ^:
-b1111 _:
-b100101 `:
-b10100011010000 a:
-b101 b:
-b1111 c:
-b100101 d:
-b10100 e:
-b101 f:
-b1111 g:
-b100101 h:
-b1010001101000010 i:
-b101 j:
-b1111 k:
-b100101 l:
-b11010001101000010 m:
-b10100 s:
-b101 t:
-b1111 u:
-b100101 v:
-b1010001101000010 w:
-b101 x:
-b1111 y:
-b100101 z:
-b100101 {:
-b10100 |:
-b101 }:
-b1111 ~:
-b100101 !;
-b100101 ";
-b1010001101000010 #;
-b101 $;
-b1111 %;
-b100101 &;
-b11010001101000010 ';
-b10100 -;
-b101 .;
-b1111 /;
-b100101 0;
-b1010001101000010 1;
-b101 2;
-b1111 3;
-b100101 4;
-b100101 5;
-b10100 6;
-b101 7;
-b1111 8;
-b100101 9;
-b100101 :;
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-b101 <;
-b1111 =;
-b100101 >;
-b11010001101000010 ?;
-b10100 E;
-b101 F;
-b1111 G;
-b100101 H;
-b1010001101000010 I;
-b101 J;
-b1111 K;
-b100101 L;
-b100101 M;
-b10100 N;
-b101 O;
-b1111 P;
-b100101 Q;
-b100101 R;
-b10100011010000 S;
-b101 T;
-b1111 U;
-b100101 V;
-b11010001101000010 W;
-b10100 ];
-b101 ^;
-b1111 _;
-b100101 `;
-b10100011010000 a;
-b101 b;
-b1111 c;
-b100101 d;
-b100101 e;
-b10100 f;
-b101 g;
-b1111 h;
-b100101 i;
-b100101 j;
-b1010001101000010 k;
-b101 l;
-b1111 m;
-b100101 n;
-b11010001101000010 o;
-b1010001101000010 u;
-b101 v;
-b1111 w;
-b100101 x;
-b1010001101 z;
-b101 {;
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-b101 ~;
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-b11111111 8
-b11111111 9
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-b11111111 F
-b11111111 G
-b11111111 H
-b1111000110111 I
-b11111111 P
-b11111111 T
-b11111111 U
-b11111111 V
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-b11111111 _
-b11111111 c
-b11111111 d
-b11111111 e
-b1111000110111 f
-b11111111 n
-b11111111 r
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-b11111111 t
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-b11111111 z
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-b11111111 !"
-b11111111 ""
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-b11111111 ,"
-b11111111 -"
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-b11111111 <"
-b11111111 ="
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-b11111111 L"
-b11111111 M"
-b11111111 N"
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-b11111111 S"
-b11111111 W"
-b11111111 X"
-b11111111 Y"
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-b11111111 _"
-b11111111 c"
-b11111111 d"
-b11111111 e"
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-b1001100000000010001001101000010 C&
-b100010011010000 G&
-b100010011010000 H&
-b100010011010000 I&
-b100010011010000 J&
-b10011010000 K&
-b1 L&
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-b10 X&
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-b10 g&
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-b10 D'
-b1001101000000 E'
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-b1001101000000 6)
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-sDupLow32\x20(1) 8)
-sS32\x20(3) 9)
-b11111111 ?)
-b10 A)
-b1001101000000 B)
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-sDupLow32\x20(1) D)
-sS32\x20(3) E)
-b11111111 K)
-b10 M)
-b1001101000000 N)
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-1R)
-b11111111 [)
-b10 ])
-b1001101000000 ^)
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-b11111111 k)
-b10 m)
-b1001101000000 n)
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-b11111111 v)
-b10 x)
-b1001101000000 y)
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-sWidth16Bit\x20(1) {)
-b11111111 $*
-b10 &*
-b1001101000000 '*
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-sWidth16Bit\x20(1) )*
-b10 ,*
-b10011010000 -*
-b1 .*
-b0 /*
-b11111111 0*
-b11111111 8*
-b10 :*
-b1001101000000 ;*
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-sDupLow32\x20(1) =*
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-b11111111 G*
-b10 I*
-b1001101000000 J*
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-sDupLow32\x20(1) L*
-1N*
-b11111111 V*
-b10 X*
-b1001101000000 Y*
-0Z*
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-b11111111 d*
-b10 f*
-b1001101000000 g*
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-sDupLow32\x20(1) i*
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-b1001101000000 v*
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-b1001101000000 '+
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-b11111111 0+
-b10 2+
-b1001101000000 3+
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-sDupLow32\x20(1) 5+
-s<invalid>\x20(15) 6+
-b11111111 <+
-b10 >+
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-1C+
-b11111111 L+
-b10 N+
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+b11111111 ?.
+sSignExt8\x20(7) C.
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+14)
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+0b(
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+0o(
+0p(
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+b11111111 0)
+sSignExt8\x20(7) 3)
+04)
+05)
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+b11111111 I)
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+b11111111 Z)
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+sSLt\x20(3) r)
+0s)
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+0)+
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+b11111111 G,
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+0M,
+b11111111 U,
+sSignExt8\x20(7) X,
+0Y,
+0Z,
+b11111111 b,
+b11111111 x,
+sSignExt8\x20(7) {,
+0|,
+0},
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+0]-
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+0k-
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+b11111111 -.
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+sSignExt\x20(1) 1.
+b0 5.
+b10 6.
+b11111111 7.
+b11111111 ?.
+sSignExt8\x20(7) C.
+0D.
+0E.
+b11111111 M.
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+0Q.
+0R.
+b11111111 Z.
+b11111111 p.
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+0t.
+0u.
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+0c/
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+090
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+b11111111 D6
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+0H6
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+b11111111 n6
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+b11111111 #7
+sSLt\x20(3) (7
+0)7
+b11111111 27
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+077
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+b11111111 F7
+b11111111 N7
+b11111111 W7
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+b11111111 f7
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+0k7
+0l7
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+0x7
+0y7
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+b11111111 98
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+0=8
+0>8
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+b11111111 R8
+sSignExt32To64BitThenShift\x20(6) ]8
+b11111111 c8
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+04)
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+0D.
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+077
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+1E.
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+1u.
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+1E.
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+1E.
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+1u.
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 b100001 N:
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-b100100 \:
-b100 ]:
-b1 ^:
-b10000 _:
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-b10001101000101 ;;
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-b1 T;
-b10000 U;
-b100001 V;
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-b100 Z;
-b11 [;
-b100100 \;
-b100 ];
-b1 ^;
-b10000 _;
-b100001 `;
-b100011010001 a;
-b1 b;
-b10000 c;
-b100001 d;
-b100001 e;
-b100 f;
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-b10000 ==
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-b10000 F=
-b1 I=
-b10000 J=
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+sCmpRBOne\x20(8) |;
+b1100 };
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+b10000 "=
+b1101 #=
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+b101111 R=
+b1101 V=
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+b100 X=
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+b100 a=
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+b1101 d=
+b110011 g=
+b110011 j=
+b1101 m=
+b110011 p=
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+b110010 y=
+b1110 z=
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+b100 0>
+b101111 1>
+b100001 3>
+b1101 5>
+b111011 6>
+b100 7>
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-sCmpRBOne\x20(8) S>
-b1100 T>
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-b0 T
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+b0 /:
+b0 ::
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+b0 G:
+b0 O:
+b0 V:
+b0 _:
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-b100001000100100011010001 H&
-b100001000100100011010001 I&
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-b1100 45
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+b110001 0:
+b110001 1:
+b110001 2:
+b10001 4:
+b110001 6:
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+b110001 P:
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+b110001 a:
+b110001 b:
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-b10001 f:
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-b10001 I=
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-b10001 ]=
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+b10001 p:
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+b110001 3>
+b110001 =>
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+b1000100100 U>
+b10010001 W>
+b10010001 Y>
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 #121000000
 b100100 (
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-b100101 8
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+b100101 7
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+b101 S9
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+b11 U9
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+b100100 !:
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-b10100010101110 #:
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-b100100 *:
-b10100010101110 +:
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+b100100 (:
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-b0 1:
-b0 3:
-b101 5:
-b100 6:
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-b100100 8:
-b10100010101110 9:
-b100 ::
-b11 ;:
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-b11 ?:
-b100100 @:
-b101000101011 A:
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-b0 G:
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-b100 L:
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+b100100 0:
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-b101000101011 S:
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-b100 f:
-b11 g:
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-b100100 5;
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-b101 E;
-b100 F;
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-b100100 L;
-b100100 M;
-b101 N;
-b100 O;
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+b100 m:
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+b101 o:
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+1s;
+b0 t;
+sS64\x20(1) u;
+b11111111 v;
+b10100010101110 w;
+sU64\x20(0) x;
+b11111111 y;
+sU64\x20(0) z;
+b11111111 {;
+sCmpRBTwo\x20(9) |;
+b11111111 };
+b11111111 ~;
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+b11110 0=
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+b101 7=
+b100010 9=
+b11101 :=
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+b100011 >=
+b100010 C=
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+b100101 Q=
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+b100 b=
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-b11111111 G*
-b11111111 V*
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-b11111111 70
-b11111111 F0
-b11111111 U0
-b11111111 a0
-b11111111 m0
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-b11111111 /1
-b11111111 :1
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+b11111111 40
+b11111111 B0
+b11111111 O0
+b11111111 e0
+b11111111 r0
+b11111111 ~0
+b11111111 11
+b11111111 ;1
+b11111111 D1
+b11111111 S1
+b11111111 g1
+b11111111 o1
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-b11111111 (2
+b11111111 !2
+b11111111 )2
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-b11111111 F2
-b11111111 R2
-b11111111 ^2
-b11111111 n2
-b11111111 ~2
-b11111111 +3
-b11111111 73
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-b11111111 C3
-b11111111 K3
-b11111111 Z3
-b11111111 i3
-b11111111 w3
-b11111111 (4
-b11111111 74
-b11111111 C4
+b11111111 D2
+b11111111 Z2
+b11111111 g2
+b11111111 s2
+b11111111 &3
+b11111111 03
+b11111111 93
+b11111111 H3
+b11111111 \3
+b11111111 d3
+b11111111 m3
+b11111111 t3
+b11111111 |3
+b11111111 ,4
+b11111111 94
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-b11111111 _4
-b11111111 o4
-b11111111 z4
-b11111111 (5
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-b11111111 45
-b11111111 <5
-b11111111 K5
-b11111111 Z5
-b11111111 h5
-b11111111 w5
-b11111111 (6
-b11111111 46
-b11111111 @6
-b11111111 P6
-b11111111 `6
-b11111111 k6
-b11111111 w6
-b0 #7
-b11111111 %7
-b11111111 -7
-b11111111 <7
-b11111111 K7
-b11111111 Y7
-b11111111 h7
-b11111111 w7
-b11111111 %8
-b11111111 18
-b11111111 A8
-b11111111 Q8
-b11111111 \8
-b11111111 h8
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-b11111111 u8
-b0 x8
-b11111111 {8
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-b0 &9
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-b0 29
-b11111111 59
-b0 89
+b11111111 \4
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+b11111111 y4
+b11111111 %5
+b11111111 .5
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+b11111111 Q5
+b11111111 Y5
+b11111111 b5
+b11111111 i5
+b11111111 q5
+b11111111 !6
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+b11111111 D6
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+b11111111 ]6
+b11111111 n6
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+b11111111 #7
+b11111111 27
+b11111111 F7
+b11111111 N7
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+b11111111 #8
+b11111111 98
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+b11111111 R8
+b11111111 c8
+b11111111 m8
+b11111111 v8
+b11111111 '9
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 #126000000
 b0 (
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 #135000000
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-b1 J;
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-b1 T;
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-b100001 V;
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-b110011110001001 Y;
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-b11 [;
-b100100 \;
-b100 ];
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-b100011010001 a;
-b1 b;
-b10000 c;
-b100001 d;
-b100001 e;
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-1y;
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-b1 <=
-b10000 ==
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-b1 I=
-b10000 J=
-b1 M=
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-b1 />
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+b1100 };
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+b101111 8>
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-b1100 <>
-b100 =>
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-b100 @>
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-b1100 B>
-b10001101000101 C>
-b1 D>
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-b1100 H>
-b100 I>
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-b100 L>
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-b1100 N>
-b100 O>
-b1 P>
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-b100 R>
-sCmpRBOne\x20(8) S>
-b1100 T>
-b100 U>
-b1 V>
-b100 W>
-b1100 X>
-b10001101000101 Y>
-b1 Z>
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-b0 7
-b0 F
-b0 T
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-b100001000100100011010001 H&
-b100001000100100011010001 I&
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-b1100 p-
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-b1100 45
-b10001 #7
-b1100 %7
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-b10001 29
-b1100 59
-b10001 89
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-b100 C9
-b1100 F9
-b10001 H9
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+b110001 0:
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-0`7
-b1001 h7
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-0o7
-b1001 w7
-sSignExt8\x20(7) |7
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-sCmpRBOne\x20(8) +8
-b1001 18
-sSLt\x20(3) 78
-088
-b1001 A8
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-0H8
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-b11 39
-b11111111 49
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-b11111111 :9
+sSignExt8\x20(7) R4
+0T4
+b1001 \4
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+b1001 %5
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+045
+b1001 =5
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+0B5
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+077
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+0,9
+sPowerIsaTimeBaseU\x20(1) 59
 b1001 ;9
-b101 =9
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-b1 C9
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-b1001 F9
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-0L9
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-0b9
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-0x9
-b0 y9
-b0 {9
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-b11 !:
+b1001 C9
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+b100100 !:
 b100100 ":
-b10101010101110 #:
-b100 $:
-b11 %:
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 b100100 &:
-b101 ':
-b100 (:
-b11 ):
-b100100 *:
-b10101010101110 +:
-b100 ,:
-b11 -:
+b100100 ':
+b100100 (:
+b100100 ):
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 b100100 .:
-b10101010101110 /:
-00:
-b0 1:
-b0 3:
-b101 5:
-b100 6:
-b11 7:
-b100100 8:
-b10101010101110 9:
-b100 ::
-b11 ;:
-b100100 <:
-b101 =:
-b100 >:
-b11 ?:
-b100100 @:
-b101010101011 A:
-b100 B:
-b11 C:
-b100100 D:
-b10101010101110 E:
-0F:
-b0 G:
-b0 I:
-b101 K:
-b100 L:
-b11 M:
+b100100 0:
+b100100 1:
+b100100 2:
+b101010101011 3:
+b100 4:
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+b100100 6:
+b10101010101110 7:
+08:
+b0 9:
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+b100100 A:
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+b100100 E:
+b0 F:
+b11 H:
+b100100 I:
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+b100100 K:
+b100100 L:
+b100100 M:
 b100100 N:
-b101 O:
-b100 P:
-b11 Q:
+b100100 P:
+b100100 Q:
 b100100 R:
-b101010101011 S:
-b100 T:
-b11 U:
-b100100 V:
-b10101010101110 W:
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-b0 Y:
-b0 [:
-b101 ]:
-b100 ^:
-b11 _:
+b100100 S:
+b100100 T:
+b100100 U:
+b100100 W:
+b100100 X:
+b100100 Y:
+b100100 Z:
+b100100 [:
+b11 \:
+b100100 ]:
+b0 ^:
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-b101010101011 a:
-b100 b:
-b11 c:
+b100100 a:
+b100100 b:
+b100100 c:
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-b101 e:
-b100 f:
-b11 g:
-b100100 h:
-b10101010101110 i:
-b100 j:
-b11 k:
-b100100 l:
-b10101010101110 m:
-0n:
-b0 o:
-b0 q:
-b101 s:
-b100 t:
-b11 u:
-b100100 v:
-b10101010101110 w:
-b100 x:
-b11 y:
-b100100 z:
-b100100 {:
-b101 |:
-b100 }:
-b11 ~:
-b100100 !;
-b100100 ";
-b10101010101110 #;
-b100 $;
-b11 %;
-b100100 &;
-b10101010101110 ';
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-b0 );
-b0 +;
-b101 -;
-b100 .;
-b11 /;
-b100100 0;
-b10101010101110 1;
-b100 2;
-b11 3;
-b100100 4;
-b100100 5;
-b101 6;
-b100 7;
-b11 8;
-b100100 9;
-b100100 :;
-b10101010101110 ;;
-b100 <;
-b11 =;
-b100100 >;
-b10101010101110 ?;
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-b0 A;
-b0 C;
-b101 E;
-b100 F;
-b11 G;
-b100100 H;
-b10101010101110 I;
-b100 J;
-b11 K;
-b100100 L;
-b100100 M;
-b101 N;
-b100 O;
-b11 P;
-b100100 Q;
-b100100 R;
-b101010101011 S;
-b100 T;
-b11 U;
-b100100 V;
-b10101010101110 W;
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-b0 Y;
-b0 [;
-b101 ];
-b100 ^;
-b11 _;
-b100100 `;
-b101010101011 a;
-b100 b;
-b11 c;
-b100100 d;
-b100100 e;
-b101 f;
-b100 g;
-b11 h;
-b100100 i;
-b100100 j;
-b10101010101110 k;
-b100 l;
-b11 m;
-b100100 n;
-b10101010101110 o;
-0p;
-b0 q;
-b0 s;
-b10101010101110 u;
-b100 v;
-b11 w;
-b100100 x;
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-b10101010 z;
-b100 {;
-b11 |;
-b101 };
-b100 ~;
-b11 !<
-b101 $<
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-b100 -=
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-b11 3=
-b101 6=
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-b11 8=
-b101 ;=
-b100 <=
-b11 ==
-b101 @=
-b100 A=
-b11 B=
-b100 E=
-b11 F=
-b100 I=
-b11 J=
-b100 M=
-b11 N=
-b100 Q=
-b11 R=
-b100 U=
-b11 V=
-b100 Y=
-b11 Z=
-b100 ]=
-b11 ^=
-b100 a=
-b11 b=
-b100 e=
-b11 f=
-b100 i=
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-b100 m=
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-b100 }=
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-b100 #>
-b11 $>
-b100 '>
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-b11 ,>
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-b11 %?
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-b100 D?
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-b100 Y?
-b11 Z?
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-b100 _?
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-b100 b?
-b11 c?
-b0 e?
-b11111111 f?
+b10101010101110 e:
+b100100 f:
+b10101010101110 g:
+b0 h:
+b100100 j:
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+b10101010 l:
+b100 m:
+b11 n:
+b101 o:
+b100 p:
+b11 q:
+1o;
+b0 p;
+sS64\x20(1) q;
+b11111111 r;
+1s;
+b0 t;
+sS64\x20(1) u;
+b11111111 v;
+b10101010101110 w;
+sU64\x20(0) x;
+b11111111 y;
+sU64\x20(0) z;
+b11111111 {;
+sCmpRBTwo\x20(9) |;
+b11111111 };
+b11111111 ~;
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+b1010 ><
+b101 ?<
+b100 @<
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+b101010 B<
+b110111 C<
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+b110001 O=
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+b110001 R=
+b101010 V=
+b11010 W=
+b100101 X=
+b110001 Y=
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+b110001 \=
+b10101 `=
+b101 a=
+b100 b=
+b11 c=
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+b10101 v=
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+b101011 }=
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 #140000000
 b0 (
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-b1111100011000000010101010101110 C&
-b110000000101010101011 G&
-b110000000101010101011 H&
-b110000000101010101011 I&
-b110000000101010101011 J&
-b0 L&
-b11111111 N&
-b11111111 V&
-b11111111 e&
-b11111111 t&
-b11111111 $'
-b11111111 3'
-b11111111 B'
-b11111111 N'
-b11111111 Z'
-b11111111 j'
-b11111111 z'
-b11111111 '(
-b11111111 3(
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-b11111111 s(
-b11111111 $)
-b11111111 3)
-b11111111 ?)
-b11111111 K)
-b11111111 [)
-b11111111 k)
-b11111111 v)
-b11111111 $*
-b0 .*
-b11111111 0*
-b11111111 8*
-b11111111 G*
-b11111111 V*
-b11111111 d*
-b11111111 s*
-b11111111 $+
-b11111111 0+
-b11111111 <+
-b11111111 L+
-b11111111 \+
-b11111111 g+
-b11111111 s+
-b0 }+
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-b11111111 ),
+b0 l"
+b1111100011000000010101010101110 X&
+b110000000101010101011 \&
+b0 ^&
+b11111111 `&
+b11111111 h&
+b11111111 v&
+b11111111 %'
+b11111111 ;'
+b11111111 H'
+b11111111 T'
+b11111111 e'
+b11111111 o'
+b11111111 x'
+b11111111 )(
+b11111111 =(
+b11111111 E(
+b11111111 N(
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+b11111111 k(
+b11111111 x(
+b11111111 0)
+b11111111 =)
+b11111111 I)
+b11111111 Z)
+b11111111 d)
+b11111111 m)
+b11111111 |)
+b11111111 2*
+b11111111 :*
+b11111111 C*
+b11111111 J*
+b11111111 R*
+b11111111 `*
+b11111111 m*
+b11111111 %+
+b11111111 2+
+b11111111 >+
+b11111111 O+
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+b11111111 b+
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+b11111111 ',
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+b11111111 b,
+b11111111 x,
+b11111111 '-
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-b11111111 70
-b11111111 F0
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+b11111111 +/
+b11111111 </
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+b11111111 O/
+b11111111 ^/
+b11111111 r/
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+b11111111 %0
+b11111111 ,0
+b11111111 40
+b11111111 B0
+b11111111 O0
+b11111111 e0
+b11111111 r0
+b11111111 ~0
+b11111111 11
+b11111111 ;1
+b11111111 D1
+b11111111 S1
+b11111111 g1
+b11111111 o1
 b11111111 x1
-b11111111 (2
+b11111111 !2
+b11111111 )2
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-b11111111 F2
-b11111111 R2
-b11111111 ^2
-b11111111 n2
-b11111111 ~2
-b11111111 +3
-b11111111 73
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-b11111111 C3
-b11111111 K3
-b11111111 Z3
-b11111111 i3
-b11111111 w3
-b11111111 (4
-b11111111 74
-b11111111 C4
+b11111111 D2
+b11111111 Z2
+b11111111 g2
+b11111111 s2
+b11111111 &3
+b11111111 03
+b11111111 93
+b11111111 H3
+b11111111 \3
+b11111111 d3
+b11111111 m3
+b11111111 t3
+b11111111 |3
+b11111111 ,4
+b11111111 94
 b11111111 O4
-b11111111 _4
-b11111111 o4
-b11111111 z4
-b11111111 (5
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-b11111111 45
-b11111111 <5
-b11111111 K5
-b11111111 Z5
-b11111111 h5
-b11111111 w5
-b11111111 (6
-b11111111 46
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-b10000 U;
-b100001 V;
-b10010001101000101 W;
-b110011110001001 Y;
-b100 Z;
-b11 [;
-b100100 \;
-b100 ];
-b1 ^;
-b10000 _;
-b100001 `;
-b100011010001 a;
-b1 b;
-b10000 c;
-b100001 d;
-b100001 e;
-b100 f;
-b1 g;
-b10000 h;
-b100001 i;
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-b10000 w;
-b100001 x;
-1y;
-b10001101 z;
-b1 {;
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-b100 };
-b1 ~;
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-b1 M=
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+sCmpRBOne\x20(8) |;
+b1100 };
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+b100 X=
+b101111 Y=
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+b11010 `=
+b100 a=
+b1 b=
+b10000 c=
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+b100001 3>
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+b100 7>
+b101111 8>
 b100 :>
-sS32\x20(3) ;>
-b1100 <>
-b100 =>
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-b100 @>
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-b1100 B>
-b10001101000101 C>
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-b1 P>
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-sCmpRBOne\x20(8) S>
-b1100 T>
-b100 U>
-b1 V>
-b100 W>
-b1100 X>
-b10001101000101 Y>
-b1 Z>
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-b10001101000101 e>
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-b10001101000101 i>
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-b10000 k>
-b10001101000101 m>
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-b10000 o>
-b100 q>
-b1 r>
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-b100 u>
-b1 v>
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-b1 z>
-b10000 {>
-b100 }>
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-b100 #?
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-b10000 %?
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+b1000 J>
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+b10000 L>
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+b1100 Z>
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 #146000000
 b0 (
-b0 7
-b0 F
-b0 T
-b0 c
+b0 6
+b0 C
+b0 Y
+b0 f
 b0 r
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+b0 %"
+b0 /"
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+b0 G"
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+b0 *:
+b0 /:
+b0 ::
+b0 <:
+b0 @:
+b0 G:
+b0 O:
+b0 V:
+b0 _:
+b0 i:
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-b110000100010010001101000101 C&
-b100001000100100011010001 G&
-b100001000100100011010001 H&
-b100001000100100011010001 I&
-b100001000100100011010001 J&
-b10001 L&
-b1100 N&
-b10001 =(
-b1100 ?(
-b10001 .*
-b1100 0*
-b10001 }+
-b1100 !,
-b10001 n-
-b1100 p-
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-b1100 a/
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-b1100 R1
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-b1100 C3
-b10001 25
-b1100 45
-b10001 #7
-b1100 %7
-b10001 r8
-b1100 u8
-b10001 x8
-b1100 {8
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-b1100 /9
-b10001 29
-b1100 59
-b10001 89
-b1100 ;9
-b10001 >9
-b1100 A9
-b100 C9
-b1100 F9
-b10001 H9
-b110001 J9
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-b10001 R9
-b110001 T9
-b10001 V9
-b110001 X9
-b10001 Z9
-b110001 \9
-b10001 ^9
-b110001 `9
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-b110001 j9
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+b110001 0:
+b110001 1:
+b110001 2:
+b10001 4:
+b110001 6:
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+b110001 B:
+b110001 C:
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+b110001 L:
+b110001 M:
 b110001 N:
-b10001 P:
+b110001 P:
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+b110001 S:
+b110001 T:
+b110001 U:
+b110001 W:
+b110001 X:
+b110001 Y:
+b110001 Z:
+b110001 [:
+b110001 ]:
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-b10001 b:
+b110001 a:
+b110001 b:
+b110001 c:
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-b10001 f:
-b110001 h:
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-b10001 U=
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-b10001 y=
-b10001 }=
-b10001 #>
-b10001 '>
-b10001 +>
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+b110001 f:
+b110001 j:
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+b10001 p:
+b10001 @<
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+b110001 {<
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+b10001 b=
+b110001 3>
+b110001 =>
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+b1000100100 U>
+b10010001 W>
+b10010001 Y>
+b1000100100 [>
+b10010001 \>
+b10010001 ]>
+b10010001 ^>
 #148000000
 b100100 (
 b100101 )
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-b100100 7
-b100101 8
-b0 9
-b0 :
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-b100100 F
-b100101 G
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+b0 8
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+b100100 C
+b100101 D
+b0 E
+b0 F
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-b100100 T
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-b100100 c
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-b0 e
-b0 f
+b0 J
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+b0 N
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+0Q
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+b0 [
+0`
+b100100 f
+b100101 g
+0i
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 b100100 r
 b100101 s
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-b0 u
-sU64\x20(0) x
-b100100 ~
-b100101 !"
-b0 ""
-b0 #"
-sU64\x20(0) &"
-b100100 ,"
-b100101 -"
-b0 ."
-b0 /"
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-b100100 <"
-b100101 ="
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-b100100 L"
-b100101 M"
-b0 N"
-b0 O"
-b100100 W"
-b100101 X"
-b0 Y"
-b0 Z"
+sHdlNone\x20(0) u
+b0 v
+sHdlNone\x20(0) x
+b0 y
+b0 z
+0{
+sFull64\x20(0) |
+b100100 %"
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+b0 '"
+sU64\x20(0) )"
+b100100 /"
+b100101 0"
+sU64\x20(0) 2"
+b100100 8"
+b100101 9"
+b0 :"
+b0 ;"
+0@"
+b100100 G"
+b100101 H"
+b0 I"
+0N"
+b100100 ["
+b100101 \"
 b100100 c"
 b100101 d"
-b0 e"
-b0 f"
-b1111100011001000010100000101110 C&
-sHdlNone\x20(0) D&
-b0 E&
-0F&
-b110010000101000001011 G&
-b110010000101000001011 H&
-b110010000101000001011 I&
-b110010000101000001011 J&
-b101000001011 K&
-b100 L&
-b11 M&
-b1001 N&
-b1001 V&
-b10100000101100 Y&
-sSignExt8\x20(7) [&
-0]&
-b1001 e&
-b10100000101100 h&
-sSignExt8\x20(7) j&
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-b1001 t&
-b10100000101100 w&
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-b1001 $'
-b10100000101100 ''
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-b1001 3'
-b10100000101100 6'
-sSignExt8\x20(7) 8'
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-b1001 B'
-b10100000101100 E'
-sSignExt8\x20(7) G'
-sU16\x20(4) H'
-b1001 N'
-b10100000101100 Q'
-sSignExt8\x20(7) S'
-sU16\x20(4) T'
-b1001 Z'
-b10100000101100 ]'
-sSLt\x20(3) `'
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-b1001 j'
-b10100000101100 m'
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-b1001 z'
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-b1001 3(
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-sSignExt\x20(1) 9(
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-b100 =(
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-b1001 ?(
-b1001 G(
-b10100000101100 J(
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-b1001 e(
-b10100000101100 h(
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-b1001 s(
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-b10100000101100 6)
-sSignExt8\x20(7) 8)
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-b10100000101100 B)
-sSignExt8\x20(7) D)
-sU64\x20(0) E)
-b1001 K)
-b10100000101100 N)
-sSLt\x20(3) Q)
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-b1001 [)
-b10100000101100 ^)
-sSLt\x20(3) a)
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-b1001 k)
-b10100000101100 n)
-b1001 v)
-b10100000101100 y)
-sSignExt\x20(1) |)
-b1001 $*
-b10100000101100 '*
-sSignExt\x20(1) **
-b101000001011 -*
-b100 .*
-b11 /*
-b1001 0*
-b1001 8*
-b10100000101100 ;*
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-b1001 G*
-b10100000101100 J*
-sSignExt8\x20(7) L*
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-b1001 d*
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-b1001 s*
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+sCmpRBOne\x20(8) |;
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-sCmpRBOne\x20(8) x
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-b100000100010010001101000101 C&
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-b1000100100011010001 H&
-b1000100100011010001 I&
-b1000100100011010001 J&
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-b1001 I/
-sSignExt\x20(1) O/
-b1001 U/
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-b1 ^/
-b100 _/
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-b1001 a/
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-0p/
-b1001 x/
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-0!0
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-100
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-0>0
-b1001 F0
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-0M0
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-0a1
-b1001 i1
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-0p1
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 sSignExt8\x20(7) -2
 0/2
 b1001 72
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-0>2
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-0R3
-b1001 Z3
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-0a3
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-0~3
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-0/4
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 b1001 O4
-sSLt\x20(3) U4
-0V4
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-0f4
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-sSignExt\x20(1) "5
-b1001 (5
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-0C5
-b1001 K5
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-0R5
-b1001 Z5
-1a5
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-0o5
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-0~5
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-sU64\x20(0) .6
-b1001 46
-sSignExt8\x20(7) 96
-sU64\x20(0) :6
-b1001 @6
-sSLt\x20(3) F6
-0G6
-b1001 P6
-sSLt\x20(3) V6
-0W6
-b1001 `6
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-b1001 w6
-sSignExt\x20(1) }6
-b1 "7
-b100 #7
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-sSignExt8\x20(7) 27
-047
-b1001 <7
-sSignExt8\x20(7) A7
-0C7
-b1001 K7
-1R7
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-0`7
-b1001 h7
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-0o7
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-b1001 18
-sSLt\x20(3) 78
-088
-b1001 A8
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-0H8
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-b11111111 49
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-b11111111 :9
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+0T4
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+077
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+b1001 '9
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+0,9
+sPowerIsaTimeBaseU\x20(1) 59
 b1001 ;9
-b101 =9
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-b1001 A9
-b1 C9
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-b1001 F9
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-0L9
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-0b9
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-0x9
-b0 y9
-b0 {9
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-b100 ~9
-b11 !:
+b1001 C9
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+b11 ~9
+b100100 !:
 b100100 ":
-b10100110101110 #:
-b100 $:
-b11 %:
+b100100 #:
+b100100 $:
 b100100 &:
-b101 ':
-b100 (:
-b11 ):
-b100100 *:
-b10100110101110 +:
-b100 ,:
-b11 -:
+b100100 ':
+b100100 (:
+b100100 ):
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+b100100 ,:
+b100100 -:
 b100100 .:
-b10100110101110 /:
-00:
-b0 1:
-b0 3:
-b101 5:
-b100 6:
-b11 7:
-b100100 8:
-b10100110101110 9:
-b100 ::
-b11 ;:
-b100100 <:
-b101 =:
-b100 >:
-b11 ?:
-b100100 @:
-b101001101011 A:
-b100 B:
-b11 C:
-b100100 D:
-b10100110101110 E:
-0F:
-b0 G:
-b0 I:
-b101 K:
-b100 L:
-b11 M:
+b100100 0:
+b100100 1:
+b100100 2:
+b101001101011 3:
+b100 4:
+b11 5:
+b100100 6:
+b10100110101110 7:
+08:
+b0 9:
+b0 ;:
+b100100 =:
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+b100100 ?:
+b100100 A:
+b100100 B:
+b100100 C:
+b11 D:
+b100100 E:
+b0 F:
+b11 H:
+b100100 I:
+b100100 J:
+b100100 K:
+b100100 L:
+b100100 M:
 b100100 N:
-b101 O:
-b100 P:
-b11 Q:
+b100100 P:
+b100100 Q:
 b100100 R:
-b101001101011 S:
-b100 T:
-b11 U:
-b100100 V:
-b10100110101110 W:
-0X:
-b0 Y:
-b0 [:
-b101 ]:
-b100 ^:
-b11 _:
+b100100 S:
+b100100 T:
+b100100 U:
+b100100 W:
+b100100 X:
+b100100 Y:
+b100100 Z:
+b100100 [:
+b11 \:
+b100100 ]:
+b0 ^:
 b100100 `:
-b101001101011 a:
-b100 b:
-b11 c:
+b100100 a:
+b100100 b:
+b100100 c:
 b100100 d:
-b101 e:
-b100 f:
-b11 g:
-b100100 h:
-b10100110101110 i:
-b100 j:
-b11 k:
-b100100 l:
-b10100110101110 m:
-0n:
-b0 o:
-b0 q:
-b101 s:
-b100 t:
-b11 u:
-b100100 v:
-b10100110101110 w:
-b100 x:
-b11 y:
-b100100 z:
-b100100 {:
-b101 |:
-b100 }:
-b11 ~:
-b100100 !;
-b100100 ";
-b10100110101110 #;
-b100 $;
-b11 %;
-b100100 &;
-b10100110101110 ';
-0(;
-b0 );
-b0 +;
-b101 -;
-b100 .;
-b11 /;
-b100100 0;
-b10100110101110 1;
-b100 2;
-b11 3;
-b100100 4;
-b100100 5;
-b101 6;
-b100 7;
-b11 8;
-b100100 9;
-b100100 :;
-b10100110101110 ;;
-b100 <;
-b11 =;
-b100100 >;
-b10100110101110 ?;
-0@;
-b0 A;
-b0 C;
-b101 E;
-b100 F;
-b11 G;
-b100100 H;
-b10100110101110 I;
-b100 J;
-b11 K;
-b100100 L;
-b100100 M;
-b101 N;
-b100 O;
-b11 P;
-b100100 Q;
-b100100 R;
-b101001101011 S;
-b100 T;
-b11 U;
-b100100 V;
-b10100110101110 W;
-0X;
-b0 Y;
-b0 [;
-b101 ];
-b100 ^;
-b11 _;
-b100100 `;
-b101001101011 a;
-b100 b;
-b11 c;
-b100100 d;
-b100100 e;
-b101 f;
-b100 g;
-b11 h;
-b100100 i;
-b100100 j;
-b10100110101110 k;
-b100 l;
-b11 m;
-b100100 n;
-b10100110101110 o;
-0p;
-b0 q;
-b0 s;
-b10100110101110 u;
-b100 v;
-b11 w;
-b100100 x;
-0y;
-b10100110 z;
-b100 {;
-b11 |;
-b101 };
-b100 ~;
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-b101 J<
-b100 K<
-b11 L<
-b10100110101110 O<
-b100 P<
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-b11 }<
-b101 "=
-b100 #=
-b11 $=
-b101 '=
-b100 (=
-b11 )=
-b101 ,=
-b100 -=
-b11 .=
-b101 1=
-b100 2=
-b11 3=
-b101 6=
-b100 7=
-b11 8=
-b101 ;=
-b100 <=
-b11 ==
-b101 @=
-b100 A=
-b11 B=
-b100 E=
-b11 F=
-b100 I=
-b11 J=
-b100 M=
-b11 N=
-b100 Q=
-b11 R=
-b100 U=
-b11 V=
-b100 Y=
-b11 Z=
-b100 ]=
-b11 ^=
-b100 a=
-b11 b=
-b100 e=
-b11 f=
-b100 i=
-b11 j=
-b100 m=
-b11 n=
-b100 q=
-b11 r=
-b100 u=
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-b100 }=
-b11 ~=
-b100 #>
-b11 $>
-b100 '>
-b11 (>
-b100 +>
-b11 ,>
-b100 />
-b11 0>
-b100 3>
-b11 4>
-b10100110101110 7>
-b100 8>
-19>
-b0 :>
-sS64\x20(1) ;>
-b11111111 <>
-b101 =>
-b100 >>
-1?>
-b0 @>
-sS64\x20(1) A>
-b11111111 B>
-b10100110101110 C>
-b100 D>
-1E>
-b0 F>
-sU64\x20(0) G>
-b11111111 H>
-b101 I>
-b100 J>
-1K>
-b0 L>
-sU64\x20(0) M>
-b11111111 N>
-b101 O>
-b100 P>
-1Q>
-b0 R>
-sCmpRBTwo\x20(9) S>
-b11111111 T>
-b101 U>
-b100 V>
-b0 W>
-b11111111 X>
-b10100110101110 Y>
-b100 Z>
-b11 [>
-b10100110101110 ]>
-b100 ^>
-b11 _>
-b10100110101110 a>
-b100 b>
-b11 c>
-b10100110101110 e>
-b100 f>
-b11 g>
-b10100110101110 i>
-b100 j>
-b11 k>
-b10100110101110 m>
-b100 n>
-b11 o>
-b101 q>
-b100 r>
-b11 s>
-b101 u>
-b100 v>
-b11 w>
-b101 y>
-b100 z>
-b11 {>
-b101 }>
-b100 ~>
-b11 !?
-b101 #?
-b100 $?
-b11 %?
-b101 '?
-b100 (?
-b11 )?
-b101 +?
-b100 ,?
-b11 -?
-b101 /?
-b100 0?
-b11 1?
-b101 3?
-b100 4?
-b11 5?
-b101 7?
-b100 8?
-b11 9?
-b101 ;?
-b100 <?
-b11 =?
-b101 ??
-b100 @?
-b11 A?
-b101 C?
-b100 D?
-b11 E?
-b101 G?
-b100 H?
-b11 I?
-b101 K?
-b100 L?
-b11 M?
-b101 O?
-b100 P?
-b11 Q?
-b100 S?
-b11 T?
-b100 V?
-b11 W?
-b100 Y?
-b11 Z?
-b100 \?
-b11 ]?
-b100 _?
-b11 `?
-b100 b?
-b11 c?
-b0 e?
-b11111111 f?
+b10100110101110 e:
+b100100 f:
+b10100110101110 g:
+b0 h:
+b100100 j:
+0k:
+b10100110 l:
+b100 m:
+b11 n:
+b101 o:
+b100 p:
+b11 q:
+1o;
+b0 p;
+sS64\x20(1) q;
+b11111111 r;
+1s;
+b0 t;
+sS64\x20(1) u;
+b11111111 v;
+b10100110101110 w;
+sU64\x20(0) x;
+b11111111 y;
+sU64\x20(0) z;
+b11111111 {;
+sCmpRBTwo\x20(9) |;
+b11111111 };
+b11111111 ~;
+b10111 =<
+b110 ><
+b101 ?<
+b100 @<
+b11 A<
+b100110 B<
+b110111 C<
+b1000 D<
+b10010 E<
+b1000 G<
+b10010 H<
+b100110 L<
+b110111 M<
+b1000 N<
+b10010 O<
+b1000 Q<
+b10010 R<
+b101 V<
+b100110 W<
+b110111 X<
+b1000 Y<
+b10010 Z<
+b1000 \<
+b10010 ]<
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+b110111 a<
+b1000 b<
+b10010 c<
+b1000 e<
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+b100110 i<
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+b1000 k<
+b10010 l<
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+b1101 }<
+b1011 ~<
+b100 !=
+b11 "=
+b100110 #=
+b11010 &=
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+b11010 0=
+b11010 3=
+b1101 7=
+b100110 9=
+b11001 :=
+b100111 ;=
+b11001 ==
+b100111 >=
+b100110 C=
+b11001 D=
+b100111 E=
+b11001 G=
+b100111 H=
+b100110 L=
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 sSignExt16\x20(5) -2
 1.2
 b11111111 72
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-1Q3
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 b100001 N:
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-b100 Z:
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-b100100 \:
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-b10000 _:
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-b10000 c:
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-b10001101000101 ;;
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-b10000 G;
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-b1 J;
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-b100001 M;
-b100 N;
-b1 O;
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-b100001 Q;
-b100001 R;
-b100011010001 S;
-b1 T;
-b10000 U;
-b100001 V;
-b10010001101000101 W;
-b110011110001001 Y;
-b100 Z;
-b11 [;
-b100100 \;
-b100 ];
-b1 ^;
-b10000 _;
-b100001 `;
-b100011010001 a;
-b1 b;
-b10000 c;
-b100001 d;
-b100001 e;
-b100 f;
-b1 g;
-b10000 h;
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-b10001101 z;
-b1 {;
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-b100 };
-b1 ~;
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-b10000 3=
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-b1 7=
-b10000 8=
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-b1 <=
-b10000 ==
-b100 @=
-b1 A=
-b10000 B=
-b1 E=
-b10000 F=
-b1 I=
-b10000 J=
-b1 M=
-b10000 N=
-b1 Q=
-b10000 R=
-b1 U=
-b10000 V=
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-b1 ]=
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-b1 i=
-b10000 j=
-b1 m=
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-b1 u=
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-b1 }=
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-b10000 $>
-b1 '>
-b10000 (>
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-b1 3>
-b10000 4>
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-b1 8>
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+0o;
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+0s;
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+sCmpRBOne\x20(8) |;
+b1100 };
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+b1101 #=
+b110011 &=
+b110011 )=
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+b1101 9=
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+b101111 R=
+b1101 V=
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+b100 X=
+b101111 Y=
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+b11010 `=
+b100 a=
+b1 b=
+b10000 c=
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+b101111 1>
+b100001 3>
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+b100 7>
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-b100 @>
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-b1100 B>
-b10001101000101 C>
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-sCmpRBOne\x20(8) S>
-b1100 T>
-b100 U>
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-b100 W>
-b1100 X>
-b10001101000101 Y>
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-b10001101000101 e>
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-b10000 s>
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-b100001000100100011010001 H&
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-b100001000100100011010001 J&
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-b1100 45
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-b1100 59
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-b11111111 49
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-b11111111 :9
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+0T4
+b1001 \4
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+b1001 %5
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+045
+b1001 =5
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+077
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+0,9
+sPowerIsaTimeBaseU\x20(1) 59
 b1001 ;9
-b101 =9
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-0L9
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-0b9
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-0x9
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-b11 !:
+b1001 C9
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+b100100 !:
 b100100 ":
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-b11 %:
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 b100100 &:
-b101 ':
-b100 (:
-b11 ):
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-b100 ,:
-b11 -:
+b100100 ':
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 b100100 .:
-b10101100101110 /:
-00:
-b0 1:
-b0 3:
-b101 5:
-b100 6:
-b11 7:
-b100100 8:
-b10101100101110 9:
-b100 ::
-b11 ;:
-b100100 <:
-b101 =:
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-b11 ?:
-b100100 @:
-b101011001011 A:
-b100 B:
-b11 C:
-b100100 D:
-b10101100101110 E:
-0F:
-b0 G:
-b0 I:
-b101 K:
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-b11 M:
+b100100 0:
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+08:
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 b100100 N:
-b101 O:
-b100 P:
-b11 Q:
+b100100 P:
+b100100 Q:
 b100100 R:
-b101011001011 S:
-b100 T:
-b11 U:
-b100100 V:
-b10101100101110 W:
-0X:
-b0 Y:
-b0 [:
-b101 ]:
-b100 ^:
-b11 _:
+b100100 S:
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+b100100 X:
+b100100 Y:
+b100100 Z:
+b100100 [:
+b11 \:
+b100100 ]:
+b0 ^:
 b100100 `:
-b101011001011 a:
-b100 b:
-b11 c:
+b100100 a:
+b100100 b:
+b100100 c:
 b100100 d:
-b101 e:
-b100 f:
-b11 g:
-b100100 h:
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-b100100 l:
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-0n:
-b0 o:
-b0 q:
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-b100100 {:
-b101 |:
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-b100100 !;
-b100100 ";
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-b10101100101110 ';
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-b0 );
-b0 +;
-b101 -;
-b100 .;
-b11 /;
-b100100 0;
-b10101100101110 1;
-b100 2;
-b11 3;
-b100100 4;
-b100100 5;
-b101 6;
-b100 7;
-b11 8;
-b100100 9;
-b100100 :;
-b10101100101110 ;;
-b100 <;
-b11 =;
-b100100 >;
-b10101100101110 ?;
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-b0 A;
-b0 C;
-b101 E;
-b100 F;
-b11 G;
-b100100 H;
-b10101100101110 I;
-b100 J;
-b11 K;
-b100100 L;
-b100100 M;
-b101 N;
-b100 O;
-b11 P;
-b100100 Q;
-b100100 R;
-b101011001011 S;
-b100 T;
-b11 U;
-b100100 V;
-b10101100101110 W;
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-b0 Y;
-b0 [;
-b101 ];
-b100 ^;
-b11 _;
-b100100 `;
-b101011001011 a;
-b100 b;
-b11 c;
-b100100 d;
-b100100 e;
-b101 f;
-b100 g;
-b11 h;
-b100100 i;
-b100100 j;
-b10101100101110 k;
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-b100100 n;
-b10101100101110 o;
-0p;
-b0 q;
-b0 s;
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-b100 v;
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-b100100 x;
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-b100 {;
-b11 |;
-b101 };
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-b100 #=
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-b100 (=
-b11 )=
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-b101 1=
-b100 2=
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-b101 6=
-b100 7=
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-b101 ;=
-b100 <=
-b11 ==
-b101 @=
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-b11 N=
-b100 Q=
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-b100 U=
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-b100 3>
-b11 4>
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-b0 :>
-sS64\x20(1) ;>
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-b0 @>
-sS64\x20(1) A>
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-b10101100101110 C>
-b100 D>
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-b0 F>
-sU64\x20(0) G>
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-b101 I>
-b100 J>
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-b0 L>
-sU64\x20(0) M>
-b11111111 N>
-b101 O>
-b100 P>
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-b0 R>
-sCmpRBTwo\x20(9) S>
-b11111111 T>
-b101 U>
-b100 V>
-b0 W>
-b11111111 X>
-b10101100101110 Y>
-b100 Z>
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-b11 _>
-b10101100101110 a>
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-b10101100101110 i>
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-b100 $?
-b11 %?
-b101 '?
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-b100 4?
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-b101 7?
-b100 8?
-b11 9?
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-b100 D?
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-b100 H?
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-b101 K?
-b100 L?
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-b11 W?
-b100 Y?
-b11 Z?
-b100 \?
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-b100 _?
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-b100 b?
-b11 c?
-b0 e?
-b11111111 f?
+b10101100101110 e:
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+b10101100101110 g:
+b0 h:
+b100100 j:
+0k:
+b10101100 l:
+b100 m:
+b11 n:
+b101 o:
+b100 p:
+b11 q:
+1o;
+b0 p;
+sS64\x20(1) q;
+b11111111 r;
+1s;
+b0 t;
+sS64\x20(1) u;
+b11111111 v;
+b10101100101110 w;
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+b11111111 y;
+sU64\x20(0) z;
+b11111111 {;
+sCmpRBTwo\x20(9) |;
+b11111111 };
+b11111111 ~;
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+b101 a=
+b100 b=
+b11 c=
+b101100 d=
+b10100 g=
+b10100 j=
+b101100 m=
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+b10100 s=
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+b1011 J>
+b100 K>
+b11 L>
+b10000101 U>
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+b11 X>
+b10100100 Y>
+b11111111 Z>
+b10000101 [>
+b10100100 \>
+b10100100 ]>
+b10100100 ^>
 #186000000
 b0 (
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-b1111100011000000010101100101110 C&
-b110000000101011001011 G&
-b110000000101011001011 H&
-b110000000101011001011 I&
-b110000000101011001011 J&
-b0 L&
-b11111111 N&
-b11111111 V&
-b11111111 e&
-b11111111 t&
-b11111111 $'
-b11111111 3'
-b11111111 B'
-b11111111 N'
-b11111111 Z'
-b11111111 j'
-b11111111 z'
-b11111111 '(
-b11111111 3(
-b0 =(
-b11111111 ?(
-b11111111 G(
-b11111111 V(
-b11111111 e(
-b11111111 s(
-b11111111 $)
-b11111111 3)
-b11111111 ?)
-b11111111 K)
-b11111111 [)
-b11111111 k)
-b11111111 v)
-b11111111 $*
-b0 .*
-b11111111 0*
-b11111111 8*
-b11111111 G*
-b11111111 V*
-b11111111 d*
-b11111111 s*
-b11111111 $+
-b11111111 0+
-b11111111 <+
-b11111111 L+
-b11111111 \+
-b11111111 g+
-b11111111 s+
-b0 }+
-b11111111 !,
-b11111111 ),
+b0 l"
+b1111100011000000010101100101110 X&
+b110000000101011001011 \&
+b0 ^&
+b11111111 `&
+b11111111 h&
+b11111111 v&
+b11111111 %'
+b11111111 ;'
+b11111111 H'
+b11111111 T'
+b11111111 e'
+b11111111 o'
+b11111111 x'
+b11111111 )(
+b11111111 =(
+b11111111 E(
+b11111111 N(
+b11111111 U(
+b11111111 ](
+b11111111 k(
+b11111111 x(
+b11111111 0)
+b11111111 =)
+b11111111 I)
+b11111111 Z)
+b11111111 d)
+b11111111 m)
+b11111111 |)
+b11111111 2*
+b11111111 :*
+b11111111 C*
+b11111111 J*
+b11111111 R*
+b11111111 `*
+b11111111 m*
+b11111111 %+
+b11111111 2+
+b11111111 >+
+b11111111 O+
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+b11111111 b+
+b11111111 q+
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-b11111111 F.
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+b11111111 b,
+b11111111 x,
+b11111111 '-
+b11111111 3-
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-b11111111 )0
-b11111111 70
-b11111111 F0
-b11111111 U0
-b11111111 a0
-b11111111 m0
-b11111111 }0
-b11111111 /1
-b11111111 :1
-b11111111 F1
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+b11111111 }.
+b11111111 +/
+b11111111 </
+b11111111 F/
+b11111111 O/
+b11111111 ^/
+b11111111 r/
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+b11111111 %0
+b11111111 ,0
+b11111111 40
+b11111111 B0
+b11111111 O0
+b11111111 e0
+b11111111 r0
+b11111111 ~0
+b11111111 11
+b11111111 ;1
+b11111111 D1
+b11111111 S1
+b11111111 g1
+b11111111 o1
 b11111111 x1
-b11111111 (2
+b11111111 !2
+b11111111 )2
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-b11111111 F2
-b11111111 R2
-b11111111 ^2
-b11111111 n2
-b11111111 ~2
-b11111111 +3
-b11111111 73
-b0 A3
-b11111111 C3
-b11111111 K3
-b11111111 Z3
-b11111111 i3
-b11111111 w3
-b11111111 (4
-b11111111 74
-b11111111 C4
+b11111111 D2
+b11111111 Z2
+b11111111 g2
+b11111111 s2
+b11111111 &3
+b11111111 03
+b11111111 93
+b11111111 H3
+b11111111 \3
+b11111111 d3
+b11111111 m3
+b11111111 t3
+b11111111 |3
+b11111111 ,4
+b11111111 94
 b11111111 O4
-b11111111 _4
-b11111111 o4
-b11111111 z4
-b11111111 (5
-b0 25
-b11111111 45
-b11111111 <5
-b11111111 K5
-b11111111 Z5
-b11111111 h5
-b11111111 w5
-b11111111 (6
-b11111111 46
-b11111111 @6
-b11111111 P6
-b11111111 `6
-b11111111 k6
-b11111111 w6
-b0 #7
-b11111111 %7
-b11111111 -7
-b11111111 <7
-b11111111 K7
-b11111111 Y7
-b11111111 h7
-b11111111 w7
-b11111111 %8
-b11111111 18
-b11111111 A8
-b11111111 Q8
-b11111111 \8
-b11111111 h8
-b0 r8
-b11111111 u8
-b0 x8
-b11111111 {8
-b0 ~8
-b11111111 #9
-b0 &9
-b11111111 )9
-b0 ,9
-b11111111 /9
-b0 29
-b11111111 59
-b0 89
+b11111111 \4
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+b11111111 q5
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+b11111111 #7
+b11111111 27
+b11111111 F7
+b11111111 N7
+b11111111 W7
+b11111111 ^7
+b11111111 f7
+b11111111 t7
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-b11 L&
-b11111111 N&
-b11111111 V&
-sSignExt16\x20(5) [&
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-b11111111 e&
-sSignExt16\x20(5) j&
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-b11111111 t&
-0z&
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-b11111111 $'
-sSignExt16\x20(5) )'
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-b11111111 3'
-sSignExt16\x20(5) 8'
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-b11111111 B'
-sSignExt16\x20(5) G'
-sS16\x20(5) H'
-b11111111 N'
-sSignExt16\x20(5) S'
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-b11111111 Z'
-sOverflow\x20(6) `'
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-sOverflow\x20(6) p'
-b11111111 z'
-b11111111 '(
-sWidth16Bit\x20(1) ,(
-b11111111 3(
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-b11 =(
-b11111111 ?(
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-sSignExt16\x20(5) L(
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-sSignExt16\x20(5) 8)
-sS64\x20(1) 9)
-b11111111 ?)
-sSignExt16\x20(5) D)
-sS64\x20(1) E)
-b11111111 K)
-sOverflow\x20(6) Q)
-b11111111 [)
-sOverflow\x20(6) a)
-b11111111 k)
-b11111111 v)
-sWidth16Bit\x20(1) {)
-b11111111 $*
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-b11 .*
-b11111111 0*
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-1>*
-b11111111 G*
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-1M*
-b11111111 V*
-0\*
-1^*
-b11111111 d*
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-b11111111 s*
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-b11111111 $+
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+b11111111 H'
+b11111111 T'
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-b100100 D;
-b100 E;
-b1 F;
-b10000 G;
-b100001 H;
-b10001101000101 I;
-b1 J;
-b10000 K;
-b100001 L;
-b100001 M;
-b100 N;
-b1 O;
-b10000 P;
-b100001 Q;
-b100001 R;
-b100011010001 S;
-b1 T;
-b10000 U;
-b100001 V;
-b10010001101000101 W;
-b110011110001001 Y;
-b100 Z;
-b11 [;
-b100100 \;
-b100 ];
-b1 ^;
-b10000 _;
-b100001 `;
-b100011010001 a;
-b1 b;
-b10000 c;
-b100001 d;
-b100001 e;
-b100 f;
-b1 g;
-b10000 h;
-b100001 i;
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-b10000 w;
-b100001 x;
-1y;
-b10001101 z;
-b1 {;
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-b100 };
-b1 ~;
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-b1 I=
-b10000 J=
-b1 M=
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-b1 8>
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+b100 X=
+b101111 Y=
+b100 [=
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+b11010 `=
+b100 a=
+b1 b=
+b10000 c=
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+b100 0>
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+b100001 3>
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+b111011 6>
+b100 7>
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 b100 :>
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-b100 q>
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-b100 y>
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 #194000000
 b0 (
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-b0 T
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+b0 V:
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-b100001000100100011010001 G&
-b100001000100100011010001 H&
-b100001000100100011010001 I&
-b100001000100100011010001 J&
-b10001 L&
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-b10001 =(
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-b10001 .*
-b1100 0*
-b10001 }+
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-b1100 p-
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-b1100 45
-b10001 #7
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-b1100 59
-b10001 89
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-b110001 X9
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-b110001 \9
-b10001 ^9
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+b110001 a:
+b110001 b:
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-b10001 }=
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+b110001 f:
+b110001 j:
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+b10001 b=
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+b110001 =>
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+b1000100100 U>
+b10010001 W>
+b10010001 Y>
+b1000100100 [>
+b10010001 \>
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+b10010001 ^>
 #196000000
 b100100 (
 b100101 )
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-b100101 8
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+b0 [
+0`
+b100100 f
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+0i
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-b100100 ,"
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-b100100 W"
-b100101 X"
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+sHdlNone\x20(0) u
+b0 v
+sHdlNone\x20(0) x
+b0 y
+b0 z
+0{
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+b100100 %"
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+b0 '"
+sU64\x20(0) )"
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+b100101 0"
+sU64\x20(0) 2"
+b100100 8"
+b100101 9"
+b0 :"
+b0 ;"
+0@"
+b100100 G"
+b100101 H"
+b0 I"
+0N"
+b100100 ["
+b100101 \"
 b100100 c"
 b100101 d"
-b0 e"
-b0 f"
-b1111100011001000010100100101110 C&
-sHdlNone\x20(0) D&
-b0 E&
-0F&
-b110010000101001001011 G&
-b110010000101001001011 H&
-b110010000101001001011 I&
-b110010000101001001011 J&
-b101001001011 K&
-b100 L&
-b11 M&
-b1001 N&
-b1001 V&
-b10100100101100 Y&
-sSignExt8\x20(7) [&
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-b1001 e&
-b10100100101100 h&
-sSignExt8\x20(7) j&
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-b1001 t&
-b10100100101100 w&
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-b1001 $'
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-b10100100101100 6'
-sSignExt8\x20(7) 8'
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-b1001 B'
-b10100100101100 E'
-sSignExt8\x20(7) G'
-sU16\x20(4) H'
-b1001 N'
-b10100100101100 Q'
-sSignExt8\x20(7) S'
-sU16\x20(4) T'
-b1001 Z'
-b10100100101100 ]'
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-b1001 j'
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-b1001 z'
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-b1001 G(
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-b1001 e(
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-b1001 $)
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-b10100100101100 6)
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-b10100100101100 B)
-sSignExt8\x20(7) D)
-sU64\x20(0) E)
-b1001 K)
-b10100100101100 N)
-sSLt\x20(3) Q)
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-b1001 [)
-b10100100101100 ^)
-sSLt\x20(3) a)
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-b1001 k)
-b10100100101100 n)
-b1001 v)
-b10100100101100 y)
-sSignExt\x20(1) |)
-b1001 $*
-b10100100101100 '*
-sSignExt\x20(1) **
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-b100 .*
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-b1001 8*
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 #197000000
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-b11111111 v)
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-sSignExt16\x20(5) f0
-sCmpRBTwo\x20(9) g0
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-sOverflow\x20(6) s0
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-sOverflow\x20(6) %1
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+sOverflow\x20(6) b/
+b11111111 r/
+b11111111 z/
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+sWidth16Bit\x20(1) (0
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+sSignExt16\x20(5) 80
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+sSignExt16\x20(5) E0
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-b110001100101001011010 I&
-b110001100101001011010 J&
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-sSignExt16\x20(5) G'
-sS16\x20(5) H'
-b11111111 N'
-sSignExt16\x20(5) S'
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-b11111111 Z'
-sOverflow\x20(6) `'
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-sOverflow\x20(6) p'
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-sOverflow\x20(6) Q)
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-sWidth16Bit\x20(1) {)
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-sWidth16Bit\x20(1) )*
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-sSignExt16\x20(5) =*
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-sSignExt16\x20(5) L*
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-sSignExt16\x20(5) x*
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-sSignExt16\x20(5) )+
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-sSignExt16\x20(5) 5+
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-sOverflow\x20(6) B+
-b11111111 L+
-sOverflow\x20(6) R+
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-sWidth16Bit\x20(1) Z/
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-sSignExt16\x20(5) }/
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-sSignExt16\x20(5) <0
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-sSignExt16\x20(5) K0
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-sSignExt16\x20(5) Z0
-sCmpRBTwo\x20(9) [0
-b11111111 a0
-sSignExt16\x20(5) f0
-sCmpRBTwo\x20(9) g0
-b11111111 m0
-sOverflow\x20(6) s0
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-sOverflow\x20(6) %1
-b11111111 /1
-b11111111 :1
-sWidth16Bit\x20(1) ?1
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-sWidth16Bit\x20(1) K1
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-b11111111 R1
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-sSignExt16\x20(5) _1
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+b11111111 +/
+sFunnelShift2x32Bit\x20(2) 6/
+b11111111 </
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+sS64\x20(1) @/
+b11111111 F/
+b11111111 O/
+sOverflow\x20(6) T/
+b11111111 ^/
+sOverflow\x20(6) b/
+b11111111 r/
+b11111111 z/
+b11111111 %0
+sWidth16Bit\x20(1) (0
+b11111111 ,0
+b11111111 40
+sSignExt16\x20(5) 80
+190
+b11111111 B0
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+1F0
+b11111111 O0
+b11111111 e0
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+1i0
+b11111111 r0
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+sFunnelShift2x32Bit\x20(2) +1
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+b11111111 ;1
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+sOverflow\x20(6) I1
+b11111111 S1
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+b11111111 g1
+b11111111 o1
 b11111111 x1
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+sWidth16Bit\x20(1) {1
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 sSignExt16\x20(5) -2
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-sSignExt16\x20(5) <2
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-sSignExt16\x20(5) K2
-sS64\x20(1) L2
-b11111111 R2
-sSignExt16\x20(5) W2
-sS64\x20(1) X2
-b11111111 ^2
-sOverflow\x20(6) d2
-b11111111 n2
-sOverflow\x20(6) t2
-b11111111 ~2
-b11111111 +3
-sWidth16Bit\x20(1) 03
-b11111111 73
-sWidth16Bit\x20(1) <3
-b11 A3
-b11111111 C3
-b11111111 K3
-sSignExt16\x20(5) P3
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-b11111111 Z3
-sSignExt16\x20(5) _3
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-b11111111 i3
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-sSignExt16\x20(5) |3
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-b11111111 (4
-sSignExt16\x20(5) -4
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-sSignExt16\x20(5) <4
-sCmpRBTwo\x20(9) =4
-b11111111 C4
-sSignExt16\x20(5) H4
-sCmpRBTwo\x20(9) I4
+sSignExt16\x20(5) :2
+1;2
+b11111111 D2
+b11111111 Z2
+sSignExt16\x20(5) ]2
+1^2
+b11111111 g2
+b11111111 s2
+sFunnelShift2x32Bit\x20(2) ~2
+b11111111 &3
+sSignExt16\x20(5) )3
+sS64\x20(1) *3
+b11111111 03
+b11111111 93
+sOverflow\x20(6) >3
+b11111111 H3
+sOverflow\x20(6) L3
+b11111111 \3
+b11111111 d3
+b11111111 m3
+sWidth16Bit\x20(1) p3
+b11111111 t3
+b11111111 |3
+sSignExt16\x20(5) "4
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+b11111111 ,4
+sSignExt16\x20(5) /4
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+b11111111 94
 b11111111 O4
-sOverflow\x20(6) U4
-b11111111 _4
-sOverflow\x20(6) e4
-b11111111 o4
-b11111111 z4
-sWidth16Bit\x20(1) !5
-b11111111 (5
-sWidth16Bit\x20(1) -5
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-b11111111 45
-b11111111 <5
-sSignExt16\x20(5) A5
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-b11111111 K5
-sSignExt16\x20(5) P5
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-sSignExt16\x20(5) m5
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-b11111111 w5
-sSignExt16\x20(5) |5
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-sSignExt16\x20(5) -6
-sS64\x20(1) .6
-b11111111 46
-sSignExt16\x20(5) 96
-sS64\x20(1) :6
-b11111111 @6
-sOverflow\x20(6) F6
-b11111111 P6
-sOverflow\x20(6) V6
-b11111111 `6
-b11111111 k6
-sWidth16Bit\x20(1) p6
-b11111111 w6
-sWidth16Bit\x20(1) |6
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 #218000000
 sAddSub\x20(0) "
 sHdlSome\x20(1) '
@@ -128363,15944 +93289,38349 @@ b100100 (
 b100101 )
 b0 *
 b0 +
-01
-sHdlSome\x20(1) 6
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-b100100 c
-b100101 d
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+00
+sHdlSome\x20(1) 5
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 sAddSubI\x20(1) "
 b100 %
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 b10100001010000 J,
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-b10100001010001 #:
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-b10100001010001 +:
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-b101 5:
-b10100001010001 9:
-b101 =:
-b101000010100 A:
-b10100001010001 E:
-b101 K:
-b101 O:
-b101000010100 S:
-b10100001010001 W:
-b101 ]:
-b101000010100 a:
-b101 e:
-b10100001010001 i:
-b10100001010001 m:
-b101 s:
-b10100001010001 w:
-b101 |:
-b10100001010001 #;
-b10100001010001 ';
-b101 -;
-b10100001010001 1;
-b101 6;
-b10100001010001 ;;
-b10100001010001 ?;
-b101 E;
-b10100001010001 I;
-b101 N;
-b101000010100 S;
-b10100001010001 W;
-b101 ];
-b101000010100 a;
-b101 f;
-b10100001010001 k;
-b10100001010001 o;
-b10100001010001 u;
-1y;
-b10100001 z;
-b101 };
-b101 $<
-b101 )<
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-b101 1=
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-b101 ;=
-b101 @=
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-b101 =>
-b10100001010001 C>
-b101 I>
-b101 O>
-b101 U>
-b10100001010001 Y>
-b10100001010001 ]>
-b10100001010001 a>
-b10100001010001 e>
-b10100001010001 i>
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-b101 q>
-b101 u>
-b101 y>
-b101 }>
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-b101 '?
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-b101 G?
-b101 K?
-b101 O?
+b1010000101000000000010 W,
+b0 e,
+b10 g,
+b1 i,
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+1k:
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+b1000 v<
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+b1 #=
+b111111 &=
+b111111 )=
+b1 -=
+b111111 0=
+b111111 3=
+b10 7=
+b1 9=
+b111110 :=
+b10 ;=
+b111110 ==
+b10 >=
+b1 C=
+b111110 D=
+b10 E=
+b111110 G=
+b10 H=
+b1 L=
+b111010 M=
+b101 N=
+b111010 O=
+b101 Q=
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+b1 V=
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+b101 X=
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+b101 a=
+b1 d=
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+b111111 j=
+b1 m=
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+b111111 s=
+b10 v=
+b1 x=
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+b10 }=
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+b111110 $>
+b10 %>
+b111110 '>
+b10 (>
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+b101 0>
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+b1 5>
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+b1010 J>
+b10000101 U>
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+b10100100 Y>
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+b10100100 \>
+b10100100 ]>
+b10100100 ^>
 #221000000
 sAddSubI\x20(1) "
 b100 %
 sHdlNone\x20(0) '
 b0 )
-b1001000110100 +
-b100 4
-sHdlNone\x20(0) 6
-b0 8
-b1001000110100 :
-b100 C
-sHdlNone\x20(0) E
-b0 G
-b1001000110100 I
-b100 Q
-sHdlNone\x20(0) S
-b0 U
-b1001000110100 W
-b100 `
-sHdlNone\x20(0) b
-b0 d
-b1001000110100 f
+b110100 *
+b10010 +
+b100 3
+sHdlNone\x20(0) 5
+b0 7
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+b100 @
+sHdlNone\x20(0) B
+b0 D
+b110100 E
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+b10 H
+b100 V
+sHdlNone\x20(0) X
+b0 Z
+b1001000110100 [
+b100 c
+sHdlNone\x20(0) e
+b100100011010000000000 g
 b100 o
 sHdlNone\x20(0) q
 b0 s
-b1001000110100 u
-b100 {
-sHdlNone\x20(0) }
-b0 !"
-b1001000110100 #"
-b100 )"
-sHdlNone\x20(0) +"
-b0 -"
-b1001000110100 /"
-b100 9"
-sHdlNone\x20(0) ;"
-b0 ="
-b1001000110100 ?"
-b1 G"
-b100 I"
-sHdlNone\x20(0) K"
-b0 M"
-b1001000110100 O"
-sStore\x20(1) Q"
-b100 T"
-sHdlNone\x20(0) V"
-b0 X"
-b1001000110100 Z"
+b110100 t
+b1001 v
+b100 ""
+sHdlNone\x20(0) $"
+b0 &"
+b1001000110100 '"
+b100 ,"
+sHdlNone\x20(0) ."
+b100100011010000000000 0"
+b100 5"
+sHdlNone\x20(0) 7"
+b0 9"
+b110100 :"
+b10010 ;"
+b100 D"
+sHdlNone\x20(0) F"
+b0 H"
+b1001000110100 I"
+b100 R"
+sHdlNone\x20(0) T"
+b1 V"
+b100 X"
+sHdlNone\x20(0) Z"
+b100100011010000000000 \"
+sStore\x20(1) ]"
 b100 `"
 sHdlNone\x20(0) b"
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-b1001000110100 f"
-b100000011001000001001000110100 C&
-b110010000010010001101 G&
-b110010000010010001101 H&
-b110010000010010001101 I&
-b110010000010010001101 J&
-b10010001101 K&
-b1001000110100 Y&
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-b1001000110100 N)
-b1001000110100 ^)
-b1001000110100 n)
-b1001000110100 y)
-b1001000110100 '*
-b10010001101 -*
-b1001000110100 ;*
-b1001000110100 J*
-b1001000110100 Y*
-b1001000110100 g*
-b1001000110100 v*
-b1001000110100 '+
-b1001000110100 3+
-b1001000110100 ?+
-b1001000110100 O+
-b1001000110100 _+
-b1001000110100 j+
-b1001000110100 v+
-b10010001101 |+
-b1001000110100 ,,
-b1001000110100 ;,
+b100100011010000000000 d"
+b100 i"
+sHdlNone\x20(0) k"
+b0 m"
+b1001000110100 n"
+b100000011001000001001000110100 X&
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+b1001000110100 k&
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+b100 ('
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+b0 ,'
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+b1 0'
+b100100011010000000010 ='
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+b11010 X'
+b1001 ['
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+b1001000110100 {'
+b100100011010000000010 +(
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+b100100011010000000010 m(
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+b110 }(
+b0 !)
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+b1 %)
+b100100011010000000010 2)
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+b11010 M)
+b1001 P)
+b100100011010000000010 \)
+b10010001101000000001000000000 e)
+b1001000110100 p)
+b100100011010000000010 ~)
+b10010001101000000001000000000 3*
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+b1001000110100 U*
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+b100 p*
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+b0 t*
+b1 v*
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+b100100011010000000010 '+
+b10010001101000000001000000000 3+
+b11010 B+
+b1001 E+
+b100100011010000000010 Q+
+b10010001101000000001000000000 Z+
+b1001000110100 e+
+b100100011010000000010 s+
+b10010001101000000001000000000 (,
+b10010001101000000001000000000 0,
+b100100011010000000010 :,
 b1001000110100 J,
-b1001000110100 X,
-b1001000110100 g,
-b1001000110100 v,
-b1001000110100 $-
-b1001000110100 0-
-b1001000110100 @-
-b1001000110100 P-
-b1001000110100 [-
-b1001000110100 g-
-b10 m-
-b10 ^/
-b10 O1
-b10 @3
-b10 15
-b10 "7
-b10 q8
-b11111111 v8
-b10 w8
-b11111111 |8
-b10 }8
-b11111111 $9
-b10 %9
-b11111111 *9
-b10 +9
-b11111111 09
-b10 19
-b11111111 69
-b10 79
-b11111111 <9
-b10 =9
-b11111111 B9
-b1001000110100 G9
-b1001000110100 K9
-b10 Q9
-b1001000110100 U9
-b10 Y9
-b1001000110100 ]9
-b1001000110100 a9
-b10 g9
-b1001000110100 k9
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-b1001000110100 w9
-b10 }9
-b1001000110100 #:
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-b1001000110100 +:
-b1001000110100 /:
-b10 5:
-b1001000110100 9:
-b10 =:
-b10010001101 A:
-b1001000110100 E:
-b10 K:
-b10 O:
-b10010001101 S:
-b1001000110100 W:
-b10 ]:
-b10010001101 a:
-b10 e:
-b1001000110100 i:
-b1001000110100 m:
-b10 s:
-b1001000110100 w:
-b10 |:
-b1001000110100 #;
-b1001000110100 ';
-b10 -;
-b1001000110100 1;
-b10 6;
-b1001000110100 ;;
-b1001000110100 ?;
-b10 E;
-b1001000110100 I;
-b10 N;
-b10010001101 S;
-b1001000110100 W;
-b10 ];
-b10010001101 a;
-b10 f;
-b1001000110100 k;
-b1001000110100 o;
-b1001000110100 u;
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-b1001000 z;
-b10 };
-b10 $<
-b10 )<
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-b1001000110100 3<
-b1001000110100 7<
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-b10 I>
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+b100 e,
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+b10010001101000000001000000000 {-
+b10010001101000000001000000000 %.
+b100100011010000000010 /.
+b10 4.
+b10 S9
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+b11111111 g9
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+b1001000110100 r9
+b1001000110100 v9
+b10 |9
+b10010001101 3:
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+b10001 }<
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+b11000 &=
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+b11000 0=
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+b101000 9=
+b10111 :=
+b101001 ;=
+b10111 ==
+b101001 >=
+b101000 C=
+b10111 D=
+b101001 E=
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+b101001 H=
+b101000 L=
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+b10 N=
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+b10 Q=
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+b10 X=
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+b11000 p=
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+b10001 v=
+b101000 x=
+b10111 y=
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+b10111 |=
+b101001 }=
+b101000 #>
+b10111 $>
+b101001 %>
+b10111 '>
+b101001 (>
+b101000 +>
+b111101 ,>
+b10 ->
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+b10110 1>
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+b111101 6>
+b10 7>
+b10110 8>
+b10 :>
+b10110 ;>
+b10 C>
+b100 J>
+b10000010 U>
+b1000100 W>
+b1000100 Y>
+b10000010 [>
+b1000100 \>
+b1000100 ]>
+b1000100 ^>
 #222000000
 sAddSub\x20(0) "
 sHdlSome\x20(1) '
 b100101 )
+b0 *
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-0.
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-b100101 8
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-b100101 G
-b0 I
-0N
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-b100101 U
-b0 W
-0Z
-0\
-sHdlSome\x20(1) b
-b100101 d
-b0 f
-0i
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+0/
+sHdlSome\x20(1) 5
+b100101 7
+b0 8
+0:
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+sHdlSome\x20(1) B
+b100101 D
+b0 E
+b0 F
+b0 H
+sHdlSome\x20(1) X
+b100101 Z
+b0 [
+0]
+0_
+sHdlSome\x20(1) e
+b100101 g
 sHdlSome\x20(1) q
 b100101 s
-b0 u
-sU64\x20(0) x
-sHdlSome\x20(1) }
-b100101 !"
-b0 #"
-sU64\x20(0) &"
-sHdlSome\x20(1) +"
-b100101 -"
-b0 /"
-sEq\x20(0) 2"
-04"
-sHdlSome\x20(1) ;"
-b100101 ="
-b0 ?"
-sEq\x20(0) B"
-0D"
-b0 G"
-sHdlSome\x20(1) K"
-b100101 M"
-b0 O"
-sLoad\x20(0) Q"
-sHdlSome\x20(1) V"
-b100101 X"
-b0 Z"
+b0 t
+b0 v
+sHdlSome\x20(1) $"
+b100101 &"
+b0 '"
+sU64\x20(0) )"
+sHdlSome\x20(1) ."
+b100101 0"
+sHdlSome\x20(1) 7"
+b100101 9"
+b0 :"
+b0 ;"
+sEq\x20(0) ="
+0?"
+sHdlSome\x20(1) F"
+b100101 H"
+b0 I"
+sEq\x20(0) K"
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+sHdlSome\x20(1) T"
+b0 V"
+sHdlSome\x20(1) Z"
+b100101 \"
+sLoad\x20(0) ]"
 sHdlSome\x20(1) b"
 b100101 d"
-b0 f"
-b1111100011001000010100000010101 C&
-b110010000101000000101 G&
-b110010000101000000101 H&
-b110010000101000000101 I&
-b110010000101000000101 J&
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-b1001000110100 7>
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-sS32\x20(3) ;>
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-b10 =>
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-b1011 B>
-b1001000110100 C>
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-sU32\x20(2) G>
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-0K>
-b11 L>
-sU32\x20(2) M>
-b1011 N>
-b10 O>
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-b11 R>
-sCmpRBOne\x20(8) S>
-b1011 T>
-b10 U>
-b11 W>
-b1011 X>
-b1001000110100 Y>
-b1100 [>
-b1001000110100 ]>
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-b10 3?
-b1100 5?
-b10 7?
-b1100 9?
-b10 ;?
-b1100 =?
-b10 ??
-b1100 A?
-b10 C?
-b1100 E?
-b10 G?
-b1100 I?
-b10 K?
-b1100 M?
-b10 O?
-b1100 Q?
-b1100 T?
-b1100 W?
-b1100 Z?
-b1100 ]?
-b1100 `?
-b1100 c?
-b11 e?
-b1011 f?
+b0 N9
+sWidth32Bit\x20(2) O9
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+0k:
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+b1011 Z>
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+b1000100 \>
+b1000100 ]>
+b1000100 ^>
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-b11111111 *
-b1111111111000100110101011 +
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-0/
-b11111111 9
-b1111111111000100110101011 :
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-0>
-b11111111 H
-b1111111111000100110101011 I
-1J
-b11111111 V
-b1111111111000100110101011 W
-1X
-0[
-b11111111 e
-b1111111111000100110101011 f
-1g
+b10101011 )
+b10001001 *
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+1P
+1Q
+b10101011 Z
+b100011111111111111111110001001 [
+b1111111111111111111000100110101011 g
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-b11111111 t
-b1111111111000100110101011 u
-1v
-sS64\x20(1) x
-b11111111 ""
-b1111111111000100110101011 #"
-1$"
-sS64\x20(1) &"
-b11111111 ."
-b1111111111000100110101011 /"
-10"
-03"
-b11111111 >"
-b1111111111000100110101011 ?"
-1@"
-0C"
-b11111111 N"
-b1111111111000100110101011 O"
-1P"
-b11111111 Y"
-b1111111111000100110101011 Z"
-1["
-b11111111 e"
-b1111111111000100110101011 f"
-1g"
-b101101101001001000100110101011 C&
-b11010010010001001101010 G&
-b11010010010001001101010 H&
-b11010010010001001101010 I&
-b11010010010001001101010 J&
-b10001001101010 K&
-b1101 M&
-b1111111111000100110101000 Y&
-1Z&
-b1111111111000100110101000 h&
-1i&
-b1111111111000100110101000 w&
-1x&
-b1111111111000100110101000 ''
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-b1111111111000100110101000 6'
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-b1111111111000100110101000 E'
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-b1111111111000100110101000 Q'
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-b1111111111000100110101000 ]'
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-b1111111111000100110101000 m'
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-b1111111111000100110101000 }'
-1~'
-b1111111111000100110101000 *(
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-b1111111111000100110101000 6(
-17(
-b10001001101010 <(
-b1101 >(
-b1111111111000100110101000 J(
-1K(
-b1111111111000100110101000 Y(
-1Z(
-b1111111111000100110101000 h(
-1i(
-b1111111111000100110101000 v(
-1w(
-b1111111111000100110101000 ')
+b10101011 s
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+1w
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+b100011111111111111111110001001 '"
+b1111111111111111111000100110101011 0"
+sS64\x20(1) 2"
+b10101011 9"
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+b101101101001001000100110101011 X&
+b11010010010001001101010 \&
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+b1101 _&
+b11111111111000100110101000 k&
+b1111111111100010011010100000000000 x&
+b0 ('
+b101 *'
+b110 ,'
+b100 .'
+b1000 0'
+12'
+13'
+14'
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+b1110001001101010000000000000000000 I'
+sSignExt8\x20(7) J'
+1K'
+1L'
+1M'
+1N'
+b10100 X'
+1Y'
+sHdlSome\x20(1) Z'
+b100 ['
+b111111 \'
+1]'
+sSignExt8\x20(7) ^'
+sSignExt16To64BitThenShift\x20(5) _'
+b1111111111100010011010100000000000 g'
+b1110001001101010000000000000000000 p'
+sSignExt8\x20(7) q'
+s<invalid>\x20(15) r'
+b11111111111000100110101000 {'
+b1111111111100010011010100000000000 +(
+b1110001001101010000000000000000000 >(
+b1110001001101010000000000000000000 F(
+sWidth64Bit\x20(3) G(
+sSignExt\x20(1) H(
+b1111111111100010011010100000000000 P(
+b11111111111000100110101000 `(
+b1111111111100010011010100000000000 m(
+b0 {(
+b101 }(
+b110 !)
+b100 #)
+b1000 %)
+1')
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-b1111111111000100110101000 6)
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-b1111111111000100110101000 B)
+1))
+1*)
+b1111111111100010011010100000000000 2)
+b1110001001101010000000000000000000 >)
+sSignExt8\x20(7) ?)
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+1A)
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-b1111111111000100110101000 N)
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-b1111111111000100110101000 ^)
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-b1111111111000100110101000 n)
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-b1111111111000100110101000 y)
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-b1111111111000100110101000 '*
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-b10001001101010 -*
-b1101 /*
-b1111111111000100110101000 ;*
-1<*
-b1111111111000100110101000 J*
-1K*
-b1111111111000100110101000 Y*
-1Z*
-b1111111111000100110101000 g*
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-b1111111111000100110101000 v*
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-b1111111111000100110101000 '+
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-b1111111111000100110101000 3+
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-b1111111111000100110101000 ?+
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-b1111111111000100110101000 O+
-1P+
-b1111111111000100110101000 _+
-1`+
-b1111111111000100110101000 j+
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-b1111111111000100110101000 v+
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-b1111111111000100110101000 ,,
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-b1111111111000100110101000 ;,
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-b1111111111000100110101000 J,
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-b1111111111000100110101000 $-
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-b1111111111000100110101000 0-
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-b1111111111000100110101000 @-
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-b1111111111000100110101000 P-
-1Q-
-b1111111111000100110101000 [-
-1\-
-b1111111111000100110101000 g-
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-b1 m-
-b1101 o-
-b1 ^/
-b1101 `/
-b1 O1
-b1101 Q1
-b1 @3
-b1101 B3
-b1 15
-b1101 35
-b1 "7
-b1101 $7
-b10001 q8
-b1101 s8
-b1100 v8
-b10001 w8
-b1101 y8
-b1100 |8
-b10001 }8
-b1101 !9
-b1100 $9
-b10001 %9
-b1101 '9
-b1100 *9
-b10001 +9
-b1101 -9
-b1100 09
-b10001 19
-b1101 39
-b1100 69
-b10001 79
-b1101 99
-b1100 <9
-b10001 =9
-b1101 ?9
-b1100 B9
-b1000100110101011 G9
-b1101 I9
-b1000100110101011 K9
-b10001 Q9
-b1101 S9
-b1000100110101011 U9
-b1101 W9
-b10001 Y9
-b1101 [9
-b1000100110101011 ]9
-b1101 _9
-b1000100110101011 a9
-b10001 g9
-b1101 i9
-b1000100110101011 k9
-b1101 m9
-b10001 o9
-b1101 q9
-b1000100110101011 s9
-b1101 u9
-b1000100110101011 w9
-b10001 }9
-b1101 !:
-b1000100110101011 #:
-b1101 %:
-b10001 ':
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-b1000100110101011 +:
-b1101 -:
-b1000100110101011 /:
-b10001 5:
-b1101 7:
-b1000100110101011 9:
-b1101 ;:
-b10001 =:
-b1101 ?:
-b10001001101010 A:
-b1101 C:
-b1000100110101011 E:
-b10001 K:
-b1101 M:
-b10001 O:
-b1101 Q:
-b10001001101010 S:
-b1101 U:
-b1000100110101011 W:
-b10001 ]:
-b1101 _:
-b10001001101010 a:
-b1101 c:
-b10001 e:
-b1101 g:
-b1000100110101011 i:
-b1101 k:
-b1000100110101011 m:
-b10001 s:
-b1101 u:
-b1000100110101011 w:
-b1101 y:
-b10001 |:
-b1101 ~:
-b1000100110101011 #;
-b1101 %;
-b1000100110101011 ';
-b10001 -;
-b1101 /;
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-b1101 3;
-b10001 6;
-b1101 8;
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-b1101 =;
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-b10001 E;
-b1101 G;
-b1000100110101011 I;
-b1101 K;
-b10001 N;
-b1101 P;
-b10001001101010 S;
-b1101 U;
-b1000100110101011 W;
-b10001 ];
-b1101 _;
-b10001001101010 a;
-b1101 c;
-b10001 f;
-b1101 h;
-b1000100110101011 k;
-b1101 m;
-b1000100110101011 o;
-b1000100110101011 u;
-b1101 w;
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-b1000100110 z;
-b1101 |;
-b10001 };
-b1101 !<
-b10001 $<
-b1101 &<
-b10001 )<
-b1101 +<
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-b1101 0<
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-b1101 5<
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+b100 P)
+b111111 Q)
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+sSignExt8\x20(7) S)
+sSignExt16To64BitThenShift\x20(5) T)
+b1111111111100010011010100000000000 \)
+b1110001001101010000000000000000000 e)
+sSignExt8\x20(7) f)
+s<invalid>\x20(15) g)
+b11111111111000100110101000 p)
+b1111111111100010011010100000000000 ~)
+b1110001001101010000000000000000000 3*
+b1110001001101010000000000000000000 ;*
+sWidth64Bit\x20(3) <*
+sSignExt\x20(1) =*
+b1111111111100010011010100000000000 E*
+b11111111111000100110101000 U*
+b1111111111100010011010100000000000 b*
+b0 p*
+b101 r*
+b110 t*
+b100 v*
+b1000 x*
+1z*
+1{*
+1|*
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+b1111111111100010011010100000000000 '+
+b1110001001101010000000000000000000 3+
+sSignExt8\x20(7) 4+
+15+
+16+
+17+
+18+
+b10100 B+
+1C+
+sHdlSome\x20(1) D+
+b100 E+
+b111111 F+
+1G+
+sSignExt8\x20(7) H+
+sSignExt16To64BitThenShift\x20(5) I+
+b1111111111100010011010100000000000 Q+
+b1110001001101010000000000000000000 Z+
+sSignExt8\x20(7) [+
+s<invalid>\x20(15) \+
+b11111111111000100110101000 e+
+b1111111111100010011010100000000000 s+
+b1110001001101010000000000000000000 (,
+b1110001001101010000000000000000000 0,
+sWidth64Bit\x20(3) 1,
+sSignExt\x20(1) 2,
+b1111111111100010011010100000000000 :,
+b11111111111000100110101000 J,
+b1111111111100010011010100000000000 W,
+b0 e,
+b101 g,
+b110 i,
+b100 k,
+b1000 m,
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+b1111111111100010011010100000000000 z,
+b1110001001101010000000000000000000 (-
+sSignExt8\x20(7) )-
+1*-
+1+-
+1,-
+1--
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+18-
+sHdlSome\x20(1) 9-
+b100 :-
+b111111 ;-
+1<-
+sSignExt8\x20(7) =-
+sSignExt16To64BitThenShift\x20(5) >-
+b1111111111100010011010100000000000 F-
+b1110001001101010000000000000000000 O-
+sSignExt8\x20(7) P-
+s<invalid>\x20(15) Q-
+b11111111111000100110101000 Z-
+b1111111111100010011010100000000000 h-
+b1110001001101010000000000000000000 {-
+b1110001001101010000000000000000000 %.
+sWidth64Bit\x20(3) &.
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+b1111111111100010011010100000000000 /.
+b1 4.
+b1101 6.
+b10001 S9
+b1101 U9
+b1100 X9
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+b1100 d9
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+b1100 j9
+b1100 m9
+b1000100110101011 r9
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+b1000100110101011 v9
+b10001 |9
+b1101 ~9
+b10001001101010 3:
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+b1000100110101011 7:
+b1101 D:
+b1101 H:
+b1101 \:
+b1000100110101011 e:
+b1000100110101011 g:
+1k:
+b1000100110 l:
+b1101 n:
+b10001 o:
+b1101 q:
+1o;
+sS64\x20(1) q;
+1s;
+sS64\x20(1) u;
+b1000100110101011 w;
+sU64\x20(0) x;
+sU64\x20(0) z;
+sCmpRBTwo\x20(9) |;
+b10101 =<
+b110 ><
+b10001 ?<
+b1101 A<
+b100110 B<
+b110101 C<
+b1010 D<
+b10000 E<
+b1010 G<
+b10000 H<
+b100110 L<
+b110101 M<
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+b10000 O<
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+b1010 Y<
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+b1010 b<
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+b10000 o<
+b100110 s<
+b110101 t<
+b1010 u<
+b10000 v<
+b1010 x<
+b10000 y<
 b1101 }<
-b10001 "=
-b1101 $=
-b10001 '=
-b1101 )=
-b10001 ,=
-b1101 .=
-b10001 1=
-b1101 3=
-b10001 6=
-b1101 8=
-b10001 ;=
-b1101 ==
-b10001 @=
-b1101 B=
-b1101 F=
-b1101 J=
-b1101 N=
-b1101 R=
-b1101 V=
-b1101 Z=
-b1101 ^=
-b1101 b=
-b1101 f=
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+b100011 ~<
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+b100110 V=
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+b100110 d=
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+b11010 s=
 b1101 v=
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-b1101 $>
-b1101 (>
-b1101 ,>
-b1101 0>
-b1101 4>
-b1000100110101011 7>
-19>
-sS64\x20(1) ;>
-b10001 =>
-1?>
-sS64\x20(1) A>
-b1000100110101011 C>
-1E>
-sU64\x20(0) G>
-b10001 I>
-1K>
-sU64\x20(0) M>
-b10001 O>
-1Q>
-sCmpRBTwo\x20(9) S>
-b10001 U>
-b1000100110101011 Y>
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-19>
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-1?>
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-1E>
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-1K>
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-1Q>
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-b1101 [>
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 0.
-1/
-0=
-1>
-0N
-0Z
-1[
-0i
-1j
-sCmpEqB\x20(10) x
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-13"
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-1C"
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-b10100111000000 ;;
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-b101001110000 a;
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+#239000000
+10
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-b10100111000000 Y>
-b1100 [>
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+#240000000
+1-
+1:
+1]
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+b1111101101001000010100110000000 X&
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+1s;
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+#241000000
+0-
+1.
+0:
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+1L"
+b1111101100001000010100111000000 X&
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+b1000 >=
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+1l
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-sCmpRBOne\x20(8) x
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-sHdlSome\x20(1) }
-b0 !"
-b1000100110101011 #"
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+b10001001 t
+sZeroExt16\x20(4) |
+b100011 !"
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+b100000000000000000000000010001001 '"
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+b10001001 :"
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-b10001001101010 K&
-b11 L&
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-b1111111111000100110101000 m'
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+b1110000100000111000100110101011 X&
+b1000001110001001101010 \&
+b10001001101010 ]&
+b11 ^&
+b100 _&
+b11111111 `&
+b11111111 h&
+b11111111111000100110101000 k&
+sSignExt16\x20(5) l&
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+b1111111111100010011010100000000000 x&
+sSignExt16\x20(5) y&
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+b11111111 %'
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+b11111111 ;'
+b1111111111100010011010100000000000 ='
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+b11111111 H'
+b1110001001101010000000000000000000 I'
+sSignExt8\x20(7) J'
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+b11111111 e'
+b1111111111100010011010100000000000 g'
+sSignExt16\x20(5) h'
+sS8\x20(7) i'
+b11111111 o'
+b1110001001101010000000000000000000 p'
+sSignExt8\x20(7) q'
+s<invalid>\x20(15) r'
+b11111111 x'
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+b11111111 E(
+b1110001001101010000000000000000000 F(
+sWidth64Bit\x20(3) G(
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+sWidth16Bit\x20(1) Q(
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+b11111111111000100110101000 `(
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+sS32\x20(3) ^)
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+b1110001001101010000000000000000000 e)
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+b11111111 :*
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+sWidth64Bit\x20(3) <*
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+b1111111111100010011010100000000000 E*
+sWidth16Bit\x20(1) F*
+b11111111 J*
+b11111111 R*
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+b100 E+
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+b1111111111100010011010100000000000 Q+
+sSignExt16\x20(5) R+
+s<invalid>\x20(15) S+
+b11111111 Y+
+b1110001001101010000000000000000000 Z+
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-b11111111 d,
-b1111111111000100110101000 g,
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-sSignExt16\x20(5) i,
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-sSignExt16\x20(5) x,
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-sSignExt16\x20(5) &-
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+b101 g,
+b110 i,
+b1000 m,
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+b11111111 x,
+b1111111111100010011010100000000000 z,
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+b11111111 '-
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+b10100 7-
+b100 :-
+b111111 ;-
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+sSignExt8\x20(7) =-
+sFunnelShift2x64Bit\x20(3) >-
+b11111111 D-
+b1111111111100010011010100000000000 F-
+sSignExt16\x20(5) G-
+s<invalid>\x20(11) H-
+b11111111 N-
+b1110001001101010000000000000000000 O-
+sSignExt8\x20(7) P-
+s<invalid>\x20(15) Q-
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+b11111111111000100110101000 Z-
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+b11111111 f-
+b1111111111100010011010100000000000 h-
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-sSignExt16\x20(5) <0
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-sSignExt16\x20(5) K0
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-b11111111 U0
-sSignExt16\x20(5) Z0
-s<invalid>\x20(11) [0
-b11111111 a0
-sSignExt16\x20(5) f0
-s<invalid>\x20(11) g0
-b11111111 m0
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-sOverflow\x20(6) s0
-b11111111 }0
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-sOverflow\x20(6) %1
-b11111111 /1
-b11111111 :1
-sWidth16Bit\x20(1) ?1
-b11111111 F1
-sWidth16Bit\x20(1) K1
-b11 P1
-b100 Q1
-b11111111 R1
-b11111111 Z1
-sSignExt16\x20(5) _1
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+b11111111 }.
+b11111111 +/
+sFunnelShift2x32Bit\x20(2) 6/
+b11111111 </
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+sS32\x20(3) @/
+b11111111 F/
+b11111111 O/
+1S/
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+1a/
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+b11111111 r/
+b11111111 z/
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+b11111111 ,0
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+190
+b11111111 B0
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+1F0
+b11111111 O0
+b11111111 e0
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+1i0
+b11111111 r0
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+s<invalid>\x20(11) 51
+b11111111 ;1
+b11111111 D1
+1H1
+sOverflow\x20(6) I1
+b11111111 S1
+1V1
+sOverflow\x20(6) W1
+b11111111 g1
+b11111111 o1
 b11111111 x1
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+sWidth16Bit\x20(1) {1
+b11111111 !2
+b11111111 )2
 sSignExt16\x20(5) -2
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 b11111111 72
-sSignExt16\x20(5) <2
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-sSignExt16\x20(5) K2
-sS32\x20(3) L2
-b11111111 R2
-sSignExt16\x20(5) W2
-sS32\x20(3) X2
-b11111111 ^2
-1c2
-sOverflow\x20(6) d2
-b11111111 n2
-1s2
-sOverflow\x20(6) t2
-b11111111 ~2
-b11111111 +3
-sWidth16Bit\x20(1) 03
-b11111111 73
-sWidth16Bit\x20(1) <3
-b11 A3
-b100 B3
-b11111111 C3
-b11111111 K3
-sSignExt16\x20(5) P3
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-b11111111 Z3
-sSignExt16\x20(5) _3
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-sSignExt16\x20(5) |3
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-b11111111 (4
-sSignExt16\x20(5) -4
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-sSignExt16\x20(5) <4
-s<invalid>\x20(11) =4
-b11111111 C4
-sSignExt16\x20(5) H4
-s<invalid>\x20(11) I4
+sSignExt16\x20(5) :2
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+b11111111 D2
+b11111111 Z2
+sSignExt16\x20(5) ]2
+1^2
+b11111111 g2
+b11111111 s2
+sFunnelShift2x32Bit\x20(2) ~2
+b11111111 &3
+sSignExt16\x20(5) )3
+sS32\x20(3) *3
+b11111111 03
+b11111111 93
+1=3
+sOverflow\x20(6) >3
+b11111111 H3
+1K3
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+b11111111 \3
+b11111111 d3
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+b11111111 t3
+b11111111 |3
+sSignExt16\x20(5) "4
+1#4
+b11111111 ,4
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+b11111111 94
 b11111111 O4
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-sOverflow\x20(6) U4
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-sOverflow\x20(6) e4
-b11111111 o4
-b11111111 z4
-sWidth16Bit\x20(1) !5
-b11111111 (5
-sWidth16Bit\x20(1) -5
-b11 25
-b100 35
-b11111111 45
-b11111111 <5
-sSignExt16\x20(5) A5
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-b11111111 K5
-sSignExt16\x20(5) P5
-1Q5
-b11111111 Z5
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-b11111111 h5
-sSignExt16\x20(5) m5
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-sSignExt16\x20(5) |5
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-b11111111 (6
-sSignExt16\x20(5) -6
-sS32\x20(3) .6
-b11111111 46
-sSignExt16\x20(5) 96
-sS32\x20(3) :6
-b11111111 @6
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-sOverflow\x20(6) F6
-b11111111 P6
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-sOverflow\x20(6) V6
-b11111111 `6
-b11111111 k6
-sWidth16Bit\x20(1) p6
-b11111111 w6
-sWidth16Bit\x20(1) |6
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-b100 $7
-b11111111 %7
-b11111111 -7
-sSignExt16\x20(5) 27
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-sSignExt16\x20(5) A7
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-b11111111 Y7
-sSignExt16\x20(5) ^7
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-b11111111 h7
-sSignExt16\x20(5) m7
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-sSignExt16\x20(5) |7
-s<invalid>\x20(11) }7
-b11111111 %8
-sSignExt16\x20(5) *8
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-sOverflow\x20(6) 78
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-b11111111 \8
-sWidth16Bit\x20(1) a8
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-sWidth16Bit\x20(1) m8
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-b11 r8
-b100 s8
-b1001 t8
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-b1100 v8
-b10001 w8
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-b100 y8
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-b1001 "9
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-b1100 $9
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-b100 '9
-b1001 (9
-b11111111 )9
-b1100 *9
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-b1001 .9
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-b1100 09
-b10001 19
-b11 29
-b100 39
-b1001 49
-b11111111 59
-b1100 69
-b10001 79
-b11 89
-b100 99
-b1001 :9
+sSignExt16\x20(5) R4
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+b11111111 \4
+b11111111 h4
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+s<invalid>\x20(11) }4
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+1v5
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+1%6
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+1H6
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+b11111111 #7
+1'7
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+b11111111 27
+157
+sOverflow\x20(6) 67
+b11111111 F7
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+b11111111 ^7
+b11111111 f7
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+b11111111 t7
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+b11111111 98
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+1=8
+b11111111 F8
+b11111111 R8
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+b11111111 c8
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+b11111111 m8
+b11111111 v8
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+sOverflow\x20(6) {8
+b11111111 '9
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+sOverflow\x20(6) +9
 b11111111 ;9
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-b11 >9
-b100 ?9
-b1001 @9
-b11111111 A9
-b1100 B9
-b0 C9
-b1 D9
-b1001 E9
-b11111111 F9
-b1000100110101011 G9
-b11 H9
-b100 I9
-b100011 J9
-b111000100110101011 K9
-b10001 Q9
-b11 R9
-b100 S9
-b100011 T9
-b1000100110101011 U9
-b11 V9
-b100 W9
-b100011 X9
-b10001 Y9
-b11 Z9
-b100 [9
-b100011 \9
-b1000100110101011 ]9
-b11 ^9
-b100 _9
-b100011 `9
-b111000100110101011 a9
-b10001 g9
-b11 h9
-b100 i9
-b100011 j9
-b1000100110101011 k9
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-b1000100110101011 s9
-b11 t9
-b100 u9
-b100011 v9
-b111000100110101011 w9
-b10001 }9
-b11 ~9
-b100 !:
+b11111111 C9
+b11111111 L9
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+b10001 S9
+b11 T9
+b100 U9
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+b11111111 W9
+b1100 X9
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+b1100 [9
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+b100 ~9
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+b101000001110000000000000000000 3+
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+07+
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-0K,
-b10100000111000 X,
-0Y,
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-0h,
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-0w,
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-0%-
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-01-
-b10100000111000 @-
-0A-
-b10100000111000 P-
-0Q-
-b10100000111000 [-
-0\-
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-0h-
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-b110010100000111000 w9
-b101 }9
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-b10100000111000 +:
-b110010100000111000 /:
-b101 5:
-b10100000111000 9:
-b101 =:
-b101000001110 A:
-b110010100000111000 E:
-b101 K:
-b101 O:
-b101000001110 S:
-b110010100000111000 W:
-b101 ]:
-b101000001110 a:
-b101 e:
-b10100000111000 i:
-b110010100000111000 m:
-b101 s:
-b10100000111000 w:
-b101 |:
-b10100000111000 #;
-b110010100000111000 ';
-b101 -;
-b10100000111000 1;
-b101 6;
-b10100000111000 ;;
-b110010100000111000 ?;
-b101 E;
-b10100000111000 I;
-b101 N;
-b101000001110 S;
-b110010100000111000 W;
-b101 ];
-b101000001110 a;
-b101 f;
-b10100000111000 k;
-b110010100000111000 o;
-b10100000111000 u;
-0y;
-b10100000 z;
-b101 };
-b101 $<
-b101 )<
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-b10100000111000 7<
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-b101 =>
-b10100000111000 C>
-b101 I>
-b101 O>
-b101 U>
-b10100000111000 Y>
-b10100000111000 ]>
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-b10100000111000 e>
-b10100000111000 i>
-b10100000111000 m>
-b101 q>
-b101 u>
-b101 y>
-b101 }>
-b101 #?
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-b101 +?
-b101 /?
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-b101 7?
-b101 ;?
-b101 ??
-b101 C?
-b101 G?
-b101 K?
-b101 O?
+b1010000011100000000000 W,
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+b0 i,
+b10 m,
+0o,
+0p,
+0q,
+0r,
+b1010000011100000000000 z,
+b101000001110000000000000000000 (-
+sFull64\x20(0) )-
+0*-
+0+-
+0,-
+0--
+b11100 7-
+08-
+sHdlNone\x20(0) 9-
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+b0 ;-
+0<-
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+b1010000011100000000000 F-
+b101000001110000000000000000000 O-
+sFull64\x20(0) P-
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+b10100000111000 Z-
+b1010000011100000000000 h-
+b101000001110000000000000000000 {-
+b101000001110000000000000000000 %.
+sWidth8Bit\x20(0) &.
+sZeroExt\x20(0) '.
+b1010000011100000000000 /.
+b101 S9
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+b111100 a<
+b11 b<
+b11101 c<
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+b11101 f<
+b100000 i<
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+b11101 v<
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+b11101 y<
+b1 }<
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+b100000 #=
+b100000 &=
+b100000 )=
+b100000 -=
+b100000 0=
+b100000 3=
+b1 7=
+b100000 9=
+b11111 :=
+b100001 ;=
+b11111 ==
+b100001 >=
+b100000 C=
+b11111 D=
+b100001 E=
+b11111 G=
+b100001 H=
+b100000 L=
+b111010 M=
+b101 N=
+b11011 O=
+b101 Q=
+b11011 R=
+b100000 V=
+b111010 W=
+b101 X=
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+b101 [=
+b11011 \=
+b1 `=
+b101 a=
+b100000 d=
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+b100001 }=
+b100000 #>
+b11111 $>
+b100001 %>
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+b100001 (>
+b100000 +>
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+b101 ->
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+b101 0>
+b11011 1>
+b100000 5>
+b111010 6>
+b101 7>
+b11011 8>
+b101 :>
+b11011 ;>
+b101 C>
+b1010 J>
+b1100101 U>
+b10100011 W>
+b10100011 Y>
+b1100101 [>
+b10100011 \>
+b10100011 ]>
+b10100011 ^>
 #251000000
 sHdlSome\x20(1) '
-sHdlSome\x20(1) 6
-sHdlSome\x20(1) E
-sHdlSome\x20(1) S
-sHdlSome\x20(1) b
+sHdlSome\x20(1) 5
+sHdlSome\x20(1) B
+sHdlSome\x20(1) X
+sHdlSome\x20(1) e
 sHdlSome\x20(1) q
-sHdlSome\x20(1) }
-sHdlSome\x20(1) +"
-sHdlSome\x20(1) ;"
-sHdlSome\x20(1) K"
-sHdlSome\x20(1) V"
+sHdlSome\x20(1) $"
+sHdlSome\x20(1) ."
+sHdlSome\x20(1) 7"
+sHdlSome\x20(1) F"
+sHdlSome\x20(1) T"
+sHdlSome\x20(1) Z"
 sHdlSome\x20(1) b"
-b1111100100000110010100000111001 C&
-b10100000111001 G9
-b110010100000111001 K9
-b10100000111001 U9
-b10100000111001 ]9
-b110010100000111001 a9
-b10100000111001 k9
-b10100000111001 s9
-b110010100000111001 w9
-b10100000111001 #:
-b10100000111001 +:
-b110010100000111001 /:
-b10100000111001 9:
-b110010100000111001 E:
-b110010100000111001 W:
-b10100000111001 i:
-b110010100000111001 m:
-b10100000111001 w:
-b10100000111001 #;
-b110010100000111001 ';
-b10100000111001 1;
-b10100000111001 ;;
-b110010100000111001 ?;
-b10100000111001 I;
-b110010100000111001 W;
-b10100000111001 k;
-b110010100000111001 o;
-b10100000111001 u;
-1y;
-b10100000111001 3<
-b10100000111001 7<
-b10100000111001 O<
-b10100000111001 7>
-b10100000111001 C>
-b10100000111001 Y>
-b10100000111001 ]>
-b10100000111001 a>
-b10100000111001 e>
-b10100000111001 i>
-b10100000111001 m>
+sHdlSome\x20(1) k"
+b1111100100000110010100000111001 X&
+b10100000111001 r9
+b110010100000111001 v9
+b110010100000111001 7:
+b10100000111001 e:
+b110010100000111001 g:
+1k:
+b10100000111001 w;
 #252000000
 sHdlNone\x20(0) '
+1.
 1/
-10
-01
-sHdlNone\x20(0) 6
-1>
-1?
-0@
-sHdlNone\x20(0) E
-sHdlNone\x20(0) S
-1[
-1\
-0]
-sHdlNone\x20(0) b
-1j
-1k
-0l
+00
+sHdlNone\x20(0) 5
+1;
+1<
+0=
+sHdlNone\x20(0) B
+sHdlNone\x20(0) X
+1^
+1_
+0`
+sHdlNone\x20(0) e
 sHdlNone\x20(0) q
-sU8\x20(6) x
-sHdlNone\x20(0) }
-sU8\x20(6) &"
-sHdlNone\x20(0) +"
-13"
-14"
-05"
-sHdlNone\x20(0) ;"
-1C"
-1D"
-0E"
-sHdlNone\x20(0) K"
-sHdlNone\x20(0) V"
+sHdlNone\x20(0) $"
+sU8\x20(6) )"
+sHdlNone\x20(0) ."
+sHdlNone\x20(0) 7"
+1>"
+1?"
+0@"
+sHdlNone\x20(0) F"
+1L"
+1M"
+0N"
+sHdlNone\x20(0) T"
+sHdlNone\x20(0) Z"
 sHdlNone\x20(0) b"
-b1111100100000110010101001111000 C&
-b1000001100101010011110 G&
-b1000001100101010011110 H&
-b1000001100101010011110 I&
-b1000001100101010011110 J&
-b101010011110 K&
-b10101001111000 Y&
-b10101001111000 h&
-b10101001111000 w&
-b10101001111000 ''
-b10101001111000 6'
-b10101001111000 E'
-b10101001111000 Q'
-b10101001111000 ]'
-b10101001111000 m'
-b10101001111000 }'
-b10101001111000 *(
-b10101001111000 6(
-b101010011110 <(
-b10101001111000 J(
-b10101001111000 Y(
-b10101001111000 h(
-b10101001111000 v(
-b10101001111000 ')
-b10101001111000 6)
-b10101001111000 B)
-b10101001111000 N)
-b10101001111000 ^)
-b10101001111000 n)
-b10101001111000 y)
-b10101001111000 '*
-b101010011110 -*
-b10101001111000 ;*
-b10101001111000 J*
-b10101001111000 Y*
-b10101001111000 g*
-b10101001111000 v*
-b10101001111000 '+
-b10101001111000 3+
-b10101001111000 ?+
-b10101001111000 O+
-b10101001111000 _+
-b10101001111000 j+
-b10101001111000 v+
-b101010011110 |+
-b10101001111000 ,,
-b10101001111000 ;,
+sHdlNone\x20(0) k"
+b1111100100000110010101001111000 X&
+b1000001100101010011110 \&
+b101010011110 ]&
+b10101001111000 k&
+b1010100111100000000000 x&
+b1 ,'
+b101 .'
+b1010100111100000000000 ='
+b101010011110000000000000000000 I'
+b111100 X'
+b10101 ['
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+b101010011110000000000000000000 p'
+b10101001111000 {'
+b1010100111100000000000 +(
+b101010011110000000000000000000 >(
+b101010011110000000000000000000 F(
+b1010100111100000000000 P(
+b10101001111000 `(
+b1010100111100000000000 m(
+b1 !)
+b101 #)
+b1010100111100000000000 2)
+b101010011110000000000000000000 >)
+b111100 M)
+b10101 P)
+b1010100111100000000000 \)
+b101010011110000000000000000000 e)
+b10101001111000 p)
+b1010100111100000000000 ~)
+b101010011110000000000000000000 3*
+b101010011110000000000000000000 ;*
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+b10101001111000 U*
+b1010100111100000000000 b*
+b1 t*
+b101 v*
+b1010100111100000000000 '+
+b101010011110000000000000000000 3+
+b111100 B+
+b10101 E+
+b1010100111100000000000 Q+
+b101010011110000000000000000000 Z+
+b10101001111000 e+
+b1010100111100000000000 s+
+b101010011110000000000000000000 (,
+b101010011110000000000000000000 0,
+b1010100111100000000000 :,
 b10101001111000 J,
-b10101001111000 X,
-b10101001111000 g,
-b10101001111000 v,
-b10101001111000 $-
-b10101001111000 0-
-b10101001111000 @-
-b10101001111000 P-
-b10101001111000 [-
-b10101001111000 g-
-b10101001111000 G9
-b110010101001111000 K9
-b10101001111000 U9
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-b110010101001111000 a9
-b10101001111000 k9
-b10101001111000 s9
-b110010101001111000 w9
-b10101001111000 #:
-b10101001111000 +:
-b110010101001111000 /:
-b10101001111000 9:
-b101010011110 A:
-b110010101001111000 E:
-b101010011110 S:
-b110010101001111000 W:
-b101010011110 a:
-b10101001111000 i:
-b110010101001111000 m:
-b10101001111000 w:
-b10101001111000 #;
-b110010101001111000 ';
-b10101001111000 1;
-b10101001111000 ;;
-b110010101001111000 ?;
-b10101001111000 I;
-b101010011110 S;
-b110010101001111000 W;
-b101010011110 a;
-b10101001111000 k;
-b110010101001111000 o;
-b10101001111000 u;
-0y;
-b10101001 z;
-b10101001111000 3<
-b10101001111000 7<
-b10101001111000 O<
-b10101001111000 7>
-b10101001111000 C>
-b10101001111000 Y>
-b10101001111000 ]>
-b10101001111000 a>
-b10101001111000 e>
-b10101001111000 i>
-b10101001111000 m>
+b1010100111100000000000 W,
+b1 i,
+b101 k,
+b1010100111100000000000 z,
+b101010011110000000000000000000 (-
+b111100 7-
+b10101 :-
+b1010100111100000000000 F-
+b101010011110000000000000000000 O-
+b10101001111000 Z-
+b1010100111100000000000 h-
+b101010011110000000000000000000 {-
+b101010011110000000000000000000 %.
+b1010100111100000000000 /.
+b10101001111000 r9
+b110010101001111000 v9
+b101010011110 3:
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+0k:
+b10101001 l:
+b10101001111000 w;
+b1001 ><
+b101001 B<
+b10100 E<
+b10100 H<
+b101001 L<
+b10100 O<
+b10100 R<
+b101001 W<
+b10100 Z<
+b10100 ]<
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+b101001 s<
+b10100 v<
+b10100 y<
+b10011 }<
+b101001 #=
+b10111 &=
+b10111 )=
+b101001 -=
+b10111 0=
+b10111 3=
+b10011 7=
+b101001 9=
+b10110 :=
+b101010 ;=
+b10110 ==
+b101010 >=
+b101001 C=
+b10110 D=
+b101010 E=
+b10110 G=
+b101010 H=
+b101001 L=
+b10010 O=
+b10010 R=
+b101001 V=
+b10010 Y=
+b10010 \=
+b10011 `=
+b101001 d=
+b10111 g=
+b10111 j=
+b101001 m=
+b10111 p=
+b10111 s=
+b10011 v=
+b101001 x=
+b10110 y=
+b101010 z=
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+b101010 }=
+b101001 #>
+b10110 $>
+b101010 %>
+b10110 '>
+b101010 (>
+b101001 +>
+b10010 .>
+b10010 1>
+b101001 5>
+b10010 8>
+b10010 ;>
 #253000000
 sHdlSome\x20(1) '
-sHdlSome\x20(1) 6
-sHdlSome\x20(1) E
-sHdlSome\x20(1) S
-sHdlSome\x20(1) b
+sHdlSome\x20(1) 5
+sHdlSome\x20(1) B
+sHdlSome\x20(1) X
+sHdlSome\x20(1) e
 sHdlSome\x20(1) q
-sHdlSome\x20(1) }
-sHdlSome\x20(1) +"
-sHdlSome\x20(1) ;"
-sHdlSome\x20(1) K"
-sHdlSome\x20(1) V"
+sHdlSome\x20(1) $"
+sHdlSome\x20(1) ."
+sHdlSome\x20(1) 7"
+sHdlSome\x20(1) F"
+sHdlSome\x20(1) T"
+sHdlSome\x20(1) Z"
 sHdlSome\x20(1) b"
-b1111100100000110010101001111001 C&
-b10101001111001 G9
-b110010101001111001 K9
-b10101001111001 U9
-b10101001111001 ]9
-b110010101001111001 a9
-b10101001111001 k9
-b10101001111001 s9
-b110010101001111001 w9
-b10101001111001 #:
-b10101001111001 +:
-b110010101001111001 /:
-b10101001111001 9:
-b110010101001111001 E:
-b110010101001111001 W:
-b10101001111001 i:
-b110010101001111001 m:
-b10101001111001 w:
-b10101001111001 #;
-b110010101001111001 ';
-b10101001111001 1;
-b10101001111001 ;;
-b110010101001111001 ?;
-b10101001111001 I;
-b110010101001111001 W;
-b10101001111001 k;
-b110010101001111001 o;
-b10101001111001 u;
-1y;
-b10101001111001 3<
-b10101001111001 7<
-b10101001111001 O<
-b10101001111001 7>
-b10101001111001 C>
-b10101001111001 Y>
-b10101001111001 ]>
-b10101001111001 a>
-b10101001111001 e>
-b10101001111001 i>
-b10101001111001 m>
+sHdlSome\x20(1) k"
+b1111100100000110010101001111001 X&
+b10101001111001 r9
+b110010101001111001 v9
+b110010101001111001 7:
+b10101001111001 e:
+b110010101001111001 g:
+1k:
+b10101001111001 w;
 #254000000
 sHdlNone\x20(0) '
-1.
-sHdlNone\x20(0) 6
-1=
-sHdlNone\x20(0) E
-1N
-sHdlNone\x20(0) S
-1Z
-sHdlNone\x20(0) b
-1i
+1-
+sHdlNone\x20(0) 5
+1:
+sHdlNone\x20(0) B
+sHdlNone\x20(0) X
+1]
+sHdlNone\x20(0) e
 sHdlNone\x20(0) q
-sS8\x20(7) x
-sHdlNone\x20(0) }
-sS8\x20(7) &"
-sHdlNone\x20(0) +"
-sSGt\x20(4) 2"
-sHdlNone\x20(0) ;"
-sSGt\x20(4) B"
-sHdlNone\x20(0) K"
-sHdlNone\x20(0) V"
+sHdlNone\x20(0) $"
+sS8\x20(7) )"
+sHdlNone\x20(0) ."
+sHdlNone\x20(0) 7"
+sSGt\x20(4) ="
+sHdlNone\x20(0) F"
+sSGt\x20(4) K"
+sHdlNone\x20(0) T"
+sHdlNone\x20(0) Z"
 sHdlNone\x20(0) b"
-b1111100100000110010101110111000 C&
-b1000001100101011101110 G&
-b1000001100101011101110 H&
-b1000001100101011101110 I&
-b1000001100101011101110 J&
-b101011101110 K&
-b10101110111000 Y&
-b10101110111000 h&
-b10101110111000 w&
-b10101110111000 ''
-b10101110111000 6'
-b10101110111000 E'
-b10101110111000 Q'
-b10101110111000 ]'
-b10101110111000 m'
-b10101110111000 }'
-b10101110111000 *(
-b10101110111000 6(
-b101011101110 <(
-b10101110111000 J(
-b10101110111000 Y(
-b10101110111000 h(
-b10101110111000 v(
-b10101110111000 ')
-b10101110111000 6)
-b10101110111000 B)
-b10101110111000 N)
-b10101110111000 ^)
-b10101110111000 n)
-b10101110111000 y)
-b10101110111000 '*
-b101011101110 -*
-b10101110111000 ;*
-b10101110111000 J*
-b10101110111000 Y*
-b10101110111000 g*
-b10101110111000 v*
-b10101110111000 '+
-b10101110111000 3+
-b10101110111000 ?+
-b10101110111000 O+
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+b101011101110000000000000000000 (,
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 b10101110111000 J,
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-b110010101110111000 o;
-b10101110111000 u;
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+b1101 1>
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+b1101 8>
+b1101 ;>
 #255000000
 sHdlSome\x20(1) '
-sHdlSome\x20(1) 6
-sHdlSome\x20(1) E
-sHdlSome\x20(1) S
-sHdlSome\x20(1) b
+sHdlSome\x20(1) 5
+sHdlSome\x20(1) B
+sHdlSome\x20(1) X
+sHdlSome\x20(1) e
 sHdlSome\x20(1) q
-sHdlSome\x20(1) }
-sHdlSome\x20(1) +"
-sHdlSome\x20(1) ;"
-sHdlSome\x20(1) K"
-sHdlSome\x20(1) V"
+sHdlSome\x20(1) $"
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+sHdlSome\x20(1) 7"
+sHdlSome\x20(1) F"
+sHdlSome\x20(1) T"
+sHdlSome\x20(1) Z"
 sHdlSome\x20(1) b"
-b1111100100000110010101110111001 C&
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-b110010101110111001 K9
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-b10101110111001 ]9
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-b110010101110111001 ';
-b10101110111001 1;
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-b110010101110111001 ?;
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+1k:
+b10101110111001 w;
 #256000000
 sHdlNone\x20(0) '
-0.
-11
-sHdlNone\x20(0) 6
-0=
-1@
-sHdlNone\x20(0) E
-0N
-sHdlNone\x20(0) S
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-1]
-sHdlNone\x20(0) b
-0i
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+0-
+10
+sHdlNone\x20(0) 5
+0:
+1=
+sHdlNone\x20(0) B
+sHdlNone\x20(0) X
+0]
+1`
+sHdlNone\x20(0) e
 sHdlNone\x20(0) q
-s<invalid>\x20(14) x
-sHdlNone\x20(0) }
-s<invalid>\x20(14) &"
-sHdlNone\x20(0) +"
-sEq\x20(0) 2"
-15"
-sHdlNone\x20(0) ;"
-sEq\x20(0) B"
-1E"
-sHdlNone\x20(0) K"
-sHdlNone\x20(0) V"
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+sHdlNone\x20(0) ."
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+sEq\x20(0) ="
+1@"
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+sEq\x20(0) K"
+1N"
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+sHdlNone\x20(0) Z"
 sHdlNone\x20(0) b"
-b1111100100000110010101101111000 C&
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+b101011011110000000000000000000 (,
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 b10101101111000 J,
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-b110010101101111000 o;
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+b1110 1>
+b101101 5>
+b1110 8>
+b1110 ;>
 #257000000
 sTransformedMove\x20(1) !
 sAddSub\x20(0) "
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+0.
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-sU64\x20(0) x
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-b0 M"
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+sU64\x20(0) )"
+b0 0"
+b0 9"
+0>"
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+b0 H"
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+b0 V"
+b0 \"
+sLoad\x20(0) ]"
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-b1111100100000110010001101111000 C&
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-b10001101111000 B)
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-b10001101111000 n)
-b10001101111000 y)
-b10001101111000 '*
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+b100011011110000000000000000000 (,
+b100011011110000000000000000000 0,
+b1000110111100000000000 :,
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-b10001101111000 g,
-b10001101111000 v,
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-b10001101111000 0-
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-b10001101111000 P-
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-b0 m-
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-b10001101111000 ;;
-b110010001101111000 ?;
-b100 E;
-b10001101111000 I;
-b100 N;
-b100011011110 S;
-b110010001101111000 W;
-b100 ];
-b100011011110 a;
-b100 f;
-b10001101111000 k;
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-b100 };
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 #258000000
 sAluBranch\x20(0) !
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 sHdlSome\x20(1) q
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-b10101100111000 ,,
-b10101100111000 ;,
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+b100101 m"
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+b1010110011100000000000 m(
+b100 !)
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+b1010110011100000000000 2)
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+b11100 M)
+b10101 P)
+b1010110011100000000000 \)
+b101011001110000000000000000000 e)
+b10101100111000 p)
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+b1010110011100000000000 '+
+b101011001110000000000000000000 3+
+b11100 B+
+b10101 E+
+b1010110011100000000000 Q+
+b101011001110000000000000000000 Z+
+b10101100111000 e+
+b1010110011100000000000 s+
+b101011001110000000000000000000 (,
+b101011001110000000000000000000 0,
+b1010110011100000000000 :,
 b10101100111000 J,
-b10101100111000 X,
-b10101100111000 g,
-b10101100111000 v,
-b10101100111000 $-
-b10101100111000 0-
-b10101100111000 @-
-b10101100111000 P-
-b10101100111000 [-
-b10101100111000 g-
-b1 m-
-0(/
-08/
-b1 ^/
-0w0
-0)1
-b1 O1
-b1 @3
-b1 15
-b1 "7
-b101 q8
-b101 w8
-b101 }8
-b101 %9
-b101 +9
-b101 19
-b101 79
-b101 =9
-b10101100111000 G9
-b110010101100111000 K9
-b101 Q9
-b10101100111000 U9
-b101 Y9
-b10101100111000 ]9
-b110010101100111000 a9
-b101 g9
-b10101100111000 k9
-b101 o9
-b10101100111000 s9
-b110010101100111000 w9
-b101 }9
-b10101100111000 #:
-b101 ':
-b10101100111000 +:
-b110010101100111000 /:
-b101 5:
-b10101100111000 9:
-b101 =:
-b101011001110 A:
-b110010101100111000 E:
-b101 K:
-b101 O:
-b101011001110 S:
-b110010101100111000 W:
-b101 ]:
-b101011001110 a:
-b101 e:
-b10101100111000 i:
-b110010101100111000 m:
-b101 s:
-b10101100111000 w:
-b101 |:
-b10101100111000 #;
-b110010101100111000 ';
-b101 -;
-b10101100111000 1;
-b101 6;
-b10101100111000 ;;
-b110010101100111000 ?;
-b101 E;
-b10101100111000 I;
-b101 N;
-b101011001110 S;
-b110010101100111000 W;
-b101 ];
-b101011001110 a;
-b101 f;
-b10101100111000 k;
-b110010101100111000 o;
-b10101100111000 u;
-0y;
-b10101100 z;
-b101 };
-b101 $<
-b101 )<
-b101 .<
-b10101100111000 3<
-b10101100111000 7<
-b101 ;<
-b101 @<
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-b101 "=
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-b101 ,=
-b101 1=
-b101 6=
-b101 ;=
-b101 @=
-b10101100111000 7>
-b101 =>
-b10101100111000 C>
-b101 I>
-b101 O>
-b101 U>
-b10101100111000 Y>
-b10101100111000 ]>
-b10101100111000 a>
-b10101100111000 e>
-b10101100111000 i>
-b10101100111000 m>
-b101 q>
-b101 u>
-b101 y>
-b101 }>
-b101 #?
-b101 '?
-b101 +?
-b101 /?
-b101 3?
-b101 7?
-b101 ;?
-b101 ??
-b101 C?
-b101 G?
-b101 K?
-b101 O?
+b1010110011100000000000 W,
+b100 i,
+b101 k,
+b1010110011100000000000 z,
+b101011001110000000000000000000 (-
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+b101011001110000000000000000000 {-
+b101011001110000000000000000000 %.
+b1010110011100000000000 /.
+b1 4.
+0X/
+0f/
+0M1
+0[1
+b101 S9
+b10101100111000 r9
+b110010101100111000 v9
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+b101011001110 3:
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+b10011 ==
+b101101 >=
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+b101101 H=
+b101100 L=
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+b111010 ,>
+b101 ->
+b101 0>
+b101100 5>
+b111010 6>
+b101 7>
+b101 :>
+b101 C>
+b1010 J>
+b1100101 U>
+b10100011 W>
+b10100011 Y>
+b1100101 [>
+b10100011 \>
+b10100011 ]>
+b10100011 ^>
 #261000000
 sHdlSome\x20(1) '
-sHdlSome\x20(1) 6
-sHdlSome\x20(1) E
-sHdlSome\x20(1) S
-sHdlSome\x20(1) b
+sHdlSome\x20(1) 5
+sHdlSome\x20(1) B
+sHdlSome\x20(1) X
+sHdlSome\x20(1) e
 sHdlSome\x20(1) q
-sHdlSome\x20(1) }
-sHdlSome\x20(1) +"
-sHdlSome\x20(1) ;"
-sHdlSome\x20(1) K"
-sHdlSome\x20(1) V"
+sHdlSome\x20(1) $"
+sHdlSome\x20(1) ."
+sHdlSome\x20(1) 7"
+sHdlSome\x20(1) F"
+sHdlSome\x20(1) T"
+sHdlSome\x20(1) Z"
 sHdlSome\x20(1) b"
-b1111100100000110010101100111001 C&
-b10101100111001 G9
-b110010101100111001 K9
-b10101100111001 U9
-b10101100111001 ]9
-b110010101100111001 a9
-b10101100111001 k9
-b10101100111001 s9
-b110010101100111001 w9
-b10101100111001 #:
-b10101100111001 +:
-b110010101100111001 /:
-b10101100111001 9:
-b110010101100111001 E:
-b110010101100111001 W:
-b10101100111001 i:
-b110010101100111001 m:
-b10101100111001 w:
-b10101100111001 #;
-b110010101100111001 ';
-b10101100111001 1;
-b10101100111001 ;;
-b110010101100111001 ?;
-b10101100111001 I;
-b110010101100111001 W;
-b10101100111001 k;
-b110010101100111001 o;
-b10101100111001 u;
-1y;
-b10101100111001 3<
-b10101100111001 7<
-b10101100111001 O<
-b10101100111001 7>
-b10101100111001 C>
-b10101100111001 Y>
-b10101100111001 ]>
-b10101100111001 a>
-b10101100111001 e>
-b10101100111001 i>
-b10101100111001 m>
+sHdlSome\x20(1) k"
+b1111100100000110010101100111001 X&
+b10101100111001 r9
+b110010101100111001 v9
+b110010101100111001 7:
+b10101100111001 e:
+b110010101100111001 g:
+1k:
+b10101100111001 w;
 #262000000
 sHdlNone\x20(0) '
-0/
-01
-sHdlNone\x20(0) 6
-0>
-0@
-sHdlNone\x20(0) E
-sHdlNone\x20(0) S
-0[
-0]
-sHdlNone\x20(0) b
-0j
-0l
+0.
+00
+sHdlNone\x20(0) 5
+0;
+0=
+sHdlNone\x20(0) B
+sHdlNone\x20(0) X
+0^
+0`
+sHdlNone\x20(0) e
 sHdlNone\x20(0) q
-sS64\x20(1) x
-sHdlNone\x20(0) }
-sS64\x20(1) &"
-sHdlNone\x20(0) +"
-03"
-05"
-sHdlNone\x20(0) ;"
-0C"
-0E"
-sHdlNone\x20(0) K"
-sHdlNone\x20(0) V"
+sHdlNone\x20(0) $"
+sS64\x20(1) )"
+sHdlNone\x20(0) ."
+sHdlNone\x20(0) 7"
+0>"
+0@"
+sHdlNone\x20(0) F"
+0L"
+0N"
+sHdlNone\x20(0) T"
+sHdlNone\x20(0) Z"
 sHdlNone\x20(0) b"
-b1111100100000110010100011111000 C&
-b1000001100101000111110 G&
-b1000001100101000111110 H&
-b1000001100101000111110 I&
-b1000001100101000111110 J&
-b101000111110 K&
-b10100011111000 Y&
-b10100011111000 h&
-b10100011111000 w&
-b10100011111000 ''
-b10100011111000 6'
-b10100011111000 E'
-b10100011111000 Q'
-b10100011111000 ]'
-b10100011111000 m'
-b10100011111000 }'
-b10100011111000 *(
-b10100011111000 6(
-b101000111110 <(
-b10100011111000 J(
-b10100011111000 Y(
-b10100011111000 h(
-b10100011111000 v(
-b10100011111000 ')
-b10100011111000 6)
-b10100011111000 B)
-b10100011111000 N)
-b10100011111000 ^)
-b10100011111000 n)
-b10100011111000 y)
-b10100011111000 '*
-b101000111110 -*
-b10100011111000 ;*
-b10100011111000 J*
-b10100011111000 Y*
-b10100011111000 g*
-b10100011111000 v*
-b10100011111000 '+
-b10100011111000 3+
-b10100011111000 ?+
-b10100011111000 O+
-b10100011111000 _+
-b10100011111000 j+
-b10100011111000 v+
-b101000111110 |+
-b10100011111000 ,,
-b10100011111000 ;,
+sHdlNone\x20(0) k"
+b1111100100000110010100011111000 X&
+b1000001100101000111110 \&
+b101000111110 ]&
+b10100011111000 k&
+b1010001111100000000000 x&
+b11 ,'
+b100 .'
+b1010001111100000000000 ='
+b101000111110000000000000000000 I'
+b111100 X'
+1Y'
+sHdlNone\x20(0) Z'
+b10100 ['
+b1010001111100000000000 g'
+b101000111110000000000000000000 p'
+b10100011111000 {'
+b1010001111100000000000 +(
+b101000111110000000000000000000 >(
+b101000111110000000000000000000 F(
+b1010001111100000000000 P(
+b10100011111000 `(
+b1010001111100000000000 m(
+b11 !)
+b100 #)
+b1010001111100000000000 2)
+b101000111110000000000000000000 >)
+b111100 M)
+1N)
+sHdlNone\x20(0) O)
+b10100 P)
+b1010001111100000000000 \)
+b101000111110000000000000000000 e)
+b10100011111000 p)
+b1010001111100000000000 ~)
+b101000111110000000000000000000 3*
+b101000111110000000000000000000 ;*
+b1010001111100000000000 E*
+b10100011111000 U*
+b1010001111100000000000 b*
+b11 t*
+b100 v*
+b1010001111100000000000 '+
+b101000111110000000000000000000 3+
+b111100 B+
+1C+
+sHdlNone\x20(0) D+
+b10100 E+
+b1010001111100000000000 Q+
+b101000111110000000000000000000 Z+
+b10100011111000 e+
+b1010001111100000000000 s+
+b101000111110000000000000000000 (,
+b101000111110000000000000000000 0,
+b1010001111100000000000 :,
 b10100011111000 J,
-b10100011111000 X,
-b10100011111000 g,
-b10100011111000 v,
-b10100011111000 $-
-b10100011111000 0-
-b10100011111000 @-
-b10100011111000 P-
-b10100011111000 [-
-b10100011111000 g-
-b10100011111000 G9
-b110010100011111000 K9
-b10100011111000 U9
-b10100011111000 ]9
-b110010100011111000 a9
-b10100011111000 k9
-b10100011111000 s9
-b110010100011111000 w9
-b10100011111000 #:
-b10100011111000 +:
-b110010100011111000 /:
-b10100011111000 9:
-b101000111110 A:
-b110010100011111000 E:
-b101000111110 S:
-b110010100011111000 W:
-b101000111110 a:
-b10100011111000 i:
-b110010100011111000 m:
-b10100011111000 w:
-b10100011111000 #;
-b110010100011111000 ';
-b10100011111000 1;
-b10100011111000 ;;
-b110010100011111000 ?;
-b10100011111000 I;
-b101000111110 S;
-b110010100011111000 W;
-b101000111110 a;
-b10100011111000 k;
-b110010100011111000 o;
-b10100011111000 u;
-0y;
-b10100011 z;
-b10100011111000 3<
-b10100011111000 7<
-b10100011111000 O<
-b10100011111000 7>
-b10100011111000 C>
-b10100011111000 Y>
-b10100011111000 ]>
-b10100011111000 a>
-b10100011111000 e>
-b10100011111000 i>
-b10100011111000 m>
+b1010001111100000000000 W,
+b11 i,
+b100 k,
+b1010001111100000000000 z,
+b101000111110000000000000000000 (-
+b111100 7-
+18-
+sHdlNone\x20(0) 9-
+b10100 :-
+b1010001111100000000000 F-
+b101000111110000000000000000000 O-
+b10100011111000 Z-
+b1010001111100000000000 h-
+b101000111110000000000000000000 {-
+b101000111110000000000000000000 %.
+b1010001111100000000000 /.
+b10100011111000 r9
+b110010100011111000 v9
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+b10100011111000 e:
+b110010100011111000 g:
+0k:
+b10100011 l:
+b10100011111000 w;
+b11 ><
+b100011 B<
+b11010 E<
+b11010 H<
+b100011 L<
+b11010 O<
+b11010 R<
+b100011 W<
+b11010 Z<
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+b11010 f<
+b100011 i<
+b11010 l<
+b11010 o<
+b100011 s<
+b11010 v<
+b11010 y<
+b111 }<
+b100011 #=
+b11101 &=
+b11101 )=
+b100011 -=
+b11101 0=
+b11101 3=
+b111 7=
+b100011 9=
+b11100 :=
+b100100 ;=
+b11100 ==
+b100100 >=
+b100011 C=
+b11100 D=
+b100100 E=
+b11100 G=
+b100100 H=
+b100011 L=
+b11000 O=
+b11000 R=
+b100011 V=
+b11000 Y=
+b11000 \=
+b111 `=
+b100011 d=
+b11101 g=
+b11101 j=
+b100011 m=
+b11101 p=
+b11101 s=
+b111 v=
+b100011 x=
+b11100 y=
+b100100 z=
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+b100100 }=
+b100011 #>
+b11100 $>
+b100100 %>
+b11100 '>
+b100100 (>
+b100011 +>
+b11000 .>
+b11000 1>
+b100011 5>
+b11000 8>
+b11000 ;>
 #263000000
 sHdlSome\x20(1) '
-sHdlSome\x20(1) 6
-sHdlSome\x20(1) E
-sHdlSome\x20(1) S
-sHdlSome\x20(1) b
+sHdlSome\x20(1) 5
+sHdlSome\x20(1) B
+sHdlSome\x20(1) X
+sHdlSome\x20(1) e
 sHdlSome\x20(1) q
-sHdlSome\x20(1) }
-sHdlSome\x20(1) +"
-sHdlSome\x20(1) ;"
-sHdlSome\x20(1) K"
-sHdlSome\x20(1) V"
+sHdlSome\x20(1) $"
+sHdlSome\x20(1) ."
+sHdlSome\x20(1) 7"
+sHdlSome\x20(1) F"
+sHdlSome\x20(1) T"
+sHdlSome\x20(1) Z"
 sHdlSome\x20(1) b"
-b1111100100000110010100011111001 C&
-b10100011111001 G9
-b110010100011111001 K9
-b10100011111001 U9
-b10100011111001 ]9
-b110010100011111001 a9
-b10100011111001 k9
-b10100011111001 s9
-b110010100011111001 w9
-b10100011111001 #:
-b10100011111001 +:
-b110010100011111001 /:
-b10100011111001 9:
-b110010100011111001 E:
-b110010100011111001 W:
-b10100011111001 i:
-b110010100011111001 m:
-b10100011111001 w:
-b10100011111001 #;
-b110010100011111001 ';
-b10100011111001 1;
-b10100011111001 ;;
-b110010100011111001 ?;
-b10100011111001 I;
-b110010100011111001 W;
-b10100011111001 k;
-b110010100011111001 o;
-b10100011111001 u;
-1y;
-b10100011111001 3<
-b10100011111001 7<
-b10100011111001 O<
-b10100011111001 7>
-b10100011111001 C>
-b10100011111001 Y>
-b10100011111001 ]>
-b10100011111001 a>
-b10100011111001 e>
-b10100011111001 i>
-b10100011111001 m>
+sHdlSome\x20(1) k"
+b1111100100000110010100011111001 X&
+b10100011111001 r9
+b110010100011111001 v9
+b110010100011111001 7:
+b10100011111001 e:
+b110010100011111001 g:
+1k:
+b10100011111001 w;
 #264000000
 sHdlNone\x20(0) '
-11
-sHdlNone\x20(0) 6
-1@
-sHdlNone\x20(0) E
-sHdlNone\x20(0) S
-1]
-sHdlNone\x20(0) b
-1l
+10
+sHdlNone\x20(0) 5
+1=
+sHdlNone\x20(0) B
+sHdlNone\x20(0) X
+1`
+sHdlNone\x20(0) e
 sHdlNone\x20(0) q
-sCmpRBTwo\x20(9) x
-sHdlNone\x20(0) }
-sCmpRBTwo\x20(9) &"
-sHdlNone\x20(0) +"
-15"
-sHdlNone\x20(0) ;"
-1E"
-sHdlNone\x20(0) K"
-sHdlNone\x20(0) V"
+sHdlNone\x20(0) $"
+sCmpRBTwo\x20(9) )"
+sHdlNone\x20(0) ."
+sHdlNone\x20(0) 7"
+1@"
+sHdlNone\x20(0) F"
+1N"
+sHdlNone\x20(0) T"
+sHdlNone\x20(0) Z"
 sHdlNone\x20(0) b"
-b1111100100000110010101000111000 C&
-b1000001100101010001110 G&
-b1000001100101010001110 H&
-b1000001100101010001110 I&
-b1000001100101010001110 J&
-b101010001110 K&
-b10101000111000 Y&
-b10101000111000 h&
-b10101000111000 w&
-b10101000111000 ''
-b10101000111000 6'
-b10101000111000 E'
-b10101000111000 Q'
-b10101000111000 ]'
-b10101000111000 m'
-b10101000111000 }'
-b10101000111000 *(
-b10101000111000 6(
-b101010001110 <(
-b10101000111000 J(
-b10101000111000 Y(
-b10101000111000 h(
-b10101000111000 v(
-b10101000111000 ')
-b10101000111000 6)
-b10101000111000 B)
-b10101000111000 N)
-b10101000111000 ^)
-b10101000111000 n)
-b10101000111000 y)
-b10101000111000 '*
-b101010001110 -*
-b10101000111000 ;*
-b10101000111000 J*
-b10101000111000 Y*
-b10101000111000 g*
-b10101000111000 v*
-b10101000111000 '+
-b10101000111000 3+
-b10101000111000 ?+
-b10101000111000 O+
-b10101000111000 _+
-b10101000111000 j+
-b10101000111000 v+
-b101010001110 |+
-b10101000111000 ,,
-b10101000111000 ;,
+sHdlNone\x20(0) k"
+b1111100100000110010101000111000 X&
+b1000001100101010001110 \&
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+b1010100011100000000000 ='
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+b11100 X'
+0Y'
+b10101 ['
+b1010100011100000000000 g'
+b101010001110000000000000000000 p'
+b10101000111000 {'
+b1010100011100000000000 +(
+b101010001110000000000000000000 >(
+b101010001110000000000000000000 F(
+b1010100011100000000000 P(
+b10101000111000 `(
+b1010100011100000000000 m(
+b0 !)
+b101 #)
+b1010100011100000000000 2)
+b101010001110000000000000000000 >)
+b11100 M)
+0N)
+b10101 P)
+b1010100011100000000000 \)
+b101010001110000000000000000000 e)
+b10101000111000 p)
+b1010100011100000000000 ~)
+b101010001110000000000000000000 3*
+b101010001110000000000000000000 ;*
+b1010100011100000000000 E*
+b10101000111000 U*
+b1010100011100000000000 b*
+b0 t*
+b101 v*
+b1010100011100000000000 '+
+b101010001110000000000000000000 3+
+b11100 B+
+0C+
+b10101 E+
+b1010100011100000000000 Q+
+b101010001110000000000000000000 Z+
+b10101000111000 e+
+b1010100011100000000000 s+
+b101010001110000000000000000000 (,
+b101010001110000000000000000000 0,
+b1010100011100000000000 :,
 b10101000111000 J,
-b10101000111000 X,
-b10101000111000 g,
-b10101000111000 v,
-b10101000111000 $-
-b10101000111000 0-
-b10101000111000 @-
-b10101000111000 P-
-b10101000111000 [-
-b10101000111000 g-
-b10101000111000 G9
-b110010101000111000 K9
-b10101000111000 U9
-b10101000111000 ]9
-b110010101000111000 a9
-b10101000111000 k9
-b10101000111000 s9
-b110010101000111000 w9
-b10101000111000 #:
-b10101000111000 +:
-b110010101000111000 /:
-b10101000111000 9:
-b101010001110 A:
-b110010101000111000 E:
-b101010001110 S:
-b110010101000111000 W:
-b101010001110 a:
-b10101000111000 i:
-b110010101000111000 m:
-b10101000111000 w:
-b10101000111000 #;
-b110010101000111000 ';
-b10101000111000 1;
-b10101000111000 ;;
-b110010101000111000 ?;
-b10101000111000 I;
-b101010001110 S;
-b110010101000111000 W;
-b101010001110 a;
-b10101000111000 k;
-b110010101000111000 o;
-b10101000111000 u;
-0y;
-b10101000 z;
-b10101000111000 3<
-b10101000111000 7<
-b10101000111000 O<
-b10101000111000 7>
-b10101000111000 C>
-b10101000111000 Y>
-b10101000111000 ]>
-b10101000111000 a>
-b10101000111000 e>
-b10101000111000 i>
-b10101000111000 m>
+b1010100011100000000000 W,
+b0 i,
+b101 k,
+b1010100011100000000000 z,
+b101010001110000000000000000000 (-
+b11100 7-
+08-
+b10101 :-
+b1010100011100000000000 F-
+b101010001110000000000000000000 O-
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+b1010100011100000000000 h-
+b101010001110000000000000000000 {-
+b101010001110000000000000000000 %.
+b1010100011100000000000 /.
+b10101000111000 r9
+b110010101000111000 v9
+b101010001110 3:
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+b110010101000111000 g:
+0k:
+b10101000 l:
+b10101000111000 w;
+b1000 ><
+b101000 B<
+b10101 E<
+b10101 H<
+b101000 L<
+b10101 O<
+b10101 R<
+b101000 W<
+b10101 Z<
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+b10101 f<
+b101000 i<
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+b101000 s<
+b10101 v<
+b10101 y<
+b10001 }<
+b101000 #=
+b11000 &=
+b11000 )=
+b101000 -=
+b11000 0=
+b11000 3=
+b10001 7=
+b101000 9=
+b10111 :=
+b101001 ;=
+b10111 ==
+b101001 >=
+b101000 C=
+b10111 D=
+b101001 E=
+b10111 G=
+b101001 H=
+b101000 L=
+b10011 O=
+b10011 R=
+b101000 V=
+b10011 Y=
+b10011 \=
+b10001 `=
+b101000 d=
+b11000 g=
+b11000 j=
+b101000 m=
+b11000 p=
+b11000 s=
+b10001 v=
+b101000 x=
+b10111 y=
+b101001 z=
+b10111 |=
+b101001 }=
+b101000 #>
+b10111 $>
+b101001 %>
+b10111 '>
+b101001 (>
+b101000 +>
+b10011 .>
+b10011 1>
+b101000 5>
+b10011 8>
+b10011 ;>
 #265000000
 sHdlSome\x20(1) '
-sHdlSome\x20(1) 6
-sHdlSome\x20(1) E
-sHdlSome\x20(1) S
-sHdlSome\x20(1) b
+sHdlSome\x20(1) 5
+sHdlSome\x20(1) B
+sHdlSome\x20(1) X
+sHdlSome\x20(1) e
 sHdlSome\x20(1) q
-sHdlSome\x20(1) }
-sHdlSome\x20(1) +"
-sHdlSome\x20(1) ;"
-sHdlSome\x20(1) K"
-sHdlSome\x20(1) V"
+sHdlSome\x20(1) $"
+sHdlSome\x20(1) ."
+sHdlSome\x20(1) 7"
+sHdlSome\x20(1) F"
+sHdlSome\x20(1) T"
+sHdlSome\x20(1) Z"
 sHdlSome\x20(1) b"
-b1111100100000110010101000111001 C&
-b10101000111001 G9
-b110010101000111001 K9
-b10101000111001 U9
-b10101000111001 ]9
-b110010101000111001 a9
-b10101000111001 k9
-b10101000111001 s9
-b110010101000111001 w9
-b10101000111001 #:
-b10101000111001 +:
-b110010101000111001 /:
-b10101000111001 9:
-b110010101000111001 E:
-b110010101000111001 W:
-b10101000111001 i:
-b110010101000111001 m:
-b10101000111001 w:
-b10101000111001 #;
-b110010101000111001 ';
-b10101000111001 1;
-b10101000111001 ;;
-b110010101000111001 ?;
-b10101000111001 I;
-b110010101000111001 W;
-b10101000111001 k;
-b110010101000111001 o;
-b10101000111001 u;
-1y;
-b10101000111001 3<
-b10101000111001 7<
-b10101000111001 O<
-b10101000111001 7>
-b10101000111001 C>
-b10101000111001 Y>
-b10101000111001 ]>
-b10101000111001 a>
-b10101000111001 e>
-b10101000111001 i>
-b10101000111001 m>
+sHdlSome\x20(1) k"
+b1111100100000110010101000111001 X&
+b10101000111001 r9
+b110010101000111001 v9
+b110010101000111001 7:
+b10101000111001 e:
+b110010101000111001 g:
+1k:
+b10101000111001 w;
 #266000000
 sHdlNone\x20(0) '
-0.
-1/
-01
-sHdlNone\x20(0) 6
+0-
+1.
+00
+sHdlNone\x20(0) 5
+0:
+1;
 0=
-1>
-0@
-sHdlNone\x20(0) E
-0N
-sHdlNone\x20(0) S
-0Z
-1[
+sHdlNone\x20(0) B
+sHdlNone\x20(0) X
 0]
-sHdlNone\x20(0) b
-0i
-1j
-0l
+1^
+0`
+sHdlNone\x20(0) e
 sHdlNone\x20(0) q
-sU32\x20(2) x
-sHdlNone\x20(0) }
-sU32\x20(2) &"
-sHdlNone\x20(0) +"
-sEq\x20(0) 2"
-13"
-05"
-sHdlNone\x20(0) ;"
-sEq\x20(0) B"
-1C"
-0E"
-sHdlNone\x20(0) K"
-sHdlNone\x20(0) V"
+sHdlNone\x20(0) $"
+sU32\x20(2) )"
+sHdlNone\x20(0) ."
+sHdlNone\x20(0) 7"
+sEq\x20(0) ="
+1>"
+0@"
+sHdlNone\x20(0) F"
+sEq\x20(0) K"
+1L"
+0N"
+sHdlNone\x20(0) T"
+sHdlNone\x20(0) Z"
 sHdlNone\x20(0) b"
-b1111100100000110010100001111000 C&
-b1000001100101000011110 G&
-b1000001100101000011110 H&
-b1000001100101000011110 I&
-b1000001100101000011110 J&
-b101000011110 K&
-b10100001111000 Y&
-b10100001111000 h&
-b10100001111000 w&
-b10100001111000 ''
-b10100001111000 6'
-b10100001111000 E'
-b10100001111000 Q'
-b10100001111000 ]'
-b10100001111000 m'
-b10100001111000 }'
-b10100001111000 *(
-b10100001111000 6(
-b101000011110 <(
-b10100001111000 J(
-b10100001111000 Y(
-b10100001111000 h(
-b10100001111000 v(
-b10100001111000 ')
-b10100001111000 6)
-b10100001111000 B)
-b10100001111000 N)
-b10100001111000 ^)
-b10100001111000 n)
-b10100001111000 y)
-b10100001111000 '*
-b101000011110 -*
-b10100001111000 ;*
-b10100001111000 J*
-b10100001111000 Y*
-b10100001111000 g*
-b10100001111000 v*
-b10100001111000 '+
-b10100001111000 3+
-b10100001111000 ?+
-b10100001111000 O+
-b10100001111000 _+
-b10100001111000 j+
-b10100001111000 v+
-b101000011110 |+
-b10100001111000 ,,
-b10100001111000 ;,
+sHdlNone\x20(0) k"
+b1111100100000110010100001111000 X&
+b1000001100101000011110 \&
+b101000011110 ]&
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+b1010000111100000000000 x&
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+b111100 X'
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+b10100001111000 `(
+b1010000111100000000000 m(
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+b100 #)
+b1010000111100000000000 2)
+b101000011110000000000000000000 >)
+b111100 M)
+b10100 P)
+b1010000111100000000000 \)
+b101000011110000000000000000000 e)
+b10100001111000 p)
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+b1010000111100000000000 '+
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+b111100 B+
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+b101000011110000000000000000000 Z+
+b10100001111000 e+
+b1010000111100000000000 s+
+b101000011110000000000000000000 (,
+b101000011110000000000000000000 0,
+b1010000111100000000000 :,
 b10100001111000 J,
-b10100001111000 X,
-b10100001111000 g,
-b10100001111000 v,
-b10100001111000 $-
-b10100001111000 0-
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-b10100001111000 P-
-b10100001111000 [-
-b10100001111000 g-
-b10100001111000 G9
-b110010100001111000 K9
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-b10100001111000 ]9
-b110010100001111000 a9
-b10100001111000 k9
-b10100001111000 s9
-b110010100001111000 w9
-b10100001111000 #:
-b10100001111000 +:
-b110010100001111000 /:
-b10100001111000 9:
-b101000011110 A:
-b110010100001111000 E:
-b101000011110 S:
-b110010100001111000 W:
-b101000011110 a:
-b10100001111000 i:
-b110010100001111000 m:
-b10100001111000 w:
-b10100001111000 #;
-b110010100001111000 ';
-b10100001111000 1;
-b10100001111000 ;;
-b110010100001111000 ?;
-b10100001111000 I;
-b101000011110 S;
-b110010100001111000 W;
-b101000011110 a;
-b10100001111000 k;
-b110010100001111000 o;
-b10100001111000 u;
-0y;
-b10100001 z;
-b10100001111000 3<
-b10100001111000 7<
-b10100001111000 O<
-b10100001111000 7>
-b10100001111000 C>
-b10100001111000 Y>
-b10100001111000 ]>
-b10100001111000 a>
-b10100001111000 e>
-b10100001111000 i>
-b10100001111000 m>
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+b11100 v<
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+b100001 #=
+b11111 &=
+b11111 )=
+b100001 -=
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+b11111 3=
+b11 7=
+b100001 9=
+b11110 :=
+b100010 ;=
+b11110 ==
+b100010 >=
+b100001 C=
+b11110 D=
+b100010 E=
+b11110 G=
+b100010 H=
+b100001 L=
+b11010 O=
+b11010 R=
+b100001 V=
+b11010 Y=
+b11010 \=
+b11 `=
+b100001 d=
+b11111 g=
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+b100001 m=
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+b11111 s=
+b11 v=
+b100001 x=
+b11110 y=
+b100010 z=
+b11110 |=
+b100010 }=
+b100001 #>
+b11110 $>
+b100010 %>
+b11110 '>
+b100010 (>
+b100001 +>
+b11010 .>
+b11010 1>
+b100001 5>
+b11010 8>
+b11010 ;>
 #267000000
 sHdlSome\x20(1) '
-sHdlSome\x20(1) 6
-sHdlSome\x20(1) E
-sHdlSome\x20(1) S
-sHdlSome\x20(1) b
+sHdlSome\x20(1) 5
+sHdlSome\x20(1) B
+sHdlSome\x20(1) X
+sHdlSome\x20(1) e
 sHdlSome\x20(1) q
-sHdlSome\x20(1) }
-sHdlSome\x20(1) +"
-sHdlSome\x20(1) ;"
-sHdlSome\x20(1) K"
-sHdlSome\x20(1) V"
+sHdlSome\x20(1) $"
+sHdlSome\x20(1) ."
+sHdlSome\x20(1) 7"
+sHdlSome\x20(1) F"
+sHdlSome\x20(1) T"
+sHdlSome\x20(1) Z"
 sHdlSome\x20(1) b"
-b1111100100000110010100001111001 C&
-b10100001111001 G9
-b110010100001111001 K9
-b10100001111001 U9
-b10100001111001 ]9
-b110010100001111001 a9
-b10100001111001 k9
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-b10100001111001 +:
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-b110010100001111001 E:
-b110010100001111001 W:
-b10100001111001 i:
-b110010100001111001 m:
-b10100001111001 w:
-b10100001111001 #;
-b110010100001111001 ';
-b10100001111001 1;
-b10100001111001 ;;
-b110010100001111001 ?;
-b10100001111001 I;
-b110010100001111001 W;
-b10100001111001 k;
-b110010100001111001 o;
-b10100001111001 u;
-1y;
-b10100001111001 3<
-b10100001111001 7<
-b10100001111001 O<
-b10100001111001 7>
-b10100001111001 C>
-b10100001111001 Y>
-b10100001111001 ]>
-b10100001111001 a>
-b10100001111001 e>
-b10100001111001 i>
-b10100001111001 m>
+sHdlSome\x20(1) k"
+b1111100100000110010100001111001 X&
+b10100001111001 r9
+b110010100001111001 v9
+b110010100001111001 7:
+b10100001111001 e:
+b110010100001111001 g:
+1k:
+b10100001111001 w;
 #268000000
 sLogicalI\x20(4) "
 sHdlNone\x20(0) '
 b0 )
-sSignExt8\x20(7) -
-10
-11
-sHdlNone\x20(0) 6
-b0 8
-sSignExt8\x20(7) <
-1?
-1@
-sHdlNone\x20(0) E
-b0 G
-1K
-1L
-1M
-sHdlNone\x20(0) S
-b0 U
-sSignExt8\x20(7) Y
-1\
-1]
-sHdlNone\x20(0) b
-b0 d
+b1110111000000000000000000 +
+0.
+sHdlNone\x20(0) 5
+b0 7
+b111011100000000000000000000000000 8
+0;
+sHdlNone\x20(0) B
+b0 D
+1R
+1S
+sHdlNone\x20(0) X
+b0 Z
+b111011100000000000000000000000000 [
+0^
+sHdlNone\x20(0) e
+b0 g
 sSignExt8\x20(7) h
+1j
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 1l
 sHdlNone\x20(0) q
 b0 s
-sSignExt8\x20(7) w
-s<invalid>\x20(14) x
-sHdlNone\x20(0) }
-b0 !"
-sSignExt8\x20(7) %"
-s<invalid>\x20(14) &"
-sHdlNone\x20(0) +"
-b0 -"
-11"
-sSLt\x20(3) 2"
-14"
-15"
-sHdlNone\x20(0) ;"
-b0 ="
-1A"
-sSLt\x20(3) B"
-1D"
-1E"
-b100 G"
-sHdlNone\x20(0) K"
-b0 M"
-sLoad\x20(0) Q"
-b10 R"
-sHdlNone\x20(0) V"
-b0 X"
-sWidth64Bit\x20(3) \"
-sSignExt\x20(1) ]"
+b111000 z
+sSignExt8\x20(7) |
+sHdlNone\x20(0) $"
+b0 &"
+b111011100000000000000000000000000 '"
+sU64\x20(0) )"
+sHdlNone\x20(0) ."
+b0 0"
+sSignExt8\x20(7) 1"
+s<invalid>\x20(14) 2"
+sHdlNone\x20(0) 7"
+b0 9"
+b1110111000000000000000000 ;"
+0>"
+sHdlNone\x20(0) F"
+b0 H"
+b111011100000000000000000000000000 I"
+0L"
+sHdlNone\x20(0) T"
+b100 V"
+sHdlNone\x20(0) Z"
+b0 \"
+sLoad\x20(0) ]"
 b10 ^"
 sHdlNone\x20(0) b"
 b0 d"
-sWidth64Bit\x20(3) h"
-sSignExt\x20(1) i"
-b1111100100000110000011101110100 C&
-b1000001100000111011101 G&
-b1000001100000111011101 H&
-b1000001100000111011101 I&
-b1000001100000111011101 J&
-b111011101 K&
-b11101110100 Y&
-b11101110100 h&
-b11101110100 w&
-b11101110100 ''
-b11101110100 6'
-b11101110100 E'
-b11101110100 Q'
-b11101110100 ]'
-b11101110100 m'
-b11101110100 }'
-b11101110100 *(
-b11101110100 6(
-b111011101 <(
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-b11101110100 Y(
-b11101110100 h(
-b11101110100 v(
-b11101110100 ')
-b11101110100 6)
-b11101110100 B)
-b11101110100 N)
-b11101110100 ^)
-b11101110100 n)
-b11101110100 y)
-b11101110100 '*
-b111011101 -*
-b11101110100 ;*
-b11101110100 J*
-b11101110100 Y*
-b11101110100 g*
-b11101110100 v*
-b11101110100 '+
-b11101110100 3+
-b11101110100 ?+
-b11101110100 O+
-b11101110100 _+
-b11101110100 j+
-b11101110100 v+
-b111011101 |+
-b11101110100 ,,
-b11101110100 ;,
+sWidth64Bit\x20(3) e"
+sSignExt\x20(1) f"
+b10 g"
+sHdlNone\x20(0) k"
+b0 m"
+b111011100000000000000000000000000 n"
+b1111100100000110000011101110100 X&
+b1000001100000111011101 \&
+b111011101 ]&
+b11101110100 k&
+b1110111010000000000 x&
+b100 ('
+b110 *'
+b101 ,'
+b11 .'
+b0 0'
+b1110111010000000000 ='
+b111011101000000000000000000 I'
+b111010 X'
+sHdlSome\x20(1) Z'
+b11 ['
+b1110111010000000000 g'
+b111011101000000000000000000 p'
+b11101110100 {'
+b1110111010000000000 +(
+b111011101000000000000000000 >(
+b111011101000000000000000000 F(
+b1110111010000000000 P(
+b11101110100 `(
+b1110111010000000000 m(
+b100 {(
+b110 }(
+b101 !)
+b11 #)
+b0 %)
+b1110111010000000000 2)
+b111011101000000000000000000 >)
+b111010 M)
+sHdlSome\x20(1) O)
+b11 P)
+b1110111010000000000 \)
+b111011101000000000000000000 e)
+b11101110100 p)
+b1110111010000000000 ~)
+b111011101000000000000000000 3*
+b111011101000000000000000000 ;*
+b1110111010000000000 E*
+b11101110100 U*
+b1110111010000000000 b*
+b100 p*
+b110 r*
+b101 t*
+b11 v*
+b0 x*
+b1110111010000000000 '+
+b111011101000000000000000000 3+
+b111010 B+
+sHdlSome\x20(1) D+
+b11 E+
+b1110111010000000000 Q+
+b111011101000000000000000000 Z+
+b11101110100 e+
+b1110111010000000000 s+
+b111011101000000000000000000 (,
+b111011101000000000000000000 0,
+b1110111010000000000 :,
 b11101110100 J,
-b11101110100 X,
-b11101110100 g,
-b11101110100 v,
-b11101110100 $-
-b11101110100 0-
-b11101110100 @-
-b11101110100 P-
-b11101110100 [-
-b11101110100 g-
-b0 m-
-1(/
-18/
-b0 ^/
-1w0
-1)1
-b0 O1
-b0 @3
-b0 15
-b0 "7
-b0 q8
-b11111111 v8
-b0 w8
-b11111111 |8
-b0 }8
-b11111111 $9
-b0 %9
-b11111111 *9
-b0 +9
-b11111111 09
-b0 19
-b11111111 69
-b0 79
-b11111111 <9
-b0 =9
-b11111111 B9
-b11101110100 G9
-b110000011101110100 K9
-b0 Q9
-b11101110100 U9
-b0 Y9
-b11101110100 ]9
-b110000011101110100 a9
-b0 g9
-b11101110100 k9
-b0 o9
-b11101110100 s9
-b110000011101110100 w9
-b0 }9
-b11101110100 #:
-b0 ':
-b11101110100 +:
-b110000011101110100 /:
-b0 5:
-b11101110100 9:
-b0 =:
-b111011101 A:
-b110000011101110100 E:
-b0 K:
-b0 O:
-b111011101 S:
-b110000011101110100 W:
-b0 ]:
-b111011101 a:
-b0 e:
-b11101110100 i:
-b110000011101110100 m:
-b0 s:
-b11101110100 w:
-b0 |:
-b11101110100 #;
-b110000011101110100 ';
-b0 -;
-b11101110100 1;
-b0 6;
-b11101110100 ;;
-b110000011101110100 ?;
-b0 E;
-b11101110100 I;
-b0 N;
-b111011101 S;
-b110000011101110100 W;
-b0 ];
-b111011101 a;
-b0 f;
-b11101110100 k;
-b110000011101110100 o;
-b11101110100 u;
-0y;
-b11101 z;
-b0 };
-b0 $<
-b0 )<
-b0 .<
-b11101110100 3<
-b11101110100 7<
-b0 ;<
-b0 @<
-b0 E<
-b0 J<
-b11101110100 O<
-b0 S<
-b0 X<
-b0 ]<
-b0 b<
-b0 g<
-b0 l<
-b0 q<
-b0 v<
-b0 {<
-b0 "=
-b0 '=
-b0 ,=
-b0 1=
-b0 6=
-b0 ;=
-b0 @=
-b11101110100 7>
-b0 =>
-b11101110100 C>
-b0 I>
-b0 O>
-b0 U>
-b11101110100 Y>
-b11101110100 ]>
-b11101110100 a>
-b11101110100 e>
-b11101110100 i>
-b11101110100 m>
-b0 q>
-b0 u>
-b0 y>
-b0 }>
-b0 #?
-b0 '?
-b0 +?
-b0 /?
-b0 3?
-b0 7?
-b0 ;?
-b0 ??
-b0 C?
-b0 G?
-b0 K?
-b0 O?
+b1110111010000000000 W,
+b100 e,
+b110 g,
+b101 i,
+b11 k,
+b0 m,
+b1110111010000000000 z,
+b111011101000000000000000000 (-
+b111010 7-
+sHdlSome\x20(1) 9-
+b11 :-
+b1110111010000000000 F-
+b111011101000000000000000000 O-
+b11101110100 Z-
+b1110111010000000000 h-
+b111011101000000000000000000 {-
+b111011101000000000000000000 %.
+b1110111010000000000 /.
+b0 4.
+1X/
+1f/
+1M1
+1[1
+b0 S9
+b11111111 X9
+b11111111 [9
+b11111111 ^9
+b11111111 a9
+b11111111 d9
+b11111111 g9
+b11111111 j9
+b11111111 m9
+b11101110100 r9
+b110000011101110100 v9
+b0 |9
+b111011101 3:
+b110000011101110100 7:
+b11101110100 e:
+b110000011101110100 g:
+0k:
+b11101 l:
+b0 o:
+b11101110100 w;
+b11010 =<
+b11101 ><
+b0 ?<
+b111101 B<
+b111010 C<
+b101 D<
+b111110 E<
+b101 G<
+b111110 H<
+b111101 L<
+b111010 M<
+b101 N<
+b111110 O<
+b101 Q<
+b111110 R<
+b0 V<
+b111101 W<
+b111010 X<
+b101 Y<
+b111110 Z<
+b101 \<
+b111110 ]<
+b111101 `<
+b111010 a<
+b101 b<
+b111110 c<
+b101 e<
+b111110 f<
+b111101 i<
+b111010 j<
+b101 k<
+b111110 l<
+b101 n<
+b111110 o<
+b111101 s<
+b111010 t<
+b101 u<
+b111110 v<
+b101 x<
+b111110 y<
+b111011 }<
+b0 ~<
+b111101 #=
+b11 &=
+b11 )=
+b111101 -=
+b11 0=
+b11 3=
+b111011 7=
+b111101 9=
+b10 :=
+b111110 ;=
+b10 ==
+b111110 >=
+b111101 C=
+b10 D=
+b111110 E=
+b10 G=
+b111110 H=
+b111101 L=
+b111111 M=
+b0 N=
+b11 O=
+b0 Q=
+b11 R=
+b111101 V=
+b111111 W=
+b0 X=
+b11 Y=
+b0 [=
+b11 \=
+b111011 `=
+b0 a=
+b111101 d=
+b11 g=
+b11 j=
+b111101 m=
+b11 p=
+b11 s=
+b111011 v=
+b111101 x=
+b10 y=
+b111110 z=
+b10 |=
+b111110 }=
+b111101 #>
+b10 $>
+b111110 %>
+b10 '>
+b111110 (>
+b111101 +>
+b111111 ,>
+b0 ->
+b11 .>
+b0 0>
+b11 1>
+b111101 5>
+b111111 6>
+b0 7>
+b11 8>
+b0 :>
+b11 ;>
+b0 C>
+b0 J>
+b1100000 U>
+b11 W>
+b11 Y>
+b1100000 [>
+b11 \>
+b11 ]>
+b11 ^>
 #269000000
 sHdlSome\x20(1) '
-sHdlSome\x20(1) 6
-sHdlSome\x20(1) E
-sHdlSome\x20(1) S
-sHdlSome\x20(1) b
+sHdlSome\x20(1) 5
+sHdlSome\x20(1) B
+sHdlSome\x20(1) X
+sHdlSome\x20(1) e
 sHdlSome\x20(1) q
-sHdlSome\x20(1) }
-sHdlSome\x20(1) +"
-sHdlSome\x20(1) ;"
-sHdlSome\x20(1) K"
-sHdlSome\x20(1) V"
+sHdlSome\x20(1) $"
+sHdlSome\x20(1) ."
+sHdlSome\x20(1) 7"
+sHdlSome\x20(1) F"
+sHdlSome\x20(1) T"
+sHdlSome\x20(1) Z"
 sHdlSome\x20(1) b"
-b1111100100000110000011101110101 C&
-b11101110101 G9
-b110000011101110101 K9
-b11101110101 U9
-b11101110101 ]9
-b110000011101110101 a9
-b11101110101 k9
-b11101110101 s9
-b110000011101110101 w9
-b11101110101 #:
-b11101110101 +:
-b110000011101110101 /:
-b11101110101 9:
-b110000011101110101 E:
-b110000011101110101 W:
-b11101110101 i:
-b110000011101110101 m:
-b11101110101 w:
-b11101110101 #;
-b110000011101110101 ';
-b11101110101 1;
-b11101110101 ;;
-b110000011101110101 ?;
-b11101110101 I;
-b110000011101110101 W;
-b11101110101 k;
-b110000011101110101 o;
-b11101110101 u;
-1y;
-b11101110101 3<
-b11101110101 7<
-b11101110101 O<
-b11101110101 7>
-b11101110101 C>
-b11101110101 Y>
-b11101110101 ]>
-b11101110101 a>
-b11101110101 e>
-b11101110101 i>
-b11101110101 m>
+sHdlSome\x20(1) k"
+b1111100100000110000011101110101 X&
+b11101110101 r9
+b110000011101110101 v9
+b110000011101110101 7:
+b11101110101 e:
+b110000011101110101 g:
+1k:
+b11101110101 w;
 #270000000
 sHdlNone\x20(0) '
-sSignExt16\x20(5) -
-sHdlNone\x20(0) 6
-sSignExt16\x20(5) <
-sHdlNone\x20(0) E
-0L
-sHdlNone\x20(0) S
-sSignExt16\x20(5) Y
-sHdlNone\x20(0) b
+b1110101000000000000000000 +
+sHdlNone\x20(0) 5
+b111010100000000000000000000000000 8
+sHdlNone\x20(0) B
+0S
+sHdlNone\x20(0) X
+b111010100000000000000000000000000 [
+sHdlNone\x20(0) e
 sSignExt16\x20(5) h
 sHdlNone\x20(0) q
-sSignExt16\x20(5) w
-sHdlNone\x20(0) }
-sSignExt16\x20(5) %"
-sHdlNone\x20(0) +"
-sUGt\x20(2) 2"
-sHdlNone\x20(0) ;"
-sUGt\x20(2) B"
-sHdlNone\x20(0) K"
-sHdlNone\x20(0) V"
-sWidth16Bit\x20(1) \"
+b101000 z
+sHdlNone\x20(0) $"
+b111010100000000000000000000000000 '"
+sHdlNone\x20(0) ."
+sSignExt16\x20(5) 1"
+sHdlNone\x20(0) 7"
+b1110101000000000000000000 ;"
+sHdlNone\x20(0) F"
+b111010100000000000000000000000000 I"
+sHdlNone\x20(0) T"
+sHdlNone\x20(0) Z"
 sHdlNone\x20(0) b"
-sWidth16Bit\x20(1) h"
-b1111100100000110000011100110100 C&
-b1000001100000111001101 G&
-b1000001100000111001101 H&
-b1000001100000111001101 I&
-b1000001100000111001101 J&
-b111001101 K&
-b11100110100 Y&
-b11100110100 h&
-b11100110100 w&
-b11100110100 ''
-b11100110100 6'
-b11100110100 E'
-b11100110100 Q'
-b11100110100 ]'
-b11100110100 m'
-b11100110100 }'
-b11100110100 *(
-b11100110100 6(
-b111001101 <(
-b11100110100 J(
-b11100110100 Y(
-b11100110100 h(
-b11100110100 v(
-b11100110100 ')
-b11100110100 6)
-b11100110100 B)
-b11100110100 N)
-b11100110100 ^)
-b11100110100 n)
-b11100110100 y)
-b11100110100 '*
-b111001101 -*
-b11100110100 ;*
-b11100110100 J*
-b11100110100 Y*
-b11100110100 g*
-b11100110100 v*
-b11100110100 '+
-b11100110100 3+
-b11100110100 ?+
-b11100110100 O+
-b11100110100 _+
-b11100110100 j+
-b11100110100 v+
-b111001101 |+
-b11100110100 ,,
-b11100110100 ;,
+sWidth16Bit\x20(1) e"
+sHdlNone\x20(0) k"
+b111010100000000000000000000000000 n"
+b1111100100000110000011100110100 X&
+b1000001100000111001101 \&
+b111001101 ]&
+b11100110100 k&
+b1110011010000000000 x&
+b100 ,'
+b1110011010000000000 ='
+b111001101000000000000000000 I'
+b11010 X'
+b1110011010000000000 g'
+b111001101000000000000000000 p'
+b11100110100 {'
+b1110011010000000000 +(
+b111001101000000000000000000 >(
+b111001101000000000000000000 F(
+b1110011010000000000 P(
+b11100110100 `(
+b1110011010000000000 m(
+b100 !)
+b1110011010000000000 2)
+b111001101000000000000000000 >)
+b11010 M)
+b1110011010000000000 \)
+b111001101000000000000000000 e)
+b11100110100 p)
+b1110011010000000000 ~)
+b111001101000000000000000000 3*
+b111001101000000000000000000 ;*
+b1110011010000000000 E*
+b11100110100 U*
+b1110011010000000000 b*
+b100 t*
+b1110011010000000000 '+
+b111001101000000000000000000 3+
+b11010 B+
+b1110011010000000000 Q+
+b111001101000000000000000000 Z+
+b11100110100 e+
+b1110011010000000000 s+
+b111001101000000000000000000 (,
+b111001101000000000000000000 0,
+b1110011010000000000 :,
 b11100110100 J,
-b11100110100 X,
-b11100110100 g,
-b11100110100 v,
-b11100110100 $-
-b11100110100 0-
-b11100110100 @-
-b11100110100 P-
-b11100110100 [-
-b11100110100 g-
-b11100110100 G9
-b110000011100110100 K9
-b11100110100 U9
-b11100110100 ]9
-b110000011100110100 a9
-b11100110100 k9
-b11100110100 s9
-b110000011100110100 w9
-b11100110100 #:
-b11100110100 +:
-b110000011100110100 /:
-b11100110100 9:
-b111001101 A:
-b110000011100110100 E:
-b111001101 S:
-b110000011100110100 W:
-b111001101 a:
-b11100110100 i:
-b110000011100110100 m:
-b11100110100 w:
-b11100110100 #;
-b110000011100110100 ';
-b11100110100 1;
-b11100110100 ;;
-b110000011100110100 ?;
-b11100110100 I;
-b111001101 S;
-b110000011100110100 W;
-b111001101 a;
-b11100110100 k;
-b110000011100110100 o;
-b11100110100 u;
-0y;
-b11100 z;
-b11100110100 3<
-b11100110100 7<
-b11100110100 O<
-b11100110100 7>
-b11100110100 C>
-b11100110100 Y>
-b11100110100 ]>
-b11100110100 a>
-b11100110100 e>
-b11100110100 i>
-b11100110100 m>
+b1110011010000000000 W,
+b100 i,
+b1110011010000000000 z,
+b111001101000000000000000000 (-
+b11010 7-
+b1110011010000000000 F-
+b111001101000000000000000000 O-
+b11100110100 Z-
+b1110011010000000000 h-
+b111001101000000000000000000 {-
+b111001101000000000000000000 %.
+b1110011010000000000 /.
+b11100110100 r9
+b110000011100110100 v9
+b111001101 3:
+b110000011100110100 7:
+b11100110100 e:
+b110000011100110100 g:
+0k:
+b11100 l:
+b11100110100 w;
+b11100 ><
+b111100 B<
+b111111 E<
+b111111 H<
+b111100 L<
+b111111 O<
+b111111 R<
+b111100 W<
+b111111 Z<
+b111111 ]<
+b111100 `<
+b111111 c<
+b111111 f<
+b111100 i<
+b111111 l<
+b111111 o<
+b111100 s<
+b111111 v<
+b111111 y<
+b111001 }<
+b111100 #=
+b100 &=
+b100 )=
+b111100 -=
+b100 0=
+b100 3=
+b111001 7=
+b111100 9=
+b11 :=
+b111101 ;=
+b11 ==
+b111101 >=
+b111100 C=
+b11 D=
+b111101 E=
+b11 G=
+b111101 H=
+b111100 L=
+b100 O=
+b100 R=
+b111100 V=
+b100 Y=
+b100 \=
+b111001 `=
+b111100 d=
+b100 g=
+b100 j=
+b111100 m=
+b100 p=
+b100 s=
+b111001 v=
+b111100 x=
+b11 y=
+b111101 z=
+b11 |=
+b111101 }=
+b111100 #>
+b11 $>
+b111101 %>
+b11 '>
+b111101 (>
+b111100 +>
+b100 .>
+b100 1>
+b111100 5>
+b100 8>
+b100 ;>
 #271000000
 sHdlSome\x20(1) '
-sHdlSome\x20(1) 6
-sHdlSome\x20(1) E
-sHdlSome\x20(1) S
-sHdlSome\x20(1) b
+sHdlSome\x20(1) 5
+sHdlSome\x20(1) B
+sHdlSome\x20(1) X
+sHdlSome\x20(1) e
 sHdlSome\x20(1) q
-sHdlSome\x20(1) }
-sHdlSome\x20(1) +"
-sHdlSome\x20(1) ;"
-sHdlSome\x20(1) K"
-sHdlSome\x20(1) V"
+sHdlSome\x20(1) $"
+sHdlSome\x20(1) ."
+sHdlSome\x20(1) 7"
+sHdlSome\x20(1) F"
+sHdlSome\x20(1) T"
+sHdlSome\x20(1) Z"
 sHdlSome\x20(1) b"
-b1111100100000110000011100110101 C&
-b11100110101 G9
-b110000011100110101 K9
-b11100110101 U9
-b11100110101 ]9
-b110000011100110101 a9
-b11100110101 k9
-b11100110101 s9
-b110000011100110101 w9
-b11100110101 #:
-b11100110101 +:
-b110000011100110101 /:
-b11100110101 9:
-b110000011100110101 E:
-b110000011100110101 W:
-b11100110101 i:
-b110000011100110101 m:
-b11100110101 w:
-b11100110101 #;
-b110000011100110101 ';
-b11100110101 1;
-b11100110101 ;;
-b110000011100110101 ?;
-b11100110101 I;
-b110000011100110101 W;
-b11100110101 k;
-b110000011100110101 o;
-b11100110101 u;
-1y;
-b11100110101 3<
-b11100110101 7<
-b11100110101 O<
-b11100110101 7>
-b11100110101 C>
-b11100110101 Y>
-b11100110101 ]>
-b11100110101 a>
-b11100110101 e>
-b11100110101 i>
-b11100110101 m>
+sHdlSome\x20(1) k"
+b1111100100000110000011100110101 X&
+b11100110101 r9
+b110000011100110101 v9
+b110000011100110101 7:
+b11100110101 e:
+b110000011100110101 g:
+1k:
+b11100110101 w;
 #272000000
 sHdlNone\x20(0) '
-sSignExt32\x20(3) -
-sHdlNone\x20(0) 6
-sSignExt32\x20(3) <
-sHdlNone\x20(0) E
-1L
-0M
-sHdlNone\x20(0) S
-sSignExt32\x20(3) Y
-sHdlNone\x20(0) b
+b1110011000000000000000000 +
+sHdlNone\x20(0) 5
+b111001100000000000000000000000000 8
+sHdlNone\x20(0) B
+1S
+sHdlNone\x20(0) X
+b111001100000000000000000000000000 [
+sHdlNone\x20(0) e
 sSignExt32\x20(3) h
 sHdlNone\x20(0) q
-sSignExt32\x20(3) w
-sHdlNone\x20(0) }
-sSignExt32\x20(3) %"
-sHdlNone\x20(0) +"
-sULt\x20(1) 2"
-sHdlNone\x20(0) ;"
-sULt\x20(1) B"
-sHdlNone\x20(0) K"
-sHdlNone\x20(0) V"
-sWidth64Bit\x20(3) \"
-sZeroExt\x20(0) ]"
+b11000 z
+sHdlNone\x20(0) $"
+b111001100000000000000000000000000 '"
+sHdlNone\x20(0) ."
+sSignExt32\x20(3) 1"
+sHdlNone\x20(0) 7"
+b1110011000000000000000000 ;"
+sHdlNone\x20(0) F"
+b111001100000000000000000000000000 I"
+sHdlNone\x20(0) T"
+sHdlNone\x20(0) Z"
 sHdlNone\x20(0) b"
-sWidth64Bit\x20(3) h"
-sZeroExt\x20(0) i"
-b1111100100000110000011110110100 C&
-b1000001100000111101101 G&
-b1000001100000111101101 H&
-b1000001100000111101101 I&
-b1000001100000111101101 J&
-b111101101 K&
-b11110110100 Y&
-b11110110100 h&
-b11110110100 w&
-b11110110100 ''
-b11110110100 6'
-b11110110100 E'
-b11110110100 Q'
-b11110110100 ]'
-b11110110100 m'
-b11110110100 }'
-b11110110100 *(
-b11110110100 6(
-b111101101 <(
-b11110110100 J(
-b11110110100 Y(
-b11110110100 h(
-b11110110100 v(
-b11110110100 ')
-b11110110100 6)
-b11110110100 B)
-b11110110100 N)
-b11110110100 ^)
-b11110110100 n)
-b11110110100 y)
-b11110110100 '*
-b111101101 -*
-b11110110100 ;*
-b11110110100 J*
-b11110110100 Y*
-b11110110100 g*
-b11110110100 v*
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 #273000000
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+sDupLow32\x20(1) a(
+1b(
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+14)
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+1)+
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+1Q.
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+1t.
+sFunnelShift2x32Bit\x20(2) 6/
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+1S4
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+b101100 M:
+b101100 N:
+b101100 P:
+b101100 Q:
+b101100 R:
+b101100 S:
+b101100 T:
+b101100 U:
+b101100 W:
+b101100 X:
+b101100 Y:
+b101100 Z:
+b101100 [:
+b101100 ]:
+b101100 `:
+b101100 a:
+b101100 b:
+b101100 c:
+b101100 d:
+b100001011100110 e:
+b101100 f:
+b100001011100110 g:
+b101100 j:
+b100001011 l:
+b1100 m:
+b1100 p:
+b100001011100110 w;
+b1011 ><
+b1100 @<
+b101011 B<
+b1001 E<
+b1001 H<
+b101011 L<
+b1001 O<
+b1001 R<
+b101011 W<
+b1001 Z<
+b1001 ]<
+b101011 `<
+b1001 c<
+b1001 f<
+b101011 i<
+b1001 l<
+b1001 o<
+b101100 q<
+b101011 s<
+b1001 v<
+b1001 y<
+b101100 {<
+b10111 }<
+b1100 !=
+b101011 #=
+b10101 &=
+b10101 )=
+b101011 -=
+b10101 0=
+b10101 3=
+b10111 7=
+b101011 9=
+b10100 :=
+b101100 ;=
+b10100 ==
+b101100 >=
+b101011 C=
+b10100 D=
+b101100 E=
+b10100 G=
+b101100 H=
+b101011 L=
+b101101 O=
+b101101 R=
+b101011 V=
+b101101 Y=
+b101101 \=
+b10111 `=
+b1100 b=
+b101011 d=
+b10101 g=
+b10101 j=
+b101011 m=
+b10101 p=
+b10101 s=
+b10111 v=
+b101011 x=
+b10100 y=
+b101100 z=
+b10100 |=
+b101100 }=
+b101011 #>
+b10100 $>
+b101100 %>
+b10100 '>
+b101100 (>
+b101011 +>
+b101101 .>
+b101101 1>
+b101100 3>
+b101011 5>
+b101101 8>
+b101101 ;>
+b101100 =>
+b1100 K>
+b110001000 U>
+b100001100 W>
+b100001100 Y>
+b110001000 [>
+b100001100 \>
+b100001100 ]>
+b100001100 ^>
+#481000000
+b1 (
+b1 6
+b1 C
+b1 Y
+b1 f
+b1 r
+b1 %"
+b1 /"
+b1 8"
+b1 G"
+sPowerIsaTimeBaseU\x20(1) U"
+b1 ["
+b1 c"
+b1 l"
+b1111100011011010100001011100110 X&
+b110110101000010111001 \&
+b1101 ^&
+sDupLow32\x20(1) l&
+1m&
+sDupLow32\x20(1) y&
+1z&
+sDupLow32\x20(1) >'
+1?'
+sFunnelShift2x32Bit\x20(2) _'
+sDupLow32\x20(1) h'
+sS16\x20(5) i'
+sSGt\x20(4) }'
+sSGt\x20(4) -(
+sWidth16Bit\x20(1) Q(
+sZeroExt\x20(0) R(
+sDupLow32\x20(1) a(
+1b(
+sDupLow32\x20(1) n(
+1o(
+sDupLow32\x20(1) 3)
+14)
+sFunnelShift2x32Bit\x20(2) T)
+sDupLow32\x20(1) ])
+sS64\x20(1) ^)
+sSGt\x20(4) r)
+sSGt\x20(4) "*
+sWidth16Bit\x20(1) F*
+sZeroExt\x20(0) G*
+sDupLow32\x20(1) V*
+1W*
+sDupLow32\x20(1) c*
+1d*
+sDupLow32\x20(1) (+
+1)+
+sFunnelShift2x32Bit\x20(2) I+
+sDupLow32\x20(1) R+
+s<invalid>\x20(13) S+
+sSGt\x20(4) g+
+sSGt\x20(4) u+
+sWidth16Bit\x20(1) ;,
+sZeroExt\x20(0) <,
+sDupLow32\x20(1) K,
+1L,
+sDupLow32\x20(1) X,
+1Y,
+sDupLow32\x20(1) {,
+1|,
+sFunnelShift2x32Bit\x20(2) >-
+sDupLow32\x20(1) G-
+sCmpRBTwo\x20(9) H-
+sSGt\x20(4) \-
+sSGt\x20(4) j-
+sWidth16Bit\x20(1) 0.
+sZeroExt\x20(0) 1.
+b1101 5.
+sDupLow32\x20(1) C.
+1D.
+sDupLow32\x20(1) P.
+1Q.
+sDupLow32\x20(1) s.
+1t.
+sFunnelShift2x32Bit\x20(2) 6/
+sDupLow32\x20(1) ?/
+sS64\x20(1) @/
+sSGt\x20(4) T/
+sSGt\x20(4) b/
+sWidth16Bit\x20(1) (0
+sZeroExt\x20(0) )0
+sDupLow32\x20(1) 80
+190
+sDupLow32\x20(1) E0
+1F0
+sDupLow32\x20(1) h0
+1i0
+sFunnelShift2x32Bit\x20(2) +1
+sDupLow32\x20(1) 41
+sCmpRBTwo\x20(9) 51
+sSGt\x20(4) I1
+sSGt\x20(4) W1
+sWidth16Bit\x20(1) {1
+sZeroExt\x20(0) |1
+sDupLow32\x20(1) -2
+1.2
+sDupLow32\x20(1) :2
+1;2
+sDupLow32\x20(1) ]2
+1^2
+sFunnelShift2x32Bit\x20(2) ~2
+sDupLow32\x20(1) )3
+sS64\x20(1) *3
+sSGt\x20(4) >3
+sSGt\x20(4) L3
+sWidth16Bit\x20(1) p3
+sZeroExt\x20(0) q3
+sDupLow32\x20(1) "4
+1#4
+sDupLow32\x20(1) /4
+104
+sDupLow32\x20(1) R4
+1S4
+sFunnelShift2x32Bit\x20(2) s4
+sDupLow32\x20(1) |4
+sCmpRBTwo\x20(9) }4
+sSGt\x20(4) 35
+sSGt\x20(4) A5
+sWidth16Bit\x20(1) e5
+sZeroExt\x20(0) f5
+sDupLow32\x20(1) u5
+1v5
+sDupLow32\x20(1) $6
+1%6
+sDupLow32\x20(1) G6
+1H6
+sFunnelShift2x32Bit\x20(2) h6
+sDupLow32\x20(1) q6
+sS64\x20(1) r6
+sSGt\x20(4) (7
+sSGt\x20(4) 67
+sWidth16Bit\x20(1) Z7
+sZeroExt\x20(0) [7
+sDupLow32\x20(1) j7
+1k7
+sDupLow32\x20(1) w7
+1x7
+sDupLow32\x20(1) <8
+1=8
+sFunnelShift2x32Bit\x20(2) ]8
+sDupLow32\x20(1) f8
+sCmpRBTwo\x20(9) g8
+sSGt\x20(4) {8
+sSGt\x20(4) +9
+sWidth16Bit\x20(1) O9
+sZeroExt\x20(0) P9
+b1101 T9
+b1101 s9
+b101101 u9
+b10100001011100110 v9
+b1101 }9
+b101101 !:
+b101101 ":
+b101101 #:
+b101101 $:
+b101101 &:
+b101101 ':
+b101101 (:
+b101101 ):
+b101101 +:
+b101101 ,:
+b101101 -:
+b101101 .:
+b101101 0:
+b101101 1:
+b101101 2:
+b1101 4:
+b101101 6:
+b10100001011100110 7:
+b101101 =:
+b101101 >:
+b101101 ?:
+b101101 A:
+b101101 B:
+b101101 C:
+b101101 E:
+b101101 I:
+b101101 J:
+b101101 K:
+b101101 L:
+b101101 M:
+b101101 N:
+b101101 P:
+b101101 Q:
+b101101 R:
+b101101 S:
+b101101 T:
+b101101 U:
+b101101 W:
+b101101 X:
+b101101 Y:
+b101101 Z:
+b101101 [:
+b101101 ]:
+b101101 `:
+b101101 a:
+b101101 b:
+b101101 c:
+b101101 d:
+b101101 f:
+b10100001011100110 g:
+b101101 j:
+b1101 m:
+b1101 p:
+b1101 @<
+b101101 q<
+b101101 {<
+b1101 !=
+b1101 b=
+b101101 3>
+b101101 =>
+b1101 K>
+b110101000 U>
+b100001101 W>
+b100001101 Y>
+b110101000 [>
+b100001101 \>
+b100001101 ]>
+b100001101 ^>
+#482000000
diff --git a/crates/cpu/tests/simple_power_isa_decoder/main.rs b/crates/cpu/tests/simple_power_isa_decoder/main.rs
index 8c7a19f..9fa5d3c 100644
--- a/crates/cpu/tests/simple_power_isa_decoder/main.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/main.rs
@@ -54,6 +54,17 @@ fn test_test_cases_assembly() -> std::io::Result<()> {
     let mut lines = stdout.lines();
     let text_line = lines.next();
     assert_eq!(text_line, Some("\t.text"));
+    let mut any_error = false;
+    macro_rules! assert_eq_cont {
+        ($l:expr, $r:expr, $($msg:tt)+) => {
+            match (&$l, &$r) {
+                (l, r) => if l != r {
+                    eprintln!("assertion failed: {}\nl={l:#?}\nr={r:#?}", format_args!($($msg)+));
+                    any_error = true;
+                }
+            }
+        };
+    }
     for test_case @ TestCase {
         mnemonic: _,
         first_input,
@@ -95,14 +106,18 @@ fn test_test_cases_assembly() -> std::io::Result<()> {
         } else {
             format!(" encoding: [0x{b0:02x},0x{b1:02x},0x{b2:02x},0x{b3:02x}]")
         };
-        assert_eq!(
-            comment, expected_comment,
+        assert_eq_cont!(
+            comment,
+            expected_comment,
             "test_case={test_case:?}\nline:\n{line}"
         );
     }
     for line in lines {
         assert!(line.trim().is_empty(), "bad trailing output line: {line:?}");
     }
+    if any_error {
+        panic!();
+    }
     Ok(())
 }
 
diff --git a/crates/cpu/tests/simple_power_isa_decoder/test_cases.rs b/crates/cpu/tests/simple_power_isa_decoder/test_cases.rs
index 9c9d063..c1975b0 100644
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases.rs
@@ -11,6 +11,7 @@ mod fixed_point_arithmetic;
 mod fixed_point_compare;
 mod fixed_point_load;
 mod fixed_point_logical;
+mod fixed_point_rotate_and_shift;
 mod fixed_point_store;
 mod move_to_from_system_register;
 mod prefixed_no_operation;
@@ -143,9 +144,15 @@ pub fn test_cases() -> Vec<TestCase> {
     fixed_point_arithmetic::test_cases_book_i_3_3_9_fixed_point_arithmetic(&mut retval);
     fixed_point_compare::test_cases_book_i_3_3_10_fixed_point_compare(&mut retval);
     fixed_point_logical::test_cases_book_i_3_3_13_fixed_point_logical(&mut retval);
+    fixed_point_rotate_and_shift::test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(
+        &mut retval,
+    );
     move_to_from_system_register::test_cases_book_i_3_3_19_move_to_from_system_register(
         &mut retval,
     );
     prefixed_no_operation::test_cases_book_i_3_3_20_prefixed_no_operation(&mut retval);
+    move_to_from_system_register::test_cases_book_iii_5_4_4_move_to_from_system_register(
+        &mut retval,
+    );
     retval
 }
diff --git a/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_rotate_and_shift.rs b/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_rotate_and_shift.rs
new file mode 100644
index 0000000..29f84b4
--- /dev/null
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/fixed_point_rotate_and_shift.rs
@@ -0,0 +1,1143 @@
+// SPDX-License-Identifier: LGPL-3.0-or-later
+// See Notices.txt for copyright information
+
+use crate::test_cases::{TestCase, insn_single};
+use cpu::instruction::{
+    MOpDestReg, MOpRegNum, OutputIntegerMode, ShiftRotateDestLogicOp, ShiftRotateMOp,
+    ShiftRotateMOpImm, ShiftRotateMode,
+};
+use fayalite::prelude::*;
+
+#[hdl]
+fn shift_imm(amount: Option<u8>, shift_right: bool) -> Expr<ShiftRotateMOpImm> {
+    #[hdl]
+    ShiftRotateMOpImm {
+        shift_rotate_amount: if let Some(amount) = amount {
+            HdlSome(amount.cast_to_static::<UInt<_>>())
+        } else {
+            HdlNone()
+        },
+        shift_rotate_right: shift_right,
+        dest_logic_op: HdlNone(),
+    }
+}
+
+#[hdl]
+fn rotate_imm(
+    amount: Option<u8>,
+    rotated_output_start_and_len: Option<(u8, u8)>,
+    fallback_is_src2: bool,
+) -> SimValue<ShiftRotateMOpImm> {
+    #[hdl(sim)]
+    ShiftRotateMOpImm {
+        shift_rotate_amount: if let Some(amount) = amount {
+            #[hdl(sim)]
+            HdlSome(amount.cast_to_static::<UInt<_>>())
+        } else {
+            #[hdl(sim)]
+            HdlNone()
+        },
+        shift_rotate_right: false,
+        dest_logic_op: if let Some((rotated_output_start, rotated_output_len)) =
+            rotated_output_start_and_len
+        {
+            #[hdl(sim)]
+            HdlSome(
+                #[hdl(sim)]
+                ShiftRotateDestLogicOp {
+                    rotated_output_start: rotated_output_start.cast_to_static::<UInt<_>>(),
+                    rotated_output_len: rotated_output_len.cast_to_static::<UInt<_>>(),
+                    fallback_is_src2,
+                },
+            )
+        } else {
+            #[hdl(sim)]
+            HdlNone()
+        },
+    }
+}
+
+#[hdl]
+fn rotate_imm_src2(imm: &SimValue<ShiftRotateMOpImm>, dest: usize) -> Expr<MOpRegNum> {
+    #[hdl(sim)]
+    match &imm.dest_logic_op {
+        HdlSome(dest_logic_op) => {
+            if *dest_logic_op.fallback_is_src2 {
+                MOpRegNum::power_isa_gpr_reg_imm(dest)
+            } else {
+                MOpRegNum::const_zero()
+            }
+        }
+        _ => MOpRegNum::const_zero(),
+    }
+}
+
+/// covers instructions in PowerISA v3.1C Book I 3.3.14 Fixed-Point Rotate and Shift Instructions
+pub fn test_cases_book_i_3_3_14_fixed_point_rotate_and_shift(retval: &mut Vec<TestCase>) {
+    macro_rules! rotate_imm {
+        (
+            $mnemonic:literal $dest:literal, $src:literal, $amount:literal $(, $args:literal)*;
+            $encoding:literal;
+            $rotated_output_start_and_len:expr;
+            $fallback_is_src2:literal;
+            $shift_rotate_mode:ident;
+        ) => {{
+            let imm = rotate_imm(Some($amount), $rotated_output_start_and_len, $fallback_is_src2);
+            let src2 = rotate_imm_src2(&imm, $dest);
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    " ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount),
+                    $(", ",
+                    stringify!($args),)*
+                ),
+                $encoding,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        src2.value,
+                    ],
+                    &imm,
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    ". ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount),
+                    $(", ",
+                    stringify!($args),)*
+                ),
+                $encoding | 1,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        src2.value,
+                    ],
+                    imm,
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+        }};
+    }
+    macro_rules! rotate {
+        (
+            $mnemonic:literal $dest:literal, $src:literal, $amount:literal $(, $args:literal)*;
+            $encoding:literal;
+            $rotated_output_start_and_len:expr;
+            $shift_rotate_mode:ident;
+        ) => {{
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    " ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount),
+                    $(", ",
+                    stringify!($args),)*
+                ),
+                $encoding,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::power_isa_gpr_reg_imm($amount).value,
+                    ],
+                    rotate_imm(None, $rotated_output_start_and_len, false),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    ". ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount),
+                    $(", ",
+                    stringify!($args),)*
+                ),
+                $encoding | 1,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::power_isa_gpr_reg_imm($amount).value,
+                    ],
+                    rotate_imm(None, $rotated_output_start_and_len, false),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+        }};
+    }
+
+    rotate_imm! {
+        "rlwinm" 3, 4, 0, 0, 0;
+        0x54830000;
+        Some((31, 1));
+        false;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwinm" 3, 4, 5, 0, 0;
+        0x54832800;
+        Some((31, 1));
+        false;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwinm" 3, 4, 31, 0, 0;
+        0x5483f800;
+        Some((31, 1));
+        false;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwinm" 3, 4, 5, 0, 16;
+        0x54832820;
+        Some((15, 17));
+        false;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwinm" 3, 4, 5, 0, 31;
+        0x5483283e;
+        Some((0, 32));
+        false;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwinm" 3, 4, 5, 31, 31;
+        0x54832ffe;
+        Some((0, 1));
+        false;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwinm" 3, 4, 5, 31, 0;
+        0x54832fc0;
+        Some((31, 34));
+        false;
+        FunnelShift2x32Bit;
+    }
+
+    rotate! {
+        "rlwnm" 3, 4, 5, 0, 0;
+        0x5c832800;
+        Some((31, 1));
+        FunnelShift2x32Bit;
+    }
+    rotate! {
+        "rlwnm" 3, 4, 5, 0, 16;
+        0x5c832820;
+        Some((15, 17));
+        FunnelShift2x32Bit;
+    }
+    rotate! {
+        "rlwnm" 3, 4, 5, 0, 31;
+        0x5c83283e;
+        Some((0, 32));
+        FunnelShift2x32Bit;
+    }
+    rotate! {
+        "rlwnm" 3, 4, 5, 31, 31;
+        0x5c832ffe;
+        Some((0, 1));
+        FunnelShift2x32Bit;
+    }
+    rotate! {
+        "rlwnm" 3, 4, 5, 31, 0;
+        0x5c832fc0;
+        Some((31, 34));
+        FunnelShift2x32Bit;
+    }
+
+    rotate_imm! {
+        "rlwimi" 3, 4, 0, 0, 0;
+        0x50830000;
+        Some((31, 1));
+        true;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwimi" 3, 4, 5, 0, 0;
+        0x50832800;
+        Some((31, 1));
+        true;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwimi" 3, 4, 31, 0, 0;
+        0x5083f800;
+        Some((31, 1));
+        true;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwimi" 3, 4, 5, 0, 16;
+        0x50832820;
+        Some((15, 17));
+        true;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwimi" 3, 4, 5, 0, 31;
+        0x5083283e;
+        Some((0, 32));
+        true;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwimi" 3, 4, 5, 31, 31;
+        0x50832ffe;
+        Some((0, 1));
+        true;
+        FunnelShift2x32Bit;
+    }
+    rotate_imm! {
+        "rlwimi" 3, 4, 5, 31, 0;
+        0x50832fc0;
+        Some((31, 34));
+        true;
+        FunnelShift2x32Bit;
+    }
+
+    rotate_imm! {
+        "rldicl" 3, 4, 0, 0;
+        0x78830000;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicl" 3, 4, 5, 0;
+        0x78832800;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicl" 3, 4, 16, 0;
+        0x78838000;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicl" 3, 4, 31, 0;
+        0x7883f800;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicl" 3, 4, 32, 0;
+        0x78830002;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicl" 3, 4, 63, 0;
+        0x7883f802;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicl" 3, 4, 5, 5;
+        0x78832940;
+        Some((0, 59));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicl" 3, 4, 5, 16;
+        0x78832c00;
+        Some((0, 48));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicl" 3, 4, 5, 31;
+        0x78832fc0;
+        Some((0, 33));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicl" 3, 4, 5, 32;
+        0x78832820;
+        Some((0, 32));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicl" 3, 4, 5, 63;
+        0x78832fe0;
+        Some((0, 1));
+        false;
+        FunnelShift2x64Bit;
+    }
+
+    rotate_imm! {
+        "rldicr" 3, 4, 0, 63;
+        0x788307e4;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicr" 3, 4, 5, 63;
+        0x78832fe4;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicr" 3, 4, 16, 63;
+        0x788387e4;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicr" 3, 4, 31, 63;
+        0x7883ffe4;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicr" 3, 4, 32, 63;
+        0x788307e6;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicr" 3, 4, 63, 63;
+        0x7883ffe6;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicr" 3, 4, 5, 0;
+        0x78832804;
+        Some((63, 1));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicr" 3, 4, 5, 5;
+        0x78832944;
+        Some((58, 6));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicr" 3, 4, 5, 16;
+        0x78832c04;
+        Some((47, 17));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicr" 3, 4, 5, 31;
+        0x78832fc4;
+        Some((32, 32));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicr" 3, 4, 5, 32;
+        0x78832824;
+        Some((31, 33));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldicr" 3, 4, 5, 63;
+        0x78832fe4;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+
+    rotate_imm! {
+        "rldic" 3, 4, 0, 0;
+        0x78830008;
+        None;
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldic" 3, 4, 0, 16;
+        0x78830408;
+        Some((0, 48));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldic" 3, 4, 0, 31;
+        0x788307c8;
+        Some((0, 33));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldic" 3, 4, 0, 32;
+        0x78830028;
+        Some((0, 32));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldic" 3, 4, 0, 63;
+        0x788307e8;
+        Some((0, 1));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldic" 3, 4, 16, 63;
+        0x788387e8;
+        Some((16, 49));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldic" 3, 4, 31, 63;
+        0x7883ffe8;
+        Some((31, 34));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldic" 3, 4, 32, 63;
+        0x788307ea;
+        Some((32, 33));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldic" 3, 4, 63, 63;
+        0x7883ffea;
+        Some((63, 2));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldic" 3, 4, 63, 32;
+        0x7883f82a;
+        Some((63, 33));
+        false;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldic" 3, 4, 63, 0;
+        0x7883f80a;
+        Some((63, 1));
+        false;
+        FunnelShift2x64Bit;
+    }
+
+    rotate! {
+        "rldcl" 3, 4, 5, 0;
+        0x78832810;
+        None;
+        FunnelShift2x64Bit;
+    }
+    rotate! {
+        "rldcl" 3, 4, 5, 5;
+        0x78832950;
+        Some((0, 59));
+        FunnelShift2x64Bit;
+    }
+    rotate! {
+        "rldcl" 3, 4, 5, 16;
+        0x78832c10;
+        Some((0, 48));
+        FunnelShift2x64Bit;
+    }
+    rotate! {
+        "rldcl" 3, 4, 5, 31;
+        0x78832fd0;
+        Some((0, 33));
+        FunnelShift2x64Bit;
+    }
+    rotate! {
+        "rldcl" 3, 4, 5, 32;
+        0x78832830;
+        Some((0, 32));
+        FunnelShift2x64Bit;
+    }
+    rotate! {
+        "rldcl" 3, 4, 5, 63;
+        0x78832ff0;
+        Some((0, 1));
+        FunnelShift2x64Bit;
+    }
+
+    rotate! {
+        "rldcr" 3, 4, 5, 0;
+        0x78832812;
+        Some((63, 1));
+        FunnelShift2x64Bit;
+    }
+    rotate! {
+        "rldcr" 3, 4, 5, 5;
+        0x78832952;
+        Some((58, 6));
+        FunnelShift2x64Bit;
+    }
+    rotate! {
+        "rldcr" 3, 4, 5, 16;
+        0x78832c12;
+        Some((47, 17));
+        FunnelShift2x64Bit;
+    }
+    rotate! {
+        "rldcr" 3, 4, 5, 31;
+        0x78832fd2;
+        Some((32, 32));
+        FunnelShift2x64Bit;
+    }
+    rotate! {
+        "rldcr" 3, 4, 5, 32;
+        0x78832832;
+        Some((31, 33));
+        FunnelShift2x64Bit;
+    }
+    rotate! {
+        "rldcr" 3, 4, 5, 63;
+        0x78832ff2;
+        None;
+        FunnelShift2x64Bit;
+    }
+
+    rotate_imm! {
+        "rldimi" 3, 4, 0, 0;
+        0x7883000c;
+        None;
+        true;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldimi" 3, 4, 0, 16;
+        0x7883040c;
+        Some((0, 48));
+        true;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldimi" 3, 4, 0, 31;
+        0x788307cc;
+        Some((0, 33));
+        true;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldimi" 3, 4, 0, 32;
+        0x7883002c;
+        Some((0, 32));
+        true;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldimi" 3, 4, 0, 63;
+        0x788307ec;
+        Some((0, 1));
+        true;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldimi" 3, 4, 16, 63;
+        0x788387ec;
+        Some((16, 49));
+        true;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldimi" 3, 4, 31, 63;
+        0x7883ffec;
+        Some((31, 34));
+        true;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldimi" 3, 4, 32, 63;
+        0x788307ee;
+        Some((32, 33));
+        true;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldimi" 3, 4, 63, 63;
+        0x7883ffee;
+        Some((63, 2));
+        true;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldimi" 3, 4, 63, 32;
+        0x7883f82e;
+        Some((63, 33));
+        true;
+        FunnelShift2x64Bit;
+    }
+    rotate_imm! {
+        "rldimi" 3, 4, 63, 0;
+        0x7883f80e;
+        Some((63, 1));
+        true;
+        FunnelShift2x64Bit;
+    }
+
+    macro_rules! shift_left {
+        (
+            $mnemonic:literal $dest:literal, $src:literal, $amount:literal;
+            $encoding:literal;
+            $shift_rotate_mode:ident;
+        ) => {{
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    " ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount)
+                ),
+                $encoding,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::const_zero().value,
+                        MOpRegNum::power_isa_gpr_reg_imm($amount).value,
+                    ],
+                    shift_imm(None, false),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    ". ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount)
+                ),
+                $encoding | 1,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(
+                        &[MOpRegNum::power_isa_gpr_reg_num($dest)],
+                        &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+                    ),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::const_zero().value,
+                        MOpRegNum::power_isa_gpr_reg_imm($amount).value,
+                    ],
+                    shift_imm(None, false),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+        }};
+    }
+    macro_rules! shift_right_unsigned {
+        (
+            $mnemonic:literal $dest:literal, $src:literal, $amount:literal;
+            $encoding:literal;
+            $shift_rotate_mode:ident;
+        ) => {{
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    " ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount)
+                ),
+                $encoding,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
+                    [
+                        MOpRegNum::const_zero().value,
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::power_isa_gpr_reg_imm($amount).value,
+                    ],
+                    shift_imm(None, true),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    ". ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount)
+                ),
+                $encoding | 1,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(
+                        &[MOpRegNum::power_isa_gpr_reg_num($dest)],
+                        &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+                    ),
+                    [
+                        MOpRegNum::const_zero().value,
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::power_isa_gpr_reg_imm($amount).value,
+                    ],
+                    shift_imm(None, true),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+        }};
+    }
+    macro_rules! shift_right_signed {
+        (
+            $mnemonic:literal $dest:literal, $src:literal, $amount:literal;
+            $encoding:literal;
+            $shift_rotate_mode:ident;
+        ) => {{
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    " ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount)
+                ),
+                $encoding,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(
+                        &[
+                            MOpRegNum::power_isa_gpr_reg_num($dest),
+                            MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                        ],
+                        &[],
+                    ),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::const_zero().value,
+                        MOpRegNum::power_isa_gpr_reg_imm($amount).value,
+                    ],
+                    shift_imm(None, true),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    ". ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount)
+                ),
+                $encoding | 1,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(
+                        &[
+                            MOpRegNum::power_isa_gpr_reg_num($dest),
+                            MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                        ],
+                        &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+                    ),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::const_zero().value,
+                        MOpRegNum::power_isa_gpr_reg_imm($amount).value,
+                    ],
+                    shift_imm(None, true),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+        }};
+    }
+    macro_rules! shift_right_signed_imm {
+        (
+            $mnemonic:literal $dest:literal, $src:literal, $amount:literal;
+            $encoding:literal;
+            $shift_rotate_mode:ident;
+        ) => {{
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    " ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount)
+                ),
+                $encoding,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(
+                        &[
+                            MOpRegNum::power_isa_gpr_reg_num($dest),
+                            MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                        ],
+                        &[],
+                    ),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::const_zero().value,
+                        MOpRegNum::const_zero().value,
+                    ],
+                    shift_imm(Some($amount), true),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    ". ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount)
+                ),
+                $encoding | 1,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(
+                        &[
+                            MOpRegNum::power_isa_gpr_reg_num($dest),
+                            MOpRegNum::POWER_ISA_XER_CA_CA32_REG_NUM,
+                        ],
+                        &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+                    ),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::const_zero().value,
+                        MOpRegNum::const_zero().value,
+                    ],
+                    shift_imm(Some($amount), true),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.$shift_rotate_mode(),
+                ),
+            ));
+        }};
+    }
+    shift_left! {
+        "slw" 3, 4, 5;
+        0x7c832830;
+        FunnelShift2x32Bit;
+    }
+    shift_right_unsigned! {
+        "srw" 3, 4, 5;
+        0x7c832c30;
+        FunnelShift2x32Bit;
+    }
+    shift_right_signed_imm! {
+        "srawi" 3, 4, 0;
+        0x7c830670;
+        SignExt32To64BitThenShift;
+    }
+    shift_right_signed_imm! {
+        "srawi" 3, 4, 5;
+        0x7c832e70;
+        SignExt32To64BitThenShift;
+    }
+    shift_right_signed_imm! {
+        "srawi" 3, 4, 16;
+        0x7c838670;
+        SignExt32To64BitThenShift;
+    }
+    shift_right_signed_imm! {
+        "srawi" 3, 4, 31;
+        0x7c83fe70;
+        SignExt32To64BitThenShift;
+    }
+    shift_right_signed! {
+        "sraw" 3, 4, 5;
+        0x7c832e30;
+        SignExt32To64BitThenShift;
+    }
+    shift_left! {
+        "sld" 3, 4, 5;
+        0x7c832836;
+        FunnelShift2x64Bit;
+    }
+    shift_right_unsigned! {
+        "srd" 3, 4, 5;
+        0x7c832c36;
+        FunnelShift2x64Bit;
+    }
+    shift_right_signed_imm! {
+        "sradi" 3, 4, 0;
+        0x7c830674;
+        ShiftSigned64;
+    }
+    shift_right_signed_imm! {
+        "sradi" 3, 4, 5;
+        0x7c832e74;
+        ShiftSigned64;
+    }
+    shift_right_signed_imm! {
+        "sradi" 3, 4, 16;
+        0x7c838674;
+        ShiftSigned64;
+    }
+    shift_right_signed_imm! {
+        "sradi" 3, 4, 31;
+        0x7c83fe74;
+        ShiftSigned64;
+    }
+    shift_right_signed_imm! {
+        "sradi" 3, 4, 32;
+        0x7c830676;
+        ShiftSigned64;
+    }
+    shift_right_signed_imm! {
+        "sradi" 3, 4, 63;
+        0x7c83fe76;
+        ShiftSigned64;
+    }
+    shift_right_signed! {
+        "srad" 3, 4, 5;
+        0x7c832e34;
+        ShiftSigned64;
+    }
+    macro_rules! extswsli {
+        (
+            $mnemonic:literal $dest:literal, $src:literal, $amount:literal;
+            $encoding:literal;
+        ) => {{
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    " ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount)
+                ),
+                $encoding,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num($dest)], &[]),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::const_zero().value,
+                        MOpRegNum::const_zero().value,
+                    ],
+                    shift_imm(Some($amount), false),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.SignExt32To64BitThenShift(),
+                ),
+            ));
+            retval.push(insn_single(
+                concat!(
+                    $mnemonic,
+                    ". ",
+                    stringify!($dest),
+                    ", ",
+                    stringify!($src),
+                    ", ",
+                    stringify!($amount)
+                ),
+                $encoding | 1,
+                None,
+                ShiftRotateMOp::shift_rotate(
+                    MOpDestReg::new_sim(
+                        &[MOpRegNum::power_isa_gpr_reg_num($dest)],
+                        &[MOpRegNum::POWER_ISA_CR_0_REG_NUM],
+                    ),
+                    [
+                        MOpRegNum::power_isa_gpr_reg_imm($src).value,
+                        MOpRegNum::const_zero().value,
+                        MOpRegNum::const_zero().value,
+                    ],
+                    shift_imm(Some($amount), false),
+                    OutputIntegerMode.Full64(),
+                    ShiftRotateMode.SignExt32To64BitThenShift(),
+                ),
+            ));
+        }};
+    }
+    extswsli! {
+        "extswsli" 3, 4, 0;
+        0x7c8306f4;
+    }
+    extswsli! {
+        "extswsli" 3, 4, 5;
+        0x7c832ef4;
+    }
+    extswsli! {
+        "extswsli" 3, 4, 16;
+        0x7c8386f4;
+    }
+    extswsli! {
+        "extswsli" 3, 4, 31;
+        0x7c83fef4;
+    }
+    extswsli! {
+        "extswsli" 3, 4, 32;
+        0x7c8306f6;
+    }
+    extswsli! {
+        "extswsli" 3, 4, 63;
+        0x7c83fef6;
+    }
+}
diff --git a/crates/cpu/tests/simple_power_isa_decoder/test_cases/move_to_from_system_register.rs b/crates/cpu/tests/simple_power_isa_decoder/test_cases/move_to_from_system_register.rs
index 8573881..0cfdd58 100644
--- a/crates/cpu/tests/simple_power_isa_decoder/test_cases/move_to_from_system_register.rs
+++ b/crates/cpu/tests/simple_power_isa_decoder/test_cases/move_to_from_system_register.rs
@@ -2,11 +2,15 @@
 // See Notices.txt for copyright information
 
 use crate::test_cases::{TestCase, insn_single};
-use cpu::instruction::{LogicalFlagsMOp, LogicalFlagsMOpImm, Lut4, MOpDestReg, MOpRegNum};
+use cpu::instruction::{
+    LogicalFlagsMOp, LogicalFlagsMOpImm, Lut4, MOpDestReg, MOpRegNum, MoveRegMOp, ReadSpecialMOp,
+    ReadSpecialMOpImm,
+};
 use fayalite::prelude::*;
 
 /// covers instructions in PowerISA v3.1C Book I 3.3.19 Move To/From System Register Instructions
 pub fn test_cases_book_i_3_3_19_move_to_from_system_register(retval: &mut Vec<TestCase>) {
+    // mfspr/mtspr are covered by test_cases_book_iii_5_4_4_move_to_from_system_register
     #[hdl]
     fn mcrxrx_imm() -> SimValue<LogicalFlagsMOpImm> {
         #[hdl(sim)]
@@ -35,3 +39,111 @@ pub fn test_cases_book_i_3_3_19_move_to_from_system_register(retval: &mut Vec<Te
         ),
     ));
 }
+
+/// covers instructions in PowerISA v3.1C Book III 5.4.4 Move To/From System Register Instructions
+pub fn test_cases_book_iii_5_4_4_move_to_from_system_register(retval: &mut Vec<TestCase>) {
+    retval.push(insn_single(
+        "mflr 3",
+        0x7c6802a6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::power_isa_lr_reg().value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    retval.push(insn_single(
+        "mtlr 3",
+        0x7c6803a6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_LR_REG_NUM], &[]),
+            [MOpRegNum::power_isa_gpr_reg_imm(3).value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    retval.push(insn_single(
+        "mfctr 3",
+        0x7c6902a6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::power_isa_ctr_reg().value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    retval.push(insn_single(
+        "mtctr 3",
+        0x7c6903a6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_CTR_REG_NUM], &[]),
+            [MOpRegNum::power_isa_gpr_reg_imm(3).value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    retval.push(insn_single(
+        "mfspr 3, 815 # mftar 3",
+        0x7c6fcaa6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::power_isa_tar_reg().value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    retval.push(insn_single(
+        "mtspr 815, 3 # mttar 3",
+        0x7c6fcba6,
+        None,
+        MoveRegMOp::move_reg(
+            MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_TAR_REG_NUM], &[]),
+            [MOpRegNum::power_isa_gpr_reg_imm(3).value],
+            0.cast_to_static::<SInt<_>>(),
+        ),
+    ));
+    // make sure we generate mfspr and not the phased-out mftb
+    retval.push(insn_single(
+        "mfspr 3, 268 # mftb 3",
+        0x7c6c42a6,
+        None,
+        ReadSpecialMOp::read_special(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::const_zero().value; 0],
+            ReadSpecialMOpImm.PowerIsaTimeBase(),
+        ),
+    ));
+    // make sure we generate mfspr and not the phased-out mftb
+    retval.push(insn_single(
+        "mfspr 3, 269 # mftbu 3",
+        0x7c6d42a6,
+        None,
+        ReadSpecialMOp::read_special(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::const_zero().value; 0],
+            ReadSpecialMOpImm.PowerIsaTimeBaseU(),
+        ),
+    ));
+    // phased-out mftb -- not actually generated by the assembler so we have to use .long
+    retval.push(insn_single(
+        ".long 0x7c6c42e6 # mftb 3, 268",
+        0x7c6c42e6,
+        None,
+        ReadSpecialMOp::read_special(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::const_zero().value; 0],
+            ReadSpecialMOpImm.PowerIsaTimeBase(),
+        ),
+    ));
+    // phased-out mftb -- not actually generated by the assembler so we have to use .long
+    retval.push(insn_single(
+        ".long 0x7c6d42e6 # mftb 3, 269",
+        0x7c6d42e6,
+        None,
+        ReadSpecialMOp::read_special(
+            MOpDestReg::new_sim(&[MOpRegNum::power_isa_gpr_reg_num(3)], &[]),
+            [MOpRegNum::const_zero().value; 0],
+            ReadSpecialMOpImm.PowerIsaTimeBaseU(),
+        ),
+    ));
+}