16 commits

Author	SHA1	Message	Date
Jacob Lifshay	231f5e72ec	WIP: completed stages of next-pc logic, still need to combine them into a pipeline	2025-12-10 20:31:04 -08:00
Jacob Lifshay	554238c544	update for new fayalite	2025-12-10 20:31:04 -08:00
Jacob Lifshay	00ddd602c5	format code	2025-08-24 19:08:58 -07:00
Jacob Lifshay	518284685f	UnitMOp now has L2RegisterFileMOp after renaming and instead has MoveRegMOp before renaming	2025-02-28 17:45:46 -08:00
Jacob Lifshay	6c91d1b0b0	start adding ROB	2025-02-27 18:22:01 -08:00
Jacob Lifshay	5b15f4a6b4	runs instructions that read other instructions' outputs	2025-02-23 19:51:45 -08:00
Jacob Lifshay	3bd5c77a3f	unit_base is basically finished, implemented AddSub[I], didn't check any tests yet	2025-02-20 20:24:14 -08:00
Jacob Lifshay	3f6e5cc600	WIP implementing unit_base	2025-02-19 23:54:41 -08:00
Jacob Lifshay	2b7e7e4946	WIP adding unit input/output values and insn tracking	2025-02-13 20:55:43 -08:00
Jacob Lifshay	1084278f34	reg_alloc: add writes to rename table	2025-02-11 19:19:06 -08:00
Jacob Lifshay	7efcd872b5	working on reg_alloc	2025-02-06 21:28:30 -08:00
Jacob Lifshay	88eff5952b	working on reg_alloc -- wire up free_regs_tracker.alloc_out	2025-01-15 19:47:00 -08:00
Jacob Lifshay	5f7766777a	working on reg_alloc -- selected_unit_nums should be correct now	2025-01-12 22:12:58 -08:00
Jacob Lifshay	12481cfab3	start debugging reg_alloc with simulator	2024-12-20 00:28:22 -08:00
Jacob Lifshay	b51109f4f6	WIP implementing reg_alloc	2024-11-05 17:34:31 -08:00
Jacob Lifshay	cb5855589f	WIP adding register allocator	2024-10-14 21:20:42 -07:00