rename_execute_retire: add more tests using unit::alu_branch

crates/cpu/tests/rename_execute_retire.rs

@@ -4270,6 +4270,43 @@ fn test_rename_execute_retire_fibonacci_combinatorial() {
     assert!(sim.read_bool(sim.io().all_outputs_written));
 }
 
+#[hdl]
+#[test]
+fn test_rename_execute_retire_fibonacci_real() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut config = CpuConfig::new(
+        vec![
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::LoadStore),
+            UnitConfig::new(UnitKind::TransformedMove),
+        ],
+        NonZeroUsize::new(20).unwrap(),
+    );
+    config.fetch_width = NonZeroUsize::new(3).unwrap();
+    let m = rename_execute_retire_test_harness::<FibonacciInsns>(
+        PhantomConst::new_sized(config),
+        AluBranchKind::Real,
+    );
+    let mut sim = Simulation::new(m);
+    let _checked_vcd_output = checked_vcd_output!(
+        &mut sim,
+        "tests/expected/rename_execute_retire_fibonacci_real.vcd",
+    );
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    for cycle in 0..200 {
+        sim.advance_time(SimDuration::from_nanos(500));
+        println!("clock tick: {cycle}");
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_nanos(500));
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.write_reset(sim.io().cd.rst, false);
+    }
+    assert!(sim.read_bool(sim.io().all_outputs_written));
+}
+
 struct SlowLoopInsns;
 
 impl SlowLoopInsns {
@@ -4389,6 +4426,46 @@ fn test_rename_execute_retire_slow_loop() {
     assert!(sim.read_bool(sim.io().started_any_l2_reg_file_ops));
 }
 
+#[hdl]
+#[test]
+fn test_rename_execute_retire_slow_loop_real() {
+    let _n = SourceLocation::normalize_files_for_tests();
+    let mut config = CpuConfig::new(
+        vec![
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::AluBranch),
+            UnitConfig::new(UnitKind::LoadStore),
+            UnitConfig::new(UnitKind::TransformedMove),
+        ],
+        NonZeroUsize::new(20).unwrap(),
+    );
+    config.fetch_width = NonZeroUsize::new(4).unwrap();
+    let m = rename_execute_retire_test_harness::<SlowLoopInsns>(
+        PhantomConst::new_sized(config),
+        AluBranchKind::Real,
+    );
+    let mut sim = Simulation::new(m);
+    let _checked_vcd_output = checked_vcd_output!(
+        &mut sim,
+        "tests/expected/rename_execute_retire_slow_loop_real.vcd",
+    );
+    sim.write_clock(sim.io().cd.clk, false);
+    sim.write_reset(sim.io().cd.rst, true);
+    for cycle in 0..350 {
+        sim.advance_time(SimDuration::from_nanos(500));
+        println!("clock tick: {cycle}");
+        sim.write_clock(sim.io().cd.clk, true);
+        sim.advance_time(SimDuration::from_nanos(500));
+        sim.write_clock(sim.io().cd.clk, false);
+        sim.write_reset(sim.io().cd.rst, false);
+    }
+    assert!(sim.read_bool(sim.io().all_outputs_written));
+    // make sure we're actually testing L2 reg file ops
+    assert!(sim.read_bool(sim.io().started_any_l2_reg_file_ops));
+}
+
 /// equivalent of Unix's `head -n1`
 struct HeadN1Insns;