From d84bfcf6bdc130582eb382374eb93a5f2b21ffcb Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 10 Jul 2026 19:16:13 -0700 Subject: [PATCH] WIP: adding load/store unit --- crates/cpu/src/unit.rs | 5 +- crates/cpu/src/unit/alu_branch.rs | 1 + crates/cpu/src/unit/load_store.rs | 417 ++++++++++++++++++++++++++++++ crates/cpu/tests/units_formal.rs | 8 +- 4 files changed, 428 insertions(+), 3 deletions(-) create mode 100644 crates/cpu/src/unit/load_store.rs diff --git a/crates/cpu/src/unit.rs b/crates/cpu/src/unit.rs index d7442a3..4864125 100644 --- a/crates/cpu/src/unit.rs +++ b/crates/cpu/src/unit.rs @@ -8,6 +8,7 @@ use crate::{ MOpVariantVisitOps, MOpVariantVisitor, MOpVisitVariants, RenamedMOp, mop_enum, }, rename_execute_retire::ExecuteToUnitInterface, + unit::load_store::LoadStoreToDCacheInterface, }; use fayalite::{ bundle::{Bundle, BundleType}, @@ -18,6 +19,7 @@ use serde::{Deserialize, Serialize}; use std::ops::ControlFlow; pub mod alu_branch; +pub mod load_store; macro_rules! all_units { ( @@ -333,7 +335,7 @@ all_units! { #[create_dyn_unit_fn = |config, unit_index, filter| todo!()] #[extract(transformed_move_mop, transformed_move_mop_sim, transformed_move_mop_sim_ref, transformed_move_mop_sim_mut)] TransformedMove(TransformedMoveOp), - #[create_dyn_unit_fn = |config, unit_index, filter| todo!()] + #[create_dyn_unit_fn = |config, unit_index, filter| load_store::LoadStore::new(config, unit_index, filter).to_dyn()] #[extract(load_store_mop, load_store_mop_sim, load_store_mop_sim_ref, load_store_mop_sim_mut)] LoadStore(LoadStoreMOp), } @@ -391,6 +393,7 @@ impl RenamedMOpFilter for () { pub struct UnitIO { pub cd: Option>, pub from_execute: Expr>>, + pub to_d_cache: Option>>>, } pub trait UnitTrait: diff --git a/crates/cpu/src/unit/alu_branch.rs b/crates/cpu/src/unit/alu_branch.rs index 52bd4ab..4af688a 100644 --- a/crates/cpu/src/unit/alu_branch.rs +++ b/crates/cpu/src/unit/alu_branch.rs @@ -1617,6 +1617,7 @@ impl UnitTrait for AluBranch { UnitIO { cd: None, from_execute: this.from_execute, + to_d_cache: None, } } diff --git a/crates/cpu/src/unit/load_store.rs b/crates/cpu/src/unit/load_store.rs new file mode 100644 index 0000000..822ce9e --- /dev/null +++ b/crates/cpu/src/unit/load_store.rs @@ -0,0 +1,417 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use crate::{ + config::{CpuConfig, PhantomConstCpuConfig}, + instruction::{ + COMMON_MOP_SRC_LEN, CommonMOp, LoadMOp, LoadStoreCommonMOp, LoadStoreMOp, PRegNum, + }, + main_memory_and_io::MemoryOperationErrorKind, + next_pc::{CallStackOp, SimValueDefault}, + register::PRegValue, + rename_execute_retire::{ + ExecuteToUnitInterface, MOpId, MOpInstance, NextPcPredictorOp, RenamedMOp, + UnitCausedCancel, UnitFinishCauseCancel, UnitInputsReady, UnitOutputReady, + }, + unit::{DynUnit, DynUnitWrapper, RenamedMOpFilter, UnitIO, UnitKind, UnitTrait}, +}; +use fayalite::{ + intern::Interned, + prelude::*, + ty::{SimValueDebug, SimValueDisplay, TraceAsStringSimValue}, + util::ready_valid::ReadyValid, +}; +use serde::{Deserialize, Serialize}; +use std::{collections::VecDeque, fmt}; + +#[hdl] +pub struct DCacheOpKindLoad { + /// if this is `false`, then if the address refers to a valid cache line, that cache line must have any dirty data + /// written back to memory and then be set to invalid before performing the load. + pub is_cacheable: Bool, + /// if this is `true`, then the load must only look in the cache (must not propagate to the L2/L3 cache or to + /// memory), must not cause any earlier operations' timing to change because this load exists, and must not change + /// any cache state that remains after all operations finish, including LRU state, random number generators, + /// predictive prefetching state, etc. + /// Speculative loads that miss the cache must return [`DCacheFinishStatus::NotFound`]. + pub is_speculative: Bool, +} + +#[hdl] +pub struct DCacheOpKindStore { + /// if this is `false`, then if the address refers to a valid cache line, that cache line must have any dirty data + /// written back to memory and then be set to invalid before performing the store. + pub is_cacheable: Bool, +} + +#[hdl] +pub enum DCacheOpKind { + Load(DCacheOpKindLoad), + Store(DCacheOpKindStore), +} + +#[hdl] +pub struct DCacheStart> { + pub kind: DCacheOpKind, + /// unaligned addresses may cause a load/store to cross a cache-line boundary + pub address: UInt<64>, + pub data_and_mask: Array>, 8>, + pub config: C, +} + +#[hdl] +pub enum DCacheFinishStatus { + /// The operation finished successfully + Success, + /// A speculative load missed the cache, so data was not returned. + NotFound, + MemoryError(MemoryOperationErrorKind), +} + +#[hdl] +pub struct DCacheFinish> { + pub status: DCacheFinishStatus, + pub data: Array, 8>, + pub config: C, +} + +#[hdl] +pub struct LoadStoreToDCacheInterface> { + pub start: ReadyValid>, + #[hdl(flip)] + pub finish: ReadyValid>, + pub config: C, +} + +#[hdl(custom_debug(sim))] +struct OpDebugState { + v: SimOnly, +} + +impl SimValueDebug for OpDebugState { + #[hdl] + fn sim_value_debug( + value: &::SimValue, + f: &mut fmt::Formatter<'_>, + ) -> fmt::Result { + f.write_str(&value.v) + } +} + +impl SimValueDefault for OpDebugState { + #[hdl] + fn sim_value_default(self) -> SimValue { + thread_local! { + static VALUE: SimOnlyValue = SimOnlyValue::new("None".into()); + } + VALUE.with(|v| { + #[hdl(sim)] + Self { v } + }) + } +} + +#[derive(Debug)] +struct Op { + id: SimValue, + pc: SimValue>, + size_in_bytes: u8, + mop: SimValue, PRegNum>>, + is_speculative: bool, + src_values: Option<[SimValue>; COMMON_MOP_SRC_LEN]>, + dest_value: Option>>, + sent_cant_cause_cancel: bool, + sent_output_ready: bool, + config: C, +} + +impl fmt::Display for Op { + #[hdl] + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + id, + pc, + size_in_bytes, + mop, + is_speculative, + src_values, + dest_value, + sent_cant_cause_cancel, + sent_output_ready, + config: _, + } = self; + if *is_speculative { + f.write_str("(s)")?; + } + if *sent_cant_cause_cancel { + f.write_str("(sccc)")?; + } + if *sent_output_ready { + f.write_str("(sor)")?; + } + write!(f, "id={id:?} pc={pc:?} sz={size_in_bytes}: {mop:?}")?; + if let Some(src_values) = src_values { + write!(f, "src_values={src_values:?}")?; + } + if let Some(dest_value) = dest_value { + write!(f, "dest_value={dest_value:?}")?; + } + Ok(()) + } +} + +impl Op { + #[hdl] + fn debug_state(&self) -> SimValue { + #[hdl(sim)] + OpDebugState { + v: SimOnlyValue::new(self.to_string()), + } + } +} + +#[hdl(get(|c| c.rob_size.get().next_power_of_two()))] +type OpsDebugLen> = DynSize; + +#[hdl(no_static)] +pub struct LoadStoreDebugState> { + ops: ArrayType, OpsDebugLen>, + config: C, +} + +#[derive(Debug)] +struct LoadStoreState { + ops: VecDeque>, + config: C, + unit_index: usize, + filter: LoadStoreFilter, +} + +impl LoadStoreState { + fn new(config: C, unit_index: usize, filter: LoadStoreFilter) -> Self { + Self { + ops: VecDeque::new(), + config, + unit_index, + filter, + } + } + #[hdl] + fn debug_state(&self) -> SimValue> { + let config = self.config; + let ty = LoadStoreDebugState[config]; + let mut ops = vec![OpDebugState.sim_value_default().into_trace_as_string(); ty.ops.len()]; + for op in &self.ops { + ops[op.id.as_int() as usize % ty.ops.len()] = op.debug_state().into_trace_as_string(); + } + #[hdl(sim)] + LoadStoreDebugState::<_> { ops, config } + } +} + +#[hdl] +async fn load_store_impl( + config: PhantomConst, + unit_index: usize, + filter: LoadStoreFilter, + cd: Expr, + from_execute: Expr>>, + to_d_cache: Expr>>, + debug_state: Expr>>, + mut sim: ExternModuleSimulationState, +) { + let mut state = LoadStoreState::new(config, unit_index, filter); + loop { + sim.write(debug_state, state.debug_state()).await; + sim.wait_for_clock_edge(cd.clk).await; + { + #[hdl] + let ExecuteToUnitInterface::<_> { + global_state, + enqueue, + inputs_ready, + is_no_longer_speculative, + cant_cause_cancel, + output_ready, + finish_cause_cancel, + unit_outputs_ready, + cancel_all, + config: _, + } = from_execute; + todo!(); + } + #[hdl] + let LoadStoreToDCacheInterface::<_> { + start, + finish, + config: _, + } = to_d_cache; + todo!(); + } +} + +#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)] +struct LoadStoreFilter { + load: bool, + store: bool, +} + +impl LoadStoreFilter { + fn new( + from_execute: ExecuteToUnitInterface>, + filter: &mut impl RenamedMOpFilter, + ) -> Self { + let LoadStoreMOp { Load, Store } = from_execute + .inputs_ready + .HdlSome + .mop + .mop + .inner_ty() + .LoadStore; + Self { + load: filter.should_include_ty(Load), + store: filter.should_include_ty(Store), + } + } +} + +#[hdl_module(extern)] +pub fn load_store( + config: PhantomConst, + unit_index: usize, + filter: &mut impl RenamedMOpFilter, +) { + #[hdl] + let cd: ClockDomain = m.input(); + + #[hdl] + let from_execute: ExecuteToUnitInterface> = + m.input(ExecuteToUnitInterface[config]); + + #[hdl] + let to_d_cache: LoadStoreToDCacheInterface> = + m.output(LoadStoreToDCacheInterface[config]); + + #[hdl] + let debug_state: LoadStoreDebugState> = + m.output(LoadStoreDebugState[config]); + + let filter = LoadStoreFilter::new(from_execute.ty(), filter); + + assert_eq!(config.get().units[unit_index].kind, UnitKind::LoadStore); + + m.register_clock_for_past(cd.clk); + + m.extern_module_simulation_fn( + ( + config, + unit_index, + filter, + cd, + from_execute, + to_d_cache, + debug_state, + ), + async |(config, unit_index, filter, cd, from_execute, to_d_cache, debug_state), mut sim| { + sim.resettable( + cd, + async |mut sim| { + #[hdl] + let ExecuteToUnitInterface::<_> { + global_state: _, + enqueue, + inputs_ready: _, + is_no_longer_speculative: _, + cant_cause_cancel, + output_ready, + finish_cause_cancel, + unit_outputs_ready: _, + cancel_all, + config: _, + } = from_execute; + sim.write(enqueue.ready, false).await; + sim.write(cant_cause_cancel, cant_cause_cancel.ty().HdlNone()) + .await; + sim.write(output_ready, output_ready.ty().HdlNone()).await; + sim.write(finish_cause_cancel, finish_cause_cancel.ty().HdlNone()) + .await; + sim.write(cancel_all.ready, false).await; + #[hdl] + let LoadStoreToDCacheInterface::<_> { + start, + finish, + config: _, + } = to_d_cache; + sim.write(start.data, start.ty().data.HdlNone()).await; + sim.write(finish.ready, false).await; + sim.write( + debug_state, + LoadStoreState::new(config, unit_index, filter).debug_state(), + ) + .await; + }, + async |sim, ()| { + load_store_impl( + config, + unit_index, + filter, + cd, + from_execute, + to_d_cache, + debug_state, + sim, + ) + .await + }, + ) + .await + }, + ); +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)] +pub struct LoadStore { + config: PhantomConst, + module: Interned>, +} + +impl LoadStore { + pub fn new( + config: PhantomConst, + unit_index: usize, + filter: &mut impl RenamedMOpFilter, + ) -> Self { + Self { + config, + module: load_store(config, unit_index, filter), + } + } +} + +impl UnitTrait for LoadStore { + type Type = load_store; + + fn ty(&self) -> Self::Type { + self.module.io_ty() + } + + fn unit_kind(&self) -> UnitKind { + UnitKind::LoadStore + } + + fn module(&self) -> Interned> { + self.module + } + + fn io(&self, this: Expr) -> UnitIO { + UnitIO { + cd: Some(this.cd), + from_execute: this.from_execute, + to_d_cache: Some(this.to_d_cache), + } + } + + fn to_dyn(&self) -> DynUnit { + DynUnitWrapper(*self).to_dyn() + } +} diff --git a/crates/cpu/tests/units_formal.rs b/crates/cpu/tests/units_formal.rs index fa3397d..2a818b8 100644 --- a/crates/cpu/tests/units_formal.rs +++ b/crates/cpu/tests/units_formal.rs @@ -94,13 +94,17 @@ fn formal_harness( let UnitIO { cd: unit_cd, from_execute: unit_from_execute, + to_d_cache, } = dyn_unit.io(unit); + if let Some(unit_cd) = unit_cd { + connect(unit_cd, cd); + } connect( unit_from_execute, ExecuteToUnitInterfaces::unit_fields(decode_and_run.to_units)[unit_index], ); - if let Some(unit_cd) = unit_cd { - connect(unit_cd, cd); + if let Some(to_d_cache) = to_d_cache { + unimplemented!("to_d_cache for {unit:?}: {to_d_cache:?}"); } } hdl_assert(cd.clk, !decode_and_run.error, "");