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decodes an addi instruction

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Jacob Lifshay 2026-01-14 21:41:25 -08:00
parent 6d40eaadb3
commit b7b6a02777
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
4 changed files with 1560 additions and 399 deletions
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1185
crates/cpu/src/decoder/simple_power_isa.rs
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0
crates/cpu/tests/expected/decode_one_32bit_insn.vcd
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667
crates/cpu/tests/expected/decode_one_insn.vcd Normal file
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@ -0,0 +1,667 @@
$timescale 1 ps $end
$scope module decode_one_insn $end
$scope struct output $end
$scope struct elements $end
$scope struct \[0] $end
$var string 1 ! \$tag $end
$scope struct AluBranch $end
$var string 1 " \$tag $end
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$scope struct alu_common $end
$scope struct common $end
$var string 0 # prefix_pad $end
$scope struct dest $end
$scope struct normal_regs $end
$scope struct \[0] $end
$var wire 8 $ value $end
$upscope $end
$scope struct \[1] $end
$var wire 8 % value $end
$upscope $end
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$scope struct \[0] $end
$var string 1 & \$tag $end
$scope struct HdlSome $end
$upscope $end
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$scope struct \[1] $end
$var string 1 ' \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$upscope $end
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$scope struct src $end
$var wire 8 ( \[0] $end
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$var wire 25 + imm_low $end
$var wire 1 , imm_sign $end
$scope struct _phantom $end
$upscope $end
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$var string 1 - output_integer_mode $end
$upscope $end
$var wire 1 . invert_src0 $end
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$var wire 1 0 invert_carry_in $end
$var wire 1 1 add_pc $end
$upscope $end
$scope struct AddSubI $end
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$scope struct common $end
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$scope struct normal_regs $end
$scope struct \[0] $end
$var wire 8 3 value $end
$upscope $end
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$scope struct \[0] $end
$var string 1 5 \$tag $end
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$scope struct _phantom $end
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$var wire 1 ? invert_carry_in $end
$var wire 1 @ add_pc $end
$upscope $end
$scope struct Logical $end
$scope struct alu_common $end
$scope struct common $end
$var string 0 A prefix_pad $end
$scope struct dest $end
$scope struct normal_regs $end
$scope struct \[0] $end
$var wire 8 B value $end
$upscope $end
$scope struct \[1] $end
$var wire 8 C value $end
$upscope $end
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$scope struct flag_regs $end
$scope struct \[0] $end
$var string 1 D \$tag $end
$scope struct HdlSome $end
$upscope $end
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$scope struct \[1] $end
$var string 1 E \$tag $end
$scope struct HdlSome $end
$upscope $end
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$var wire 8 F \[0] $end
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$scope struct src $end
$var wire 8 R \[0] $end
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$var wire 1 X prefix_pad $end
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$scope struct normal_regs $end
$scope struct \[0] $end
$var wire 8 Y value $end
$upscope $end
$scope struct \[1] $end
$var wire 8 Z value $end
$upscope $end
$upscope $end
$scope struct flag_regs $end
$scope struct \[0] $end
$var string 1 [ \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct \[1] $end
$var string 1 \ \$tag $end
$scope struct HdlSome $end
$upscope $end
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$scope struct src $end
$var wire 8 ] \[0] $end
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$var wire 8 _ \[2] $end
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$var wire 25 ` imm_low $end
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$scope struct _phantom $end
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$upscope $end
$scope struct Store $end
$var wire 1 b prefix_pad $end
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$scope struct normal_regs $end
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$var wire 8 c value $end
$upscope $end
$scope struct \[1] $end
$var wire 8 d value $end
$upscope $end
$upscope $end
$scope struct flag_regs $end
$scope struct \[0] $end
$var string 1 e \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$scope struct \[1] $end
$var string 1 f \$tag $end
$scope struct HdlSome $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope struct src $end
$var wire 8 g \[0] $end
$var wire 8 h \[1] $end
$var wire 8 i \[2] $end
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$var wire 25 j imm_low $end
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$scope struct _phantom $end
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$scope struct \[1] $end
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$upscope $end
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$scope struct HdlSome $end
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$scope struct HdlSome $end
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$scope struct src $end
$var wire 8 s \[0] $end
$var wire 8 t \[1] $end
$var wire 8 u \[2] $end
$upscope $end
$var wire 25 v imm_low $end
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$scope struct _phantom $end
$upscope $end
$upscope $end
$var string 1 x output_integer_mode $end
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$var wire 1 y invert_src0 $end
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$var wire 1 { invert_carry_in $end
$var wire 1 | add_pc $end
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$scope struct common $end
$var string 0 } prefix_pad $end
$scope struct dest $end
$scope struct normal_regs $end
$scope struct \[0] $end
$var wire 8 ~ value $end
$upscope $end
$scope struct \[1] $end
$var wire 8 !" value $end
$upscope $end
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$scope struct flag_regs $end
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$var string 1 "" \$tag $end
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$var wire 1 ," invert_carry_in $end
$var wire 1 -" add_pc $end
$upscope $end
$scope struct Logical $end
$scope struct alu_common $end
$scope struct common $end
$var string 0 ." prefix_pad $end
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$var wire 8 /" value $end
$upscope $end
$scope struct \[1] $end
$var wire 8 0" value $end
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$scope struct flag_regs $end
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$var string 1 1" \$tag $end
$scope struct HdlSome $end
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$scope struct \[1] $end
$var string 1 2" \$tag $end
$scope struct HdlSome $end
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$scope struct dest $end
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$scope struct flag_regs $end
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$var string 1 >" \$tag $end
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$enddefinitions $end
$dumpvars
sAluBranch\x20(0) !
sAddSubI\x20(1) "
s0 #
b100011 $
b0 %
sHdlNone\x20(0) &
sHdlNone\x20(0) '
b100100 (
b0 )
b0 *
b1001000110100 +
0,
sFull64\x20(0) -
0.
0/
00
01
s0 2
b100011 3
b0 4
sHdlNone\x20(0) 5
sHdlNone\x20(0) 6
b100100 7
b0 8
b0 9
b1001000110100 :
0;
sFull64\x20(0) <
0=
0>
0?
0@
s0 A
b100011 B
b0 C
sHdlNone\x20(0) D
sHdlNone\x20(0) E
b100100 F
b0 G
b0 H
b1001000110100 I
0J
sFull64\x20(0) K
b0 L
b1 M
b100011 N
b0 O
sHdlNone\x20(0) P
sHdlNone\x20(0) Q
b100100 R
b0 S
b0 T
b1001000110100 U
0V
sStore\x20(1) W
0X
b100011 Y
b0 Z
sHdlNone\x20(0) [
sHdlNone\x20(0) \
b100100 ]
b0 ^
b0 _
b1001000110100 `
0a
0b
b100011 c
b0 d
sHdlNone\x20(0) e
sHdlNone\x20(0) f
b100100 g
b0 h
b0 i
b1001000110100 j
0k
sAluBranch\x20(0) l
sAddSub\x20(0) m
s0 n
b0 o
b0 p
sHdlNone\x20(0) q
sHdlNone\x20(0) r
b0 s
b0 t
b0 u
b0 v
0w
sFull64\x20(0) x
0y
0z
0{
0|
s0 }
b0 ~
b0 !"
sHdlNone\x20(0) ""
sHdlNone\x20(0) #"
b0 $"
b0 %"
b0 &"
b0 '"
0("
sFull64\x20(0) )"
0*"
0+"
0,"
0-"
s0 ."
b0 /"
b0 0"
sHdlNone\x20(0) 1"
sHdlNone\x20(0) 2"
b0 3"
b0 4"
b0 5"
b0 6"
07"
sFull64\x20(0) 8"
b0 9"
b0 :"
b0 ;"
b0 <"
sHdlNone\x20(0) ="
sHdlNone\x20(0) >"
b0 ?"
b0 @"
b0 A"
b0 B"
0C"
sLoad\x20(0) D"
0E"
b0 F"
b0 G"
sHdlNone\x20(0) H"
sHdlNone\x20(0) I"
b0 J"
b0 K"
b0 L"
b0 M"
0N"
0O"
b0 P"
b0 Q"
sHdlNone\x20(0) R"
sHdlNone\x20(0) S"
b0 T"
b0 U"
b0 V"
b0 W"
0X"
b1 Y"
sPhantomConst(\"0..=2\") Z"
0["
b111000011001000001001000110100 \"
sHdlNone\x20(0) ]"
b0 ^"
0_"
b1001000110100 `"
b100 a"
b11 b"
b100100 c"
$end
#1000000

107
crates/cpu/tests/simple_power_isa_decoder.rs
View file

@ -2,7 +2,7 @@
// See Notices.txt for copyright information // See Notices.txt for copyright information
use cpu::{ use cpu::{
decoder::simple_power_isa::decode_one_32bit_insn, decoder::simple_power_isa::decode_one_insn,
instruction::{AddSubMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode}, instruction::{AddSubMOp, MOp, MOpDestReg, MOpRegNum, OutputIntegerMode},
util::array_vec::ArrayVec, util::array_vec::ArrayVec,
}; };
@ -15,7 +15,8 @@ use std::{
struct TestCase { struct TestCase {
mnemonic: &'static str, mnemonic: &'static str,
input: u32, first_input: u32,
second_input: Option<u32>,
output: SimValue<ArrayVec<MOp, ConstUsize<2>>>, output: SimValue<ArrayVec<MOp, ConstUsize<2>>>,
loc: &'static std::panic::Location<'static>, loc: &'static std::panic::Location<'static>,
} }
@ -24,13 +25,21 @@ impl fmt::Debug for TestCase {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
let Self { let Self {
mnemonic, mnemonic,
input, first_input,
second_input,
output, output,
loc, loc,
} = self; } = self;
f.debug_struct("TestCase") let mut debug_struct = f.debug_struct("TestCase");
debug_struct
.field("mnemonic", mnemonic) .field("mnemonic", mnemonic)
.field("input", &format_args!("0x{input:08x}")) .field("first_input", &format_args!("0x{first_input:08x}"));
if let Some(second_input) = second_input {
debug_struct.field("second_input", &format_args!("0x{second_input:08x}"));
} else {
debug_struct.field("second_input", &format_args!("None"));
}
debug_struct
.field("output", &ArrayVec::elements_sim_ref(output)) .field("output", &ArrayVec::elements_sim_ref(output))
.field("loc", &format_args!("{loc}")) .field("loc", &format_args!("{loc}"))
.finish() .finish()
@ -43,7 +52,8 @@ fn test_cases() -> Vec<TestCase> {
#[track_caller] #[track_caller]
fn insn_single( fn insn_single(
mnemonic: &'static str, mnemonic: &'static str,
input: u32, first_input: u32,
second_input: Option<u32>,
output: impl ToSimValue<Type = MOp>, output: impl ToSimValue<Type = MOp>,
) -> TestCase { ) -> TestCase {
let zero_mop = UInt::new_dyn(MOp.canonical().bit_width()) let zero_mop = UInt::new_dyn(MOp.canonical().bit_width())
@ -54,7 +64,8 @@ fn test_cases() -> Vec<TestCase> {
ArrayVec::elements_sim_mut(&mut single_storage)[0] = output.to_sim_value(); ArrayVec::elements_sim_mut(&mut single_storage)[0] = output.to_sim_value();
TestCase { TestCase {
mnemonic, mnemonic,
input, first_input,
second_input,
output: single_storage.clone(), output: single_storage.clone(),
loc: std::panic::Location::caller(), loc: std::panic::Location::caller(),
} }
@ -62,8 +73,9 @@ fn test_cases() -> Vec<TestCase> {
retval.push(insn_single( retval.push(insn_single(
"addi 3, 4, 0x1234", "addi 3, 4, 0x1234",
0x38641234, 0x38641234,
None,
AddSubMOp::add_sub_i( AddSubMOp::add_sub_i(
MOpDestReg::new_sim(&[3], &[]), MOpDestReg::new_sim(&[MOpRegNum::POWER_ISA_GPR_REG_NUMS.start + 3], &[]),
[ [
(MOpRegNum::POWER_ISA_GPR_REG_NUMS.start + 4).cast_to_static::<UInt<_>>(), (MOpRegNum::POWER_ISA_GPR_REG_NUMS.start + 4).cast_to_static::<UInt<_>>(),
MOpRegNum::CONST_ZERO_REG_NUM.cast_to_static::<UInt<_>>(), MOpRegNum::CONST_ZERO_REG_NUM.cast_to_static::<UInt<_>>(),
@ -91,7 +103,8 @@ fn test_test_cases_assembly() -> std::io::Result<()> {
let mut assembly = String::new(); let mut assembly = String::new();
for TestCase { for TestCase {
mnemonic, mnemonic,
input: _, first_input: _,
second_input: _,
output: _, output: _,
loc: _, loc: _,
} in &test_cases } in &test_cases
@ -123,15 +136,29 @@ fn test_test_cases_assembly() -> std::io::Result<()> {
let mut lines = stdout.lines(); let mut lines = stdout.lines();
let text_line = lines.next(); let text_line = lines.next();
assert_eq!(text_line, Some("\t.text")); assert_eq!(text_line, Some("\t.text"));
for test_case in test_cases { for test_case @ TestCase {
mnemonic: _,
first_input,
second_input,
output: _,
loc: _,
} in test_cases
{
let Some(line) = lines.next() else { let Some(line) = lines.next() else {
panic!("output missing line for: {test_case:?}"); panic!("output missing line for: {test_case:?}");
}; };
let Some((_, comment)) = line.split_once('#') else { let Some((_, comment)) = line.split_once('#') else {
panic!("output line missing comment. test_case={test_case:?}\nline:\n{line}"); panic!("output line missing comment. test_case={test_case:?}\nline:\n{line}");
}; };
let [b0, b1, b2, b3] = test_case.input.to_le_bytes(); let [b0, b1, b2, b3] = first_input.to_le_bytes();
let expected_comment = format!(" encoding: [0x{b0:02x},0x{b1:02x},0x{b2:02x},0x{b3:02x}]"); let expected_comment = if let Some(second_input) = second_input {
let [b4, b5, b6, b7] = second_input.to_le_bytes();
format!(
" encoding: [0x{b0:02x},0x{b1:02x},0x{b2:02x},0x{b3:02x},0x{b4:02x},0x{b5:02x},0x{b6:02x},0x{b7:02x}]"
)
} else {
format!(" encoding: [0x{b0:02x},0x{b1:02x},0x{b2:02x},0x{b3:02x}]")
};
assert_eq!( assert_eq!(
comment, expected_comment, comment, expected_comment,
"test_case={test_case:?}\nline:\n{line}" "test_case={test_case:?}\nline:\n{line}"
@ -145,9 +172,9 @@ fn test_test_cases_assembly() -> std::io::Result<()> {
#[hdl] #[hdl]
#[test] #[test]
fn test_decode_one_32bit_insn() { fn test_decode_insn() {
let _n = SourceLocation::normalize_files_for_tests(); let _n = SourceLocation::normalize_files_for_tests();
let m = decode_one_32bit_insn(); let m = decode_one_insn();
let mut sim = Simulation::new(m); let mut sim = Simulation::new(m);
let writer = RcWriter::default(); let writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
@ -165,20 +192,60 @@ fn test_decode_one_32bit_insn() {
let mut writer = DumpVcdOnDrop { let mut writer = DumpVcdOnDrop {
writer: Some(writer), writer: Some(writer),
}; };
for test_case in test_cases() { for test_case @ TestCase {
sim.write(sim.io().input, test_case.input); mnemonic: _,
first_input,
second_input,
output: _,
loc: _,
} in test_cases()
{
sim.write(sim.io().first_input, first_input);
sim.write(
sim.io().second_input,
if let Some(v) = second_input {
#[hdl(sim)]
HdlSome(v)
} else {
#[hdl(sim)]
HdlNone()
},
);
sim.advance_time(SimDuration::from_micros(1)); sim.advance_time(SimDuration::from_micros(1));
let second_input_used = sim.read_bool(sim.io().second_input_used);
let is_illegal = sim.read_bool(sim.io().is_illegal);
let output = sim.read(sim.io().output); let output = sim.read(sim.io().output);
let expected = format!("{:?}", ArrayVec::elements_sim_ref(&test_case.output)); #[derive(Debug)]
let output = format!("{:?}", ArrayVec::elements_sim_ref(&output)); #[expect(dead_code, reason = "used only for Debug formatting")]
struct FormattedOutput<'a> {
insns: &'a [SimValue<MOp>],
second_input_used: bool,
is_illegal: bool,
}
let expected = format!(
"{:#?}",
FormattedOutput {
insns: ArrayVec::elements_sim_ref(&test_case.output),
second_input_used: second_input.is_some(),
is_illegal: false,
},
);
let output = format!(
"{:#?}",
FormattedOutput {
insns: ArrayVec::elements_sim_ref(&output),
second_input_used,
is_illegal,
},
);
assert!( assert!(
expected == output, expected == output,
"test_case={test_case:?}\noutput={output}" "test_case={test_case:#?}\noutput={output}"
); );
} }
let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap(); let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap();
println!("####### VCD:\n{vcd}\n#######"); println!("####### VCD:\n{vcd}\n#######");
if vcd != include_str!("expected/decode_one_32bit_insn.vcd") { if vcd != include_str!("expected/decode_one_insn.vcd") {
panic!(); panic!();
} }
} }