From ace4f155c39275e07b4b6434354629664b63a78d Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 4 Feb 2026 17:55:14 -0800 Subject: [PATCH] added fetch::l1_i_cache -- WIP test --- crates/cpu/src/config.rs | 72 + crates/cpu/src/fetch.rs | 1464 +++ crates/cpu/src/lib.rs | 1 + crates/cpu/src/next_pc.rs | 8 +- crates/cpu/src/util/array_vec.rs | 42 + crates/cpu/tests/expected/fetch.vcd | 16294 ++++++++++++++++++++++++++ crates/cpu/tests/fetch.rs | 669 ++ 7 files changed, 18546 insertions(+), 4 deletions(-) create mode 100644 crates/cpu/src/fetch.rs create mode 100644 crates/cpu/tests/expected/fetch.vcd create mode 100644 crates/cpu/tests/fetch.rs diff --git a/crates/cpu/src/config.rs b/crates/cpu/src/config.rs index cf2fd08..9826955 100644 --- a/crates/cpu/src/config.rs +++ b/crates/cpu/src/config.rs @@ -37,6 +37,9 @@ pub struct CpuConfig { pub max_branches_per_fetch: NonZeroUsize, pub max_fetches_in_flight: NonZeroUsize, pub log2_fetch_width_in_bytes: u8, + pub log2_cache_line_size_in_bytes: u8, + pub log2_l1_i_cache_line_count: u8, + pub l1_i_cache_max_misses_in_flight: NonZeroUsize, /// default value for [`UnitConfig::max_in_flight`] pub default_unit_max_in_flight: NonZeroUsize, pub rob_size: NonZeroUsize, @@ -63,6 +66,14 @@ impl CpuConfig { v }; pub const DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES: u8 = 3; + pub const DEFAULT_LOG2_CACHE_LINE_SIZE_IN_BYTES: u8 = 6; + pub const DEFAULT_LOG2_L1_I_CACHE_LINE_COUNT: u8 = 8; + pub const DEFAULT_L1_I_CACHE_MAX_MISSES_IN_FLIGHT: NonZeroUsize = { + let Some(v) = NonZeroUsize::new(2) else { + unreachable!(); + }; + v + }; pub const DEFAULT_UNIT_MAX_IN_FLIGHT: NonZeroUsize = { let Some(v) = NonZeroUsize::new(8) else { unreachable!(); @@ -77,6 +88,9 @@ impl CpuConfig { max_branches_per_fetch: Self::DEFAULT_MAX_BRANCHES_PER_FETCH, max_fetches_in_flight: Self::DEFAULT_MAX_FETCHES_IN_FLIGHT, log2_fetch_width_in_bytes: Self::DEFAULT_LOG2_FETCH_WIDTH_IN_BYTES, + log2_cache_line_size_in_bytes: Self::DEFAULT_LOG2_CACHE_LINE_SIZE_IN_BYTES, + log2_l1_i_cache_line_count: Self::DEFAULT_LOG2_L1_I_CACHE_LINE_COUNT, + l1_i_cache_max_misses_in_flight: Self::DEFAULT_L1_I_CACHE_MAX_MISSES_IN_FLIGHT, default_unit_max_in_flight: Self::DEFAULT_UNIT_MAX_IN_FLIGHT, rob_size, } @@ -141,6 +155,37 @@ impl CpuConfig { .checked_shl(self.log2_fetch_width_in_bytes.into()) .expect("log2_fetch_width_in_bytes is too big") } + pub fn cache_line_size_in_bytes(&self) -> usize { + 1usize + .checked_shl(self.log2_cache_line_size_in_bytes.into()) + .expect("log2_cache_line_size_in_bytes is too big") + } + pub fn log2_fetches_per_cache_line(&self) -> usize { + self.log2_cache_line_size_in_bytes + .checked_sub(self.log2_fetch_width_in_bytes) + .expect("cache line size in bytes must not be smaller than fetch width in bytes") + .into() + } + pub fn fetches_per_cache_line(&self) -> usize { + self.log2_fetches_per_cache_line() + .try_into() + .ok() + .and_then(|v| 1usize.checked_shl(v)) + .expect("log2_fetches_per_cache_line is too big") + } + pub fn l1_i_cache_line_count(&self) -> usize { + 1usize + .checked_shl(self.log2_l1_i_cache_line_count.into()) + .expect("log2_l1_i_cache_line_count is too big") + } + pub fn log2_l1_i_cache_size_in_bytes(&self) -> usize { + self.log2_l1_i_cache_line_count as usize + self.log2_cache_line_size_in_bytes as usize + } + pub fn l1_i_cache_size_in_bytes(&self) -> usize { + 1usize + .checked_shl(self.log2_l1_i_cache_size_in_bytes() as _) + .expect("L1 I-Cache is too big") + } } #[hdl(get(|c| c.fetch_width.get()))] @@ -161,6 +206,33 @@ pub type CpuConfigLog2FetchWidthInBytes> = DynSize #[hdl(get(|c| c.fetch_width_in_bytes()))] pub type CpuConfigFetchWidthInBytes> = DynSize; +#[hdl(get(|c| c.log2_fetches_per_cache_line()))] +pub type CpuConfigLog2FetchesPerCacheLine> = DynSize; + +#[hdl(get(|c| c.fetches_per_cache_line()))] +pub type CpuConfigFetchesPerCacheLine> = DynSize; + +#[hdl(get(|c| c.log2_cache_line_size_in_bytes.into()))] +pub type CpuConfigLog2CacheLineSizeInBytes> = DynSize; + +#[hdl(get(|c| c.cache_line_size_in_bytes()))] +pub type CpuConfigCacheLineSizeInBytes> = DynSize; + +#[hdl(get(|c| c.log2_l1_i_cache_line_count.into()))] +pub type CpuConfigLog2L1ICacheLineCount> = DynSize; + +#[hdl(get(|c| c.l1_i_cache_line_count()))] +pub type CpuConfigL1ICacheLineCount> = DynSize; + +#[hdl(get(|c| c.log2_l1_i_cache_size_in_bytes()))] +pub type CpuConfigLog2L1ICacheSizeInBytes> = DynSize; + +#[hdl(get(|c| c.l1_i_cache_size_in_bytes()))] +pub type CpuConfigL1ICacheSizeInBytes> = DynSize; + +#[hdl(get(|c| c.l1_i_cache_max_misses_in_flight.get()))] +pub type CpuConfigL1ICacheMaxMissesInFlight> = DynSize; + #[hdl(get(|c| c.rob_size.get()))] pub type CpuConfigRobSize> = DynSize; diff --git a/crates/cpu/src/fetch.rs b/crates/cpu/src/fetch.rs new file mode 100644 index 0000000..2fdedf9 --- /dev/null +++ b/crates/cpu/src/fetch.rs @@ -0,0 +1,1464 @@ +// SPDX-License-Identifier: LGPL-3.0-or-later +// See Notices.txt for copyright information + +use crate::{ + config::{ + CpuConfig, CpuConfigFetchWidthInBytes, CpuConfigFetchesPerCacheLine, + CpuConfigL1ICacheLineCount, CpuConfigL1ICacheMaxMissesInFlight, + CpuConfigLog2FetchWidthInBytes, CpuConfigLog2L1ICacheLineCount, + CpuConfigMaxFetchesInFlight, PhantomConstCpuConfig, + }, + next_pc::{ + FETCH_BLOCK_ID_WIDTH, NextPcToFetchInterface, NextPcToFetchInterfaceInner, ResetStatus, + ResetSteps, SimValueDefault, + }, + util::array_vec::ArrayVec, +}; +use fayalite::{ + int::{UIntInRangeInclusiveType, UIntInRangeType}, + memory::{ReadWriteStruct, memory_addr_width, splat_mask}, + prelude::*, + util::{DebugAsDisplay, ready_valid::ReadyValid}, +}; +use std::{collections::VecDeque, fmt}; + +#[hdl] +pub enum MemoryOperationKind { + Read, + Write, +} + +#[hdl(no_static)] +pub struct MemoryOperationStart + PhantomConstCpuConfig> { + pub kind: MemoryOperationKind, + pub addr: UInt<64>, + pub write_data: ArrayType, CpuConfigFetchWidthInBytes>, + pub fetch_block_id: UInt<8>, // for debugging + pub config: C, +} + +#[hdl] +pub enum MemoryOperationErrorKind { + Generic, +} + +#[hdl] +pub enum MemoryOperationFinishKind { + Success(MemoryOperationKind), + Error(MemoryOperationErrorKind), +} + +#[hdl(no_static)] +pub struct MemoryOperationFinish + PhantomConstCpuConfig> { + pub kind: MemoryOperationFinishKind, + pub read_data: ArrayType, CpuConfigFetchWidthInBytes>, + pub config: C, +} + +#[hdl(no_static)] +pub struct MemoryInterface + PhantomConstCpuConfig> { + pub start: ReadyValid>, + #[hdl(flip)] + pub finish: ReadyValid>, + /// for debugging + #[hdl(flip)] + pub next_fetch_block_ids: + HdlOption, CpuConfigMaxFetchesInFlight>>, + pub config: C, +} + +#[hdl(no_static)] +pub struct FetchToDecodeInterfaceInner + PhantomConstCpuConfig> { + pub start_pc: UInt<64>, + pub fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, + pub fetch_block_data: ArrayType, CpuConfigFetchWidthInBytes>, + pub error: HdlOption, + pub config: C, +} + +#[hdl(no_static)] +pub struct FetchToDecodeInterface + PhantomConstCpuConfig> { + pub fetched: ReadyValid>, + /// when both fetch and cancel are triggered in the same clock cycle, that means to cancel and then start a new fetch + pub cancel: HdlOption, CpuConfigMaxFetchesInFlight>>, +} + +#[hdl(no_static)] +struct CacheLine + PhantomConstCpuConfig> { + data: ArrayType< + ArrayType, CpuConfigFetchWidthInBytes>, + CpuConfigFetchesPerCacheLine, + >, + addr: HdlOption>>, + config: C, +} + +impl SimValueDefault for CacheLine { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { data, addr, config } = self; + #[hdl(sim)] + Self { + data: data.sim_value_default(), + addr: addr.sim_value_default(), + config, + } + } +} + +#[hdl(get(|c| 64usize.saturating_sub(c.log2_l1_i_cache_size_in_bytes())))] +type CacheLineTagAddrWidth> = DynSize; + +#[hdl] +enum CacheLookupState { + Start, + ReadingCache, + CacheMiss, + AfterCacheMiss, + ReadingCacheAfterCacheMiss, + Returning, +} + +#[hdl(no_static)] +struct FetchQueueEntry + PhantomConstCpuConfig> { + start_pc: UInt<64>, + fetch_block_id: UInt<{ FETCH_BLOCK_ID_WIDTH }>, + state: CacheLookupState, + error: HdlOption, + fetch_block_data: ArrayType, CpuConfigFetchWidthInBytes>, + config: C, +} + +impl SimValueDefault for FetchQueueEntry { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + start_pc: _, + fetch_block_id, + state: _, + error: _, + fetch_block_data, + config, + } = self; + #[hdl(sim)] + Self { + start_pc: 0u64, + fetch_block_id: fetch_block_id.zero(), + state: #[hdl(sim)] + CacheLookupState.Start(), + error: #[hdl(sim)] + HdlNone(), + fetch_block_data: fetch_block_data.sim_value_default(), + config, + } + } +} + +#[hdl(no_static)] +struct CacheMiss + PhantomConstCpuConfig> { + addr: UInt<64>, + fetch_block_id: UInt<8>, + next_start_fetch_block: HdlOption>, + next_finish_fetch_block: HdlOption>, + error: HdlOption, + config: C, +} + +impl CacheMiss { + #[hdl] + fn next_fetch_block( + next_opt: &mut SimValue>>, + limit: Option, + ) -> Option>> { + let next: &mut SimValue> = #[hdl(sim)] + match &mut *next_opt { + HdlSome(next) => next, + HdlNone => return None, + }; + let limit = limit.unwrap_or(next.ty().end()); + if **next >= limit { + return None; + } + let retval = next.clone(); + if **next + 1 >= limit { + *next_opt = #[hdl(sim)] + (next_opt.ty()).HdlNone(); + } else { + **next += 1; + } + Some(retval) + } + #[hdl] + fn next_start_fetch_block( + this: &mut SimValue, + ) -> Option>> { + #[hdl(sim)] + if let HdlSome(_) = &this.error { + return None; + } + Self::next_fetch_block(&mut this.next_start_fetch_block, None) + } + #[hdl] + fn next_finish_fetch_block( + this: &mut SimValue, + ) -> Option>> { + let mut limit = None; + #[hdl(sim)] + if let HdlSome(_) = &this.error { + #[hdl(sim)] + if let HdlSome(v) = &this.next_start_fetch_block { + limit = Some(**v); + } + } + Self::next_fetch_block(&mut this.next_finish_fetch_block, limit) + } +} + +impl SimValueDefault for CacheMiss { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + addr: _, + fetch_block_id, + next_start_fetch_block, + next_finish_fetch_block, + error: _, + config, + } = self; + #[hdl(sim)] + Self { + addr: 0u64, + fetch_block_id: fetch_block_id.zero(), + next_start_fetch_block: #[hdl(sim)] + next_start_fetch_block.HdlNone(), + next_finish_fetch_block: #[hdl(sim)] + next_finish_fetch_block.HdlNone(), + error: #[hdl(sim)] + HdlNone(), + config, + } + } +} + +#[hdl(no_static)] +struct L1ICacheState + PhantomConstCpuConfig> { + queue: ArrayVec, CpuConfigMaxFetchesInFlight>, + cache_misses: ArrayVec, CpuConfigL1ICacheMaxMissesInFlight>, + config: C, +} + +#[derive(Clone)] +struct L1ICacheStateSim { + queue: VecDeque>>, + cache_misses: VecDeque>>, + state_expr: Expr>, +} + +impl fmt::Debug for L1ICacheStateSim { + #[hdl] + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + queue, + cache_misses, + state_expr: _, + } = self; + f.debug_struct("L1ICacheStateSim") + .field( + "queue", + &fmt::from_fn(|f| { + let mut debug_list = f.debug_list(); + for entry in queue { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id, + state, + error, + fetch_block_data, + config: _, + } = entry; + let entry = fmt::from_fn(|f| { + f.debug_struct("FetchQueueEntry") + .field("start_pc", start_pc) + .field("fetch_block_id", fetch_block_id) + .field( + "state", + #[hdl(sim)] + match state { + CacheLookupState::Start => &DebugAsDisplay("Start"), + CacheLookupState::ReadingCache => { + &DebugAsDisplay("ReadingCache") + } + CacheLookupState::CacheMiss => &DebugAsDisplay("CacheMiss"), + CacheLookupState::AfterCacheMiss => { + &DebugAsDisplay("AfterCacheMiss") + } + CacheLookupState::ReadingCacheAfterCacheMiss => { + &DebugAsDisplay("ReadingCacheAfterCacheMiss") + } + CacheLookupState::Returning => &DebugAsDisplay("Returning"), + CacheLookupState::Unknown => state, + }, + ) + .field( + "error", + &fmt::from_fn(|f| { + #[hdl(sim)] + match error { + HdlSome(v) => { + write!(f, "HdlSome({v:?})") + } + HdlNone => write!(f, "HdlNone"), + } + }), + ) + .field("fetch_block_data", fetch_block_data) + .finish() + }); + debug_list.entry(&format_args!("{entry}")); + } + debug_list.finish() + }), + ) + .field( + "cache_misses", + &fmt::from_fn(|f| { + let mut debug_list = f.debug_list(); + for cache_miss in cache_misses { + #[hdl(sim)] + let CacheMiss::<_> { + addr, + fetch_block_id, + next_start_fetch_block, + next_finish_fetch_block, + error, + config: _, + } = cache_miss; + let entry = fmt::from_fn(|f| { + f.debug_struct("CacheMiss") + .field("addr", addr) + .field("fetch_block_id", fetch_block_id) + .field( + "next_start_fetch_block", + &fmt::from_fn(|f| { + #[hdl(sim)] + match next_start_fetch_block { + HdlSome(v) => { + write!(f, "HdlSome({})", **v) + } + HdlNone => write!(f, "HdlNone"), + } + }), + ) + .field( + "next_finish_fetch_block", + &fmt::from_fn(|f| { + #[hdl(sim)] + match next_finish_fetch_block { + HdlSome(v) => { + write!(f, "HdlSome({})", **v) + } + HdlNone => write!(f, "HdlNone"), + } + }), + ) + .field( + "error", + &fmt::from_fn(|f| { + #[hdl(sim)] + match error { + HdlSome(v) => { + write!(f, "HdlSome({v:?})") + } + HdlNone => write!(f, "HdlNone"), + } + }), + ) + .finish() + }); + debug_list.entry(&format_args!("{entry}")); + } + debug_list.finish() + }), + ) + .finish_non_exhaustive() + } +} + +#[hdl(no_static)] +struct WriteBackStep + PhantomConstCpuConfig> { + cache_line_index: UIntType>, + data: CacheLine, + mask: AsMask>, +} + +#[hdl(no_static)] +struct CacheRead + PhantomConstCpuConfig> { + cache_line_index: UIntType>, + config: C, +} + +#[hdl(no_static)] +struct CacheReadData + PhantomConstCpuConfig> { + cache_line_index: UIntType>, + cache_line: CacheLine, +} + +#[hdl] +type FetchBlockInCacheLine + PhantomConstCpuConfig> = + UIntInRangeType, CpuConfigFetchesPerCacheLine>; + +#[hdl(no_static)] +struct SplitAddr + PhantomConstCpuConfig> { + // fields must be in LSB to MSB order + byte_in_fetch_block: UIntType>, + fetch_block_in_cache_line: FetchBlockInCacheLine, + cache_line_index: UIntType>, + tag: UIntType>, +} + +impl SplitAddr { + #[hdl] + fn split_addr_sim(self, addr: impl ToSimValueWithType>) -> SimValue { + let addr = addr.into_sim_value_with_type(UInt::<64>::new_static()); + assert_eq!( + self.fetch_block_in_cache_line.bit_width(), + self.fetch_block_in_cache_line.end().ilog2() as usize + ); + addr.cast_bits_to(self) + } + #[hdl] + fn addr_sim(this: impl ToSimValue) -> SimValue> { + SimValue::from_dyn_int(this.into_sim_value().cast_to_bits()) + } +} + +struct ReadyForMemoryOperationFinish { + cache_miss_index: usize, +} + +struct ReadyForFetch {} + +impl L1ICacheStateSim { + fn new(state_expr: Expr>) -> Self { + let config = state_expr.ty().config; + Self { + queue: VecDeque::with_capacity(CpuConfigMaxFetchesInFlight[config]), + cache_misses: VecDeque::with_capacity(CpuConfigL1ICacheMaxMissesInFlight[config]), + state_expr, + } + } + fn config(&self) -> C { + self.state_expr.ty().config + } + #[hdl] + fn try_start_memory_operation(&mut self) -> Option>> { + let config = self.config(); + for cache_miss in &mut self.cache_misses { + let Some(next_start_fetch_block) = CacheMiss::next_start_fetch_block(cache_miss) else { + continue; + }; + #[hdl(sim)] + let CacheMiss::<_> { + addr, + fetch_block_id, + next_start_fetch_block: _, + next_finish_fetch_block: _, + error: _, // handled by CacheMiss::next_start_fetch_block() + config: _, + } = cache_miss; + let mem_op_ty = MemoryOperationStart[config]; + let mut addr = SplitAddr[config].split_addr_sim(addr); + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block, + fetch_block_in_cache_line, + cache_line_index: _, + tag: _, + } = &mut addr; + assert!(*byte_in_fetch_block.cmp_eq(0u8), "{addr:?}"); + assert!(*fetch_block_in_cache_line.cmp_eq(0u8), "{addr:?}"); + *fetch_block_in_cache_line = next_start_fetch_block; + return Some( + #[hdl(sim)] + MemoryOperationStart::<_> { + kind: #[hdl(sim)] + MemoryOperationKind.Read(), + addr: SplitAddr::addr_sim(addr), + write_data: repeat( + mem_op_ty.write_data.element().zero(), + mem_op_ty.write_data.len(), + ), + fetch_block_id, + config, + }, + ); + } + None + } + #[hdl] + fn queue_front_state_is_after_cache_miss(&self) -> bool { + self.queue.front().is_some_and(|entry| { + #[hdl(sim)] + match &entry.state { + CacheLookupState::Start + | CacheLookupState::ReadingCache + | CacheLookupState::CacheMiss + | CacheLookupState::Returning => false, + CacheLookupState::AfterCacheMiss | CacheLookupState::ReadingCacheAfterCacheMiss => { + true + } + CacheLookupState::Unknown => unreachable!(), + } + }) + } + #[hdl] + fn ready_for_memory_operation_finish(&self) -> Option { + if self.queue_front_state_is_after_cache_miss() { + println!("ready_for_memory_operation_finish: queue_front_state_is_after_cache_miss"); + return None; + } + for (cache_miss_index, cache_miss) in self.cache_misses.iter().enumerate() { + let Some(_next_finish_cache_block) = + CacheMiss::next_finish_fetch_block(&mut cache_miss.clone()) + else { + continue; + }; + return Some(ReadyForMemoryOperationFinish { cache_miss_index }); + } + None + } + #[must_use] + #[hdl] + fn do_memory_operation_finish<'a>( + &mut self, + ready_for_memory_operation_finish: ReadyForMemoryOperationFinish, + memory_operation_finish: impl ToSimValue>, + ) -> Option>> { + let config = self.config(); + let cache_miss = &mut self.cache_misses[ready_for_memory_operation_finish.cache_miss_index]; + let Some(fetch_block) = CacheMiss::next_finish_fetch_block(cache_miss) else { + unreachable!(); + }; + #[hdl(sim)] + let CacheMiss::<_> { + addr, + fetch_block_id: _, + next_start_fetch_block: _, + next_finish_fetch_block, + error, + config: _, + } = cache_miss; + #[hdl(sim)] + let MemoryOperationFinish::<_> { + kind, + read_data, + config: _, + } = memory_operation_finish; + #[hdl(sim)] + match kind { + MemoryOperationFinishKind::Success(success) => + { + #[hdl(sim)] + match success { + MemoryOperationKind::Read => {} + MemoryOperationKind::Write => unreachable!(), + } + } + MemoryOperationFinishKind::Error(e) => + { + #[hdl(sim)] + if let HdlNone = &error { + *error = #[hdl(sim)] + HdlSome(e); + } + } + } + #[hdl(sim)] + if let HdlSome(_) = error { + return None; + } + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block, + fetch_block_in_cache_line, + cache_line_index, + tag, + } = SplitAddr[config].split_addr_sim(&addr); + assert!(*byte_in_fetch_block.cmp_eq(0u8), "{addr:?}"); + assert!(*fetch_block_in_cache_line.cmp_eq(0u8), "{addr:?}"); + let write_back_step_ty = WriteBackStep[config]; + let mut data = write_back_step_ty.data.sim_value_default(); + let mut mask = splat_mask(write_back_step_ty.data, false.to_expr()).into_sim_value(); + #[hdl(sim)] + let AsMask::> { + data: mask_data, + addr: mask_addr, + config: _, + } = &mut mask; + #[hdl(sim)] + let CacheLine::<_> { + data: data_data, + addr: data_addr, + config: _, + } = &mut data; + // set cache line tag, making sure to mark partially-filled cache lines as invalid + **mask_addr = true; + let data_addr_ty = data_addr.ty(); + *data_addr = #[hdl(sim)] + if let HdlNone = next_finish_fetch_block { + #[hdl(sim)] + data_addr_ty.HdlSome(tag) + } else { + #[hdl(sim)] + data_addr_ty.HdlNone() + }; + data_data[*fetch_block] = read_data.clone(); + for mask_data_byte in &mut mask_data[*fetch_block] { + **mask_data_byte = true; + } + Some( + #[hdl(sim)] + WriteBackStep::<_> { + cache_line_index, + data, + mask, + }, + ) + } + #[hdl] + async fn write_debug_state(&self, sim: &mut ExternModuleSimulationState) { + dbg!(self); + let L1ICacheState { + queue, + cache_misses, + config, + } = self.state_expr.ty(); + let queue = queue + .from_iter_sim(queue.element().sim_value_default(), &self.queue) + .expect("known to fit"); + let cache_misses = cache_misses + .from_iter_sim( + cache_misses.element().sim_value_default(), + &self.cache_misses, + ) + .expect("known to fit"); + sim.write( + self.state_expr, + #[hdl(sim)] + L1ICacheState::<_> { + queue, + cache_misses, + config, + }, + ) + .await; + } + #[hdl] + fn check_memory_next_fetch_block_ids( + &self, + memory_next_fetch_block_ids: SimValue< + ArrayVec, CpuConfigMaxFetchesInFlight>, + >, + ) { + let memory_next_fetch_block_ids = ArrayVec::elements_sim_ref(&memory_next_fetch_block_ids); + let mut expected_memory_next_fetch_block_ids = Vec::new(); + for cache_miss in &self.cache_misses { + let range_start = #[hdl(sim)] + match &cache_miss.next_finish_fetch_block { + HdlSome(v) => **v, + HdlNone => continue, // fully finished + }; + let range_end = #[hdl(sim)] + match &cache_miss.next_start_fetch_block { + HdlSome(v) => **v, + HdlNone => cache_miss.next_start_fetch_block.ty().HdlSome.end(), + }; + for _ in range_start..range_end { + expected_memory_next_fetch_block_ids.push(cache_miss.fetch_block_id.clone()); + } + } + assert_eq!( + memory_next_fetch_block_ids, + expected_memory_next_fetch_block_ids + ); + } + #[hdl] + fn ready_for_fetch(&self) -> Option { + if self.queue_front_state_is_after_cache_miss() { + println!("ready_for_fetch: queue_front_state_is_after_cache_miss"); + return None; + } + let config = self.config(); + let max_fetches_in_flight = CpuConfigMaxFetchesInFlight[config]; + assert!(self.queue.len() <= max_fetches_in_flight); + (self.queue.len() < max_fetches_in_flight).then_some(ReadyForFetch {}) + } + #[hdl] + fn do_fetch<'a>( + &mut self, + ready_for_fetch: ReadyForFetch, + fetch: impl ToSimValue, + ) { + let ReadyForFetch {} = ready_for_fetch; + let config = self.config(); + let max_fetches_in_flight = CpuConfigMaxFetchesInFlight[config]; + assert!(self.queue.len() < max_fetches_in_flight); + #[hdl(sim)] + let NextPcToFetchInterfaceInner { + start_pc, + fetch_block_id, + } = fetch; + let entry_ty = FetchQueueEntry[config]; + self.queue.push_back( + #[hdl(sim)] + FetchQueueEntry::<_> { + start_pc, + fetch_block_id, + state: #[hdl(sim)] + CacheLookupState.Start(), + error: #[hdl(sim)] + HdlNone(), + fetch_block_data: entry_ty.fetch_block_data.sim_value_default(), + config, + }, + ); + } + #[hdl] + fn cancel_fetches(&mut self, in_progress_fetches_to_cancel: usize) { + // cancel in-progress fetches from newest to oldest + self.queue.truncate( + self.queue + .len() + .saturating_sub(in_progress_fetches_to_cancel), + ); + } + #[hdl] + fn finish_cache_misses(&mut self) { + let split_addr_ty = SplitAddr[self.config()]; + let cache_miss = self.cache_misses.pop_front_if(|cache_miss| { + let mut cache_miss = cache_miss.clone(); + CacheMiss::next_start_fetch_block(&mut cache_miss).is_none() + && CacheMiss::next_finish_fetch_block(&mut cache_miss).is_none() + }); + let Some(cache_miss) = cache_miss else { + return; + }; + #[hdl(sim)] + let CacheMiss::<_> { + addr, + fetch_block_id: _, + next_start_fetch_block: _, + next_finish_fetch_block: _, + error, + config: _, + } = cache_miss; + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block, + fetch_block_in_cache_line, + cache_line_index, + tag, + } = split_addr_ty.split_addr_sim(&addr); + assert!(*byte_in_fetch_block.cmp_eq(0u8), "{addr:?}"); + assert!(*fetch_block_in_cache_line.cmp_eq(0u8), "{addr:?}"); + for entry in &mut self.queue { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id: _, + state, + error: entry_error, + fetch_block_data: _, + config: _, + } = entry; + #[hdl(sim)] + match &state { + CacheLookupState::Start + | CacheLookupState::ReadingCache + | CacheLookupState::AfterCacheMiss + | CacheLookupState::ReadingCacheAfterCacheMiss + | CacheLookupState::Returning => continue, + CacheLookupState::CacheMiss => {} + CacheLookupState::Unknown => unreachable!(), + } + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block: _, + fetch_block_in_cache_line: _, + cache_line_index: entry_cache_line_index, + tag: entry_tag, + } = split_addr_ty.split_addr_sim(start_pc); + if *cache_line_index.cmp_eq(entry_cache_line_index) && *tag.cmp_eq(entry_tag) { + *entry_error = error.clone(); + *state = #[hdl(sim)] + if let HdlSome(_) = &error { + #[hdl(sim)] + CacheLookupState.Returning() + } else { + #[hdl(sim)] + CacheLookupState.AfterCacheMiss() + }; + } + } + } + #[must_use] + #[hdl] + fn next_cache_read(&mut self) -> Option>> { + let config = self.config(); + for entry in &mut self.queue { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id: _, + state, + error: _, + fetch_block_data: _, + config: _, + } = entry; + *state = #[hdl(sim)] + match &state { + CacheLookupState::Start => + { + #[hdl(sim)] + CacheLookupState.ReadingCache() + } + CacheLookupState::AfterCacheMiss => + { + #[hdl(sim)] + CacheLookupState.ReadingCacheAfterCacheMiss() + } + CacheLookupState::ReadingCache + | CacheLookupState::CacheMiss + | CacheLookupState::ReadingCacheAfterCacheMiss + | CacheLookupState::Returning => continue, + CacheLookupState::Unknown => unreachable!(), + }; + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block: _, + fetch_block_in_cache_line: _, + cache_line_index, + tag: _, + } = SplitAddr[config].split_addr_sim(start_pc); + return Some( + #[hdl(sim)] + CacheRead::<_> { + cache_line_index, + config, + }, + ); + } + None + } + #[hdl] + fn cache_read_data(&mut self, cache_read_data: impl ToSimValue>) { + #[hdl(sim)] + let CacheReadData::<_> { + cache_line_index: read_cache_line_index, + cache_line, + } = cache_read_data; + let config = self.config(); + for entry in &mut self.queue { + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id, + state, + error: _, + fetch_block_data, + config: _, + } = entry; + #[hdl(sim)] + match &state { + CacheLookupState::Start + | CacheLookupState::CacheMiss + | CacheLookupState::AfterCacheMiss + | CacheLookupState::Returning => continue, + CacheLookupState::ReadingCache | CacheLookupState::ReadingCacheAfterCacheMiss => {} + CacheLookupState::Unknown => unreachable!(), + } + let split_addr_ty = SplitAddr[config]; + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block: _, + fetch_block_in_cache_line, + cache_line_index, + tag, + } = split_addr_ty.split_addr_sim(start_pc); + if *cache_line_index.cmp_ne(&read_cache_line_index) { + break; + } + let addr_ty = cache_line.addr.ty(); + let opt_tag = #[hdl(sim)] + addr_ty.HdlSome(&tag); + if *opt_tag.cmp_eq(&cache_line.addr) { + // cache hit + *fetch_block_data = cache_line.data[*fetch_block_in_cache_line].clone(); + *state = #[hdl(sim)] + CacheLookupState.Returning(); + } else { + // cache miss + let is_matching_cache_miss = |cache_miss: &SimValue>| { + let addr = &cache_miss.addr; + #[hdl(sim)] + let SplitAddr::<_> { + byte_in_fetch_block: cache_miss_byte_in_fetch_block, + fetch_block_in_cache_line: cache_miss_fetch_block_in_cache_line, + cache_line_index: cache_miss_cache_line_index, + tag: cache_miss_tag, + } = split_addr_ty.split_addr_sim(addr); + assert!(*cache_miss_byte_in_fetch_block.cmp_eq(0u8), "{addr:?}"); + assert!( + *cache_miss_fetch_block_in_cache_line.cmp_eq(0u8), + "{addr:?}" + ); + *cache_line_index.cmp_eq(cache_miss_cache_line_index) + && *tag.cmp_eq(cache_miss_tag) + }; + if self.cache_misses.iter().any(is_matching_cache_miss) { + *state = #[hdl(sim)] + CacheLookupState.CacheMiss(); + } else if self.cache_misses.len() < CpuConfigL1ICacheMaxMissesInFlight[config] { + let CacheMiss { + addr: _, + fetch_block_id: _, + next_start_fetch_block, + next_finish_fetch_block, + error, + config: _, + } = CacheMiss[config]; + self.cache_misses.push_back( + #[hdl(sim)] + CacheMiss::<_> { + addr: SplitAddr::::addr_sim( + #[hdl(sim)] + SplitAddr::<_> { + byte_in_fetch_block: split_addr_ty.byte_in_fetch_block.zero(), + fetch_block_in_cache_line: 0usize.to_sim_value_with_type( + split_addr_ty.fetch_block_in_cache_line, + ), + cache_line_index, + tag, + }, + ), + fetch_block_id, + next_start_fetch_block: #[hdl(sim)] + next_start_fetch_block.HdlSome(0usize), + next_finish_fetch_block: #[hdl(sim)] + next_finish_fetch_block.HdlSome(0usize), + error: #[hdl(sim)] + error.HdlNone(), + config, + }, + ); + *state = #[hdl(sim)] + CacheLookupState.CacheMiss(); + } else { + // no space for a cache miss, wait until there's space + *state = #[hdl(sim)] + CacheLookupState.Start(); + } + } + break; + } + } + #[hdl] + fn to_decode_fetched(&mut self) -> Option>> { + let entry = self.queue.front_mut()?; + #[hdl(sim)] + let FetchQueueEntry::<_> { + start_pc, + fetch_block_id, + state, + error, + fetch_block_data, + config, + } = &mut *entry; + #[hdl(sim)] + match &state { + CacheLookupState::Start + | CacheLookupState::ReadingCache + | CacheLookupState::CacheMiss + | CacheLookupState::AfterCacheMiss + | CacheLookupState::ReadingCacheAfterCacheMiss => return None, + CacheLookupState::Returning => {} + CacheLookupState::Unknown => unreachable!(), + } + let retval = #[hdl(sim)] + FetchToDecodeInterfaceInner::<_> { + start_pc, + fetch_block_id, + fetch_block_data, + error, + config, + }; + self.queue.pop_front(); + Some(retval) + } +} + +impl SimValueDefault for L1ICacheState { + #[hdl] + fn sim_value_default(self) -> SimValue { + let Self { + queue, + cache_misses, + config, + } = self; + #[hdl(sim)] + Self { + queue: queue.sim_value_default(), + cache_misses: cache_misses.sim_value_default(), + config, + } + } +} + +impl ResetSteps for L1ICacheState { + #[hdl] + fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus { + #[hdl(sim)] + let Self { + // overwritten every cycle, no reset needed + queue: _, + // overwritten every cycle, no reset needed + cache_misses: _, + config: _, + } = this; + let _ = step; + ResetStatus::Done + } +} + +#[hdl_module(extern)] +fn l1_i_cache_impl(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.output(MemoryInterface[config]); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode_fetched: ReadyValid>> = + m.output(ReadyValid[FetchToDecodeInterfaceInner[config]]); + #[hdl] + let max_cancel_in_fetch: UIntInRangeInclusiveType< + ConstUsize<0>, + CpuConfigMaxFetchesInFlight>, + > = m.output(UIntInRangeInclusiveType[ConstUsize::<0>][CpuConfigMaxFetchesInFlight[config]]); + // i_cache_port.clk is externally overridden with cd.clk + #[hdl] + let i_cache_port: ReadWriteStruct>, DynSize> = m.output( + ReadWriteStruct[CacheLine[config]][memory_addr_width(CpuConfigL1ICacheLineCount[config])], + ); + #[hdl] + let state_for_debug: L1ICacheState> = m.output(L1ICacheState[config]); + m.register_clock_for_past(cd.clk); + #[hdl] + async fn run( + mut sim: ExternModuleSimulationState, + cd: Expr, + memory_interface: Expr>>, + from_next_pc: Expr>>, + to_decode_fetched: Expr>>>, + max_cancel_in_fetch: Expr< + UIntInRangeInclusiveType< + ConstUsize<0>, + CpuConfigMaxFetchesInFlight>, + >, + >, + i_cache_port: Expr>, DynSize>>, + state_expr: Expr>>, + ) { + let config = state_expr.ty().config; + let l1_i_cache_line_count = CpuConfigL1ICacheLineCount[config]; + let cache_line_ty = CacheLine[config]; + for step in 0usize..l1_i_cache_line_count { + sim.write(i_cache_port.en, false).await; + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, step.cast_to(addr.ty())).await; + sim.write(en, true).await; + sim.write(wmode, true).await; + sim.write(wdata, CacheLine::sim_value_default(wdata.ty())) + .await; + sim.write(wmask, splat_mask(cache_line_ty, true.to_expr())) + .await; + sim.wait_for_clock_edge(cd.clk).await; + } + sim.write(from_next_pc.cancel.ready, true).await; + let memory_interface_start_data_ty = memory_interface.start.data.ty(); + let to_decode_fetched_data_ty = to_decode_fetched.data.ty(); + let cache_read_data_ty = CacheReadData[config]; + let mut state = L1ICacheStateSim::new(state_expr); + loop { + state.finish_cache_misses(); + sim.write(from_next_pc.fetch.ready, state.ready_for_fetch().is_some()) + .await; + sim.write( + memory_interface.finish.ready, + state.ready_for_memory_operation_finish().is_some(), + ) + .await; + sim.write( + memory_interface.start.data, + if let Some(v) = state.clone().try_start_memory_operation() { + #[hdl(sim)] + memory_interface_start_data_ty.HdlSome(v) + } else { + #[hdl(sim)] + memory_interface_start_data_ty.HdlNone() + }, + ) + .await; + sim.write( + to_decode_fetched.data, + if let Some(v) = state.clone().to_decode_fetched() { + #[hdl(sim)] + to_decode_fetched_data_ty.HdlSome(v) + } else { + #[hdl(sim)] + to_decode_fetched_data_ty.HdlNone() + }, + ) + .await; + state.write_debug_state(&mut sim).await; + sim.write(max_cancel_in_fetch, state.queue.len()).await; + sim.wait_for_clock_edge(cd.clk).await; + #[hdl(sim)] + if let HdlSome(next_fetch_block_ids) = sim + .read_past(memory_interface.next_fetch_block_ids, cd.clk) + .await + { + state.check_memory_next_fetch_block_ids(next_fetch_block_ids); + } + if sim + .read_past_bool(memory_interface.start.ready, cd.clk) + .await + { + state.try_start_memory_operation(); + } + if sim.read_past_bool(to_decode_fetched.ready, cd.clk).await { + state.to_decode_fetched(); + } + if sim.read_past_bool(i_cache_port.en, cd.clk).await + && !sim.read_past_bool(i_cache_port.wmode, cd.clk).await + { + let addr = sim.read_past(i_cache_port.addr, cd.clk).await; + let cache_line = sim.read_past(i_cache_port.rdata, cd.clk).await; + state.cache_read_data( + #[hdl(sim)] + CacheReadData::<_> { + cache_line_index: addr.cast_to(cache_read_data_ty.cache_line_index), + cache_line, + }, + ); + } + let mut write_back_step = None; + if sim + .read_past_bool(memory_interface.finish.ready, cd.clk) + .await + { + let Some(ready_for_memory_operation_finish) = + state.ready_for_memory_operation_finish() + else { + unreachable!(); + }; + #[hdl(sim)] + if let HdlSome(memory_operation_finish) = + sim.read_past(memory_interface.finish.data, cd.clk).await + { + write_back_step = state.do_memory_operation_finish( + ready_for_memory_operation_finish, + memory_operation_finish, + ); + } + } + // handle cancels before pushing new fetch op + if sim.read_past_bool(from_next_pc.cancel.ready, cd.clk).await { + #[hdl(sim)] + if let HdlSome(in_progress_fetches_to_cancel) = + sim.read_past(from_next_pc.cancel.data, cd.clk).await + { + state.cancel_fetches(*in_progress_fetches_to_cancel); + } + } + if let Some(ready_for_fetch) = state.ready_for_fetch() { + // handle pushing new fetch op after handling cancels + #[hdl(sim)] + if let HdlSome(fetch) = sim.read_past(from_next_pc.fetch.data, cd.clk).await { + state.do_fetch(ready_for_fetch, fetch); + } + } + if let Some(write_back_step) = write_back_step { + #[hdl(sim)] + let WriteBackStep::<_> { + cache_line_index, + data, + mask, + } = write_back_step; + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, cache_line_index.cast_to(addr.ty())).await; + sim.write(en, true).await; + sim.write(wmode, true).await; + sim.write(wdata, data).await; + sim.write(wmask, mask).await; + } else if let Some(cache_read) = state.next_cache_read() { + #[hdl] + let CacheRead::<_> { + cache_line_index, + config: _, + } = cache_read; + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, cache_line_index.cast_to(addr.ty())).await; + sim.write(en, true).await; + sim.write(wmode, false).await; + sim.write(wdata, CacheLine::sim_value_default(wdata.ty())) + .await; + sim.write(wmask, splat_mask(cache_line_ty, false.to_expr())) + .await; + } else { + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, // externally overridden with cd.clk + rdata: _, + wmode, + wdata, + wmask, + } = i_cache_port; + sim.write(addr, 0u8.cast_to(addr.ty())).await; + sim.write(en, false).await; + sim.write(wmode, false).await; + sim.write(wdata, CacheLine::sim_value_default(wdata.ty())) + .await; + sim.write(wmask, splat_mask(cache_line_ty, false.to_expr())) + .await; + } + } + } + m.extern_module_simulation_fn( + ( + cd, + memory_interface, + from_next_pc, + to_decode_fetched, + max_cancel_in_fetch, + i_cache_port, + state_for_debug, + ), + |( + cd, + memory_interface, + from_next_pc, + to_decode_fetched, + max_cancel_in_fetch, + i_cache_port, + state_for_debug, + ), + mut sim| async move { + let config = memory_interface.ty().config; + let cache_line_ty = CacheLine[config]; + sim.write(i_cache_port.clk, false).await; // externally overridden with cd.clk, so just write a constant here + sim.resettable( + cd, + |mut sim: ExternModuleSimulationState| async move { + sim.write( + memory_interface.start.data, + memory_interface.ty().start.data.HdlNone(), + ) + .await; + sim.write(memory_interface.finish.ready, false).await; + sim.write( + from_next_pc.next_fetch_block_ids, + from_next_pc.ty().next_fetch_block_ids.HdlNone(), + ) + .await; + sim.write(from_next_pc.fetch.ready, false).await; + sim.write(from_next_pc.cancel.ready, false).await; + sim.write( + to_decode_fetched.data, + to_decode_fetched.ty().data.HdlNone(), + ) + .await; + sim.write(max_cancel_in_fetch, 0usize).await; + sim.write(i_cache_port.addr, 0u8.cast_to(i_cache_port.addr.ty())) + .await; + sim.write(i_cache_port.en, false).await; + sim.write(i_cache_port.wmode, false).await; + sim.write( + i_cache_port.wdata, + CacheLine::sim_value_default(cache_line_ty), + ) + .await; + sim.write( + i_cache_port.wmask, + splat_mask(cache_line_ty, false.to_expr()), + ) + .await; + sim.write(state_for_debug, state_for_debug.ty().sim_value_default()) + .await; + }, + |sim, ()| { + run( + sim, + cd, + memory_interface, + from_next_pc, + to_decode_fetched, + max_cancel_in_fetch, + i_cache_port, + state_for_debug, + ) + }, + ) + .await; + }, + ); +} + +/// implements a direct-mapped L1 I-Cache +#[hdl_module] +pub fn l1_i_cache(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.output(MemoryInterface[config]); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode: FetchToDecodeInterface> = + m.output(FetchToDecodeInterface[config]); + let cache_line_ty = CacheLine[config]; + let cache_line_count = CpuConfigL1ICacheLineCount[config]; + // TODO: convert to memory with single read/write port once semantics + // for read/write latencies are properly implemented in the simulator: + // https://git.libre-chip.org/libre-chip/fayalite/src/commit/c632e5d570d4763e8e18d764e95b7a9e515ebf99/crates/fayalite/src/sim/compiler.rs#L4774 + // which depends on: + // https://github.com/chipsalliance/firrtl-spec/issues/263 + #[hdl] + let i_cache = reg_builder() + .clock_domain(cd) + .no_reset(ArrayType[cache_line_ty][cache_line_count]); + #[hdl] + let l1_i_cache_impl = instance(l1_i_cache_impl(config)); + connect(l1_i_cache_impl.cd, cd); + connect(memory_interface, l1_i_cache_impl.memory_interface); + connect(l1_i_cache_impl.from_next_pc, from_next_pc); + connect(to_decode.fetched, l1_i_cache_impl.to_decode_fetched); + let to_decode_cancel_ty = to_decode.cancel.ty(); + connect(to_decode.cancel, to_decode_cancel_ty.HdlNone()); + #[hdl] + if from_next_pc.cancel.ready { + #[hdl] + if let HdlSome(cancel) = from_next_pc.cancel.data { + let cancel = cancel.cast_to(UInt[cancel.ty().bit_width()]); + #[hdl] + if cancel.cmp_gt(l1_i_cache_impl.max_cancel_in_fetch) { + connect( + to_decode.cancel, + to_decode_cancel_ty.HdlSome( + (cancel - l1_i_cache_impl.max_cancel_in_fetch.cast_to(cancel.ty())) + .cast_to(to_decode_cancel_ty.HdlSome), + ), + ); + } + } + } + #[hdl] + let ReadWriteStruct::<_, _> { + addr, + en, + clk: _, + rdata, + wmode, + wdata, + wmask, + } = l1_i_cache_impl.i_cache_port; + connect(rdata, rdata.ty().uninit()); + #[hdl] + if en { + let i_cache_line = i_cache[addr]; + #[hdl] + if wmode { + #[hdl] + let CacheLine::<_> { + data: wdata_data, + addr: wdata_addr, + config: _, + } = wdata; + for ((dest, src), mask) in i_cache_line + .data + .into_iter() + .zip(wdata_data) + .zip(wmask.data) + { + for ((dest, src), mask) in dest.into_iter().zip(src).zip(mask) { + #[hdl] + if mask { + connect(dest, src); + } + } + } + #[hdl] + if wmask.addr { + connect(i_cache_line.addr, wdata_addr); + } + } else { + connect(rdata, i_cache_line); + } + } +} + +#[hdl_module] +pub fn fetch(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.output(MemoryInterface[config]); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode: FetchToDecodeInterface> = + m.output(FetchToDecodeInterface[config]); + #[hdl] + let l1_i_cache = instance(l1_i_cache(config)); + connect(l1_i_cache.cd, cd); + connect(memory_interface, l1_i_cache.memory_interface); + connect(l1_i_cache.from_next_pc, from_next_pc); + connect(to_decode, l1_i_cache.to_decode); +} diff --git a/crates/cpu/src/lib.rs b/crates/cpu/src/lib.rs index 7992ec5..62936de 100644 --- a/crates/cpu/src/lib.rs +++ b/crates/cpu/src/lib.rs @@ -2,6 +2,7 @@ // See Notices.txt for copyright information pub mod config; pub mod decoder; +pub mod fetch; pub mod instruction; pub mod next_pc; pub mod powerisa_instructions_xml; diff --git a/crates/cpu/src/next_pc.rs b/crates/cpu/src/next_pc.rs index db22f7e..379dbfd 100644 --- a/crates/cpu/src/next_pc.rs +++ b/crates/cpu/src/next_pc.rs @@ -2719,13 +2719,13 @@ impl SimValueDefault for BranchPredictionState { #[derive(Copy, Clone, Debug)] #[must_use] -enum ResetStatus { +pub(crate) enum ResetStatus { Done, Working, } impl ResetStatus { - fn and(self, other: Self) -> Self { + pub(crate) fn and(self, other: Self) -> Self { match (self, other) { (ResetStatus::Done, ResetStatus::Done) => ResetStatus::Done, (ResetStatus::Done | ResetStatus::Working, ResetStatus::Working) @@ -2734,7 +2734,7 @@ impl ResetStatus { } } -trait SimValueDefault: Type { +pub(crate) trait SimValueDefault: Type { fn sim_value_default(self) -> SimValue; } @@ -2828,7 +2828,7 @@ impl SimValueDefault for WipDecodedInsn { } } -trait ResetSteps: Type { +pub(crate) trait ResetSteps: Type { fn reset_step(this: &mut SimValue, step: usize) -> ResetStatus; } diff --git a/crates/cpu/src/util/array_vec.rs b/crates/cpu/src/util/array_vec.rs index 71275b1..b4ac8f0 100644 --- a/crates/cpu/src/util/array_vec.rs +++ b/crates/cpu/src/util/array_vec.rs @@ -2,6 +2,24 @@ // See Notices.txt for copyright information use fayalite::{expr::ops::ExprIndex, int::UIntInRangeInclusiveType, prelude::*}; +use std::fmt; + +#[derive(Clone, Debug)] +pub struct ArrayVecFullError { + pub value: V, + pub rest: std::iter::Chain, I>, +} + +impl fmt::Display for ArrayVecFullError { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "ArrayVec is full") + } +} + +impl + fmt::Debug> std::error::Error + for ArrayVecFullError +{ +} #[hdl] pub type Length = UIntInRangeInclusiveType, Max>; @@ -46,6 +64,30 @@ impl ArrayVec { len: self.elements.len().to_sim_value_with_type(self.len), } } + pub fn from_iter_sim>>( + self, + uninit_element: impl ToSimValueWithType, + iter: I, + ) -> Result, ArrayVecFullError, I::IntoIter>> { + let mut value = Self::new_sim(self, uninit_element); + let element = self.element(); + let mut iter = iter.into_iter(); + for i in 0..self.capacity() { + let Some(v) = iter.next() else { + break; + }; + value.elements[i] = v.into_sim_value_with_type(element); + *value.len = i + 1; + } + if let Some(extra) = iter.next() { + Err(ArrayVecFullError { + value, + rest: std::iter::once(extra).chain(iter), + }) + } else { + Ok(value) + } + } pub fn element(self) -> T { self.elements.element() } diff --git a/crates/cpu/tests/expected/fetch.vcd b/crates/cpu/tests/expected/fetch.vcd new file mode 100644 index 0000000..c435d7a --- /dev/null +++ b/crates/cpu/tests/expected/fetch.vcd @@ -0,0 +1,16294 @@ +$timescale 1 ps $end +$scope module dut $end +$scope struct cd $end +$var wire 1 ! clk $end +$var wire 1 " rst $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 # \$tag $end +$scope struct HdlSome $end +$var wire 64 $ start_pc $end +$var wire 8 % fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 & ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 ' \$tag $end +$scope struct HdlSome $end +$var wire 5 ( value $end +$var string 1 ) range $end +$upscope $end +$upscope $end +$var wire 1 * ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 + \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 , \[0] $end +$var wire 8 - \[1] $end +$var wire 8 . \[2] $end +$var wire 8 / \[3] $end +$var wire 8 0 \[4] $end +$var wire 8 1 \[5] $end +$var wire 8 2 \[6] $end +$var wire 8 3 \[7] $end +$var wire 8 4 \[8] $end +$var wire 8 5 \[9] $end +$var wire 8 6 \[10] $end +$var wire 8 7 \[11] $end +$var wire 8 8 \[12] $end +$var wire 8 9 \[13] $end +$var wire 8 : \[14] $end +$var wire 8 ; \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 < value $end +$var string 1 = range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 > config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 ? \$tag $end +$scope struct HdlSome $end +$var wire 64 @ start_pc $end +$var wire 8 A fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 B \[0] $end +$var wire 8 C \[1] $end +$var wire 8 D \[2] $end +$var wire 8 E \[3] $end +$var wire 8 F \[4] $end +$var wire 8 G \[5] $end +$var wire 8 H \[6] $end +$var wire 8 I \[7] $end +$upscope $end +$scope struct error $end +$var string 1 J \$tag $end +$var string 1 K HdlSome $end +$upscope $end +$var string 1 L config $end +$upscope $end +$upscope $end +$var wire 1 M ready $end +$upscope $end +$scope struct cancel $end +$var string 1 N \$tag $end +$scope struct HdlSome $end +$var wire 5 O value $end +$var string 1 P range $end +$upscope $end +$upscope $end +$upscope $end +$scope struct fetch $end +$scope struct cd $end +$var wire 1 14 clk $end +$var wire 1 24 rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 34 \$tag $end +$scope struct HdlSome $end +$var string 1 44 kind $end +$var wire 64 54 addr $end +$scope struct write_data $end +$var wire 8 64 \[0] $end +$var wire 8 74 \[1] $end +$var wire 8 84 \[2] $end +$var wire 8 94 \[3] $end +$var wire 8 :4 \[4] $end +$var wire 8 ;4 \[5] $end +$var wire 8 <4 \[6] $end +$var wire 8 =4 \[7] $end +$upscope $end +$var wire 8 >4 fetch_block_id $end +$var string 1 ?4 config $end +$upscope $end +$upscope $end +$var wire 1 @4 ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 A4 \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 B4 \$tag $end +$var string 1 C4 Success $end +$var string 1 D4 Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 E4 \[0] $end +$var wire 8 F4 \[1] $end +$var wire 8 G4 \[2] $end +$var wire 8 H4 \[3] $end +$var wire 8 I4 \[4] $end +$var wire 8 J4 \[5] $end +$var wire 8 K4 \[6] $end +$var wire 8 L4 \[7] $end +$upscope $end +$var string 1 M4 config $end +$upscope $end +$upscope $end +$var wire 1 N4 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 O4 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 P4 \[0] $end +$var wire 8 Q4 \[1] $end +$var wire 8 R4 \[2] $end +$var wire 8 S4 \[3] $end +$var wire 8 T4 \[4] $end +$var wire 8 U4 \[5] $end +$var wire 8 V4 \[6] $end +$var wire 8 W4 \[7] $end +$var wire 8 X4 \[8] $end +$var wire 8 Y4 \[9] $end +$var wire 8 Z4 \[10] $end +$var wire 8 [4 \[11] $end +$var wire 8 \4 \[12] $end +$var wire 8 ]4 \[13] $end +$var wire 8 ^4 \[14] $end +$var wire 8 _4 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 `4 value $end +$var string 1 a4 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 b4 config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 c4 \$tag $end +$scope struct HdlSome $end +$var wire 64 d4 start_pc $end +$var wire 8 e4 fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 f4 ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 g4 \$tag $end +$scope struct HdlSome $end +$var wire 5 h4 value $end +$var string 1 i4 range $end +$upscope $end +$upscope $end +$var wire 1 j4 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 k4 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 l4 \[0] $end +$var wire 8 m4 \[1] $end +$var wire 8 n4 \[2] $end +$var wire 8 o4 \[3] $end +$var wire 8 p4 \[4] $end +$var wire 8 q4 \[5] $end +$var wire 8 r4 \[6] $end +$var wire 8 s4 \[7] $end +$var wire 8 t4 \[8] $end +$var wire 8 u4 \[9] $end +$var wire 8 v4 \[10] $end +$var wire 8 w4 \[11] $end +$var wire 8 x4 \[12] $end +$var wire 8 y4 \[13] $end +$var wire 8 z4 \[14] $end +$var wire 8 {4 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 |4 value $end +$var string 1 }4 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 ~4 config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 !5 \$tag $end +$scope struct HdlSome $end +$var wire 64 "5 start_pc $end +$var wire 8 #5 fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 $5 \[0] $end +$var wire 8 %5 \[1] $end +$var wire 8 &5 \[2] $end +$var wire 8 '5 \[3] $end +$var wire 8 (5 \[4] $end +$var wire 8 )5 \[5] $end +$var wire 8 *5 \[6] $end +$var wire 8 +5 \[7] $end +$upscope $end +$scope struct error $end +$var string 1 ,5 \$tag $end +$var string 1 -5 HdlSome $end +$upscope $end +$var string 1 .5 config $end +$upscope $end +$upscope $end +$var wire 1 /5 ready $end +$upscope $end +$scope struct cancel $end +$var string 1 05 \$tag $end +$scope struct HdlSome $end +$var wire 5 15 value $end +$var string 1 25 range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module fetch_2 $end +$scope struct cd $end +$var wire 1 Q clk $end +$var wire 1 R rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 S \$tag $end +$scope struct HdlSome $end +$var string 1 T kind $end +$var wire 64 U addr $end +$scope struct write_data $end +$var wire 8 V \[0] $end +$var wire 8 W \[1] $end +$var wire 8 X \[2] $end +$var wire 8 Y \[3] $end +$var wire 8 Z \[4] $end +$var wire 8 [ \[5] $end +$var wire 8 \ \[6] $end +$var wire 8 ] \[7] $end +$upscope $end +$var wire 8 ^ fetch_block_id $end +$var string 1 _ config $end +$upscope $end +$upscope $end +$var wire 1 ` ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 a \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 b \$tag $end +$var string 1 c Success $end +$var string 1 d Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 e \[0] $end +$var wire 8 f \[1] $end +$var wire 8 g \[2] $end +$var wire 8 h \[3] $end +$var wire 8 i \[4] $end +$var wire 8 j \[5] $end +$var wire 8 k \[6] $end +$var wire 8 l \[7] $end +$upscope $end +$var string 1 m config $end +$upscope $end +$upscope $end +$var wire 1 n ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 o \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 p \[0] $end +$var wire 8 q \[1] $end +$var wire 8 r \[2] $end +$var wire 8 s \[3] $end +$var wire 8 t \[4] $end +$var wire 8 u \[5] $end +$var wire 8 v \[6] $end +$var wire 8 w \[7] $end +$var wire 8 x \[8] $end +$var wire 8 y \[9] $end +$var wire 8 z \[10] $end +$var wire 8 { \[11] $end +$var wire 8 | \[12] $end +$var wire 8 } \[13] $end +$var wire 8 ~ \[14] $end +$var wire 8 !" \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 "" value $end +$var string 1 #" range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 $" config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 %" \$tag $end +$scope struct HdlSome $end +$var wire 64 &" start_pc $end +$var wire 8 '" fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 (" ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 )" \$tag $end +$scope struct HdlSome $end +$var wire 5 *" value $end +$var string 1 +" range $end +$upscope $end +$upscope $end +$var wire 1 ," ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 -" \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 ." \[0] $end +$var wire 8 /" \[1] $end +$var wire 8 0" \[2] $end +$var wire 8 1" \[3] $end +$var wire 8 2" \[4] $end +$var wire 8 3" \[5] $end +$var wire 8 4" \[6] $end +$var wire 8 5" \[7] $end +$var wire 8 6" \[8] $end +$var wire 8 7" \[9] $end +$var wire 8 8" \[10] $end +$var wire 8 9" \[11] $end +$var wire 8 :" \[12] $end +$var wire 8 ;" \[13] $end +$var wire 8 <" \[14] $end +$var wire 8 =" \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 >" value $end +$var string 1 ?" range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 @" config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 A" \$tag $end +$scope struct HdlSome $end +$var wire 64 B" start_pc $end +$var wire 8 C" fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 D" \[0] $end +$var wire 8 E" \[1] $end +$var wire 8 F" \[2] $end +$var wire 8 G" \[3] $end +$var wire 8 H" \[4] $end +$var wire 8 I" \[5] $end +$var wire 8 J" \[6] $end +$var wire 8 K" \[7] $end +$upscope $end +$scope struct error $end +$var string 1 L" \$tag $end +$var string 1 M" HdlSome $end +$upscope $end +$var string 1 N" config $end +$upscope $end +$upscope $end +$var wire 1 O" ready $end +$upscope $end +$scope struct cancel $end +$var string 1 P" \$tag $end +$scope struct HdlSome $end +$var wire 5 Q" value $end +$var string 1 R" range $end +$upscope $end +$upscope $end +$upscope $end +$scope struct l1_i_cache $end +$scope struct cd $end +$var wire 1 /3 clk $end +$var wire 1 03 rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 13 \$tag $end +$scope struct HdlSome $end +$var string 1 23 kind $end +$var wire 64 33 addr $end +$scope struct write_data $end +$var wire 8 43 \[0] $end +$var wire 8 53 \[1] $end +$var wire 8 63 \[2] $end +$var wire 8 73 \[3] $end +$var wire 8 83 \[4] $end +$var wire 8 93 \[5] $end +$var wire 8 :3 \[6] $end +$var wire 8 ;3 \[7] $end +$upscope $end +$var wire 8 <3 fetch_block_id $end +$var string 1 =3 config $end +$upscope $end +$upscope $end +$var wire 1 >3 ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 ?3 \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 @3 \$tag $end +$var string 1 A3 Success $end +$var string 1 B3 Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 C3 \[0] $end +$var wire 8 D3 \[1] $end +$var wire 8 E3 \[2] $end +$var wire 8 F3 \[3] $end +$var wire 8 G3 \[4] $end +$var wire 8 H3 \[5] $end +$var wire 8 I3 \[6] $end +$var wire 8 J3 \[7] $end +$upscope $end +$var string 1 K3 config $end +$upscope $end +$upscope $end +$var wire 1 L3 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 M3 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 N3 \[0] $end +$var wire 8 O3 \[1] $end +$var wire 8 P3 \[2] $end +$var wire 8 Q3 \[3] $end +$var wire 8 R3 \[4] $end +$var wire 8 S3 \[5] $end +$var wire 8 T3 \[6] $end +$var wire 8 U3 \[7] $end +$var wire 8 V3 \[8] $end +$var wire 8 W3 \[9] $end +$var wire 8 X3 \[10] $end +$var wire 8 Y3 \[11] $end +$var wire 8 Z3 \[12] $end +$var wire 8 [3 \[13] $end +$var wire 8 \3 \[14] $end +$var wire 8 ]3 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 ^3 value $end +$var string 1 _3 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 `3 config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 a3 \$tag $end +$scope struct HdlSome $end +$var wire 64 b3 start_pc $end +$var wire 8 c3 fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 d3 ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 e3 \$tag $end +$scope struct HdlSome $end +$var wire 5 f3 value $end +$var string 1 g3 range $end +$upscope $end +$upscope $end +$var wire 1 h3 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 i3 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 j3 \[0] $end +$var wire 8 k3 \[1] $end +$var wire 8 l3 \[2] $end +$var wire 8 m3 \[3] $end +$var wire 8 n3 \[4] $end +$var wire 8 o3 \[5] $end +$var wire 8 p3 \[6] $end +$var wire 8 q3 \[7] $end +$var wire 8 r3 \[8] $end +$var wire 8 s3 \[9] $end +$var wire 8 t3 \[10] $end +$var wire 8 u3 \[11] $end +$var wire 8 v3 \[12] $end +$var wire 8 w3 \[13] $end +$var wire 8 x3 \[14] $end +$var wire 8 y3 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 z3 value $end +$var string 1 {3 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 |3 config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 }3 \$tag $end +$scope struct HdlSome $end +$var wire 64 ~3 start_pc $end +$var wire 8 !4 fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 "4 \[0] $end +$var wire 8 #4 \[1] $end +$var wire 8 $4 \[2] $end +$var wire 8 %4 \[3] $end +$var wire 8 &4 \[4] $end +$var wire 8 '4 \[5] $end +$var wire 8 (4 \[6] $end +$var wire 8 )4 \[7] $end +$upscope $end +$scope struct error $end +$var string 1 *4 \$tag $end +$var string 1 +4 HdlSome $end +$upscope $end +$var string 1 ,4 config $end +$upscope $end +$upscope $end +$var wire 1 -4 ready $end +$upscope $end +$scope struct cancel $end +$var string 1 .4 \$tag $end +$scope struct HdlSome $end +$var wire 5 /4 value $end +$var string 1 04 range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module l1_i_cache_2 $end +$scope struct cd $end +$var wire 1 S" clk $end +$var wire 1 T" rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 U" \$tag $end +$scope struct HdlSome $end +$var string 1 V" kind $end +$var wire 64 W" addr $end +$scope struct write_data $end +$var wire 8 X" \[0] $end +$var wire 8 Y" \[1] $end +$var wire 8 Z" \[2] $end +$var wire 8 [" \[3] $end +$var wire 8 \" \[4] $end +$var wire 8 ]" \[5] $end +$var wire 8 ^" \[6] $end +$var wire 8 _" \[7] $end +$upscope $end +$var wire 8 `" fetch_block_id $end +$var string 1 a" config $end +$upscope $end +$upscope $end +$var wire 1 b" ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 c" \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 d" \$tag $end +$var string 1 e" Success $end +$var string 1 f" Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 g" \[0] $end +$var wire 8 h" \[1] $end +$var wire 8 i" \[2] $end +$var wire 8 j" \[3] $end +$var wire 8 k" \[4] $end +$var wire 8 l" \[5] $end +$var wire 8 m" \[6] $end +$var wire 8 n" \[7] $end +$upscope $end +$var string 1 o" config $end +$upscope $end +$upscope $end +$var wire 1 p" ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 q" \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 r" \[0] $end +$var wire 8 s" \[1] $end +$var wire 8 t" \[2] $end +$var wire 8 u" \[3] $end +$var wire 8 v" \[4] $end +$var wire 8 w" \[5] $end +$var wire 8 x" \[6] $end +$var wire 8 y" \[7] $end +$var wire 8 z" \[8] $end +$var wire 8 {" \[9] $end +$var wire 8 |" \[10] $end +$var wire 8 }" \[11] $end +$var wire 8 ~" \[12] $end +$var wire 8 !# \[13] $end +$var wire 8 "# \[14] $end +$var wire 8 ## \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 $# value $end +$var string 1 %# range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 &# config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 '# \$tag $end +$scope struct HdlSome $end +$var wire 64 (# start_pc $end +$var wire 8 )# fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 *# ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 +# \$tag $end +$scope struct HdlSome $end +$var wire 5 ,# value $end +$var string 1 -# range $end +$upscope $end +$upscope $end +$var wire 1 .# ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 /# \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 0# \[0] $end +$var wire 8 1# \[1] $end +$var wire 8 2# \[2] $end +$var wire 8 3# \[3] $end +$var wire 8 4# \[4] $end +$var wire 8 5# \[5] $end +$var wire 8 6# \[6] $end +$var wire 8 7# \[7] $end +$var wire 8 8# \[8] $end +$var wire 8 9# \[9] $end +$var wire 8 :# \[10] $end +$var wire 8 ;# \[11] $end +$var wire 8 <# \[12] $end +$var wire 8 =# \[13] $end +$var wire 8 ># \[14] $end +$var wire 8 ?# \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 @# value $end +$var string 1 A# range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 B# config $end +$upscope $end +$scope struct to_decode $end +$scope struct fetched $end +$scope struct data $end +$var string 1 C# \$tag $end +$scope struct HdlSome $end +$var wire 64 D# start_pc $end +$var wire 8 E# fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 F# \[0] $end +$var wire 8 G# \[1] $end +$var wire 8 H# \[2] $end +$var wire 8 I# \[3] $end +$var wire 8 J# \[4] $end +$var wire 8 K# \[5] $end +$var wire 8 L# \[6] $end +$var wire 8 M# \[7] $end +$upscope $end +$scope struct error $end +$var string 1 N# \$tag $end +$var string 1 O# HdlSome $end +$upscope $end +$var string 1 P# config $end +$upscope $end +$upscope $end +$var wire 1 Q# ready $end +$upscope $end +$scope struct cancel $end +$var string 1 R# \$tag $end +$scope struct HdlSome $end +$var wire 5 S# value $end +$var string 1 T# range $end +$upscope $end +$upscope $end +$upscope $end +$scope struct i_cache $end +$scope struct \[0] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 U# \[0] $end +$var reg 8 V# \[1] $end +$var reg 8 W# \[2] $end +$var reg 8 X# \[3] $end +$var reg 8 Y# \[4] $end +$var reg 8 Z# \[5] $end +$var reg 8 [# \[6] $end +$var reg 8 \# \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 ]# \[0] $end +$var reg 8 ^# \[1] $end +$var reg 8 _# \[2] $end +$var reg 8 `# \[3] $end +$var reg 8 a# \[4] $end +$var reg 8 b# \[5] $end +$var reg 8 c# \[6] $end +$var reg 8 d# \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 e# \[0] $end +$var reg 8 f# \[1] $end +$var reg 8 g# \[2] $end +$var reg 8 h# \[3] $end +$var reg 8 i# \[4] $end +$var reg 8 j# \[5] $end +$var reg 8 k# \[6] $end +$var reg 8 l# \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 m# \[0] $end +$var reg 8 n# \[1] $end +$var reg 8 o# \[2] $end +$var reg 8 p# \[3] $end +$var reg 8 q# \[4] $end +$var reg 8 r# \[5] $end +$var reg 8 s# \[6] $end +$var reg 8 t# \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 u# \$tag $end +$var reg 55 v# HdlSome $end +$upscope $end +$var string 1 w# config $end +$upscope $end +$scope struct \[1] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 x# \[0] $end +$var reg 8 y# \[1] $end +$var reg 8 z# \[2] $end +$var reg 8 {# \[3] $end +$var reg 8 |# \[4] $end +$var reg 8 }# \[5] $end +$var reg 8 ~# \[6] $end +$var reg 8 !$ \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 "$ \[0] $end +$var reg 8 #$ \[1] $end +$var reg 8 $$ \[2] $end +$var reg 8 %$ \[3] $end +$var reg 8 &$ \[4] $end +$var reg 8 '$ \[5] $end +$var reg 8 ($ \[6] $end +$var reg 8 )$ \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 *$ \[0] $end +$var reg 8 +$ \[1] $end +$var reg 8 ,$ \[2] $end +$var reg 8 -$ \[3] $end +$var reg 8 .$ \[4] $end +$var reg 8 /$ \[5] $end +$var reg 8 0$ \[6] $end +$var reg 8 1$ \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 2$ \[0] $end +$var reg 8 3$ \[1] $end +$var reg 8 4$ \[2] $end +$var reg 8 5$ \[3] $end +$var reg 8 6$ \[4] $end +$var reg 8 7$ \[5] $end +$var reg 8 8$ \[6] $end +$var reg 8 9$ \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 :$ \$tag $end +$var reg 55 ;$ HdlSome $end +$upscope $end +$var string 1 <$ config $end +$upscope $end +$scope struct \[2] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 =$ \[0] $end +$var reg 8 >$ \[1] $end +$var reg 8 ?$ \[2] $end +$var reg 8 @$ \[3] $end +$var reg 8 A$ \[4] $end +$var reg 8 B$ \[5] $end +$var reg 8 C$ \[6] $end +$var reg 8 D$ \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 E$ \[0] $end +$var reg 8 F$ \[1] $end +$var reg 8 G$ \[2] $end +$var reg 8 H$ \[3] $end +$var reg 8 I$ \[4] $end +$var reg 8 J$ \[5] $end +$var reg 8 K$ \[6] $end +$var reg 8 L$ \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 M$ \[0] $end +$var reg 8 N$ \[1] $end +$var reg 8 O$ \[2] $end +$var reg 8 P$ \[3] $end +$var reg 8 Q$ \[4] $end +$var reg 8 R$ \[5] $end +$var reg 8 S$ \[6] $end +$var reg 8 T$ \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 U$ \[0] $end +$var reg 8 V$ \[1] $end +$var reg 8 W$ \[2] $end +$var reg 8 X$ \[3] $end +$var reg 8 Y$ \[4] $end +$var reg 8 Z$ \[5] $end +$var reg 8 [$ \[6] $end +$var reg 8 \$ \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 ]$ \$tag $end +$var reg 55 ^$ HdlSome $end +$upscope $end +$var string 1 _$ config $end +$upscope $end +$scope struct \[3] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 `$ \[0] $end +$var reg 8 a$ \[1] $end +$var reg 8 b$ \[2] $end +$var reg 8 c$ \[3] $end +$var reg 8 d$ \[4] $end +$var reg 8 e$ \[5] $end +$var reg 8 f$ \[6] $end +$var reg 8 g$ \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 h$ \[0] $end +$var reg 8 i$ \[1] $end +$var reg 8 j$ \[2] $end +$var reg 8 k$ \[3] $end +$var reg 8 l$ \[4] $end +$var reg 8 m$ \[5] $end +$var reg 8 n$ \[6] $end +$var reg 8 o$ \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 p$ \[0] $end +$var reg 8 q$ \[1] $end +$var reg 8 r$ \[2] $end +$var reg 8 s$ \[3] $end +$var reg 8 t$ \[4] $end +$var reg 8 u$ \[5] $end +$var reg 8 v$ \[6] $end +$var reg 8 w$ \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 x$ \[0] $end +$var reg 8 y$ \[1] $end +$var reg 8 z$ \[2] $end +$var reg 8 {$ \[3] $end +$var reg 8 |$ \[4] $end +$var reg 8 }$ \[5] $end +$var reg 8 ~$ \[6] $end +$var reg 8 !% \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 "% \$tag $end +$var reg 55 #% HdlSome $end +$upscope $end +$var string 1 $% config $end +$upscope $end +$scope struct \[4] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 %% \[0] $end +$var reg 8 &% \[1] $end +$var reg 8 '% \[2] $end +$var reg 8 (% \[3] $end +$var reg 8 )% \[4] $end +$var reg 8 *% \[5] $end +$var reg 8 +% \[6] $end +$var reg 8 ,% \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 -% \[0] $end +$var reg 8 .% \[1] $end +$var reg 8 /% \[2] $end +$var reg 8 0% \[3] $end +$var reg 8 1% \[4] $end +$var reg 8 2% \[5] $end +$var reg 8 3% \[6] $end +$var reg 8 4% \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 5% \[0] $end +$var reg 8 6% \[1] $end +$var reg 8 7% \[2] $end +$var reg 8 8% \[3] $end +$var reg 8 9% \[4] $end +$var reg 8 :% \[5] $end +$var reg 8 ;% \[6] $end +$var reg 8 <% \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 =% \[0] $end +$var reg 8 >% \[1] $end +$var reg 8 ?% \[2] $end +$var reg 8 @% \[3] $end +$var reg 8 A% \[4] $end +$var reg 8 B% \[5] $end +$var reg 8 C% \[6] $end +$var reg 8 D% \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 E% \$tag $end +$var reg 55 F% HdlSome $end +$upscope $end +$var string 1 G% config $end +$upscope $end +$scope struct \[5] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 H% \[0] $end +$var reg 8 I% \[1] $end +$var reg 8 J% \[2] $end +$var reg 8 K% \[3] $end +$var reg 8 L% \[4] $end +$var reg 8 M% \[5] $end +$var reg 8 N% \[6] $end +$var reg 8 O% \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 P% \[0] $end +$var reg 8 Q% \[1] $end +$var reg 8 R% \[2] $end +$var reg 8 S% \[3] $end +$var reg 8 T% \[4] $end +$var reg 8 U% \[5] $end +$var reg 8 V% \[6] $end +$var reg 8 W% \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 X% \[0] $end +$var reg 8 Y% \[1] $end +$var reg 8 Z% \[2] $end +$var reg 8 [% \[3] $end +$var reg 8 \% \[4] $end +$var reg 8 ]% \[5] $end +$var reg 8 ^% \[6] $end +$var reg 8 _% \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 `% \[0] $end +$var reg 8 a% \[1] $end +$var reg 8 b% \[2] $end +$var reg 8 c% \[3] $end +$var reg 8 d% \[4] $end +$var reg 8 e% \[5] $end +$var reg 8 f% \[6] $end +$var reg 8 g% \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 h% \$tag $end +$var reg 55 i% HdlSome $end +$upscope $end +$var string 1 j% config $end +$upscope $end +$scope struct \[6] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 k% \[0] $end +$var reg 8 l% \[1] $end +$var reg 8 m% \[2] $end +$var reg 8 n% \[3] $end +$var reg 8 o% \[4] $end +$var reg 8 p% \[5] $end +$var reg 8 q% \[6] $end +$var reg 8 r% \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 s% \[0] $end +$var reg 8 t% \[1] $end +$var reg 8 u% \[2] $end +$var reg 8 v% \[3] $end +$var reg 8 w% \[4] $end +$var reg 8 x% \[5] $end +$var reg 8 y% \[6] $end +$var reg 8 z% \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 {% \[0] $end +$var reg 8 |% \[1] $end +$var reg 8 }% \[2] $end +$var reg 8 ~% \[3] $end +$var reg 8 !& \[4] $end +$var reg 8 "& \[5] $end +$var reg 8 #& \[6] $end +$var reg 8 $& \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 %& \[0] $end +$var reg 8 && \[1] $end +$var reg 8 '& \[2] $end +$var reg 8 (& \[3] $end +$var reg 8 )& \[4] $end +$var reg 8 *& \[5] $end +$var reg 8 +& \[6] $end +$var reg 8 ,& \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 -& \$tag $end +$var reg 55 .& HdlSome $end +$upscope $end +$var string 1 /& config $end +$upscope $end +$scope struct \[7] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 0& \[0] $end +$var reg 8 1& \[1] $end +$var reg 8 2& \[2] $end +$var reg 8 3& \[3] $end +$var reg 8 4& \[4] $end +$var reg 8 5& \[5] $end +$var reg 8 6& \[6] $end +$var reg 8 7& \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 8& \[0] $end +$var reg 8 9& \[1] $end +$var reg 8 :& \[2] $end +$var reg 8 ;& \[3] $end +$var reg 8 <& \[4] $end +$var reg 8 =& \[5] $end +$var reg 8 >& \[6] $end +$var reg 8 ?& \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 @& \[0] $end +$var reg 8 A& \[1] $end +$var reg 8 B& \[2] $end +$var reg 8 C& \[3] $end +$var reg 8 D& \[4] $end +$var reg 8 E& \[5] $end +$var reg 8 F& \[6] $end +$var reg 8 G& \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 H& \[0] $end +$var reg 8 I& \[1] $end +$var reg 8 J& \[2] $end +$var reg 8 K& \[3] $end +$var reg 8 L& \[4] $end +$var reg 8 M& \[5] $end +$var reg 8 N& \[6] $end +$var reg 8 O& \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 P& \$tag $end +$var reg 55 Q& HdlSome $end +$upscope $end +$var string 1 R& config $end +$upscope $end +$scope struct \[8] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 S& \[0] $end +$var reg 8 T& \[1] $end +$var reg 8 U& \[2] $end +$var reg 8 V& \[3] $end +$var reg 8 W& \[4] $end +$var reg 8 X& \[5] $end +$var reg 8 Y& \[6] $end +$var reg 8 Z& \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 [& \[0] $end +$var reg 8 \& \[1] $end +$var reg 8 ]& \[2] $end +$var reg 8 ^& \[3] $end +$var reg 8 _& \[4] $end +$var reg 8 `& \[5] $end +$var reg 8 a& \[6] $end +$var reg 8 b& \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 c& \[0] $end +$var reg 8 d& \[1] $end +$var reg 8 e& \[2] $end +$var reg 8 f& \[3] $end +$var reg 8 g& \[4] $end +$var reg 8 h& \[5] $end +$var reg 8 i& \[6] $end +$var reg 8 j& \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 k& \[0] $end +$var reg 8 l& \[1] $end +$var reg 8 m& \[2] $end +$var reg 8 n& \[3] $end +$var reg 8 o& \[4] $end +$var reg 8 p& \[5] $end +$var reg 8 q& \[6] $end +$var reg 8 r& \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 s& \$tag $end +$var reg 55 t& HdlSome $end +$upscope $end +$var string 1 u& config $end +$upscope $end +$scope struct \[9] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 v& \[0] $end +$var reg 8 w& \[1] $end +$var reg 8 x& \[2] $end +$var reg 8 y& \[3] $end +$var reg 8 z& \[4] $end +$var reg 8 {& \[5] $end +$var reg 8 |& \[6] $end +$var reg 8 }& \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 ~& \[0] $end +$var reg 8 !' \[1] $end +$var reg 8 "' \[2] $end +$var reg 8 #' \[3] $end +$var reg 8 $' \[4] $end +$var reg 8 %' \[5] $end +$var reg 8 &' \[6] $end +$var reg 8 '' \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 (' \[0] $end +$var reg 8 )' \[1] $end +$var reg 8 *' \[2] $end +$var reg 8 +' \[3] $end +$var reg 8 ,' \[4] $end +$var reg 8 -' \[5] $end +$var reg 8 .' \[6] $end +$var reg 8 /' \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 0' \[0] $end +$var reg 8 1' \[1] $end +$var reg 8 2' \[2] $end +$var reg 8 3' \[3] $end +$var reg 8 4' \[4] $end +$var reg 8 5' \[5] $end +$var reg 8 6' \[6] $end +$var reg 8 7' \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 8' \$tag $end +$var reg 55 9' HdlSome $end +$upscope $end +$var string 1 :' config $end +$upscope $end +$scope struct \[10] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 ;' \[0] $end +$var reg 8 <' \[1] $end +$var reg 8 =' \[2] $end +$var reg 8 >' \[3] $end +$var reg 8 ?' \[4] $end +$var reg 8 @' \[5] $end +$var reg 8 A' \[6] $end +$var reg 8 B' \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 C' \[0] $end +$var reg 8 D' \[1] $end +$var reg 8 E' \[2] $end +$var reg 8 F' \[3] $end +$var reg 8 G' \[4] $end +$var reg 8 H' \[5] $end +$var reg 8 I' \[6] $end +$var reg 8 J' \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 K' \[0] $end +$var reg 8 L' \[1] $end +$var reg 8 M' \[2] $end +$var reg 8 N' \[3] $end +$var reg 8 O' \[4] $end +$var reg 8 P' \[5] $end +$var reg 8 Q' \[6] $end +$var reg 8 R' \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 S' \[0] $end +$var reg 8 T' \[1] $end +$var reg 8 U' \[2] $end +$var reg 8 V' \[3] $end +$var reg 8 W' \[4] $end +$var reg 8 X' \[5] $end +$var reg 8 Y' \[6] $end +$var reg 8 Z' \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 [' \$tag $end +$var reg 55 \' HdlSome $end +$upscope $end +$var string 1 ]' config $end +$upscope $end +$scope struct \[11] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 ^' \[0] $end +$var reg 8 _' \[1] $end +$var reg 8 `' \[2] $end +$var reg 8 a' \[3] $end +$var reg 8 b' \[4] $end +$var reg 8 c' \[5] $end +$var reg 8 d' \[6] $end +$var reg 8 e' \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 f' \[0] $end +$var reg 8 g' \[1] $end +$var reg 8 h' \[2] $end +$var reg 8 i' \[3] $end +$var reg 8 j' \[4] $end +$var reg 8 k' \[5] $end +$var reg 8 l' \[6] $end +$var reg 8 m' \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 n' \[0] $end +$var reg 8 o' \[1] $end +$var reg 8 p' \[2] $end +$var reg 8 q' \[3] $end +$var reg 8 r' \[4] $end +$var reg 8 s' \[5] $end +$var reg 8 t' \[6] $end +$var reg 8 u' \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 v' \[0] $end +$var reg 8 w' \[1] $end +$var reg 8 x' \[2] $end +$var reg 8 y' \[3] $end +$var reg 8 z' \[4] $end +$var reg 8 {' \[5] $end +$var reg 8 |' \[6] $end +$var reg 8 }' \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 ~' \$tag $end +$var reg 55 !( HdlSome $end +$upscope $end +$var string 1 "( config $end +$upscope $end +$scope struct \[12] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 #( \[0] $end +$var reg 8 $( \[1] $end +$var reg 8 %( \[2] $end +$var reg 8 &( \[3] $end +$var reg 8 '( \[4] $end +$var reg 8 (( \[5] $end +$var reg 8 )( \[6] $end +$var reg 8 *( \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 +( \[0] $end +$var reg 8 ,( \[1] $end +$var reg 8 -( \[2] $end +$var reg 8 .( \[3] $end +$var reg 8 /( \[4] $end +$var reg 8 0( \[5] $end +$var reg 8 1( \[6] $end +$var reg 8 2( \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 3( \[0] $end +$var reg 8 4( \[1] $end +$var reg 8 5( \[2] $end +$var reg 8 6( \[3] $end +$var reg 8 7( \[4] $end +$var reg 8 8( \[5] $end +$var reg 8 9( \[6] $end +$var reg 8 :( \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 ;( \[0] $end +$var reg 8 <( \[1] $end +$var reg 8 =( \[2] $end +$var reg 8 >( \[3] $end +$var reg 8 ?( \[4] $end +$var reg 8 @( \[5] $end +$var reg 8 A( \[6] $end +$var reg 8 B( \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 C( \$tag $end +$var reg 55 D( HdlSome $end +$upscope $end +$var string 1 E( config $end +$upscope $end +$scope struct \[13] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 F( \[0] $end +$var reg 8 G( \[1] $end +$var reg 8 H( \[2] $end +$var reg 8 I( \[3] $end +$var reg 8 J( \[4] $end +$var reg 8 K( \[5] $end +$var reg 8 L( \[6] $end +$var reg 8 M( \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 N( \[0] $end +$var reg 8 O( \[1] $end +$var reg 8 P( \[2] $end +$var reg 8 Q( \[3] $end +$var reg 8 R( \[4] $end +$var reg 8 S( \[5] $end +$var reg 8 T( \[6] $end +$var reg 8 U( \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 V( \[0] $end +$var reg 8 W( \[1] $end +$var reg 8 X( \[2] $end +$var reg 8 Y( \[3] $end +$var reg 8 Z( \[4] $end +$var reg 8 [( \[5] $end +$var reg 8 \( \[6] $end +$var reg 8 ]( \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 ^( \[0] $end +$var reg 8 _( \[1] $end +$var reg 8 `( \[2] $end +$var reg 8 a( \[3] $end +$var reg 8 b( \[4] $end +$var reg 8 c( \[5] $end +$var reg 8 d( \[6] $end +$var reg 8 e( \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 f( \$tag $end +$var reg 55 g( HdlSome $end +$upscope $end +$var string 1 h( config $end +$upscope $end +$scope struct \[14] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 i( \[0] $end +$var reg 8 j( \[1] $end +$var reg 8 k( \[2] $end +$var reg 8 l( \[3] $end +$var reg 8 m( \[4] $end +$var reg 8 n( \[5] $end +$var reg 8 o( \[6] $end +$var reg 8 p( \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 q( \[0] $end +$var reg 8 r( \[1] $end +$var reg 8 s( \[2] $end +$var reg 8 t( \[3] $end +$var reg 8 u( \[4] $end +$var reg 8 v( \[5] $end +$var reg 8 w( \[6] $end +$var reg 8 x( \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 y( \[0] $end +$var reg 8 z( \[1] $end +$var reg 8 {( \[2] $end +$var reg 8 |( \[3] $end +$var reg 8 }( \[4] $end +$var reg 8 ~( \[5] $end +$var reg 8 !) \[6] $end +$var reg 8 ") \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 #) \[0] $end +$var reg 8 $) \[1] $end +$var reg 8 %) \[2] $end +$var reg 8 &) \[3] $end +$var reg 8 ') \[4] $end +$var reg 8 () \[5] $end +$var reg 8 )) \[6] $end +$var reg 8 *) \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 +) \$tag $end +$var reg 55 ,) HdlSome $end +$upscope $end +$var string 1 -) config $end +$upscope $end +$scope struct \[15] $end +$scope struct data $end +$scope struct \[0] $end +$var reg 8 .) \[0] $end +$var reg 8 /) \[1] $end +$var reg 8 0) \[2] $end +$var reg 8 1) \[3] $end +$var reg 8 2) \[4] $end +$var reg 8 3) \[5] $end +$var reg 8 4) \[6] $end +$var reg 8 5) \[7] $end +$upscope $end +$scope struct \[1] $end +$var reg 8 6) \[0] $end +$var reg 8 7) \[1] $end +$var reg 8 8) \[2] $end +$var reg 8 9) \[3] $end +$var reg 8 :) \[4] $end +$var reg 8 ;) \[5] $end +$var reg 8 <) \[6] $end +$var reg 8 =) \[7] $end +$upscope $end +$scope struct \[2] $end +$var reg 8 >) \[0] $end +$var reg 8 ?) \[1] $end +$var reg 8 @) \[2] $end +$var reg 8 A) \[3] $end +$var reg 8 B) \[4] $end +$var reg 8 C) \[5] $end +$var reg 8 D) \[6] $end +$var reg 8 E) \[7] $end +$upscope $end +$scope struct \[3] $end +$var reg 8 F) \[0] $end +$var reg 8 G) \[1] $end +$var reg 8 H) \[2] $end +$var reg 8 I) \[3] $end +$var reg 8 J) \[4] $end +$var reg 8 K) \[5] $end +$var reg 8 L) \[6] $end +$var reg 8 M) \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 N) \$tag $end +$var reg 55 O) HdlSome $end +$upscope $end +$var string 1 P) config $end +$upscope $end +$upscope $end +$scope struct l1_i_cache_impl $end +$scope struct cd $end +$var wire 1 @. clk $end +$var wire 1 A. rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 B. \$tag $end +$scope struct HdlSome $end +$var string 1 C. kind $end +$var wire 64 D. addr $end +$scope struct write_data $end +$var wire 8 E. \[0] $end +$var wire 8 F. \[1] $end +$var wire 8 G. \[2] $end +$var wire 8 H. \[3] $end +$var wire 8 I. \[4] $end +$var wire 8 J. \[5] $end +$var wire 8 K. \[6] $end +$var wire 8 L. \[7] $end +$upscope $end +$var wire 8 M. fetch_block_id $end +$var string 1 N. config $end +$upscope $end +$upscope $end +$var wire 1 O. ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 P. \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 Q. \$tag $end +$var string 1 R. Success $end +$var string 1 S. Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 T. \[0] $end +$var wire 8 U. \[1] $end +$var wire 8 V. \[2] $end +$var wire 8 W. \[3] $end +$var wire 8 X. \[4] $end +$var wire 8 Y. \[5] $end +$var wire 8 Z. \[6] $end +$var wire 8 [. \[7] $end +$upscope $end +$var string 1 \. config $end +$upscope $end +$upscope $end +$var wire 1 ]. ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 ^. \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 _. \[0] $end +$var wire 8 `. \[1] $end +$var wire 8 a. \[2] $end +$var wire 8 b. \[3] $end +$var wire 8 c. \[4] $end +$var wire 8 d. \[5] $end +$var wire 8 e. \[6] $end +$var wire 8 f. \[7] $end +$var wire 8 g. \[8] $end +$var wire 8 h. \[9] $end +$var wire 8 i. \[10] $end +$var wire 8 j. \[11] $end +$var wire 8 k. \[12] $end +$var wire 8 l. \[13] $end +$var wire 8 m. \[14] $end +$var wire 8 n. \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 o. value $end +$var string 1 p. range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 q. config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 r. \$tag $end +$scope struct HdlSome $end +$var wire 64 s. start_pc $end +$var wire 8 t. fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 u. ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 v. \$tag $end +$scope struct HdlSome $end +$var wire 5 w. value $end +$var string 1 x. range $end +$upscope $end +$upscope $end +$var wire 1 y. ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 z. \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 {. \[0] $end +$var wire 8 |. \[1] $end +$var wire 8 }. \[2] $end +$var wire 8 ~. \[3] $end +$var wire 8 !/ \[4] $end +$var wire 8 "/ \[5] $end +$var wire 8 #/ \[6] $end +$var wire 8 $/ \[7] $end +$var wire 8 %/ \[8] $end +$var wire 8 &/ \[9] $end +$var wire 8 '/ \[10] $end +$var wire 8 (/ \[11] $end +$var wire 8 )/ \[12] $end +$var wire 8 */ \[13] $end +$var wire 8 +/ \[14] $end +$var wire 8 ,/ \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 -/ value $end +$var string 1 ./ range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 // config $end +$upscope $end +$scope struct to_decode_fetched $end +$scope struct data $end +$var string 1 0/ \$tag $end +$scope struct HdlSome $end +$var wire 64 1/ start_pc $end +$var wire 8 2/ fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 3/ \[0] $end +$var wire 8 4/ \[1] $end +$var wire 8 5/ \[2] $end +$var wire 8 6/ \[3] $end +$var wire 8 7/ \[4] $end +$var wire 8 8/ \[5] $end +$var wire 8 9/ \[6] $end +$var wire 8 :/ \[7] $end +$upscope $end +$scope struct error $end +$var string 1 ;/ \$tag $end +$var string 1 / ready $end +$upscope $end +$scope struct max_cancel_in_fetch $end +$var wire 5 ?/ value $end +$var string 1 @/ range $end +$upscope $end +$scope struct i_cache_port $end +$var wire 4 A/ addr $end +$var wire 1 B/ en $end +$var wire 1 C/ clk $end +$scope struct rdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 D/ \[0] $end +$var wire 8 E/ \[1] $end +$var wire 8 F/ \[2] $end +$var wire 8 G/ \[3] $end +$var wire 8 H/ \[4] $end +$var wire 8 I/ \[5] $end +$var wire 8 J/ \[6] $end +$var wire 8 K/ \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 L/ \[0] $end +$var wire 8 M/ \[1] $end +$var wire 8 N/ \[2] $end +$var wire 8 O/ \[3] $end +$var wire 8 P/ \[4] $end +$var wire 8 Q/ \[5] $end +$var wire 8 R/ \[6] $end +$var wire 8 S/ \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 T/ \[0] $end +$var wire 8 U/ \[1] $end +$var wire 8 V/ \[2] $end +$var wire 8 W/ \[3] $end +$var wire 8 X/ \[4] $end +$var wire 8 Y/ \[5] $end +$var wire 8 Z/ \[6] $end +$var wire 8 [/ \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 \/ \[0] $end +$var wire 8 ]/ \[1] $end +$var wire 8 ^/ \[2] $end +$var wire 8 _/ \[3] $end +$var wire 8 `/ \[4] $end +$var wire 8 a/ \[5] $end +$var wire 8 b/ \[6] $end +$var wire 8 c/ \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 d/ \$tag $end +$var wire 55 e/ HdlSome $end +$upscope $end +$var string 1 f/ config $end +$upscope $end +$var wire 1 g/ wmode $end +$scope struct wdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 h/ \[0] $end +$var wire 8 i/ \[1] $end +$var wire 8 j/ \[2] $end +$var wire 8 k/ \[3] $end +$var wire 8 l/ \[4] $end +$var wire 8 m/ \[5] $end +$var wire 8 n/ \[6] $end +$var wire 8 o/ \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 p/ \[0] $end +$var wire 8 q/ \[1] $end +$var wire 8 r/ \[2] $end +$var wire 8 s/ \[3] $end +$var wire 8 t/ \[4] $end +$var wire 8 u/ \[5] $end +$var wire 8 v/ \[6] $end +$var wire 8 w/ \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 x/ \[0] $end +$var wire 8 y/ \[1] $end +$var wire 8 z/ \[2] $end +$var wire 8 {/ \[3] $end +$var wire 8 |/ \[4] $end +$var wire 8 }/ \[5] $end +$var wire 8 ~/ \[6] $end +$var wire 8 !0 \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 "0 \[0] $end +$var wire 8 #0 \[1] $end +$var wire 8 $0 \[2] $end +$var wire 8 %0 \[3] $end +$var wire 8 &0 \[4] $end +$var wire 8 '0 \[5] $end +$var wire 8 (0 \[6] $end +$var wire 8 )0 \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 *0 \$tag $end +$var wire 55 +0 HdlSome $end +$upscope $end +$var string 1 ,0 config $end +$upscope $end +$scope struct wmask $end +$scope struct data $end +$scope struct \[0] $end +$var wire 1 -0 \[0] $end +$var wire 1 .0 \[1] $end +$var wire 1 /0 \[2] $end +$var wire 1 00 \[3] $end +$var wire 1 10 \[4] $end +$var wire 1 20 \[5] $end +$var wire 1 30 \[6] $end +$var wire 1 40 \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 1 50 \[0] $end +$var wire 1 60 \[1] $end +$var wire 1 70 \[2] $end +$var wire 1 80 \[3] $end +$var wire 1 90 \[4] $end +$var wire 1 :0 \[5] $end +$var wire 1 ;0 \[6] $end +$var wire 1 <0 \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 1 =0 \[0] $end +$var wire 1 >0 \[1] $end +$var wire 1 ?0 \[2] $end +$var wire 1 @0 \[3] $end +$var wire 1 A0 \[4] $end +$var wire 1 B0 \[5] $end +$var wire 1 C0 \[6] $end +$var wire 1 D0 \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 1 E0 \[0] $end +$var wire 1 F0 \[1] $end +$var wire 1 G0 \[2] $end +$var wire 1 H0 \[3] $end +$var wire 1 I0 \[4] $end +$var wire 1 J0 \[5] $end +$var wire 1 K0 \[6] $end +$var wire 1 L0 \[7] $end +$upscope $end +$upscope $end +$var wire 1 M0 addr $end +$scope struct config $end +$upscope $end +$upscope $end +$upscope $end +$scope struct state_for_debug $end +$scope struct queue $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 N0 start_pc $end +$var wire 8 O0 fetch_block_id $end +$var string 1 P0 state $end +$scope struct error $end +$var string 1 Q0 \$tag $end +$var string 1 R0 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 S0 \[0] $end +$var wire 8 T0 \[1] $end +$var wire 8 U0 \[2] $end +$var wire 8 V0 \[3] $end +$var wire 8 W0 \[4] $end +$var wire 8 X0 \[5] $end +$var wire 8 Y0 \[6] $end +$var wire 8 Z0 \[7] $end +$upscope $end +$var string 1 [0 config $end +$upscope $end +$scope struct \[1] $end +$var wire 64 \0 start_pc $end +$var wire 8 ]0 fetch_block_id $end +$var string 1 ^0 state $end +$scope struct error $end +$var string 1 _0 \$tag $end +$var string 1 `0 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 a0 \[0] $end +$var wire 8 b0 \[1] $end +$var wire 8 c0 \[2] $end +$var wire 8 d0 \[3] $end +$var wire 8 e0 \[4] $end +$var wire 8 f0 \[5] $end +$var wire 8 g0 \[6] $end +$var wire 8 h0 \[7] $end +$upscope $end +$var string 1 i0 config $end +$upscope $end +$scope struct \[2] $end +$var wire 64 j0 start_pc $end +$var wire 8 k0 fetch_block_id $end +$var string 1 l0 state $end +$scope struct error $end +$var string 1 m0 \$tag $end +$var string 1 n0 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 o0 \[0] $end +$var wire 8 p0 \[1] $end +$var wire 8 q0 \[2] $end +$var wire 8 r0 \[3] $end +$var wire 8 s0 \[4] $end +$var wire 8 t0 \[5] $end +$var wire 8 u0 \[6] $end +$var wire 8 v0 \[7] $end +$upscope $end +$var string 1 w0 config $end +$upscope $end +$scope struct \[3] $end +$var wire 64 x0 start_pc $end +$var wire 8 y0 fetch_block_id $end +$var string 1 z0 state $end +$scope struct error $end +$var string 1 {0 \$tag $end +$var string 1 |0 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 }0 \[0] $end +$var wire 8 ~0 \[1] $end +$var wire 8 !1 \[2] $end +$var wire 8 "1 \[3] $end +$var wire 8 #1 \[4] $end +$var wire 8 $1 \[5] $end +$var wire 8 %1 \[6] $end +$var wire 8 &1 \[7] $end +$upscope $end +$var string 1 '1 config $end +$upscope $end +$scope struct \[4] $end +$var wire 64 (1 start_pc $end +$var wire 8 )1 fetch_block_id $end +$var string 1 *1 state $end +$scope struct error $end +$var string 1 +1 \$tag $end +$var string 1 ,1 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 -1 \[0] $end +$var wire 8 .1 \[1] $end +$var wire 8 /1 \[2] $end +$var wire 8 01 \[3] $end +$var wire 8 11 \[4] $end +$var wire 8 21 \[5] $end +$var wire 8 31 \[6] $end +$var wire 8 41 \[7] $end +$upscope $end +$var string 1 51 config $end +$upscope $end +$scope struct \[5] $end +$var wire 64 61 start_pc $end +$var wire 8 71 fetch_block_id $end +$var string 1 81 state $end +$scope struct error $end +$var string 1 91 \$tag $end +$var string 1 :1 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ;1 \[0] $end +$var wire 8 <1 \[1] $end +$var wire 8 =1 \[2] $end +$var wire 8 >1 \[3] $end +$var wire 8 ?1 \[4] $end +$var wire 8 @1 \[5] $end +$var wire 8 A1 \[6] $end +$var wire 8 B1 \[7] $end +$upscope $end +$var string 1 C1 config $end +$upscope $end +$scope struct \[6] $end +$var wire 64 D1 start_pc $end +$var wire 8 E1 fetch_block_id $end +$var string 1 F1 state $end +$scope struct error $end +$var string 1 G1 \$tag $end +$var string 1 H1 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 I1 \[0] $end +$var wire 8 J1 \[1] $end +$var wire 8 K1 \[2] $end +$var wire 8 L1 \[3] $end +$var wire 8 M1 \[4] $end +$var wire 8 N1 \[5] $end +$var wire 8 O1 \[6] $end +$var wire 8 P1 \[7] $end +$upscope $end +$var string 1 Q1 config $end +$upscope $end +$scope struct \[7] $end +$var wire 64 R1 start_pc $end +$var wire 8 S1 fetch_block_id $end +$var string 1 T1 state $end +$scope struct error $end +$var string 1 U1 \$tag $end +$var string 1 V1 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 W1 \[0] $end +$var wire 8 X1 \[1] $end +$var wire 8 Y1 \[2] $end +$var wire 8 Z1 \[3] $end +$var wire 8 [1 \[4] $end +$var wire 8 \1 \[5] $end +$var wire 8 ]1 \[6] $end +$var wire 8 ^1 \[7] $end +$upscope $end +$var string 1 _1 config $end +$upscope $end +$scope struct \[8] $end +$var wire 64 `1 start_pc $end +$var wire 8 a1 fetch_block_id $end +$var string 1 b1 state $end +$scope struct error $end +$var string 1 c1 \$tag $end +$var string 1 d1 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 e1 \[0] $end +$var wire 8 f1 \[1] $end +$var wire 8 g1 \[2] $end +$var wire 8 h1 \[3] $end +$var wire 8 i1 \[4] $end +$var wire 8 j1 \[5] $end +$var wire 8 k1 \[6] $end +$var wire 8 l1 \[7] $end +$upscope $end +$var string 1 m1 config $end +$upscope $end +$scope struct \[9] $end +$var wire 64 n1 start_pc $end +$var wire 8 o1 fetch_block_id $end +$var string 1 p1 state $end +$scope struct error $end +$var string 1 q1 \$tag $end +$var string 1 r1 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 s1 \[0] $end +$var wire 8 t1 \[1] $end +$var wire 8 u1 \[2] $end +$var wire 8 v1 \[3] $end +$var wire 8 w1 \[4] $end +$var wire 8 x1 \[5] $end +$var wire 8 y1 \[6] $end +$var wire 8 z1 \[7] $end +$upscope $end +$var string 1 {1 config $end +$upscope $end +$scope struct \[10] $end +$var wire 64 |1 start_pc $end +$var wire 8 }1 fetch_block_id $end +$var string 1 ~1 state $end +$scope struct error $end +$var string 1 !2 \$tag $end +$var string 1 "2 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 #2 \[0] $end +$var wire 8 $2 \[1] $end +$var wire 8 %2 \[2] $end +$var wire 8 &2 \[3] $end +$var wire 8 '2 \[4] $end +$var wire 8 (2 \[5] $end +$var wire 8 )2 \[6] $end +$var wire 8 *2 \[7] $end +$upscope $end +$var string 1 +2 config $end +$upscope $end +$scope struct \[11] $end +$var wire 64 ,2 start_pc $end +$var wire 8 -2 fetch_block_id $end +$var string 1 .2 state $end +$scope struct error $end +$var string 1 /2 \$tag $end +$var string 1 02 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 12 \[0] $end +$var wire 8 22 \[1] $end +$var wire 8 32 \[2] $end +$var wire 8 42 \[3] $end +$var wire 8 52 \[4] $end +$var wire 8 62 \[5] $end +$var wire 8 72 \[6] $end +$var wire 8 82 \[7] $end +$upscope $end +$var string 1 92 config $end +$upscope $end +$scope struct \[12] $end +$var wire 64 :2 start_pc $end +$var wire 8 ;2 fetch_block_id $end +$var string 1 <2 state $end +$scope struct error $end +$var string 1 =2 \$tag $end +$var string 1 >2 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ?2 \[0] $end +$var wire 8 @2 \[1] $end +$var wire 8 A2 \[2] $end +$var wire 8 B2 \[3] $end +$var wire 8 C2 \[4] $end +$var wire 8 D2 \[5] $end +$var wire 8 E2 \[6] $end +$var wire 8 F2 \[7] $end +$upscope $end +$var string 1 G2 config $end +$upscope $end +$scope struct \[13] $end +$var wire 64 H2 start_pc $end +$var wire 8 I2 fetch_block_id $end +$var string 1 J2 state $end +$scope struct error $end +$var string 1 K2 \$tag $end +$var string 1 L2 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 M2 \[0] $end +$var wire 8 N2 \[1] $end +$var wire 8 O2 \[2] $end +$var wire 8 P2 \[3] $end +$var wire 8 Q2 \[4] $end +$var wire 8 R2 \[5] $end +$var wire 8 S2 \[6] $end +$var wire 8 T2 \[7] $end +$upscope $end +$var string 1 U2 config $end +$upscope $end +$scope struct \[14] $end +$var wire 64 V2 start_pc $end +$var wire 8 W2 fetch_block_id $end +$var string 1 X2 state $end +$scope struct error $end +$var string 1 Y2 \$tag $end +$var string 1 Z2 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 [2 \[0] $end +$var wire 8 \2 \[1] $end +$var wire 8 ]2 \[2] $end +$var wire 8 ^2 \[3] $end +$var wire 8 _2 \[4] $end +$var wire 8 `2 \[5] $end +$var wire 8 a2 \[6] $end +$var wire 8 b2 \[7] $end +$upscope $end +$var string 1 c2 config $end +$upscope $end +$scope struct \[15] $end +$var wire 64 d2 start_pc $end +$var wire 8 e2 fetch_block_id $end +$var string 1 f2 state $end +$scope struct error $end +$var string 1 g2 \$tag $end +$var string 1 h2 HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 i2 \[0] $end +$var wire 8 j2 \[1] $end +$var wire 8 k2 \[2] $end +$var wire 8 l2 \[3] $end +$var wire 8 m2 \[4] $end +$var wire 8 n2 \[5] $end +$var wire 8 o2 \[6] $end +$var wire 8 p2 \[7] $end +$upscope $end +$var string 1 q2 config $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 5 r2 value $end +$var string 1 s2 range $end +$upscope $end +$upscope $end +$scope struct cache_misses $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 t2 addr $end +$var wire 8 u2 fetch_block_id $end +$scope struct next_start_fetch_block $end +$var string 1 v2 \$tag $end +$scope struct HdlSome $end +$var wire 2 w2 value $end +$var string 1 x2 range $end +$upscope $end +$upscope $end +$scope struct next_finish_fetch_block $end +$var string 1 y2 \$tag $end +$scope struct HdlSome $end +$var wire 2 z2 value $end +$var string 1 {2 range $end +$upscope $end +$upscope $end +$scope struct error $end +$var string 1 |2 \$tag $end +$var string 1 }2 HdlSome $end +$upscope $end +$var string 1 ~2 config $end +$upscope $end +$scope struct \[1] $end +$var wire 64 !3 addr $end +$var wire 8 "3 fetch_block_id $end +$scope struct next_start_fetch_block $end +$var string 1 #3 \$tag $end +$scope struct HdlSome $end +$var wire 2 $3 value $end +$var string 1 %3 range $end +$upscope $end +$upscope $end +$scope struct next_finish_fetch_block $end +$var string 1 &3 \$tag $end +$scope struct HdlSome $end +$var wire 2 '3 value $end +$var string 1 (3 range $end +$upscope $end +$upscope $end +$scope struct error $end +$var string 1 )3 \$tag $end +$var string 1 *3 HdlSome $end +$upscope $end +$var string 1 +3 config $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 2 ,3 value $end +$var string 1 -3 range $end +$upscope $end +$upscope $end +$var string 1 .3 config $end +$upscope $end +$upscope $end +$scope module l1_i_cache_impl_2 $end +$scope struct cd $end +$var wire 1 Q) clk $end +$var wire 1 R) rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 S) \$tag $end +$scope struct HdlSome $end +$var string 1 T) kind $end +$var wire 64 U) addr $end +$scope struct write_data $end +$var wire 8 V) \[0] $end +$var wire 8 W) \[1] $end +$var wire 8 X) \[2] $end +$var wire 8 Y) \[3] $end +$var wire 8 Z) \[4] $end +$var wire 8 [) \[5] $end +$var wire 8 \) \[6] $end +$var wire 8 ]) \[7] $end +$upscope $end +$var wire 8 ^) fetch_block_id $end +$var string 1 _) config $end +$upscope $end +$upscope $end +$var wire 1 `) ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 a) \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 b) \$tag $end +$var string 1 c) Success $end +$var string 1 d) Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 e) \[0] $end +$var wire 8 f) \[1] $end +$var wire 8 g) \[2] $end +$var wire 8 h) \[3] $end +$var wire 8 i) \[4] $end +$var wire 8 j) \[5] $end +$var wire 8 k) \[6] $end +$var wire 8 l) \[7] $end +$upscope $end +$var string 1 m) config $end +$upscope $end +$upscope $end +$var wire 1 n) ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 o) \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 p) \[0] $end +$var wire 8 q) \[1] $end +$var wire 8 r) \[2] $end +$var wire 8 s) \[3] $end +$var wire 8 t) \[4] $end +$var wire 8 u) \[5] $end +$var wire 8 v) \[6] $end +$var wire 8 w) \[7] $end +$var wire 8 x) \[8] $end +$var wire 8 y) \[9] $end +$var wire 8 z) \[10] $end +$var wire 8 {) \[11] $end +$var wire 8 |) \[12] $end +$var wire 8 }) \[13] $end +$var wire 8 ~) \[14] $end +$var wire 8 !* \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 "* value $end +$var string 1 #* range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 $* config $end +$upscope $end +$scope struct from_next_pc $end +$scope struct fetch $end +$scope struct data $end +$var string 1 %* \$tag $end +$scope struct HdlSome $end +$var wire 64 &* start_pc $end +$var wire 8 '* fetch_block_id $end +$upscope $end +$upscope $end +$var wire 1 (* ready $end +$upscope $end +$scope struct cancel $end +$scope struct data $end +$var string 1 )* \$tag $end +$scope struct HdlSome $end +$var wire 5 ** value $end +$var string 1 +* range $end +$upscope $end +$upscope $end +$var wire 1 ,* ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 -* \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 .* \[0] $end +$var wire 8 /* \[1] $end +$var wire 8 0* \[2] $end +$var wire 8 1* \[3] $end +$var wire 8 2* \[4] $end +$var wire 8 3* \[5] $end +$var wire 8 4* \[6] $end +$var wire 8 5* \[7] $end +$var wire 8 6* \[8] $end +$var wire 8 7* \[9] $end +$var wire 8 8* \[10] $end +$var wire 8 9* \[11] $end +$var wire 8 :* \[12] $end +$var wire 8 ;* \[13] $end +$var wire 8 <* \[14] $end +$var wire 8 =* \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 >* value $end +$var string 1 ?* range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 @* config $end +$upscope $end +$scope struct to_decode_fetched $end +$scope struct data $end +$var string 1 A* \$tag $end +$scope struct HdlSome $end +$var wire 64 B* start_pc $end +$var wire 8 C* fetch_block_id $end +$scope struct fetch_block_data $end +$var wire 8 D* \[0] $end +$var wire 8 E* \[1] $end +$var wire 8 F* \[2] $end +$var wire 8 G* \[3] $end +$var wire 8 H* \[4] $end +$var wire 8 I* \[5] $end +$var wire 8 J* \[6] $end +$var wire 8 K* \[7] $end +$upscope $end +$scope struct error $end +$var string 1 L* \$tag $end +$var string 1 M* HdlSome $end +$upscope $end +$var string 1 N* config $end +$upscope $end +$upscope $end +$var wire 1 O* ready $end +$upscope $end +$scope struct max_cancel_in_fetch $end +$var wire 5 P* value $end +$var string 1 Q* range $end +$upscope $end +$scope struct i_cache_port $end +$var wire 4 R* addr $end +$var wire 1 S* en $end +$var wire 1 T* clk $end +$scope struct rdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 U* \[0] $end +$var wire 8 V* \[1] $end +$var wire 8 W* \[2] $end +$var wire 8 X* \[3] $end +$var wire 8 Y* \[4] $end +$var wire 8 Z* \[5] $end +$var wire 8 [* \[6] $end +$var wire 8 \* \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 ]* \[0] $end +$var wire 8 ^* \[1] $end +$var wire 8 _* \[2] $end +$var wire 8 `* \[3] $end +$var wire 8 a* \[4] $end +$var wire 8 b* \[5] $end +$var wire 8 c* \[6] $end +$var wire 8 d* \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 e* \[0] $end +$var wire 8 f* \[1] $end +$var wire 8 g* \[2] $end +$var wire 8 h* \[3] $end +$var wire 8 i* \[4] $end +$var wire 8 j* \[5] $end +$var wire 8 k* \[6] $end +$var wire 8 l* \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 m* \[0] $end +$var wire 8 n* \[1] $end +$var wire 8 o* \[2] $end +$var wire 8 p* \[3] $end +$var wire 8 q* \[4] $end +$var wire 8 r* \[5] $end +$var wire 8 s* \[6] $end +$var wire 8 t* \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 u* \$tag $end +$var wire 55 v* HdlSome $end +$upscope $end +$var string 1 w* config $end +$upscope $end +$var wire 1 x* wmode $end +$scope struct wdata $end +$scope struct data $end +$scope struct \[0] $end +$var wire 8 y* \[0] $end +$var wire 8 z* \[1] $end +$var wire 8 {* \[2] $end +$var wire 8 |* \[3] $end +$var wire 8 }* \[4] $end +$var wire 8 ~* \[5] $end +$var wire 8 !+ \[6] $end +$var wire 8 "+ \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 8 #+ \[0] $end +$var wire 8 $+ \[1] $end +$var wire 8 %+ \[2] $end +$var wire 8 &+ \[3] $end +$var wire 8 '+ \[4] $end +$var wire 8 (+ \[5] $end +$var wire 8 )+ \[6] $end +$var wire 8 *+ \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 8 ++ \[0] $end +$var wire 8 ,+ \[1] $end +$var wire 8 -+ \[2] $end +$var wire 8 .+ \[3] $end +$var wire 8 /+ \[4] $end +$var wire 8 0+ \[5] $end +$var wire 8 1+ \[6] $end +$var wire 8 2+ \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 8 3+ \[0] $end +$var wire 8 4+ \[1] $end +$var wire 8 5+ \[2] $end +$var wire 8 6+ \[3] $end +$var wire 8 7+ \[4] $end +$var wire 8 8+ \[5] $end +$var wire 8 9+ \[6] $end +$var wire 8 :+ \[7] $end +$upscope $end +$upscope $end +$scope struct addr $end +$var string 1 ;+ \$tag $end +$var wire 55 <+ HdlSome $end +$upscope $end +$var string 1 =+ config $end +$upscope $end +$scope struct wmask $end +$scope struct data $end +$scope struct \[0] $end +$var wire 1 >+ \[0] $end +$var wire 1 ?+ \[1] $end +$var wire 1 @+ \[2] $end +$var wire 1 A+ \[3] $end +$var wire 1 B+ \[4] $end +$var wire 1 C+ \[5] $end +$var wire 1 D+ \[6] $end +$var wire 1 E+ \[7] $end +$upscope $end +$scope struct \[1] $end +$var wire 1 F+ \[0] $end +$var wire 1 G+ \[1] $end +$var wire 1 H+ \[2] $end +$var wire 1 I+ \[3] $end +$var wire 1 J+ \[4] $end +$var wire 1 K+ \[5] $end +$var wire 1 L+ \[6] $end +$var wire 1 M+ \[7] $end +$upscope $end +$scope struct \[2] $end +$var wire 1 N+ \[0] $end +$var wire 1 O+ \[1] $end +$var wire 1 P+ \[2] $end +$var wire 1 Q+ \[3] $end +$var wire 1 R+ \[4] $end +$var wire 1 S+ \[5] $end +$var wire 1 T+ \[6] $end +$var wire 1 U+ \[7] $end +$upscope $end +$scope struct \[3] $end +$var wire 1 V+ \[0] $end +$var wire 1 W+ \[1] $end +$var wire 1 X+ \[2] $end +$var wire 1 Y+ \[3] $end +$var wire 1 Z+ \[4] $end +$var wire 1 [+ \[5] $end +$var wire 1 \+ \[6] $end +$var wire 1 ]+ \[7] $end +$upscope $end +$upscope $end +$var wire 1 ^+ addr $end +$scope struct config $end +$upscope $end +$upscope $end +$upscope $end +$scope struct state_for_debug $end +$scope struct queue $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 _+ start_pc $end +$var wire 8 `+ fetch_block_id $end +$var string 1 a+ state $end +$scope struct error $end +$var string 1 b+ \$tag $end +$var string 1 c+ HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 d+ \[0] $end +$var wire 8 e+ \[1] $end +$var wire 8 f+ \[2] $end +$var wire 8 g+ \[3] $end +$var wire 8 h+ \[4] $end +$var wire 8 i+ \[5] $end +$var wire 8 j+ \[6] $end +$var wire 8 k+ \[7] $end +$upscope $end +$var string 1 l+ config $end +$upscope $end +$scope struct \[1] $end +$var wire 64 m+ start_pc $end +$var wire 8 n+ fetch_block_id $end +$var string 1 o+ state $end +$scope struct error $end +$var string 1 p+ \$tag $end +$var string 1 q+ HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 r+ \[0] $end +$var wire 8 s+ \[1] $end +$var wire 8 t+ \[2] $end +$var wire 8 u+ \[3] $end +$var wire 8 v+ \[4] $end +$var wire 8 w+ \[5] $end +$var wire 8 x+ \[6] $end +$var wire 8 y+ \[7] $end +$upscope $end +$var string 1 z+ config $end +$upscope $end +$scope struct \[2] $end +$var wire 64 {+ start_pc $end +$var wire 8 |+ fetch_block_id $end +$var string 1 }+ state $end +$scope struct error $end +$var string 1 ~+ \$tag $end +$var string 1 !, HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ", \[0] $end +$var wire 8 #, \[1] $end +$var wire 8 $, \[2] $end +$var wire 8 %, \[3] $end +$var wire 8 &, \[4] $end +$var wire 8 ', \[5] $end +$var wire 8 (, \[6] $end +$var wire 8 ), \[7] $end +$upscope $end +$var string 1 *, config $end +$upscope $end +$scope struct \[3] $end +$var wire 64 +, start_pc $end +$var wire 8 ,, fetch_block_id $end +$var string 1 -, state $end +$scope struct error $end +$var string 1 ., \$tag $end +$var string 1 /, HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 0, \[0] $end +$var wire 8 1, \[1] $end +$var wire 8 2, \[2] $end +$var wire 8 3, \[3] $end +$var wire 8 4, \[4] $end +$var wire 8 5, \[5] $end +$var wire 8 6, \[6] $end +$var wire 8 7, \[7] $end +$upscope $end +$var string 1 8, config $end +$upscope $end +$scope struct \[4] $end +$var wire 64 9, start_pc $end +$var wire 8 :, fetch_block_id $end +$var string 1 ;, state $end +$scope struct error $end +$var string 1 <, \$tag $end +$var string 1 =, HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 >, \[0] $end +$var wire 8 ?, \[1] $end +$var wire 8 @, \[2] $end +$var wire 8 A, \[3] $end +$var wire 8 B, \[4] $end +$var wire 8 C, \[5] $end +$var wire 8 D, \[6] $end +$var wire 8 E, \[7] $end +$upscope $end +$var string 1 F, config $end +$upscope $end +$scope struct \[5] $end +$var wire 64 G, start_pc $end +$var wire 8 H, fetch_block_id $end +$var string 1 I, state $end +$scope struct error $end +$var string 1 J, \$tag $end +$var string 1 K, HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 L, \[0] $end +$var wire 8 M, \[1] $end +$var wire 8 N, \[2] $end +$var wire 8 O, \[3] $end +$var wire 8 P, \[4] $end +$var wire 8 Q, \[5] $end +$var wire 8 R, \[6] $end +$var wire 8 S, \[7] $end +$upscope $end +$var string 1 T, config $end +$upscope $end +$scope struct \[6] $end +$var wire 64 U, start_pc $end +$var wire 8 V, fetch_block_id $end +$var string 1 W, state $end +$scope struct error $end +$var string 1 X, \$tag $end +$var string 1 Y, HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 Z, \[0] $end +$var wire 8 [, \[1] $end +$var wire 8 \, \[2] $end +$var wire 8 ], \[3] $end +$var wire 8 ^, \[4] $end +$var wire 8 _, \[5] $end +$var wire 8 `, \[6] $end +$var wire 8 a, \[7] $end +$upscope $end +$var string 1 b, config $end +$upscope $end +$scope struct \[7] $end +$var wire 64 c, start_pc $end +$var wire 8 d, fetch_block_id $end +$var string 1 e, state $end +$scope struct error $end +$var string 1 f, \$tag $end +$var string 1 g, HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 h, \[0] $end +$var wire 8 i, \[1] $end +$var wire 8 j, \[2] $end +$var wire 8 k, \[3] $end +$var wire 8 l, \[4] $end +$var wire 8 m, \[5] $end +$var wire 8 n, \[6] $end +$var wire 8 o, \[7] $end +$upscope $end +$var string 1 p, config $end +$upscope $end +$scope struct \[8] $end +$var wire 64 q, start_pc $end +$var wire 8 r, fetch_block_id $end +$var string 1 s, state $end +$scope struct error $end +$var string 1 t, \$tag $end +$var string 1 u, HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 v, \[0] $end +$var wire 8 w, \[1] $end +$var wire 8 x, \[2] $end +$var wire 8 y, \[3] $end +$var wire 8 z, \[4] $end +$var wire 8 {, \[5] $end +$var wire 8 |, \[6] $end +$var wire 8 }, \[7] $end +$upscope $end +$var string 1 ~, config $end +$upscope $end +$scope struct \[9] $end +$var wire 64 !- start_pc $end +$var wire 8 "- fetch_block_id $end +$var string 1 #- state $end +$scope struct error $end +$var string 1 $- \$tag $end +$var string 1 %- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 &- \[0] $end +$var wire 8 '- \[1] $end +$var wire 8 (- \[2] $end +$var wire 8 )- \[3] $end +$var wire 8 *- \[4] $end +$var wire 8 +- \[5] $end +$var wire 8 ,- \[6] $end +$var wire 8 -- \[7] $end +$upscope $end +$var string 1 .- config $end +$upscope $end +$scope struct \[10] $end +$var wire 64 /- start_pc $end +$var wire 8 0- fetch_block_id $end +$var string 1 1- state $end +$scope struct error $end +$var string 1 2- \$tag $end +$var string 1 3- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 4- \[0] $end +$var wire 8 5- \[1] $end +$var wire 8 6- \[2] $end +$var wire 8 7- \[3] $end +$var wire 8 8- \[4] $end +$var wire 8 9- \[5] $end +$var wire 8 :- \[6] $end +$var wire 8 ;- \[7] $end +$upscope $end +$var string 1 <- config $end +$upscope $end +$scope struct \[11] $end +$var wire 64 =- start_pc $end +$var wire 8 >- fetch_block_id $end +$var string 1 ?- state $end +$scope struct error $end +$var string 1 @- \$tag $end +$var string 1 A- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 B- \[0] $end +$var wire 8 C- \[1] $end +$var wire 8 D- \[2] $end +$var wire 8 E- \[3] $end +$var wire 8 F- \[4] $end +$var wire 8 G- \[5] $end +$var wire 8 H- \[6] $end +$var wire 8 I- \[7] $end +$upscope $end +$var string 1 J- config $end +$upscope $end +$scope struct \[12] $end +$var wire 64 K- start_pc $end +$var wire 8 L- fetch_block_id $end +$var string 1 M- state $end +$scope struct error $end +$var string 1 N- \$tag $end +$var string 1 O- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 P- \[0] $end +$var wire 8 Q- \[1] $end +$var wire 8 R- \[2] $end +$var wire 8 S- \[3] $end +$var wire 8 T- \[4] $end +$var wire 8 U- \[5] $end +$var wire 8 V- \[6] $end +$var wire 8 W- \[7] $end +$upscope $end +$var string 1 X- config $end +$upscope $end +$scope struct \[13] $end +$var wire 64 Y- start_pc $end +$var wire 8 Z- fetch_block_id $end +$var string 1 [- state $end +$scope struct error $end +$var string 1 \- \$tag $end +$var string 1 ]- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 ^- \[0] $end +$var wire 8 _- \[1] $end +$var wire 8 `- \[2] $end +$var wire 8 a- \[3] $end +$var wire 8 b- \[4] $end +$var wire 8 c- \[5] $end +$var wire 8 d- \[6] $end +$var wire 8 e- \[7] $end +$upscope $end +$var string 1 f- config $end +$upscope $end +$scope struct \[14] $end +$var wire 64 g- start_pc $end +$var wire 8 h- fetch_block_id $end +$var string 1 i- state $end +$scope struct error $end +$var string 1 j- \$tag $end +$var string 1 k- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 l- \[0] $end +$var wire 8 m- \[1] $end +$var wire 8 n- \[2] $end +$var wire 8 o- \[3] $end +$var wire 8 p- \[4] $end +$var wire 8 q- \[5] $end +$var wire 8 r- \[6] $end +$var wire 8 s- \[7] $end +$upscope $end +$var string 1 t- config $end +$upscope $end +$scope struct \[15] $end +$var wire 64 u- start_pc $end +$var wire 8 v- fetch_block_id $end +$var string 1 w- state $end +$scope struct error $end +$var string 1 x- \$tag $end +$var string 1 y- HdlSome $end +$upscope $end +$scope struct fetch_block_data $end +$var wire 8 z- \[0] $end +$var wire 8 {- \[1] $end +$var wire 8 |- \[2] $end +$var wire 8 }- \[3] $end +$var wire 8 ~- \[4] $end +$var wire 8 !. \[5] $end +$var wire 8 ". \[6] $end +$var wire 8 #. \[7] $end +$upscope $end +$var string 1 $. config $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 5 %. value $end +$var string 1 &. range $end +$upscope $end +$upscope $end +$scope struct cache_misses $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 '. addr $end +$var wire 8 (. fetch_block_id $end +$scope struct next_start_fetch_block $end +$var string 1 ). \$tag $end +$scope struct HdlSome $end +$var wire 2 *. value $end +$var string 1 +. range $end +$upscope $end +$upscope $end +$scope struct next_finish_fetch_block $end +$var string 1 ,. \$tag $end +$scope struct HdlSome $end +$var wire 2 -. value $end +$var string 1 .. range $end +$upscope $end +$upscope $end +$scope struct error $end +$var string 1 /. \$tag $end +$var string 1 0. HdlSome $end +$upscope $end +$var string 1 1. config $end +$upscope $end +$scope struct \[1] $end +$var wire 64 2. addr $end +$var wire 8 3. fetch_block_id $end +$scope struct next_start_fetch_block $end +$var string 1 4. \$tag $end +$scope struct HdlSome $end +$var wire 2 5. value $end +$var string 1 6. range $end +$upscope $end +$upscope $end +$scope struct next_finish_fetch_block $end +$var string 1 7. \$tag $end +$scope struct HdlSome $end +$var wire 2 8. value $end +$var string 1 9. range $end +$upscope $end +$upscope $end +$scope struct error $end +$var string 1 :. \$tag $end +$var string 1 ;. HdlSome $end +$upscope $end +$var string 1 <. config $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 2 =. value $end +$var string 1 >. range $end +$upscope $end +$upscope $end +$var string 1 ?. config $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope struct mock_memory $end +$scope struct cd $end +$var wire 1 96 clk $end +$var wire 1 :6 rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 ;6 \$tag $end +$scope struct HdlSome $end +$var string 1 <6 kind $end +$var wire 64 =6 addr $end +$scope struct write_data $end +$var wire 8 >6 \[0] $end +$var wire 8 ?6 \[1] $end +$var wire 8 @6 \[2] $end +$var wire 8 A6 \[3] $end +$var wire 8 B6 \[4] $end +$var wire 8 C6 \[5] $end +$var wire 8 D6 \[6] $end +$var wire 8 E6 \[7] $end +$upscope $end +$var wire 8 F6 fetch_block_id $end +$var string 1 G6 config $end +$upscope $end +$upscope $end +$var wire 1 H6 ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 I6 \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 J6 \$tag $end +$var string 1 K6 Success $end +$var string 1 L6 Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 M6 \[0] $end +$var wire 8 N6 \[1] $end +$var wire 8 O6 \[2] $end +$var wire 8 P6 \[3] $end +$var wire 8 Q6 \[4] $end +$var wire 8 R6 \[5] $end +$var wire 8 S6 \[6] $end +$var wire 8 T6 \[7] $end +$upscope $end +$var string 1 U6 config $end +$upscope $end +$upscope $end +$var wire 1 V6 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 W6 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 X6 \[0] $end +$var wire 8 Y6 \[1] $end +$var wire 8 Z6 \[2] $end +$var wire 8 [6 \[3] $end +$var wire 8 \6 \[4] $end +$var wire 8 ]6 \[5] $end +$var wire 8 ^6 \[6] $end +$var wire 8 _6 \[7] $end +$var wire 8 `6 \[8] $end +$var wire 8 a6 \[9] $end +$var wire 8 b6 \[10] $end +$var wire 8 c6 \[11] $end +$var wire 8 d6 \[12] $end +$var wire 8 e6 \[13] $end +$var wire 8 f6 \[14] $end +$var wire 8 g6 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 h6 value $end +$var string 1 i6 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 j6 config $end +$upscope $end +$scope struct queue_debug $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 k6 addr $end +$var wire 8 l6 fetch_block_id $end +$var wire 8 m6 cycles_left $end +$upscope $end +$scope struct \[1] $end +$var wire 64 n6 addr $end +$var wire 8 o6 fetch_block_id $end +$var wire 8 p6 cycles_left $end +$upscope $end +$scope struct \[2] $end +$var wire 64 q6 addr $end +$var wire 8 r6 fetch_block_id $end +$var wire 8 s6 cycles_left $end +$upscope $end +$scope struct \[3] $end +$var wire 64 t6 addr $end +$var wire 8 u6 fetch_block_id $end +$var wire 8 v6 cycles_left $end +$upscope $end +$scope struct \[4] $end +$var wire 64 w6 addr $end +$var wire 8 x6 fetch_block_id $end +$var wire 8 y6 cycles_left $end +$upscope $end +$scope struct \[5] $end +$var wire 64 z6 addr $end +$var wire 8 {6 fetch_block_id $end +$var wire 8 |6 cycles_left $end +$upscope $end +$scope struct \[6] $end +$var wire 64 }6 addr $end +$var wire 8 ~6 fetch_block_id $end +$var wire 8 !7 cycles_left $end +$upscope $end +$scope struct \[7] $end +$var wire 64 "7 addr $end +$var wire 8 #7 fetch_block_id $end +$var wire 8 $7 cycles_left $end +$upscope $end +$scope struct \[8] $end +$var wire 64 %7 addr $end +$var wire 8 &7 fetch_block_id $end +$var wire 8 '7 cycles_left $end +$upscope $end +$scope struct \[9] $end +$var wire 64 (7 addr $end +$var wire 8 )7 fetch_block_id $end +$var wire 8 *7 cycles_left $end +$upscope $end +$scope struct \[10] $end +$var wire 64 +7 addr $end +$var wire 8 ,7 fetch_block_id $end +$var wire 8 -7 cycles_left $end +$upscope $end +$scope struct \[11] $end +$var wire 64 .7 addr $end +$var wire 8 /7 fetch_block_id $end +$var wire 8 07 cycles_left $end +$upscope $end +$scope struct \[12] $end +$var wire 64 17 addr $end +$var wire 8 27 fetch_block_id $end +$var wire 8 37 cycles_left $end +$upscope $end +$scope struct \[13] $end +$var wire 64 47 addr $end +$var wire 8 57 fetch_block_id $end +$var wire 8 67 cycles_left $end +$upscope $end +$scope struct \[14] $end +$var wire 64 77 addr $end +$var wire 8 87 fetch_block_id $end +$var wire 8 97 cycles_left $end +$upscope $end +$scope struct \[15] $end +$var wire 64 :7 addr $end +$var wire 8 ;7 fetch_block_id $end +$var wire 8 <7 cycles_left $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 5 =7 value $end +$var string 1 >7 range $end +$upscope $end +$upscope $end +$upscope $end +$scope module mock_memory_2 $end +$scope struct cd $end +$var wire 1 35 clk $end +$var wire 1 45 rst $end +$upscope $end +$scope struct memory_interface $end +$scope struct start $end +$scope struct data $end +$var string 1 55 \$tag $end +$scope struct HdlSome $end +$var string 1 65 kind $end +$var wire 64 75 addr $end +$scope struct write_data $end +$var wire 8 85 \[0] $end +$var wire 8 95 \[1] $end +$var wire 8 :5 \[2] $end +$var wire 8 ;5 \[3] $end +$var wire 8 <5 \[4] $end +$var wire 8 =5 \[5] $end +$var wire 8 >5 \[6] $end +$var wire 8 ?5 \[7] $end +$upscope $end +$var wire 8 @5 fetch_block_id $end +$var string 1 A5 config $end +$upscope $end +$upscope $end +$var wire 1 B5 ready $end +$upscope $end +$scope struct finish $end +$scope struct data $end +$var string 1 C5 \$tag $end +$scope struct HdlSome $end +$scope struct kind $end +$var string 1 D5 \$tag $end +$var string 1 E5 Success $end +$var string 1 F5 Error $end +$upscope $end +$scope struct read_data $end +$var wire 8 G5 \[0] $end +$var wire 8 H5 \[1] $end +$var wire 8 I5 \[2] $end +$var wire 8 J5 \[3] $end +$var wire 8 K5 \[4] $end +$var wire 8 L5 \[5] $end +$var wire 8 M5 \[6] $end +$var wire 8 N5 \[7] $end +$upscope $end +$var string 1 O5 config $end +$upscope $end +$upscope $end +$var wire 1 P5 ready $end +$upscope $end +$scope struct next_fetch_block_ids $end +$var string 1 Q5 \$tag $end +$scope struct HdlSome $end +$scope struct elements $end +$var wire 8 R5 \[0] $end +$var wire 8 S5 \[1] $end +$var wire 8 T5 \[2] $end +$var wire 8 U5 \[3] $end +$var wire 8 V5 \[4] $end +$var wire 8 W5 \[5] $end +$var wire 8 X5 \[6] $end +$var wire 8 Y5 \[7] $end +$var wire 8 Z5 \[8] $end +$var wire 8 [5 \[9] $end +$var wire 8 \5 \[10] $end +$var wire 8 ]5 \[11] $end +$var wire 8 ^5 \[12] $end +$var wire 8 _5 \[13] $end +$var wire 8 `5 \[14] $end +$var wire 8 a5 \[15] $end +$upscope $end +$scope struct len $end +$var wire 5 b5 value $end +$var string 1 c5 range $end +$upscope $end +$upscope $end +$upscope $end +$var string 1 d5 config $end +$upscope $end +$scope struct queue_debug $end +$scope struct elements $end +$scope struct \[0] $end +$var wire 64 e5 addr $end +$var wire 8 f5 fetch_block_id $end +$var wire 8 g5 cycles_left $end +$upscope $end +$scope struct \[1] $end +$var wire 64 h5 addr $end +$var wire 8 i5 fetch_block_id $end +$var wire 8 j5 cycles_left $end +$upscope $end +$scope struct \[2] $end +$var wire 64 k5 addr $end +$var wire 8 l5 fetch_block_id $end +$var wire 8 m5 cycles_left $end +$upscope $end +$scope struct \[3] $end +$var wire 64 n5 addr $end +$var wire 8 o5 fetch_block_id $end +$var wire 8 p5 cycles_left $end +$upscope $end +$scope struct \[4] $end +$var wire 64 q5 addr $end +$var wire 8 r5 fetch_block_id $end +$var wire 8 s5 cycles_left $end +$upscope $end +$scope struct \[5] $end +$var wire 64 t5 addr $end +$var wire 8 u5 fetch_block_id $end +$var wire 8 v5 cycles_left $end +$upscope $end +$scope struct \[6] $end +$var wire 64 w5 addr $end +$var wire 8 x5 fetch_block_id $end +$var wire 8 y5 cycles_left $end +$upscope $end +$scope struct \[7] $end +$var wire 64 z5 addr $end +$var wire 8 {5 fetch_block_id $end +$var wire 8 |5 cycles_left $end +$upscope $end +$scope struct \[8] $end +$var wire 64 }5 addr $end +$var wire 8 ~5 fetch_block_id $end +$var wire 8 !6 cycles_left $end +$upscope $end +$scope struct \[9] $end +$var wire 64 "6 addr $end +$var wire 8 #6 fetch_block_id $end +$var wire 8 $6 cycles_left $end +$upscope $end +$scope struct \[10] $end +$var wire 64 %6 addr $end +$var wire 8 &6 fetch_block_id $end +$var wire 8 '6 cycles_left $end +$upscope $end +$scope struct \[11] $end +$var wire 64 (6 addr $end +$var wire 8 )6 fetch_block_id $end +$var wire 8 *6 cycles_left $end +$upscope $end +$scope struct \[12] $end +$var wire 64 +6 addr $end +$var wire 8 ,6 fetch_block_id $end +$var wire 8 -6 cycles_left $end +$upscope $end +$scope struct \[13] $end +$var wire 64 .6 addr $end +$var wire 8 /6 fetch_block_id $end +$var wire 8 06 cycles_left $end +$upscope $end +$scope struct \[14] $end +$var wire 64 16 addr $end +$var wire 8 26 fetch_block_id $end +$var wire 8 36 cycles_left $end +$upscope $end +$scope struct \[15] $end +$var wire 64 46 addr $end +$var wire 8 56 fetch_block_id $end +$var wire 8 66 cycles_left $end +$upscope $end +$upscope $end +$scope struct len $end +$var wire 5 76 value $end +$var string 1 86 range $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +0! +1" +sHdlSome\x20(1) # +b1000000000000 $ +b0 % +0& +sHdlNone\x20(0) ' +b0 ( +sPhantomConst(\"1..=16\") ) +0* +sHdlNone\x20(0) + +b0 , +b0 - +b0 . +b0 / +b0 0 +b0 1 +b0 2 +b0 3 +b0 4 +b0 5 +b0 6 +b0 7 +b0 8 +b0 9 +b0 : +b0 ; +b0 < +sPhantomConst(\"0..=16\") = +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) > +sHdlNone\x20(0) ? +b0 @ +b0 A +b0 B +b0 C +b0 D +b0 E +b0 F +b0 G +b0 H +b0 I +sHdlNone\x20(0) J +sGeneric\x20(0) K +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) L +1M +sHdlNone\x20(0) N +b0 O +sPhantomConst(\"1..=16\") P +0Q +1R +sHdlNone\x20(0) S +sRead\x20(0) T +b0 U +b0 V +b0 W +b0 X +b0 Y +b0 Z +b0 [ +b0 \ +b0 ] +b0 ^ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) _ +0` +sHdlNone\x20(0) a +sSuccess\x20(0) b +sRead\x20(0) c +sGeneric\x20(0) d +b0 e +b0 f +b0 g +b0 h +b0 i +b0 j +b0 k +b0 l +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m +0n +sHdlNone\x20(0) o +b0 p +b0 q +b0 r +b0 s +b0 t +b0 u +b0 v +b0 w +b0 x +b0 y +b0 z +b0 { +b0 | +b0 } +b0 ~ +b0 !" +b0 "" +sPhantomConst(\"0..=16\") #" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) $" +sHdlSome\x20(1) %" +b1000000000000 &" +b0 '" +0(" +sHdlNone\x20(0) )" +b0 *" +sPhantomConst(\"1..=16\") +" +0," +sHdlNone\x20(0) -" +b0 ." +b0 /" +b0 0" +b0 1" +b0 2" +b0 3" +b0 4" +b0 5" +b0 6" +b0 7" +b0 8" +b0 9" +b0 :" +b0 ;" +b0 <" +b0 =" +b0 >" +sPhantomConst(\"0..=16\") ?" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) @" +sHdlNone\x20(0) A" +b0 B" +b0 C" +b0 D" +b0 E" +b0 F" +b0 G" +b0 H" +b0 I" +b0 J" +b0 K" +sHdlNone\x20(0) L" +sGeneric\x20(0) M" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) N" +1O" +sHdlNone\x20(0) P" +b0 Q" +sPhantomConst(\"1..=16\") R" +0S" +1T" +sHdlNone\x20(0) U" +sRead\x20(0) V" +b0 W" +b0 X" +b0 Y" +b0 Z" +b0 [" +b0 \" +b0 ]" +b0 ^" +b0 _" +b0 `" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) a" +0b" +sHdlNone\x20(0) c" +sSuccess\x20(0) d" +sRead\x20(0) e" +sGeneric\x20(0) f" +b0 g" +b0 h" +b0 i" +b0 j" +b0 k" +b0 l" +b0 m" +b0 n" +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) o" +0p" +sHdlNone\x20(0) q" +b0 r" +b0 s" +b0 t" +b0 u" +b0 v" +b0 w" +b0 x" +b0 y" +b0 z" +b0 {" +b0 |" +b0 }" +b0 ~" +b0 !# +b0 "# +b0 ## +b0 $# +sPhantomConst(\"0..=16\") %# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) &# +sHdlSome\x20(1) '# +b1000000000000 (# +b0 )# +0*# +sHdlNone\x20(0) +# +b0 ,# +sPhantomConst(\"1..=16\") -# +0.# +sHdlNone\x20(0) /# +b0 0# +b0 1# +b0 2# +b0 3# +b0 4# +b0 5# +b0 6# +b0 7# +b0 8# +b0 9# +b0 :# +b0 ;# +b0 <# +b0 =# +b0 ># +b0 ?# +b0 @# +sPhantomConst(\"0..=16\") A# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) B# +sHdlNone\x20(0) C# +b0 D# +b0 E# +b0 F# +b0 G# +b0 H# +b0 I# +b0 J# +b0 K# +b0 L# +b0 M# +sHdlNone\x20(0) N# +sGeneric\x20(0) O# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) P# +1Q# +sHdlNone\x20(0) R# +b0 S# +sPhantomConst(\"1..=16\") T# +b0 U# +b0 V# +b0 W# +b0 X# +b0 Y# +b0 Z# +b0 [# +b0 \# +b0 ]# +b0 ^# +b0 _# +b0 `# +b0 a# +b0 b# +b0 c# +b0 d# +b0 e# +b0 f# +b0 g# +b0 h# +b0 i# +b0 j# +b0 k# +b0 l# +b0 m# +b0 n# +b0 o# +b0 p# +b0 q# +b0 r# +b0 s# +b0 t# +sHdlNone\x20(0) u# +b0 v# +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) w# +b0 x# +b0 y# +b0 z# +b0 {# +b0 |# +b0 }# +b0 ~# +b0 !$ +b0 "$ +b0 #$ +b0 $$ +b0 %$ +b0 &$ +b0 '$ +b0 ($ +b0 )$ +b0 *$ +b0 +$ +b0 ,$ +b0 -$ +b0 .$ +b0 /$ +b0 0$ +b0 1$ +b0 2$ +b0 3$ +b0 4$ +b0 5$ +b0 6$ +b0 7$ +b0 8$ +b0 9$ +sHdlNone\x20(0) :$ +b0 ;$ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) <$ +b0 =$ +b0 >$ +b0 ?$ +b0 @$ +b0 A$ +b0 B$ +b0 C$ +b0 D$ +b0 E$ +b0 F$ +b0 G$ +b0 H$ +b0 I$ +b0 J$ +b0 K$ +b0 L$ +b0 M$ +b0 N$ +b0 O$ +b0 P$ +b0 Q$ +b0 R$ +b0 S$ +b0 T$ +b0 U$ +b0 V$ +b0 W$ +b0 X$ +b0 Y$ +b0 Z$ +b0 [$ +b0 \$ +sHdlNone\x20(0) ]$ +b0 ^$ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) _$ +b0 `$ +b0 a$ +b0 b$ +b0 c$ +b0 d$ +b0 e$ +b0 f$ +b0 g$ +b0 h$ +b0 i$ +b0 j$ +b0 k$ +b0 l$ +b0 m$ +b0 n$ +b0 o$ +b0 p$ +b0 q$ +b0 r$ +b0 s$ +b0 t$ +b0 u$ +b0 v$ +b0 w$ +b0 x$ +b0 y$ +b0 z$ +b0 {$ +b0 |$ +b0 }$ +b0 ~$ +b0 !% +sHdlNone\x20(0) "% +b0 #% +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) $% +b0 %% +b0 &% +b0 '% +b0 (% +b0 )% +b0 *% +b0 +% +b0 ,% +b0 -% +b0 .% +b0 /% +b0 0% +b0 1% +b0 2% +b0 3% +b0 4% +b0 5% +b0 6% +b0 7% +b0 8% +b0 9% +b0 :% +b0 ;% +b0 <% +b0 =% +b0 >% +b0 ?% +b0 @% +b0 A% +b0 B% +b0 C% +b0 D% +sHdlNone\x20(0) E% +b0 F% +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) G% +b0 H% +b0 I% +b0 J% +b0 K% +b0 L% +b0 M% +b0 N% +b0 O% +b0 P% +b0 Q% +b0 R% +b0 S% +b0 T% +b0 U% +b0 V% +b0 W% +b0 X% +b0 Y% +b0 Z% +b0 [% +b0 \% +b0 ]% +b0 ^% +b0 _% +b0 `% +b0 a% +b0 b% +b0 c% +b0 d% +b0 e% +b0 f% +b0 g% +sHdlNone\x20(0) h% +b0 i% +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) j% +b0 k% +b0 l% +b0 m% +b0 n% +b0 o% +b0 p% +b0 q% +b0 r% +b0 s% +b0 t% +b0 u% +b0 v% +b0 w% +b0 x% +b0 y% +b0 z% +b0 {% +b0 |% +b0 }% +b0 ~% +b0 !& +b0 "& +b0 #& +b0 $& +b0 %& +b0 && +b0 '& +b0 (& +b0 )& +b0 *& +b0 +& +b0 ,& +sHdlNone\x20(0) -& +b0 .& +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) /& +b0 0& +b0 1& +b0 2& +b0 3& +b0 4& +b0 5& +b0 6& +b0 7& +b0 8& +b0 9& +b0 :& +b0 ;& +b0 <& +b0 =& +b0 >& +b0 ?& +b0 @& +b0 A& +b0 B& +b0 C& +b0 D& +b0 E& +b0 F& +b0 G& +b0 H& +b0 I& +b0 J& +b0 K& +b0 L& +b0 M& +b0 N& +b0 O& +sHdlNone\x20(0) P& +b0 Q& +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) R& +b0 S& +b0 T& +b0 U& +b0 V& +b0 W& +b0 X& +b0 Y& +b0 Z& +b0 [& +b0 \& +b0 ]& +b0 ^& +b0 _& +b0 `& +b0 a& +b0 b& +b0 c& +b0 d& +b0 e& +b0 f& +b0 g& +b0 h& +b0 i& +b0 j& +b0 k& +b0 l& +b0 m& +b0 n& +b0 o& +b0 p& +b0 q& +b0 r& +sHdlNone\x20(0) s& +b0 t& +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) u& +b0 v& +b0 w& +b0 x& +b0 y& +b0 z& +b0 {& +b0 |& +b0 }& +b0 ~& +b0 !' +b0 "' +b0 #' +b0 $' +b0 %' +b0 &' +b0 '' +b0 (' +b0 )' +b0 *' +b0 +' +b0 ,' +b0 -' +b0 .' +b0 /' +b0 0' +b0 1' +b0 2' +b0 3' +b0 4' +b0 5' +b0 6' +b0 7' +sHdlNone\x20(0) 8' +b0 9' +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) :' +b0 ;' +b0 <' +b0 =' +b0 >' +b0 ?' +b0 @' +b0 A' +b0 B' +b0 C' +b0 D' +b0 E' +b0 F' +b0 G' +b0 H' +b0 I' +b0 J' +b0 K' +b0 L' +b0 M' +b0 N' +b0 O' +b0 P' +b0 Q' +b0 R' +b0 S' +b0 T' +b0 U' +b0 V' +b0 W' +b0 X' +b0 Y' +b0 Z' +sHdlNone\x20(0) [' +b0 \' +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ]' +b0 ^' +b0 _' +b0 `' +b0 a' +b0 b' +b0 c' +b0 d' +b0 e' +b0 f' +b0 g' +b0 h' +b0 i' +b0 j' +b0 k' +b0 l' +b0 m' +b0 n' +b0 o' +b0 p' +b0 q' +b0 r' +b0 s' +b0 t' +b0 u' +b0 v' +b0 w' +b0 x' +b0 y' +b0 z' +b0 {' +b0 |' +b0 }' +sHdlNone\x20(0) ~' +b0 !( +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) "( +b0 #( +b0 $( +b0 %( +b0 &( +b0 '( +b0 (( +b0 )( +b0 *( +b0 +( +b0 ,( +b0 -( +b0 .( +b0 /( +b0 0( +b0 1( +b0 2( +b0 3( +b0 4( +b0 5( +b0 6( +b0 7( +b0 8( +b0 9( +b0 :( +b0 ;( +b0 <( +b0 =( +b0 >( +b0 ?( +b0 @( +b0 A( +b0 B( +sHdlNone\x20(0) C( +b0 D( +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) E( +b0 F( +b0 G( +b0 H( +b0 I( +b0 J( +b0 K( +b0 L( +b0 M( +b0 N( +b0 O( +b0 P( +b0 Q( +b0 R( +b0 S( +b0 T( +b0 U( +b0 V( +b0 W( +b0 X( +b0 Y( +b0 Z( +b0 [( +b0 \( +b0 ]( +b0 ^( +b0 _( +b0 `( +b0 a( +b0 b( +b0 c( +b0 d( +b0 e( +sHdlNone\x20(0) f( +b0 g( +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) h( +b0 i( +b0 j( +b0 k( +b0 l( +b0 m( +b0 n( +b0 o( +b0 p( +b0 q( +b0 r( +b0 s( +b0 t( +b0 u( +b0 v( +b0 w( +b0 x( +b0 y( +b0 z( +b0 {( +b0 |( +b0 }( +b0 ~( +b0 !) +b0 ") +b0 #) +b0 $) +b0 %) +b0 &) +b0 ') +b0 () +b0 )) +b0 *) +sHdlNone\x20(0) +) +b0 ,) +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) -) +b0 .) +b0 /) +b0 0) +b0 1) +b0 2) +b0 3) +b0 4) +b0 5) +b0 6) +b0 7) +b0 8) +b0 9) +b0 :) +b0 ;) +b0 <) +b0 =) +b0 >) +b0 ?) +b0 @) +b0 A) +b0 B) +b0 C) +b0 D) +b0 E) +b0 F) +b0 G) +b0 H) +b0 I) +b0 J) +b0 K) +b0 L) +b0 M) +sHdlNone\x20(0) N) +b0 O) +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) P) +0Q) +1R) +sHdlNone\x20(0) S) +sRead\x20(0) T) +b0 U) +b0 V) +b0 W) +b0 X) +b0 Y) +b0 Z) +b0 [) +b0 \) +b0 ]) +b0 ^) +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) _) +0`) +sHdlNone\x20(0) a) +sSuccess\x20(0) b) +sRead\x20(0) c) +sGeneric\x20(0) d) +b0 e) +b0 f) +b0 g) +b0 h) +b0 i) +b0 j) +b0 k) +b0 l) +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m) +0n) +sHdlNone\x20(0) o) +b0 p) +b0 q) +b0 r) +b0 s) +b0 t) +b0 u) +b0 v) +b0 w) +b0 x) +b0 y) +b0 z) +b0 {) +b0 |) +b0 }) +b0 ~) +b0 !* +b0 "* +sPhantomConst(\"0..=16\") #* +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) $* +sHdlSome\x20(1) %* +b1000000000000 &* +b0 '* +0(* +sHdlNone\x20(0) )* +b0 ** +sPhantomConst(\"1..=16\") +* +0,* +sHdlNone\x20(0) -* +b0 .* +b0 /* +b0 0* +b0 1* +b0 2* +b0 3* +b0 4* +b0 5* +b0 6* +b0 7* +b0 8* +b0 9* +b0 :* +b0 ;* +b0 <* +b0 =* +b0 >* +sPhantomConst(\"0..=16\") ?* +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) @* +sHdlNone\x20(0) A* +b0 B* +b0 C* +b0 D* +b0 E* +b0 F* +b0 G* +b0 H* +b0 I* +b0 J* +b0 K* +sHdlNone\x20(0) L* +sGeneric\x20(0) M* +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) N* +1O* +b0 P* +sPhantomConst(\"0..=16\") Q* +b0 R* +0S* +0T* +b0 U* +b0 V* +b0 W* +b0 X* +b0 Y* +b0 Z* +b0 [* +b0 \* +b0 ]* +b0 ^* +b0 _* +b0 `* +b0 a* +b0 b* +b0 c* +b0 d* +b0 e* +b0 f* +b0 g* +b0 h* +b0 i* +b0 j* +b0 k* +b0 l* +b0 m* +b0 n* +b0 o* +b0 p* +b0 q* +b0 r* +b0 s* +b0 t* +sHdlNone\x20(0) u* +b0 v* +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) w* +0x* +b0 y* +b0 z* +b0 {* +b0 |* +b0 }* +b0 ~* +b0 !+ +b0 "+ +b0 #+ +b0 $+ +b0 %+ +b0 &+ +b0 '+ +b0 (+ +b0 )+ +b0 *+ +b0 ++ +b0 ,+ +b0 -+ +b0 .+ +b0 /+ +b0 0+ +b0 1+ +b0 2+ +b0 3+ +b0 4+ +b0 5+ +b0 6+ +b0 7+ +b0 8+ +b0 9+ +b0 :+ +sHdlNone\x20(0) ;+ +b0 <+ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) =+ +0>+ +0?+ +0@+ +0A+ +0B+ +0C+ +0D+ +0E+ +0F+ +0G+ +0H+ +0I+ +0J+ +0K+ +0L+ +0M+ +0N+ +0O+ +0P+ +0Q+ +0R+ +0S+ +0T+ +0U+ +0V+ +0W+ +0X+ +0Y+ +0Z+ +0[+ +0\+ +0]+ +0^+ +b0 _+ +b0 `+ +sStart\x20(0) a+ +sHdlNone\x20(0) b+ +sGeneric\x20(0) c+ +b0 d+ +b0 e+ +b0 f+ +b0 g+ +b0 h+ +b0 i+ +b0 j+ +b0 k+ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) l+ +b0 m+ +b0 n+ +sStart\x20(0) o+ +sHdlNone\x20(0) p+ +sGeneric\x20(0) q+ +b0 r+ +b0 s+ +b0 t+ +b0 u+ +b0 v+ +b0 w+ +b0 x+ +b0 y+ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) z+ +b0 {+ +b0 |+ +sStart\x20(0) }+ +sHdlNone\x20(0) ~+ +sGeneric\x20(0) !, +b0 ", +b0 #, +b0 $, +b0 %, +b0 &, +b0 ', +b0 (, +b0 ), +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) *, +b0 +, +b0 ,, +sStart\x20(0) -, +sHdlNone\x20(0) ., +sGeneric\x20(0) /, +b0 0, +b0 1, +b0 2, +b0 3, +b0 4, +b0 5, +b0 6, +b0 7, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 8, +b0 9, +b0 :, +sStart\x20(0) ;, +sHdlNone\x20(0) <, +sGeneric\x20(0) =, +b0 >, +b0 ?, +b0 @, +b0 A, +b0 B, +b0 C, +b0 D, +b0 E, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) F, +b0 G, +b0 H, +sStart\x20(0) I, +sHdlNone\x20(0) J, +sGeneric\x20(0) K, +b0 L, +b0 M, +b0 N, +b0 O, +b0 P, +b0 Q, +b0 R, +b0 S, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) T, +b0 U, +b0 V, +sStart\x20(0) W, +sHdlNone\x20(0) X, +sGeneric\x20(0) Y, +b0 Z, +b0 [, +b0 \, +b0 ], +b0 ^, +b0 _, +b0 `, +b0 a, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) b, +b0 c, +b0 d, +sStart\x20(0) e, +sHdlNone\x20(0) f, +sGeneric\x20(0) g, +b0 h, +b0 i, +b0 j, +b0 k, +b0 l, +b0 m, +b0 n, +b0 o, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) p, +b0 q, +b0 r, +sStart\x20(0) s, +sHdlNone\x20(0) t, +sGeneric\x20(0) u, +b0 v, +b0 w, +b0 x, +b0 y, +b0 z, +b0 {, +b0 |, +b0 }, +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ~, +b0 !- +b0 "- +sStart\x20(0) #- +sHdlNone\x20(0) $- +sGeneric\x20(0) %- +b0 &- +b0 '- +b0 (- +b0 )- +b0 *- +b0 +- +b0 ,- +b0 -- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) .- +b0 /- +b0 0- +sStart\x20(0) 1- +sHdlNone\x20(0) 2- +sGeneric\x20(0) 3- +b0 4- +b0 5- +b0 6- +b0 7- +b0 8- +b0 9- +b0 :- +b0 ;- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) <- +b0 =- +b0 >- +sStart\x20(0) ?- +sHdlNone\x20(0) @- +sGeneric\x20(0) A- +b0 B- +b0 C- +b0 D- +b0 E- +b0 F- +b0 G- +b0 H- +b0 I- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) J- +b0 K- +b0 L- +sStart\x20(0) M- +sHdlNone\x20(0) N- +sGeneric\x20(0) O- +b0 P- +b0 Q- +b0 R- +b0 S- +b0 T- +b0 U- +b0 V- +b0 W- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) X- +b0 Y- +b0 Z- +sStart\x20(0) [- +sHdlNone\x20(0) \- +sGeneric\x20(0) ]- +b0 ^- +b0 _- +b0 `- +b0 a- +b0 b- +b0 c- +b0 d- +b0 e- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) f- +b0 g- +b0 h- +sStart\x20(0) i- +sHdlNone\x20(0) j- +sGeneric\x20(0) k- +b0 l- +b0 m- +b0 n- +b0 o- +b0 p- +b0 q- +b0 r- +b0 s- +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) t- +b0 u- +b0 v- +sStart\x20(0) w- +sHdlNone\x20(0) x- +sGeneric\x20(0) y- +b0 z- +b0 {- +b0 |- +b0 }- +b0 ~- +b0 !. +b0 ". +b0 #. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) $. +b0 %. +sPhantomConst(\"0..=16\") &. +b0 '. +b0 (. +sHdlNone\x20(0) ). +b0 *. +sPhantomConst(\"0..4\") +. +sHdlNone\x20(0) ,. +b0 -. +sPhantomConst(\"0..4\") .. +sHdlNone\x20(0) /. +sGeneric\x20(0) 0. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 1. +b0 2. +b0 3. +sHdlNone\x20(0) 4. +b0 5. +sPhantomConst(\"0..4\") 6. +sHdlNone\x20(0) 7. +b0 8. +sPhantomConst(\"0..4\") 9. +sHdlNone\x20(0) :. +sGeneric\x20(0) ;. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) <. +b0 =. +sPhantomConst(\"0..=2\") >. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?. +0@. +1A. +sHdlNone\x20(0) B. +sRead\x20(0) C. +b0 D. +b0 E. +b0 F. +b0 G. +b0 H. +b0 I. +b0 J. +b0 K. +b0 L. +b0 M. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) N. +0O. +sHdlNone\x20(0) P. +sSuccess\x20(0) Q. +sRead\x20(0) R. +sGeneric\x20(0) S. +b0 T. +b0 U. +b0 V. +b0 W. +b0 X. +b0 Y. +b0 Z. +b0 [. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) \. +0]. +sHdlNone\x20(0) ^. +b0 _. +b0 `. +b0 a. +b0 b. +b0 c. +b0 d. +b0 e. +b0 f. +b0 g. +b0 h. +b0 i. +b0 j. +b0 k. +b0 l. +b0 m. +b0 n. +b0 o. +sPhantomConst(\"0..=16\") p. +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) q. +sHdlSome\x20(1) r. +b1000000000000 s. +b0 t. +0u. +sHdlNone\x20(0) v. +b0 w. +sPhantomConst(\"1..=16\") x. +0y. +sHdlNone\x20(0) z. +b0 {. +b0 |. +b0 }. +b0 ~. +b0 !/ +b0 "/ +b0 #/ +b0 $/ +b0 %/ +b0 &/ +b0 '/ +b0 (/ +b0 )/ +b0 */ +b0 +/ +b0 ,/ +b0 -/ +sPhantomConst(\"0..=16\") ./ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) // +sHdlNone\x20(0) 0/ +b0 1/ +b0 2/ +b0 3/ +b0 4/ +b0 5/ +b0 6/ +b0 7/ +b0 8/ +b0 9/ +b0 :/ +sHdlNone\x20(0) ;/ +sGeneric\x20(0) / +b0 ?/ +sPhantomConst(\"0..=16\") @/ +b0 A/ +0B/ +0C/ +b0 D/ +b0 E/ +b0 F/ +b0 G/ +b0 H/ +b0 I/ +b0 J/ +b0 K/ +b0 L/ +b0 M/ +b0 N/ +b0 O/ +b0 P/ +b0 Q/ +b0 R/ +b0 S/ +b0 T/ +b0 U/ +b0 V/ +b0 W/ +b0 X/ +b0 Y/ +b0 Z/ +b0 [/ +b0 \/ +b0 ]/ +b0 ^/ +b0 _/ +b0 `/ +b0 a/ +b0 b/ +b0 c/ +sHdlNone\x20(0) d/ +b0 e/ +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) f/ +0g/ +b0 h/ +b0 i/ +b0 j/ +b0 k/ +b0 l/ +b0 m/ +b0 n/ +b0 o/ +b0 p/ +b0 q/ +b0 r/ +b0 s/ +b0 t/ +b0 u/ +b0 v/ +b0 w/ +b0 x/ +b0 y/ +b0 z/ +b0 {/ +b0 |/ +b0 }/ +b0 ~/ +b0 !0 +b0 "0 +b0 #0 +b0 $0 +b0 %0 +b0 &0 +b0 '0 +b0 (0 +b0 )0 +sHdlNone\x20(0) *0 +b0 +0 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,0 +0-0 +0.0 +0/0 +000 +010 +020 +030 +040 +050 +060 +070 +080 +090 +0:0 +0;0 +0<0 +0=0 +0>0 +0?0 +0@0 +0A0 +0B0 +0C0 +0D0 +0E0 +0F0 +0G0 +0H0 +0I0 +0J0 +0K0 +0L0 +0M0 +b0 N0 +b0 O0 +sStart\x20(0) P0 +sHdlNone\x20(0) Q0 +sGeneric\x20(0) R0 +b0 S0 +b0 T0 +b0 U0 +b0 V0 +b0 W0 +b0 X0 +b0 Y0 +b0 Z0 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) [0 +b0 \0 +b0 ]0 +sStart\x20(0) ^0 +sHdlNone\x20(0) _0 +sGeneric\x20(0) `0 +b0 a0 +b0 b0 +b0 c0 +b0 d0 +b0 e0 +b0 f0 +b0 g0 +b0 h0 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) i0 +b0 j0 +b0 k0 +sStart\x20(0) l0 +sHdlNone\x20(0) m0 +sGeneric\x20(0) n0 +b0 o0 +b0 p0 +b0 q0 +b0 r0 +b0 s0 +b0 t0 +b0 u0 +b0 v0 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) w0 +b0 x0 +b0 y0 +sStart\x20(0) z0 +sHdlNone\x20(0) {0 +sGeneric\x20(0) |0 +b0 }0 +b0 ~0 +b0 !1 +b0 "1 +b0 #1 +b0 $1 +b0 %1 +b0 &1 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) '1 +b0 (1 +b0 )1 +sStart\x20(0) *1 +sHdlNone\x20(0) +1 +sGeneric\x20(0) ,1 +b0 -1 +b0 .1 +b0 /1 +b0 01 +b0 11 +b0 21 +b0 31 +b0 41 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 51 +b0 61 +b0 71 +sStart\x20(0) 81 +sHdlNone\x20(0) 91 +sGeneric\x20(0) :1 +b0 ;1 +b0 <1 +b0 =1 +b0 >1 +b0 ?1 +b0 @1 +b0 A1 +b0 B1 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) C1 +b0 D1 +b0 E1 +sStart\x20(0) F1 +sHdlNone\x20(0) G1 +sGeneric\x20(0) H1 +b0 I1 +b0 J1 +b0 K1 +b0 L1 +b0 M1 +b0 N1 +b0 O1 +b0 P1 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) Q1 +b0 R1 +b0 S1 +sStart\x20(0) T1 +sHdlNone\x20(0) U1 +sGeneric\x20(0) V1 +b0 W1 +b0 X1 +b0 Y1 +b0 Z1 +b0 [1 +b0 \1 +b0 ]1 +b0 ^1 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) _1 +b0 `1 +b0 a1 +sStart\x20(0) b1 +sHdlNone\x20(0) c1 +sGeneric\x20(0) d1 +b0 e1 +b0 f1 +b0 g1 +b0 h1 +b0 i1 +b0 j1 +b0 k1 +b0 l1 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) m1 +b0 n1 +b0 o1 +sStart\x20(0) p1 +sHdlNone\x20(0) q1 +sGeneric\x20(0) r1 +b0 s1 +b0 t1 +b0 u1 +b0 v1 +b0 w1 +b0 x1 +b0 y1 +b0 z1 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) {1 +b0 |1 +b0 }1 +sStart\x20(0) ~1 +sHdlNone\x20(0) !2 +sGeneric\x20(0) "2 +b0 #2 +b0 $2 +b0 %2 +b0 &2 +b0 '2 +b0 (2 +b0 )2 +b0 *2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +2 +b0 ,2 +b0 -2 +sStart\x20(0) .2 +sHdlNone\x20(0) /2 +sGeneric\x20(0) 02 +b0 12 +b0 22 +b0 32 +b0 42 +b0 52 +b0 62 +b0 72 +b0 82 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) 92 +b0 :2 +b0 ;2 +sStart\x20(0) <2 +sHdlNone\x20(0) =2 +sGeneric\x20(0) >2 +b0 ?2 +b0 @2 +b0 A2 +b0 B2 +b0 C2 +b0 D2 +b0 E2 +b0 F2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) G2 +b0 H2 +b0 I2 +sStart\x20(0) J2 +sHdlNone\x20(0) K2 +sGeneric\x20(0) L2 +b0 M2 +b0 N2 +b0 O2 +b0 P2 +b0 Q2 +b0 R2 +b0 S2 +b0 T2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) U2 +b0 V2 +b0 W2 +sStart\x20(0) X2 +sHdlNone\x20(0) Y2 +sGeneric\x20(0) Z2 +b0 [2 +b0 \2 +b0 ]2 +b0 ^2 +b0 _2 +b0 `2 +b0 a2 +b0 b2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) c2 +b0 d2 +b0 e2 +sStart\x20(0) f2 +sHdlNone\x20(0) g2 +sGeneric\x20(0) h2 +b0 i2 +b0 j2 +b0 k2 +b0 l2 +b0 m2 +b0 n2 +b0 o2 +b0 p2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) q2 +b0 r2 +sPhantomConst(\"0..=16\") s2 +b0 t2 +b0 u2 +sHdlNone\x20(0) v2 +b0 w2 +sPhantomConst(\"0..4\") x2 +sHdlNone\x20(0) y2 +b0 z2 +sPhantomConst(\"0..4\") {2 +sHdlNone\x20(0) |2 +sGeneric\x20(0) }2 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ~2 +b0 !3 +b0 "3 +sHdlNone\x20(0) #3 +b0 $3 +sPhantomConst(\"0..4\") %3 +sHdlNone\x20(0) &3 +b0 '3 +sPhantomConst(\"0..4\") (3 +sHdlNone\x20(0) )3 +sGeneric\x20(0) *3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) +3 +b0 ,3 +sPhantomConst(\"0..=2\") -3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) .3 +0/3 +103 +sHdlNone\x20(0) 13 +sRead\x20(0) 23 +b0 33 +b0 43 +b0 53 +b0 63 +b0 73 +b0 83 +b0 93 +b0 :3 +b0 ;3 +b0 <3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) =3 +0>3 +sHdlNone\x20(0) ?3 +sSuccess\x20(0) @3 +sRead\x20(0) A3 +sGeneric\x20(0) B3 +b0 C3 +b0 D3 +b0 E3 +b0 F3 +b0 G3 +b0 H3 +b0 I3 +b0 J3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) K3 +0L3 +sHdlNone\x20(0) M3 +b0 N3 +b0 O3 +b0 P3 +b0 Q3 +b0 R3 +b0 S3 +b0 T3 +b0 U3 +b0 V3 +b0 W3 +b0 X3 +b0 Y3 +b0 Z3 +b0 [3 +b0 \3 +b0 ]3 +b0 ^3 +sPhantomConst(\"0..=16\") _3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) `3 +sHdlSome\x20(1) a3 +b1000000000000 b3 +b0 c3 +0d3 +sHdlNone\x20(0) e3 +b0 f3 +sPhantomConst(\"1..=16\") g3 +0h3 +sHdlNone\x20(0) i3 +b0 j3 +b0 k3 +b0 l3 +b0 m3 +b0 n3 +b0 o3 +b0 p3 +b0 q3 +b0 r3 +b0 s3 +b0 t3 +b0 u3 +b0 v3 +b0 w3 +b0 x3 +b0 y3 +b0 z3 +sPhantomConst(\"0..=16\") {3 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) |3 +sHdlNone\x20(0) }3 +b0 ~3 +b0 !4 +b0 "4 +b0 #4 +b0 $4 +b0 %4 +b0 &4 +b0 '4 +b0 (4 +b0 )4 +sHdlNone\x20(0) *4 +sGeneric\x20(0) +4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ,4 +1-4 +sHdlNone\x20(0) .4 +b0 /4 +sPhantomConst(\"1..=16\") 04 +014 +124 +sHdlNone\x20(0) 34 +sRead\x20(0) 44 +b0 54 +b0 64 +b0 74 +b0 84 +b0 94 +b0 :4 +b0 ;4 +b0 <4 +b0 =4 +b0 >4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ?4 +0@4 +sHdlNone\x20(0) A4 +sSuccess\x20(0) B4 +sRead\x20(0) C4 +sGeneric\x20(0) D4 +b0 E4 +b0 F4 +b0 G4 +b0 H4 +b0 I4 +b0 J4 +b0 K4 +b0 L4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) M4 +0N4 +sHdlNone\x20(0) O4 +b0 P4 +b0 Q4 +b0 R4 +b0 S4 +b0 T4 +b0 U4 +b0 V4 +b0 W4 +b0 X4 +b0 Y4 +b0 Z4 +b0 [4 +b0 \4 +b0 ]4 +b0 ^4 +b0 _4 +b0 `4 +sPhantomConst(\"0..=16\") a4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) b4 +sHdlSome\x20(1) c4 +b1000000000000 d4 +b0 e4 +0f4 +sHdlNone\x20(0) g4 +b0 h4 +sPhantomConst(\"1..=16\") i4 +0j4 +sHdlNone\x20(0) k4 +b0 l4 +b0 m4 +b0 n4 +b0 o4 +b0 p4 +b0 q4 +b0 r4 +b0 s4 +b0 t4 +b0 u4 +b0 v4 +b0 w4 +b0 x4 +b0 y4 +b0 z4 +b0 {4 +b0 |4 +sPhantomConst(\"0..=16\") }4 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) ~4 +sHdlNone\x20(0) !5 +b0 "5 +b0 #5 +b0 $5 +b0 %5 +b0 &5 +b0 '5 +b0 (5 +b0 )5 +b0 *5 +b0 +5 +sHdlNone\x20(0) ,5 +sGeneric\x20(0) -5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) .5 +1/5 +sHdlNone\x20(0) 05 +b0 15 +sPhantomConst(\"1..=16\") 25 +035 +145 +sHdlNone\x20(0) 55 +sRead\x20(0) 65 +b0 75 +b0 85 +b0 95 +b0 :5 +b0 ;5 +b0 <5 +b0 =5 +b0 >5 +b0 ?5 +b0 @5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) A5 +0B5 +sHdlNone\x20(0) C5 +sSuccess\x20(0) D5 +sRead\x20(0) E5 +sGeneric\x20(0) F5 +b0 G5 +b0 H5 +b0 I5 +b0 J5 +b0 K5 +b0 L5 +b0 M5 +b0 N5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) O5 +0P5 +sHdlNone\x20(0) Q5 +b0 R5 +b0 S5 +b0 T5 +b0 U5 +b0 V5 +b0 W5 +b0 X5 +b0 Y5 +b0 Z5 +b0 [5 +b0 \5 +b0 ]5 +b0 ^5 +b0 _5 +b0 `5 +b0 a5 +b0 b5 +sPhantomConst(\"0..=16\") c5 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) d5 +b0 e5 +b0 f5 +b0 g5 +b0 h5 +b0 i5 +b0 j5 +b0 k5 +b0 l5 +b0 m5 +b0 n5 +b0 o5 +b0 p5 +b0 q5 +b0 r5 +b0 s5 +b0 t5 +b0 u5 +b0 v5 +b0 w5 +b0 x5 +b0 y5 +b0 z5 +b0 {5 +b0 |5 +b0 }5 +b0 ~5 +b0 !6 +b0 "6 +b0 #6 +b0 $6 +b0 %6 +b0 &6 +b0 '6 +b0 (6 +b0 )6 +b0 *6 +b0 +6 +b0 ,6 +b0 -6 +b0 .6 +b0 /6 +b0 06 +b0 16 +b0 26 +b0 36 +b0 46 +b0 56 +b0 66 +b0 76 +sPhantomConst(\"0..=16\") 86 +096 +1:6 +sHdlNone\x20(0) ;6 +sRead\x20(0) <6 +b0 =6 +b0 >6 +b0 ?6 +b0 @6 +b0 A6 +b0 B6 +b0 C6 +b0 D6 +b0 E6 +b0 F6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) G6 +0H6 +sHdlNone\x20(0) I6 +sSuccess\x20(0) J6 +sRead\x20(0) K6 +sGeneric\x20(0) L6 +b0 M6 +b0 N6 +b0 O6 +b0 P6 +b0 Q6 +b0 R6 +b0 S6 +b0 T6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) U6 +0V6 +sHdlNone\x20(0) W6 +b0 X6 +b0 Y6 +b0 Z6 +b0 [6 +b0 \6 +b0 ]6 +b0 ^6 +b0 _6 +b0 `6 +b0 a6 +b0 b6 +b0 c6 +b0 d6 +b0 e6 +b0 f6 +b0 g6 +b0 h6 +sPhantomConst(\"0..=16\") i6 +sPhantomConst({\"units\":[{\"kind\":\"AluBranch\",\"max_in_flight\":null},{\"kind\":\"AluBranch\",\"max_in_flight\":null}],\"out_reg_num_width\":4,\"fetch_width\":2,\"max_branches_per_fetch\":1,\"max_fetches_in_flight\":16,\"log2_fetch_width_in_bytes\":3,\"log2_cache_line_size_in_bytes\":5,\"log2_l1_i_cache_line_count\":4,\"l1_i_cache_max_misses_in_flight\":2,\"default_unit_max_in_flight\":8,\"rob_size\":20}) j6 +b0 k6 +b0 l6 +b0 m6 +b0 n6 +b0 o6 +b0 p6 +b0 q6 +b0 r6 +b0 s6 +b0 t6 +b0 u6 +b0 v6 +b0 w6 +b0 x6 +b0 y6 +b0 z6 +b0 {6 +b0 |6 +b0 }6 +b0 ~6 +b0 !7 +b0 "7 +b0 #7 +b0 $7 +b0 %7 +b0 &7 +b0 '7 +b0 (7 +b0 )7 +b0 *7 +b0 +7 +b0 ,7 +b0 -7 +b0 .7 +b0 /7 +b0 07 +b0 17 +b0 27 +b0 37 +b0 47 +b0 57 +b0 67 +b0 77 +b0 87 +b0 97 +b0 :7 +b0 ;7 +b0 <7 +b0 =7 +sPhantomConst(\"0..=16\") >7 +$end +1S* +1x* +1>+ +1?+ +1@+ +1A+ +1B+ +1C+ +1D+ +1E+ +1F+ +1G+ +1H+ +1I+ +1J+ +1K+ +1L+ +1M+ +1N+ +1O+ +1P+ +1Q+ +1R+ +1S+ +1T+ +1U+ +1V+ +1W+ +1X+ +1Y+ +1Z+ +1[+ +1\+ +1]+ +1^+ +1B/ +1g/ +1-0 +1.0 +1/0 +100 +110 +120 +130 +140 +150 +160 +170 +180 +190 +1:0 +1;0 +1<0 +1=0 +1>0 +1?0 +1@0 +1A0 +1B0 +1C0 +1D0 +1E0 +1F0 +1G0 +1H0 +1I0 +1J0 +1K0 +1L0 +1M0 +1` +sHdlSome\x20(1) o +1b" +sHdlSome\x20(1) q" +1`) +sHdlSome\x20(1) o) +1O. +sHdlSome\x20(1) ^. +1>3 +sHdlSome\x20(1) M3 +1@4 +sHdlSome\x20(1) O4 +1B5 +sHdlSome\x20(1) Q5 +1H6 +sHdlSome\x20(1) W6 +#500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b1 R* +b1 A/ +b0 R* +b0 A/ +#1000000 +0! +0" +0Q +0R +0S" +0T" +0Q) +0R) +0@. +0A. +0/3 +003 +014 +024 +035 +045 +096 +0:6 +#1500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b1 R* +b1 A/ +#2000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#2500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10 R* +b10 A/ +#3000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#3500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b11 R* +b11 A/ +#4000000 +0! +0Q +0S" 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+0Z+ +0[+ +0\+ +0]+ +0^+ +sReadingCacheAfterCacheMiss\x20(4) a+ +b1010 D/ +b1010011 E/ +b1100101 F/ +b1100011 G/ +b1101111 H/ +b1101110 I/ +b1100100 J/ +b100000 K/ +b1000011 L/ +b1100001 M/ +b1100011 N/ +b1101000 O/ +b1100101 P/ +b100000 Q/ +b1001100 R/ +b1101001 S/ +b1101110 T/ +b1100101 U/ +b1010 V/ +b1010100 W/ +b1100101 X/ +b1110011 Y/ +b1110100 Z/ +b1101001 [/ +b1101110 \/ +b1100111 ]/ +b101110 ^/ +b101110 _/ +b101110 `/ +b101110 a/ +b101110 b/ +b1010 c/ +sHdlSome\x20(1) d/ +b1000 e/ +0g/ +b0 "0 +b0 #0 +b0 $0 +b0 %0 +b0 &0 +b0 '0 +b0 (0 +b0 )0 +sHdlNone\x20(0) *0 +b0 +0 +0E0 +0F0 +0G0 +0H0 +0I0 +0J0 +0K0 +0L0 +0M0 +sReadingCacheAfterCacheMiss\x20(4) P0 +#58000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#58500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlSome\x20(1) ? +b1000000100000 @ +b10 A +b1010 B +b1010011 C +b1100101 D +b1100011 E +b1101111 F +b1101110 G +b1100100 H +b100000 I +1n +sHdlSome\x20(1) A" +b1000000100000 B" +b10 C" +b1010 D" +b1010011 E" +b1100101 F" +b1100011 G" +b1101111 H" +b1101110 I" +b1100100 J" +b100000 K" +1p" +sHdlSome\x20(1) C# +b1000000100000 D# +b10 E# +b1010 F# +b1010011 G# +b1100101 H# +b1100011 I# +b1101111 J# +b1101110 K# +b1100100 L# +b100000 M# +1n) +sHdlSome\x20(1) A* +b1000000100000 B* +b10 C* +b1010 D* +b1010011 E* +b1100101 F* +b1100011 G* +b1101111 H* +b1101110 I* +b1100100 J* +b100000 K* +b1000 R* +b0 U* +b0 V* +b0 W* +b0 X* +b0 Y* +b0 Z* +b0 [* +b0 \* +b0 ]* +b0 ^* +b0 _* +b0 `* +b0 a* +b0 b* +b0 c* +b0 d* +b0 e* +b0 f* +b0 g* +b0 h* +b0 i* +b0 j* +b0 k* +b0 l* +b0 m* +b0 n* +b0 o* +b0 p* +b0 q* +b0 r* +b0 s* +b0 t* +sHdlNone\x20(0) u* +b0 v* +sReturning\x20(5) a+ +b1010 d+ +b1010011 e+ +b1100101 f+ +b1100011 g+ +b1101111 h+ +b1101110 i+ +b1100100 j+ +b100000 k+ +sReadingCache\x20(1) }+ +1]. +sHdlSome\x20(1) 0/ +b1000000100000 1/ +b10 2/ +b1010 3/ +b1010011 4/ +b1100101 5/ +b1100011 6/ +b1101111 7/ +b1101110 8/ +b1100100 9/ +b100000 :/ +b1000 A/ +b0 D/ +b0 E/ +b0 F/ +b0 G/ +b0 H/ +b0 I/ +b0 J/ +b0 K/ +b0 L/ +b0 M/ +b0 N/ +b0 O/ +b0 P/ +b0 Q/ +b0 R/ +b0 S/ +b0 T/ +b0 U/ +b0 V/ +b0 W/ +b0 X/ +b0 Y/ +b0 Z/ +b0 [/ +b0 \/ +b0 ]/ +b0 ^/ +b0 _/ +b0 `/ +b0 a/ +b0 b/ +b0 c/ +sHdlNone\x20(0) d/ +b0 e/ +sReturning\x20(5) P0 +b1010 S0 +b1010011 T0 +b1100101 U0 +b1100011 V0 +b1101111 W0 +b1101110 X0 +b1100100 Y0 +b100000 Z0 +sReadingCache\x20(1) l0 +1L3 +sHdlSome\x20(1) }3 +b1000000100000 ~3 +b10 !4 +b1010 "4 +b1010011 #4 +b1100101 $4 +b1100011 %4 +b1101111 &4 +b1101110 '4 +b1100100 (4 +b100000 )4 +1N4 +sHdlSome\x20(1) !5 +b1000000100000 "5 +b10 #5 +b1010 $5 +b1010011 %5 +b1100101 &5 +b1100011 '5 +b1101111 (5 +b1101110 )5 +b1100100 *5 +b100000 +5 +1P5 +1V6 +#59000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#59500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlNone\x20(0) ? +b0 @ +b0 A +b0 B +b0 C +b0 D +b0 E +b0 F +b0 G +b0 H +b0 I +sHdlSome\x20(1) S +b10000111100000000 U +b100 ^ +sHdlNone\x20(0) A" +b0 B" +b0 C" +b0 D" +b0 E" +b0 F" +b0 G" +b0 H" +b0 I" +b0 J" +b0 K" +sHdlSome\x20(1) U" +b10000111100000000 W" +b100 `" +sHdlNone\x20(0) C# +b0 D# +b0 E# +b0 F# +b0 G# +b0 H# +b0 I# +b0 J# +b0 K# +b0 L# +b0 M# +sHdlSome\x20(1) S) +b10000111100000000 U) +b100 ^) +sHdlNone\x20(0) A* +b0 B* +b0 C* +b0 D* +b0 E* +b0 F* +b0 G* +b0 H* +b0 I* +b0 J* +b0 K* +b100000000 _+ +b11 `+ +sCacheMiss\x20(2) a+ +b0 d+ +b0 e+ +b0 f+ +b0 g+ +b0 h+ +b0 i+ +b0 j+ +b0 k+ +b10000111100000000 m+ +b100 n+ +b10001111100000000 {+ +b101 |+ +b10010111100000000 +, +b110 ,, +b10011111100000000 9, +b111 :, +b1000000000000 G, +b1000 H, +b1000000010000 U, +b1001 V, +b1000000100000 c, +b1010 d, +b1000000000000 q, +b1011 r, +b1000000010000 /- +b1100 0- +b1000000100000 =- +b1101 >- +b10000000000000 K- +b1110 L- +b1111 Z- +b10000 h- +b10001 v- +b1 -. +sHdlSome\x20(1) /. +b10000111100000000 2. +b100 3. +sHdlSome\x20(1) 4. +sHdlSome\x20(1) 7. +b10 =. +sHdlSome\x20(1) B. +b10000111100000000 D. +b100 M. +sHdlNone\x20(0) 0/ +b0 1/ +b0 2/ +b0 3/ +b0 4/ +b0 5/ +b0 6/ +b0 7/ +b0 8/ +b0 9/ +b0 :/ +b100000000 N0 +b11 O0 +sCacheMiss\x20(2) P0 +b0 S0 +b0 T0 +b0 U0 +b0 V0 +b0 W0 +b0 X0 +b0 Y0 +b0 Z0 +b10000111100000000 \0 +b100 ]0 +b10001111100000000 j0 +b101 k0 +b10010111100000000 x0 +b110 y0 +b10011111100000000 (1 +b111 )1 +b1000000000000 61 +b1000 71 +b1000000010000 D1 +b1001 E1 +b1000000100000 R1 +b1010 S1 +b1000000000000 `1 +b1011 a1 +b1000000010000 |1 +b1100 }1 +b1000000100000 ,2 +b1101 -2 +b10000000000000 :2 +b1110 ;2 +b1111 I2 +b10000 W2 +b10001 e2 +b1 z2 +sHdlSome\x20(1) |2 +b10000111100000000 !3 +b100 "3 +sHdlSome\x20(1) #3 +sHdlSome\x20(1) &3 +b10 ,3 +sHdlSome\x20(1) 13 +b10000111100000000 33 +b100 <3 +sHdlNone\x20(0) }3 +b0 ~3 +b0 !4 +b0 "4 +b0 #4 +b0 $4 +b0 %4 +b0 &4 +b0 '4 +b0 (4 +b0 )4 +sHdlSome\x20(1) 34 +b10000111100000000 54 +b100 >4 +sHdlNone\x20(0) !5 +b0 "5 +b0 #5 +b0 $5 +b0 %5 +b0 &5 +b0 '5 +b0 (5 +b0 )5 +b0 *5 +b0 +5 +sHdlSome\x20(1) 55 +b10000111100000000 75 +b100 @5 +sHdlSome\x20(1) ;6 +b10000111100000000 =6 +b100 F6 +b0 s +b11 "" +b0 u" +b11 $# +b0 s) +b11 "* +b0 b. +b11 o. +b0 Q3 +b11 ^3 +b0 S4 +b11 `4 +b0 U5 +b11 b5 +b100001000 e5 +b100010000 h5 +b100011000 k5 +b0 n5 +b0 o5 +b11 76 +b0 [6 +b11 h6 +b100001000 k6 +b100010000 n6 +b100011000 q6 +b0 t6 +b0 u6 +b11 =7 +#60000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#60500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10000111100001000 U +b10000111100001000 W" +b10000111100001000 U) +b10 -. +b1 5. +b10000111100001000 D. +b10 z2 +b1 $3 +b10000111100001000 33 +b10000111100001000 54 +b10000111100001000 75 +b10000111100001000 =6 +0` +b100 r +0b" +b100 t" +0`) +b100 r) +0O. +b100 a. +0>3 +b100 P3 +0@4 +b100 R4 +0B5 +b100 T5 +b100010000 e5 +b100011000 h5 +b10000111100000000 k5 +b100 l5 +b100 m5 +0H6 +b100 Z6 +b100010000 k6 +b100011000 n6 +b10000111100000000 q6 +b100 r6 +b100 s6 +#61000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#61500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b11 -. +b11 z2 +1` +b100 q +b0 r +b10 "" +1b" +b100 s" +b0 t" +b10 $# +1`) +b100 q) +b0 r) +b10 "* +1O. +b100 `. +b0 a. +b10 o. +1>3 +b100 O3 +b0 P3 +b10 ^3 +1@4 +b100 Q4 +b0 R4 +b10 `4 +1B5 +b100 S5 +b0 T5 +b10 b5 +b100011000 e5 +b10000111100000000 h5 +b100 i5 +b11 j5 +b0 k5 +b0 l5 +b0 m5 +b10 76 +1H6 +b100 Y6 +b0 Z6 +b10 h6 +b100011000 k6 +b10000111100000000 n6 +b100 o6 +b11 p6 +b0 q6 +b0 r6 +b0 s6 +b10 =7 +#62000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#62500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlSome\x20(1) ? +b100000000 @ +b11 A +sHdlSome\x20(1) J +b10000111100010000 U +sHdlSome\x20(1) A" +b100000000 B" +b11 C" +sHdlSome\x20(1) L" +b10000111100010000 W" +sHdlSome\x20(1) C# +b100000000 D# +b11 E# +sHdlSome\x20(1) N# +b10000111100010000 U) +sHdlSome\x20(1) A* +b100000000 B* +b11 C* +sHdlSome\x20(1) L* +sReturning\x20(5) a+ +sHdlSome\x20(1) b+ +b10000111100000000 '. +b100 (. +sHdlSome\x20(1) ). +b10 *. +b0 -. +sHdlNone\x20(0) /. +b0 2. +b0 3. +sHdlNone\x20(0) 4. +b0 5. +sHdlNone\x20(0) 7. +b1 =. +b10000111100010000 D. +sHdlSome\x20(1) 0/ +b100000000 1/ +b11 2/ +sHdlSome\x20(1) ;/ +sReturning\x20(5) P0 +sHdlSome\x20(1) Q0 +b10000111100000000 t2 +b100 u2 +sHdlSome\x20(1) v2 +b10 w2 +b0 z2 +sHdlNone\x20(0) |2 +b0 !3 +b0 "3 +sHdlNone\x20(0) #3 +b0 $3 +sHdlNone\x20(0) &3 +b1 ,3 +b10000111100010000 33 +sHdlSome\x20(1) }3 +b100000000 ~3 +b11 !4 +sHdlSome\x20(1) *4 +b10000111100010000 54 +sHdlSome\x20(1) !5 +b100000000 "5 +b11 #5 +sHdlSome\x20(1) ,5 +b10000111100010000 75 +b10000111100010000 =6 +sHdlNone\x20(0) a +sSuccess\x20(0) b +b100 p +sHdlNone\x20(0) c" +sSuccess\x20(0) d" +b100 r" +sHdlNone\x20(0) a) +sSuccess\x20(0) b) +b100 p) +sHdlNone\x20(0) P. +sSuccess\x20(0) Q. +b100 _. +sHdlNone\x20(0) ?3 +sSuccess\x20(0) @3 +b100 N3 +sHdlNone\x20(0) A4 +sSuccess\x20(0) B4 +b100 P4 +sHdlNone\x20(0) C5 +sSuccess\x20(0) D5 +b100 R5 +b10000111100000000 e5 +b100 f5 +b10 g5 +b10000111100001000 h5 +b100 j5 +sHdlNone\x20(0) I6 +sSuccess\x20(0) J6 +b100 X6 +b10000111100000000 k6 +b100 l6 +b10 m6 +b10000111100001000 n6 +b100 p6 +#63000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#63500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlNone\x20(0) ? +b0 @ +b0 A +sHdlNone\x20(0) J +b10000111100011000 U +sHdlNone\x20(0) A" +b0 B" +b0 C" +sHdlNone\x20(0) L" +b10000111100011000 W" +sHdlNone\x20(0) C# +b0 D# +b0 E# +sHdlNone\x20(0) N# +b10000111100011000 U) +sHdlNone\x20(0) A* +b0 B* +b0 C* +sHdlNone\x20(0) L* +b10000111100000000 _+ +b100 `+ +sCacheMiss\x20(2) a+ +sHdlNone\x20(0) b+ +b10001111100000000 m+ +b101 n+ +b10010111100000000 {+ +b110 |+ +b10011111100000000 +, +b111 ,, +b1000000000000 9, +b1000 :, +b1000000010000 G, +b1001 H, +b1000000100000 U, +b1010 V, +b1000000000000 c, +b1011 d, +b1000000010000 !- +b1100 "- +b1000000100000 /- +b1101 0- +b10000000000000 =- +b1110 >- +b1111 L- +b10000 Z- +b10001 h- +b11 *. +b10001111100000000 2. +b101 3. +sHdlSome\x20(1) 4. +sHdlSome\x20(1) 7. +b10 =. +b10000111100011000 D. +sHdlNone\x20(0) 0/ +b0 1/ +b0 2/ +sHdlNone\x20(0) ;/ +b10000111100000000 N0 +b100 O0 +sCacheMiss\x20(2) P0 +sHdlNone\x20(0) Q0 +b10001111100000000 \0 +b101 ]0 +b10010111100000000 j0 +b110 k0 +b10011111100000000 x0 +b111 y0 +b1000000000000 (1 +b1000 )1 +b1000000010000 61 +b1001 71 +b1000000100000 D1 +b1010 E1 +b1000000000000 R1 +b1011 S1 +b1000000010000 n1 +b1100 o1 +b1000000100000 |1 +b1101 }1 +b10000000000000 ,2 +b1110 -2 +b1111 ;2 +b10000 I2 +b10001 W2 +b11 w2 +b10001111100000000 !3 +b101 "3 +sHdlSome\x20(1) #3 +sHdlSome\x20(1) &3 +b10 ,3 +b10000111100011000 33 +sHdlNone\x20(0) }3 +b0 ~3 +b0 !4 +sHdlNone\x20(0) *4 +b10000111100011000 54 +sHdlNone\x20(0) !5 +b0 "5 +b0 #5 +sHdlNone\x20(0) ,5 +b10000111100011000 75 +b10000111100011000 =6 +b100 r +b11 "" +b100 t" +b11 $# +b100 r) +b11 "* +b100 a. +b11 o. +b100 P3 +b11 ^3 +b100 R4 +b11 `4 +b100 T5 +b11 b5 +b1 g5 +b11 j5 +b10000111100010000 k5 +b100 l5 +b100 m5 +b11 76 +b100 Z6 +b11 h6 +b1 m6 +b11 p6 +b10000111100010000 q6 +b100 r6 +b100 s6 +b11 =7 +#64000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#64500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10001111100000000 U +b101 ^ +b10001111100000000 W" +b101 `" +b10001111100000000 U) +b101 ^) +sHdlNone\x20(0) ). +b0 *. +b10001111100000000 D. +b101 M. +sHdlNone\x20(0) v2 +b0 w2 +b10001111100000000 33 +b101 <3 +b10001111100000000 54 +b101 >4 +b10001111100000000 75 +b101 @5 +b10001111100000000 =6 +b101 F6 +sHdlSome\x20(1) a +sError\x20(1) b +b100 s +b100 "" +sHdlSome\x20(1) c" +sError\x20(1) d" +b100 u" +b100 $# +sHdlSome\x20(1) a) +sError\x20(1) b) +b100 s) +b100 "* +sHdlSome\x20(1) P. +sError\x20(1) Q. +b100 b. +b100 o. +sHdlSome\x20(1) ?3 +sError\x20(1) @3 +b100 Q3 +b100 ^3 +sHdlSome\x20(1) A4 +sError\x20(1) B4 +b100 S4 +b100 `4 +sHdlSome\x20(1) C5 +sError\x20(1) D5 +b100 U5 +b100 b5 +b0 g5 +b10 j5 +b11 m5 +b10000111100011000 n5 +b100 o5 +b100 p5 +b100 76 +sHdlSome\x20(1) I6 +sError\x20(1) J6 +b100 [6 +b100 h6 +b0 m6 +b10 p6 +b11 s6 +b10000111100011000 t6 +b100 u6 +b100 v6 +b100 =7 +#65000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#65500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10001111100001000 U +b10001111100001000 W" +b10001111100001000 U) +b1 -. +sHdlSome\x20(1) /. +b1 5. +b10001111100001000 D. +b1 z2 +sHdlSome\x20(1) |2 +b1 $3 +b10001111100001000 33 +b10001111100001000 54 +b10001111100001000 75 +b10001111100001000 =6 +sHdlNone\x20(0) a +sSuccess\x20(0) b +b101 s +sHdlNone\x20(0) c" +sSuccess\x20(0) d" +b101 u" +sHdlNone\x20(0) a) +sSuccess\x20(0) b) +b101 s) +sHdlNone\x20(0) P. +sSuccess\x20(0) Q. +b101 b. +sHdlNone\x20(0) ?3 +sSuccess\x20(0) @3 +b101 Q3 +sHdlNone\x20(0) A4 +sSuccess\x20(0) B4 +b101 S4 +sHdlNone\x20(0) C5 +sSuccess\x20(0) D5 +b101 U5 +b10000111100001000 e5 +b1 g5 +b10000111100010000 h5 +b10000111100011000 k5 +b10001111100000000 n5 +b101 o5 +sHdlNone\x20(0) I6 +sSuccess\x20(0) J6 +b101 [6 +b10000111100001000 k6 +b1 m6 +b10000111100010000 n6 +b10000111100011000 q6 +b10001111100000000 t6 +b101 u6 +#66000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#66500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10001111100010000 U +b10001111100010000 W" +b10001111100010000 U) +b10 5. +b10001111100010000 D. +b10 $3 +b10001111100010000 33 +b10001111100010000 54 +b10001111100010000 75 +b10001111100010000 =6 +sHdlSome\x20(1) a +sError\x20(1) b +b101 t +b101 "" +sHdlSome\x20(1) c" +sError\x20(1) d" +b101 v" +b101 $# +sHdlSome\x20(1) a) +sError\x20(1) b) +b101 t) +b101 "* +sHdlSome\x20(1) P. +sError\x20(1) Q. +b101 c. +b101 o. +sHdlSome\x20(1) ?3 +sError\x20(1) @3 +b101 R3 +b101 ^3 +sHdlSome\x20(1) A4 +sError\x20(1) B4 +b101 T4 +b101 `4 +sHdlSome\x20(1) C5 +sError\x20(1) D5 +b101 V5 +b101 b5 +b0 g5 +b1 j5 +b10 m5 +b11 p5 +b10001111100001000 q5 +b101 r5 +b100 s5 +b101 76 +sHdlSome\x20(1) I6 +sError\x20(1) J6 +b101 \6 +b101 h6 +b0 m6 +b1 p6 +b10 s6 +b11 v6 +b10001111100001000 w6 +b101 x6 +b100 y6 +b101 =7 +#67000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#67500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10001111100011000 U +b10001111100011000 W" +b10001111100011000 U) +b10 -. +b11 5. +b10001111100011000 D. +b10 z2 +b11 $3 +b10001111100011000 33 +b10001111100011000 54 +b10001111100011000 75 +b10001111100011000 =6 +b101 r +b101 t" +b101 r) +b101 a. +b101 P3 +b101 R4 +b101 T5 +b10000111100010000 e5 +b10000111100011000 h5 +b10001111100000000 k5 +b101 l5 +b10001111100001000 n5 +b10001111100010000 q5 +b101 Z6 +b10000111100010000 k6 +b10000111100011000 n6 +b10001111100000000 q6 +b101 r6 +b10001111100001000 t6 +b10001111100010000 w6 +#68000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#68500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlNone\x20(0) S +b0 U +b0 ^ +sHdlNone\x20(0) U" +b0 W" +b0 `" +sHdlNone\x20(0) S) +b0 U) +b0 ^) +b11 -. +sHdlNone\x20(0) 4. +b0 5. +sHdlNone\x20(0) B. +b0 D. +b0 M. +b11 z2 +sHdlNone\x20(0) #3 +b0 $3 +sHdlNone\x20(0) 13 +b0 33 +b0 <3 +sHdlNone\x20(0) 34 +b0 54 +b0 >4 +sHdlNone\x20(0) 55 +b0 75 +b0 @5 +sHdlNone\x20(0) ;6 +b0 =6 +b0 F6 +b101 q +b101 s" +b101 q) +b101 `. +b101 O3 +b101 Q4 +b101 S5 +b10000111100011000 e5 +b10001111100000000 h5 +b101 i5 +b10001111100001000 k5 +b10001111100010000 n5 +b10001111100011000 q5 +b101 Y6 +b10000111100011000 k6 +b10001111100000000 n6 +b101 o6 +b10001111100001000 q6 +b10001111100010000 t6 +b10001111100011000 w6 +#69000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#69500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlSome\x20(1) ? +b10000111100000000 @ +b100 A +sHdlSome\x20(1) J +sHdlSome\x20(1) A" +b10000111100000000 B" +b100 C" +sHdlSome\x20(1) L" +sHdlSome\x20(1) C# +b10000111100000000 D# +b100 E# +sHdlSome\x20(1) N# +sHdlSome\x20(1) A* +b10000111100000000 B* +b100 C* +sHdlSome\x20(1) L* +sReturning\x20(5) a+ +sHdlSome\x20(1) b+ +b10001111100000000 '. +b101 (. +b0 -. +sHdlNone\x20(0) /. +b0 2. +b0 3. +sHdlNone\x20(0) 7. +b1 =. +sHdlSome\x20(1) 0/ +b10000111100000000 1/ +b100 2/ +sHdlSome\x20(1) ;/ +sReturning\x20(5) P0 +sHdlSome\x20(1) Q0 +b10001111100000000 t2 +b101 u2 +b0 z2 +sHdlNone\x20(0) |2 +b0 !3 +b0 "3 +sHdlNone\x20(0) &3 +b1 ,3 +sHdlSome\x20(1) }3 +b10000111100000000 ~3 +b100 !4 +sHdlSome\x20(1) *4 +sHdlSome\x20(1) !5 +b10000111100000000 "5 +b100 #5 +sHdlSome\x20(1) ,5 +sSuccess\x20(0) b +b11111111 e +b11111111 f +b11111111 g +b11111111 h +b11111111 i +b11111111 j +b11111111 k +b11111111 l +b101 p +b0 t +b100 "" +sSuccess\x20(0) d" +b11111111 g" +b11111111 h" +b11111111 i" +b11111111 j" +b11111111 k" +b11111111 l" +b11111111 m" +b11111111 n" +b101 r" +b0 v" +b100 $# +sSuccess\x20(0) b) +b11111111 e) +b11111111 f) +b11111111 g) +b11111111 h) +b11111111 i) +b11111111 j) +b11111111 k) +b11111111 l) +b101 p) +b0 t) +b100 "* +sSuccess\x20(0) Q. +b11111111 T. +b11111111 U. +b11111111 V. +b11111111 W. +b11111111 X. +b11111111 Y. +b11111111 Z. +b11111111 [. +b101 _. +b0 c. +b100 o. +sSuccess\x20(0) @3 +b11111111 C3 +b11111111 D3 +b11111111 E3 +b11111111 F3 +b11111111 G3 +b11111111 H3 +b11111111 I3 +b11111111 J3 +b101 N3 +b0 R3 +b100 ^3 +sSuccess\x20(0) B4 +b11111111 E4 +b11111111 F4 +b11111111 G4 +b11111111 H4 +b11111111 I4 +b11111111 J4 +b11111111 K4 +b11111111 L4 +b101 P4 +b0 T4 +b100 `4 +sSuccess\x20(0) D5 +b11111111 G5 +b11111111 H5 +b11111111 I5 +b11111111 J5 +b11111111 K5 +b11111111 L5 +b11111111 M5 +b11111111 N5 +b101 R5 +b0 V5 +b100 b5 +b10001111100000000 e5 +b101 f5 +b10001111100001000 h5 +b10001111100010000 k5 +b10001111100011000 n5 +b0 q5 +b0 r5 +b0 s5 +b100 76 +sSuccess\x20(0) J6 +b11111111 M6 +b11111111 N6 +b11111111 O6 +b11111111 P6 +b11111111 Q6 +b11111111 R6 +b11111111 S6 +b11111111 T6 +b101 X6 +b0 \6 +b100 h6 +b10001111100000000 k6 +b101 l6 +b10001111100001000 n6 +b10001111100010000 q6 +b10001111100011000 t6 +b0 w6 +b0 x6 +b0 y6 +b100 =7 +#70000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#70500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlNone\x20(0) ? +b0 @ +b0 A +sHdlNone\x20(0) J +sHdlSome\x20(1) S +b10010111100000000 U +b110 ^ +sHdlNone\x20(0) A" +b0 B" +b0 C" +sHdlNone\x20(0) L" +sHdlSome\x20(1) U" +b10010111100000000 W" +b110 `" +sHdlNone\x20(0) C# +b0 D# +b0 E# +sHdlNone\x20(0) N# +sHdlSome\x20(1) S) +b10010111100000000 U) +b110 ^) +sHdlNone\x20(0) A* +b0 B* +b0 C* +sHdlNone\x20(0) L* +1x* +b11111111 y* +b11111111 z* +b11111111 {* +b11111111 |* +b11111111 }* +b11111111 ~* +b11111111 !+ +b11111111 "+ +1>+ +1?+ +1@+ +1A+ +1B+ +1C+ +1D+ +1E+ +1^+ +b10001111100000000 _+ +b101 `+ +sCacheMiss\x20(2) a+ +sHdlNone\x20(0) b+ +b10010111100000000 m+ +b110 n+ +b10011111100000000 {+ +b111 |+ +sStart\x20(0) }+ +b1000000000000 +, +b1000 ,, +b1000000010000 9, +b1001 :, +b1000000100000 G, +b1010 H, +b1000000000000 U, +b1011 V, +b1000000010000 q, +b1100 r, +b1000000100000 !- +b1101 "- +b10000000000000 /- +b1110 0- +b1111 >- +b10000 L- +b10001 Z- +b1 -. +b10010111100000000 2. +b110 3. +sHdlSome\x20(1) 4. +sHdlSome\x20(1) 7. +b10 =. +sHdlSome\x20(1) B. +b10010111100000000 D. +b110 M. +sHdlNone\x20(0) 0/ +b0 1/ +b0 2/ +sHdlNone\x20(0) ;/ +1g/ +b11111111 h/ +b11111111 i/ +b11111111 j/ +b11111111 k/ +b11111111 l/ +b11111111 m/ +b11111111 n/ +b11111111 o/ +1-0 +1.0 +1/0 +100 +110 +120 +130 +140 +1M0 +b10001111100000000 N0 +b101 O0 +sCacheMiss\x20(2) P0 +sHdlNone\x20(0) Q0 +b10010111100000000 \0 +b110 ]0 +b10011111100000000 j0 +b111 k0 +sStart\x20(0) l0 +b1000000000000 x0 +b1000 y0 +b1000000010000 (1 +b1001 )1 +b1000000100000 61 +b1010 71 +b1000000000000 D1 +b1011 E1 +b1000000010000 `1 +b1100 a1 +b1000000100000 n1 +b1101 o1 +b10000000000000 |1 +b1110 }1 +b1111 -2 +b10000 ;2 +b10001 I2 +b1 z2 +b10010111100000000 !3 +b110 "3 +sHdlSome\x20(1) #3 +sHdlSome\x20(1) &3 +b10 ,3 +sHdlSome\x20(1) 13 +b10010111100000000 33 +b110 <3 +sHdlNone\x20(0) }3 +b0 ~3 +b0 !4 +sHdlNone\x20(0) *4 +sHdlSome\x20(1) 34 +b10010111100000000 54 +b110 >4 +sHdlNone\x20(0) !5 +b0 "5 +b0 #5 +sHdlNone\x20(0) ,5 +sHdlSome\x20(1) 55 +b10010111100000000 75 +b110 @5 +sHdlSome\x20(1) ;6 +b10010111100000000 =6 +b110 F6 +sError\x20(1) b +b0 e +b0 f +b0 g +b0 h +b0 i +b0 j +b0 k +b0 l +b0 s +b11 "" +sError\x20(1) d" +b0 g" +b0 h" +b0 i" +b0 j" +b0 k" +b0 l" +b0 m" +b0 n" +b0 u" +b11 $# +sError\x20(1) b) +b0 e) +b0 f) +b0 g) +b0 h) +b0 i) +b0 j) +b0 k) +b0 l) +b0 s) +b11 "* +sError\x20(1) Q. +b0 T. +b0 U. +b0 V. +b0 W. +b0 X. +b0 Y. +b0 Z. +b0 [. +b0 b. +b11 o. +sError\x20(1) @3 +b0 C3 +b0 D3 +b0 E3 +b0 F3 +b0 G3 +b0 H3 +b0 I3 +b0 J3 +b0 Q3 +b11 ^3 +sError\x20(1) B4 +b0 E4 +b0 F4 +b0 G4 +b0 H4 +b0 I4 +b0 J4 +b0 K4 +b0 L4 +b0 S4 +b11 `4 +sError\x20(1) D5 +b0 G5 +b0 H5 +b0 I5 +b0 J5 +b0 K5 +b0 L5 +b0 M5 +b0 N5 +b0 U5 +b11 b5 +b10001111100001000 e5 +b10001111100010000 h5 +b10001111100011000 k5 +b0 n5 +b0 o5 +b0 p5 +b11 76 +sError\x20(1) J6 +b0 M6 +b0 N6 +b0 O6 +b0 P6 +b0 Q6 +b0 R6 +b0 S6 +b0 T6 +b0 [6 +b11 h6 +b10001111100001000 k6 +b10001111100010000 n6 +b10001111100011000 q6 +b0 t6 +b0 u6 +b0 v6 +b11 =7 +#71000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#71500000 +1! +1Q +1S" +b11111111 S& +b11111111 T& +b11111111 U& +b11111111 V& +b11111111 W& +b11111111 X& +b11111111 Y& +b11111111 Z& +1Q) +1@. +1/3 +114 +135 +196 +b10010111100001000 U +b10010111100001000 W" +b10010111100001000 U) +b11111111 U* +b11111111 V* +b11111111 W* +b11111111 X* +b11111111 Y* +b11111111 Z* +b11111111 [* +b11111111 \* +0x* +b0 y* +b0 z* +b0 {* +b0 |* +b0 }* +b0 ~* +b0 !+ +b0 "+ +0>+ +0?+ +0@+ +0A+ +0B+ +0C+ +0D+ +0E+ +0^+ +sReadingCache\x20(1) }+ +b10 -. +sHdlSome\x20(1) /. +b1 5. +b10010111100001000 D. +b11111111 D/ +b11111111 E/ +b11111111 F/ +b11111111 G/ +b11111111 H/ +b11111111 I/ +b11111111 J/ +b11111111 K/ +0g/ +b0 h/ +b0 i/ +b0 j/ +b0 k/ +b0 l/ +b0 m/ +b0 n/ +b0 o/ +0-0 +0.0 +0/0 +000 +010 +020 +030 +040 +0M0 +sReadingCache\x20(1) l0 +b10 z2 +sHdlSome\x20(1) |2 +b1 $3 +b10010111100001000 33 +b10010111100001000 54 +b10010111100001000 75 +b10010111100001000 =6 +b110 r +b110 t" +b110 r) +b110 a. +b110 P3 +b110 R4 +b110 T5 +b10001111100010000 e5 +b10001111100011000 h5 +b10010111100000000 k5 +b110 l5 +b100 m5 +b110 Z6 +b10001111100010000 k6 +b10001111100011000 n6 +b10010111100000000 q6 +b110 r6 +b100 s6 +#72000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#72500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10010111100010000 U +b10010111100010000 W" +b10010111100010000 U) +b11 -. +b10 5. +b10010111100010000 D. +b11 z2 +b10 $3 +b10010111100010000 33 +b10010111100010000 54 +b10010111100010000 75 +b10010111100010000 =6 +b110 q +b110 s" +b110 q) +b110 `. +b110 O3 +b110 Q4 +b110 S5 +b10001111100011000 e5 +b10010111100000000 h5 +b110 i5 +b11 j5 +b10010111100001000 k5 +b110 Y6 +b10001111100011000 k6 +b10010111100000000 n6 +b110 o6 +b11 p6 +b10010111100001000 q6 +#73000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#73500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlSome\x20(1) ? +b10001111100000000 @ +b101 A +sHdlSome\x20(1) J +b10010111100011000 U +sHdlSome\x20(1) A" +b10001111100000000 B" +b101 C" +sHdlSome\x20(1) L" +b10010111100011000 W" +sHdlSome\x20(1) C# +b10001111100000000 D# +b101 E# +sHdlSome\x20(1) N# +b10010111100011000 U) +sHdlSome\x20(1) A* +b10001111100000000 B* +b101 C* +sHdlSome\x20(1) L* +sReturning\x20(5) a+ +sHdlSome\x20(1) b+ +b10010111100000000 '. +b110 (. +sHdlSome\x20(1) ). +b11 *. +b0 -. +sHdlNone\x20(0) /. +b0 2. +b0 3. +sHdlNone\x20(0) 4. +b0 5. +sHdlNone\x20(0) 7. +b1 =. +b10010111100011000 D. +sHdlSome\x20(1) 0/ +b10001111100000000 1/ +b101 2/ +sHdlSome\x20(1) ;/ +sReturning\x20(5) P0 +sHdlSome\x20(1) Q0 +b10010111100000000 t2 +b110 u2 +sHdlSome\x20(1) v2 +b11 w2 +b0 z2 +sHdlNone\x20(0) |2 +b0 !3 +b0 "3 +sHdlNone\x20(0) #3 +b0 $3 +sHdlNone\x20(0) &3 +b1 ,3 +b10010111100011000 33 +sHdlSome\x20(1) }3 +b10001111100000000 ~3 +b101 !4 +sHdlSome\x20(1) *4 +b10010111100011000 54 +sHdlSome\x20(1) !5 +b10001111100000000 "5 +b101 #5 +sHdlSome\x20(1) ,5 +b10010111100011000 75 +b10010111100011000 =6 +sHdlNone\x20(0) a +sSuccess\x20(0) b +b110 p +sHdlNone\x20(0) c" +sSuccess\x20(0) d" +b110 r" +sHdlNone\x20(0) a) +sSuccess\x20(0) b) +b110 p) +sHdlNone\x20(0) P. +sSuccess\x20(0) Q. +b110 _. +sHdlNone\x20(0) ?3 +sSuccess\x20(0) @3 +b110 N3 +sHdlNone\x20(0) A4 +sSuccess\x20(0) B4 +b110 P4 +sHdlNone\x20(0) C5 +sSuccess\x20(0) D5 +b110 R5 +b10010111100000000 e5 +b110 f5 +b10 g5 +b10010111100001000 h5 +b10010111100010000 k5 +sHdlNone\x20(0) I6 +sSuccess\x20(0) J6 +b110 X6 +b10010111100000000 k6 +b110 l6 +b10 m6 +b10010111100001000 n6 +b10010111100010000 q6 +#74000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#74500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlNone\x20(0) ? +b0 @ +b0 A +sHdlNone\x20(0) J +b10011111100000000 U +b111 ^ +sHdlNone\x20(0) A" +b0 B" +b0 C" +sHdlNone\x20(0) L" +b10011111100000000 W" +b111 `" +sHdlNone\x20(0) C# +b0 D# +b0 E# +sHdlNone\x20(0) N# +b10011111100000000 U) +b111 ^) +sHdlNone\x20(0) A* +b0 B* +b0 C* +sHdlNone\x20(0) L* +b0 R* +b1010100 U* +b1100101 V* +b1110011 W* +b1110100 X* +b100000 Y* +b1100100 Z* +b1100001 [* +b1110100 \* +b1100001 ]* +b101100 ^* +b100000 _* +b1110100 `* +b1100101 a* +b1110011 b* +b1110100 c* +b1101001 d* +b1101110 e* +b1100111 f* +b101110 g* +b101110 h* +b101110 i* +b1010 j* +b1010100 k* +b1100101 l* +b1110011 m* +b1110100 n* +b100000 o* +b1010100 p* +b1100101 q* +b1110011 r* +b1110100 s* +b100001 t* +sHdlSome\x20(1) u* +b1000 v* +b10010111100000000 _+ +b110 `+ +sCacheMiss\x20(2) a+ +sHdlNone\x20(0) b+ +b10011111100000000 m+ +b111 n+ +b1000000000000 {+ +b1000 |+ +b1000000010000 +, +b1001 ,, +b1000000100000 9, +b1010 :, +b1000000000000 G, +b1011 H, +b1000000010000 c, +b1100 d, +b1000000100000 q, +b1101 r, +b10000000000000 !- +b1110 "- +b1111 0- +b10000 >- +b10001 L- +sHdlNone\x20(0) ). +b0 *. +b10011111100000000 2. +b111 3. +sHdlSome\x20(1) 4. +sHdlSome\x20(1) 7. +b10 =. +b10011111100000000 D. +b111 M. +sHdlNone\x20(0) 0/ +b0 1/ +b0 2/ +sHdlNone\x20(0) ;/ +b0 A/ +b1010100 D/ +b1100101 E/ +b1110011 F/ +b1110100 G/ +b100000 H/ +b1100100 I/ +b1100001 J/ +b1110100 K/ +b1100001 L/ +b101100 M/ +b100000 N/ +b1110100 O/ +b1100101 P/ +b1110011 Q/ +b1110100 R/ +b1101001 S/ +b1101110 T/ +b1100111 U/ +b101110 V/ +b101110 W/ +b101110 X/ +b1010 Y/ +b1010100 Z/ +b1100101 [/ +b1110011 \/ +b1110100 ]/ +b100000 ^/ +b1010100 _/ +b1100101 `/ +b1110011 a/ +b1110100 b/ +b100001 c/ +sHdlSome\x20(1) d/ +b1000 e/ +b10010111100000000 N0 +b110 O0 +sCacheMiss\x20(2) P0 +sHdlNone\x20(0) Q0 +b10011111100000000 \0 +b111 ]0 +b1000000000000 j0 +b1000 k0 +b1000000010000 x0 +b1001 y0 +b1000000100000 (1 +b1010 )1 +b1000000000000 61 +b1011 71 +b1000000010000 R1 +b1100 S1 +b1000000100000 `1 +b1101 a1 +b10000000000000 n1 +b1110 o1 +b1111 }1 +b10000 -2 +b10001 ;2 +sHdlNone\x20(0) v2 +b0 w2 +b10011111100000000 !3 +b111 "3 +sHdlSome\x20(1) #3 +sHdlSome\x20(1) &3 +b10 ,3 +b10011111100000000 33 +b111 <3 +sHdlNone\x20(0) }3 +b0 ~3 +b0 !4 +sHdlNone\x20(0) *4 +b10011111100000000 54 +b111 >4 +sHdlNone\x20(0) !5 +b0 "5 +b0 #5 +sHdlNone\x20(0) ,5 +b10011111100000000 75 +b111 @5 +b10011111100000000 =6 +b111 F6 +b110 s +b100 "" +b110 u" +b100 $# +b110 s) +b100 "* +b110 b. +b100 o. +b110 Q3 +b100 ^3 +b110 S4 +b100 `4 +b110 U5 +b100 b5 +b1 g5 +b10 j5 +b11 m5 +b10010111100011000 n5 +b110 o5 +b100 p5 +b100 76 +b110 [6 +b100 h6 +b1 m6 +b10 p6 +b11 s6 +b10010111100011000 t6 +b110 u6 +b100 v6 +b100 =7 +#75000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#75500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10011111100001000 U +b10011111100001000 W" +b10011111100001000 U) +sReturning\x20(5) }+ +b1010100 ", +b1100101 #, +b1110011 $, +b1110100 %, +b100000 &, +b1100100 ', +b1100001 (, +b1110100 ), +sReadingCache\x20(1) -, +b1 5. +b10011111100001000 D. +sReturning\x20(5) l0 +b1010100 o0 +b1100101 p0 +b1110011 q0 +b1110100 r0 +b100000 s0 +b1100100 t0 +b1100001 u0 +b1110100 v0 +sReadingCache\x20(1) z0 +b1 $3 +b10011111100001000 33 +b10011111100001000 54 +b10011111100001000 75 +b10011111100001000 =6 +sHdlSome\x20(1) a +b11111111 e +b11111111 f +b11111111 g +b11111111 h +b11111111 i +b11111111 j +b11111111 k +b11111111 l +b111 t +b101 "" +sHdlSome\x20(1) c" +b11111111 g" +b11111111 h" +b11111111 i" +b11111111 j" +b11111111 k" +b11111111 l" +b11111111 m" +b11111111 n" +b111 v" +b101 $# +sHdlSome\x20(1) a) +b11111111 e) +b11111111 f) +b11111111 g) +b11111111 h) +b11111111 i) +b11111111 j) +b11111111 k) +b11111111 l) +b111 t) +b101 "* +sHdlSome\x20(1) P. +b11111111 T. +b11111111 U. +b11111111 V. +b11111111 W. +b11111111 X. +b11111111 Y. +b11111111 Z. +b11111111 [. +b111 c. +b101 o. +sHdlSome\x20(1) ?3 +b11111111 C3 +b11111111 D3 +b11111111 E3 +b11111111 F3 +b11111111 G3 +b11111111 H3 +b11111111 I3 +b11111111 J3 +b111 R3 +b101 ^3 +sHdlSome\x20(1) A4 +b11111111 E4 +b11111111 F4 +b11111111 G4 +b11111111 H4 +b11111111 I4 +b11111111 J4 +b11111111 K4 +b11111111 L4 +b111 T4 +b101 `4 +sHdlSome\x20(1) C5 +b11111111 G5 +b11111111 H5 +b11111111 I5 +b11111111 J5 +b11111111 K5 +b11111111 L5 +b11111111 M5 +b11111111 N5 +b111 V5 +b101 b5 +b0 g5 +b1 j5 +b10 m5 +b11 p5 +b10011111100000000 q5 +b111 r5 +b100 s5 +b101 76 +sHdlSome\x20(1) I6 +b11111111 M6 +b11111111 N6 +b11111111 O6 +b11111111 P6 +b11111111 Q6 +b11111111 R6 +b11111111 S6 +b11111111 T6 +b111 \6 +b101 h6 +b0 m6 +b1 p6 +b10 s6 +b11 v6 +b10011111100000000 w6 +b111 x6 +b100 y6 +b101 =7 +#76000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#76500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10011111100010000 U +b10011111100010000 W" +b10011111100010000 U) +b1000 R* +b0 U* +b0 V* +b0 W* +b0 X* +b0 Y* +b0 Z* +b0 [* +b0 \* +b0 ]* +b0 ^* +b0 _* +b0 `* +b0 a* +b0 b* +b0 c* +b0 d* +b0 e* +b0 f* +b0 g* +b0 h* +b0 i* +b0 j* +b0 k* +b0 l* +b0 m* +b0 n* +b0 o* +b0 p* +b0 q* +b0 r* +b0 s* +b0 t* +sHdlNone\x20(0) u* +b0 v* +1x* +b11111111 y* +b11111111 z* +b11111111 {* +b11111111 |* +b11111111 }* +b11111111 ~* +b11111111 !+ +b11111111 "+ +1>+ +1?+ +1@+ +1A+ +1B+ +1C+ +1D+ +1E+ +1^+ +sReturning\x20(5) -, +b1101110 0, +b1100111 1, +b101110 2, +b101110 3, +b101110 4, +b1010 5, +b1010100 6, +b1100101 7, +b1 -. +b10 5. +b10011111100010000 D. +b1000 A/ +b0 D/ +b0 E/ +b0 F/ +b0 G/ +b0 H/ +b0 I/ +b0 J/ +b0 K/ +b0 L/ +b0 M/ +b0 N/ +b0 O/ +b0 P/ +b0 Q/ +b0 R/ +b0 S/ +b0 T/ +b0 U/ +b0 V/ +b0 W/ +b0 X/ +b0 Y/ +b0 Z/ +b0 [/ +b0 \/ +b0 ]/ +b0 ^/ +b0 _/ +b0 `/ +b0 a/ +b0 b/ +b0 c/ +sHdlNone\x20(0) d/ +b0 e/ +1g/ +b11111111 h/ +b11111111 i/ +b11111111 j/ +b11111111 k/ +b11111111 l/ +b11111111 m/ +b11111111 n/ +b11111111 o/ +1-0 +1.0 +1/0 +100 +110 +120 +130 +140 +1M0 +sReturning\x20(5) z0 +b1101110 }0 +b1100111 ~0 +b101110 !1 +b101110 "1 +b101110 #1 +b1010 $1 +b1010100 %1 +b1100101 &1 +b1 z2 +b10 $3 +b10011111100010000 33 +b10011111100010000 54 +b10011111100010000 75 +b10011111100010000 =6 +sError\x20(1) b +b0 e +b0 f +b0 g +b0 h +b0 i +b0 j +b0 k +b0 l +b111 s +sError\x20(1) d" +b0 g" +b0 h" +b0 i" +b0 j" +b0 k" +b0 l" +b0 m" +b0 n" +b111 u" +sError\x20(1) b) +b0 e) +b0 f) +b0 g) +b0 h) +b0 i) +b0 j) +b0 k) +b0 l) +b111 s) +sError\x20(1) Q. +b0 T. +b0 U. +b0 V. +b0 W. +b0 X. +b0 Y. +b0 Z. +b0 [. +b111 b. +sError\x20(1) @3 +b0 C3 +b0 D3 +b0 E3 +b0 F3 +b0 G3 +b0 H3 +b0 I3 +b0 J3 +b111 Q3 +sError\x20(1) B4 +b0 E4 +b0 F4 +b0 G4 +b0 H4 +b0 I4 +b0 J4 +b0 K4 +b0 L4 +b111 S4 +sError\x20(1) D5 +b0 G5 +b0 H5 +b0 I5 +b0 J5 +b0 K5 +b0 L5 +b0 M5 +b0 N5 +b111 U5 +b10010111100001000 e5 +b10010111100010000 h5 +b10010111100011000 k5 +b10011111100000000 n5 +b111 o5 +b10011111100001000 q5 +sError\x20(1) J6 +b0 M6 +b0 N6 +b0 O6 +b0 P6 +b0 Q6 +b0 R6 +b0 S6 +b0 T6 +b111 [6 +b10010111100001000 k6 +b10010111100010000 n6 +b10010111100011000 q6 +b10011111100000000 t6 +b111 u6 +b10011111100001000 w6 +#77000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#77500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10011111100011000 U +b10011111100011000 W" +b10011111100011000 U) +b1 R* +b1010 U* +b1010011 V* +b1100101 W* +b1100011 X* +b1101111 Y* +b1101110 Z* +b1100100 [* +b100000 \* +b1000011 ]* +b1100001 ^* +b1100011 _* +b1101000 `* +b1100101 a* +b100000 b* +b1001100 c* +b1101001 d* +b1101110 e* +b1100101 f* +b1010 g* +b1010100 h* +b1100101 i* +b1110011 j* +b1110100 k* +b1101001 l* +b1101110 m* +b1100111 n* +b101110 o* +b101110 p* +b101110 q* +b101110 r* +b101110 s* +b1010 t* +sHdlSome\x20(1) u* +b1000 v* +0x* +b0 y* +b0 z* +b0 {* +b0 |* +b0 }* +b0 ~* +b0 !+ +b0 "+ +0>+ +0?+ +0@+ +0A+ +0B+ +0C+ +0D+ +0E+ +0^+ +sReadingCache\x20(1) ;, +b10 -. +sHdlSome\x20(1) /. +b11 5. +b10011111100011000 D. +b1 A/ +b1010 D/ +b1010011 E/ +b1100101 F/ +b1100011 G/ +b1101111 H/ +b1101110 I/ +b1100100 J/ +b100000 K/ +b1000011 L/ +b1100001 M/ +b1100011 N/ +b1101000 O/ +b1100101 P/ +b100000 Q/ +b1001100 R/ +b1101001 S/ +b1101110 T/ +b1100101 U/ +b1010 V/ +b1010100 W/ +b1100101 X/ +b1110011 Y/ +b1110100 Z/ +b1101001 [/ +b1101110 \/ +b1100111 ]/ +b101110 ^/ +b101110 _/ +b101110 `/ +b101110 a/ +b101110 b/ +b1010 c/ +sHdlSome\x20(1) d/ +b1000 e/ +0g/ +b0 h/ +b0 i/ +b0 j/ +b0 k/ +b0 l/ +b0 m/ +b0 n/ +b0 o/ +0-0 +0.0 +0/0 +000 +010 +020 +030 +040 +0M0 +sReadingCache\x20(1) *1 +b10 z2 +sHdlSome\x20(1) |2 +b11 $3 +b10011111100011000 33 +b10011111100011000 54 +b10011111100011000 75 +b10011111100011000 =6 +b111 r +b111 t" +b111 r) +b111 a. +b111 P3 +b111 R4 +b111 T5 +b10010111100010000 e5 +b10010111100011000 h5 +b10011111100000000 k5 +b111 l5 +b10011111100001000 n5 +b10011111100010000 q5 +b111 Z6 +b10010111100010000 k6 +b10010111100011000 n6 +b10011111100000000 q6 +b111 r6 +b10011111100001000 t6 +b10011111100010000 w6 +#78000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#78500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlNone\x20(0) S +b0 U +b0 ^ +sHdlNone\x20(0) U" +b0 W" +b0 `" +sHdlNone\x20(0) S) +b0 U) +b0 ^) +b0 R* +b1010100 U* +b1100101 V* +b1110011 W* +b1110100 X* +b100000 Y* +b1100100 Z* +b1100001 [* +b1110100 \* +b1100001 ]* +b101100 ^* +b100000 _* +b1110100 `* +b1110011 b* +b1110100 c* +b1100111 f* +b101110 g* +b101110 h* +b101110 i* +b1010 j* +b1010100 k* +b1100101 l* +b1110011 m* +b1110100 n* +b100000 o* +b1010100 p* +b1100101 q* +b1110011 r* +b1110100 s* +b100001 t* +sReturning\x20(5) ;, +b1010 >, +b1010011 ?, +b1100101 @, +b1100011 A, +b1101111 B, +b1101110 C, +b1100100 D, +b100000 E, +sReadingCache\x20(1) I, +b11 -. +sHdlNone\x20(0) 4. +b0 5. +sHdlNone\x20(0) B. +b0 D. +b0 M. +b0 A/ +b1010100 D/ +b1100101 E/ +b1110011 F/ +b1110100 G/ +b100000 H/ +b1100100 I/ +b1100001 J/ +b1110100 K/ +b1100001 L/ +b101100 M/ +b100000 N/ +b1110100 O/ +b1110011 Q/ +b1110100 R/ +b1100111 U/ +b101110 V/ +b101110 W/ +b101110 X/ +b1010 Y/ +b1010100 Z/ +b1100101 [/ +b1110011 \/ +b1110100 ]/ +b100000 ^/ +b1010100 _/ +b1100101 `/ +b1110011 a/ +b1110100 b/ +b100001 c/ +sReturning\x20(5) *1 +b1010 -1 +b1010011 .1 +b1100101 /1 +b1100011 01 +b1101111 11 +b1101110 21 +b1100100 31 +b100000 41 +sReadingCache\x20(1) 81 +b11 z2 +sHdlNone\x20(0) #3 +b0 $3 +sHdlNone\x20(0) 13 +b0 33 +b0 <3 +sHdlNone\x20(0) 34 +b0 54 +b0 >4 +sHdlNone\x20(0) 55 +b0 75 +b0 @5 +sHdlNone\x20(0) ;6 +b0 =6 +b0 F6 +b111 q +b111 s" +b111 q) +b111 `. +b111 O3 +b111 Q4 +b111 S5 +b10010111100011000 e5 +b10011111100000000 h5 +b111 i5 +b10011111100001000 k5 +b10011111100010000 n5 +b10011111100011000 q5 +b11101 s5 +b111 Y6 +b10010111100011000 k6 +b10011111100000000 n6 +b111 o6 +b10011111100001000 q6 +b10011111100010000 t6 +b10011111100011000 w6 +b11101 y6 +#79000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#79500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlSome\x20(1) ? +b10010111100000000 @ +b110 A +sHdlSome\x20(1) J +sHdlSome\x20(1) A" +b10010111100000000 B" +b110 C" +sHdlSome\x20(1) L" +sHdlSome\x20(1) C# +b10010111100000000 D# +b110 E# +sHdlSome\x20(1) N# +sHdlSome\x20(1) A* +b10010111100000000 B* +b110 C* +sHdlSome\x20(1) L* +sReturning\x20(5) a+ +sHdlSome\x20(1) b+ +sReturning\x20(5) I, +b1010100 L, +b1100101 M, +b1110011 N, +b1110100 O, +b100000 P, +b1100100 Q, +b1100001 R, +b1110100 S, +sReadingCache\x20(1) W, +b10011111100000000 '. +b111 (. +b0 -. +sHdlNone\x20(0) /. +b0 2. +b0 3. +sHdlNone\x20(0) 7. +b1 =. +sHdlSome\x20(1) 0/ +b10010111100000000 1/ +b110 2/ +sHdlSome\x20(1) ;/ +sReturning\x20(5) P0 +sHdlSome\x20(1) Q0 +sReturning\x20(5) 81 +b1010100 ;1 +b1100101 <1 +b1110011 =1 +b1110100 >1 +b100000 ?1 +b1100100 @1 +b1100001 A1 +b1110100 B1 +sReadingCache\x20(1) F1 +b10011111100000000 t2 +b111 u2 +b0 z2 +sHdlNone\x20(0) |2 +b0 !3 +b0 "3 +sHdlNone\x20(0) &3 +b1 ,3 +sHdlSome\x20(1) }3 +b10010111100000000 ~3 +b110 !4 +sHdlSome\x20(1) *4 +sHdlSome\x20(1) !5 +b10010111100000000 "5 +b110 #5 +sHdlSome\x20(1) ,5 +sSuccess\x20(0) b +b11111111 e +b11111111 f +b11111111 g +b11111111 h +b11111111 i +b11111111 j +b11111111 k +b11111111 l +b111 p +b0 t +b100 "" +sSuccess\x20(0) d" +b11111111 g" +b11111111 h" +b11111111 i" +b11111111 j" +b11111111 k" +b11111111 l" +b11111111 m" +b11111111 n" +b111 r" +b0 v" +b100 $# +sSuccess\x20(0) b) +b11111111 e) +b11111111 f) +b11111111 g) +b11111111 h) +b11111111 i) +b11111111 j) +b11111111 k) +b11111111 l) +b111 p) +b0 t) +b100 "* +sSuccess\x20(0) Q. +b11111111 T. +b11111111 U. +b11111111 V. +b11111111 W. +b11111111 X. +b11111111 Y. +b11111111 Z. +b11111111 [. +b111 _. +b0 c. +b100 o. +sSuccess\x20(0) @3 +b11111111 C3 +b11111111 D3 +b11111111 E3 +b11111111 F3 +b11111111 G3 +b11111111 H3 +b11111111 I3 +b11111111 J3 +b111 N3 +b0 R3 +b100 ^3 +sSuccess\x20(0) B4 +b11111111 E4 +b11111111 F4 +b11111111 G4 +b11111111 H4 +b11111111 I4 +b11111111 J4 +b11111111 K4 +b11111111 L4 +b111 P4 +b0 T4 +b100 `4 +sSuccess\x20(0) D5 +b11111111 G5 +b11111111 H5 +b11111111 I5 +b11111111 J5 +b11111111 K5 +b11111111 L5 +b11111111 M5 +b11111111 N5 +b111 R5 +b0 V5 +b100 b5 +b10011111100000000 e5 +b111 f5 +b10011111100001000 h5 +b10011111100010000 k5 +b10011111100011000 n5 +b11100 p5 +b0 q5 +b0 r5 +b0 s5 +b100 76 +sSuccess\x20(0) J6 +b11111111 M6 +b11111111 N6 +b11111111 O6 +b11111111 P6 +b11111111 Q6 +b11111111 R6 +b11111111 S6 +b11111111 T6 +b111 X6 +b0 \6 +b100 h6 +b10011111100000000 k6 +b111 l6 +b10011111100001000 n6 +b10011111100010000 q6 +b10011111100011000 t6 +b11100 v6 +b0 w6 +b0 x6 +b0 y6 +b100 =7 +#80000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#80500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlNone\x20(0) ? +b0 @ +b0 A +sHdlNone\x20(0) J +sHdlNone\x20(0) A" +b0 B" +b0 C" +sHdlNone\x20(0) L" +sHdlNone\x20(0) C# +b0 D# +b0 E# +sHdlNone\x20(0) N# +sHdlNone\x20(0) A* +b0 B* +b0 C* +sHdlNone\x20(0) L* +b1000 R* +b0 U* +b0 V* +b0 W* +b0 X* +b0 Y* +b0 Z* +b0 [* +b0 \* +b0 ]* +b0 ^* +b0 _* +b0 `* +b0 a* +b0 b* +b0 c* +b0 d* +b0 e* +b0 f* +b0 g* +b0 h* +b0 i* +b0 j* +b0 k* +b0 l* +b0 m* +b0 n* +b0 o* +b0 p* +b0 q* +b0 r* +b0 s* +b0 t* +sHdlNone\x20(0) u* +b0 v* +1x* +b11111111 y* +b11111111 z* +b11111111 {* +b11111111 |* +b11111111 }* +b11111111 ~* +b11111111 !+ +b11111111 "+ +1>+ +1?+ +1@+ +1A+ +1B+ +1C+ +1D+ +1E+ +1^+ +b10011111100000000 _+ +b111 `+ +sCacheMiss\x20(2) a+ +sHdlNone\x20(0) b+ +b1000000000000 m+ +b1000 n+ +sReturning\x20(5) o+ +b1010100 r+ +b1100101 s+ +b1110011 t+ +b1110100 u+ +b100000 v+ +b1100100 w+ +b1100001 x+ +b1110100 y+ +b1000000010000 {+ +b1001 |+ +b1101110 ", +b1100111 #, +b101110 $, +b101110 %, +b101110 &, +b1010 ', +b1010100 (, +b1100101 ), +b1000000100000 +, +b1010 ,, +b1010 0, +b1010011 1, +b1100101 2, +b1100011 3, +b1101111 4, +b1101110 5, +b1100100 6, +b100000 7, +b1000000000000 9, +b1011 :, +b1010100 >, +b1100101 ?, +b1110011 @, +b1110100 A, +b100000 B, +b1100100 C, +b1100001 D, +b1110100 E, +b1000000010000 U, +b1100 V, +sStart\x20(0) W, +b1000000100000 c, +b1101 d, +b10000000000000 q, +b1110 r, +b1111 "- +b10000 0- +b10001 >- +b1 -. +sHdlNone\x20(0) 0/ +b0 1/ +b0 2/ +sHdlNone\x20(0) ;/ +b1000 A/ +b0 D/ +b0 E/ +b0 F/ +b0 G/ +b0 H/ +b0 I/ +b0 J/ +b0 K/ +b0 L/ +b0 M/ +b0 N/ +b0 O/ +b0 P/ +b0 Q/ +b0 R/ +b0 S/ +b0 T/ +b0 U/ +b0 V/ +b0 W/ +b0 X/ +b0 Y/ +b0 Z/ +b0 [/ +b0 \/ +b0 ]/ +b0 ^/ +b0 _/ +b0 `/ +b0 a/ +b0 b/ +b0 c/ +sHdlNone\x20(0) d/ +b0 e/ +1g/ +b11111111 h/ +b11111111 i/ +b11111111 j/ +b11111111 k/ +b11111111 l/ +b11111111 m/ +b11111111 n/ +b11111111 o/ +1-0 +1.0 +1/0 +100 +110 +120 +130 +140 +1M0 +b10011111100000000 N0 +b111 O0 +sCacheMiss\x20(2) P0 +sHdlNone\x20(0) Q0 +b1000000000000 \0 +b1000 ]0 +sReturning\x20(5) ^0 +b1010100 a0 +b1100101 b0 +b1110011 c0 +b1110100 d0 +b100000 e0 +b1100100 f0 +b1100001 g0 +b1110100 h0 +b1000000010000 j0 +b1001 k0 +b1101110 o0 +b1100111 p0 +b101110 q0 +b101110 r0 +b101110 s0 +b1010 t0 +b1010100 u0 +b1100101 v0 +b1000000100000 x0 +b1010 y0 +b1010 }0 +b1010011 ~0 +b1100101 !1 +b1100011 "1 +b1101111 #1 +b1101110 $1 +b1100100 %1 +b100000 &1 +b1000000000000 (1 +b1011 )1 +b1010100 -1 +b1100101 .1 +b1110011 /1 +b1110100 01 +b100000 11 +b1100100 21 +b1100001 31 +b1110100 41 +b1000000010000 D1 +b1100 E1 +sStart\x20(0) F1 +b1000000100000 R1 +b1101 S1 +b10000000000000 `1 +b1110 a1 +b1111 o1 +b10000 }1 +b10001 -2 +b1 z2 +sHdlNone\x20(0) }3 +b0 ~3 +b0 !4 +sHdlNone\x20(0) *4 +sHdlNone\x20(0) !5 +b0 "5 +b0 #5 +sHdlNone\x20(0) ,5 +sError\x20(1) b +b0 e +b0 f +b0 g +b0 h +b0 i +b0 j +b0 k +b0 l +b0 s +b11 "" +sError\x20(1) d" +b0 g" +b0 h" +b0 i" +b0 j" +b0 k" +b0 l" +b0 m" +b0 n" +b0 u" +b11 $# +sError\x20(1) b) +b0 e) +b0 f) +b0 g) +b0 h) +b0 i) +b0 j) +b0 k) +b0 l) +b0 s) +b11 "* +sError\x20(1) Q. +b0 T. +b0 U. +b0 V. +b0 W. +b0 X. +b0 Y. +b0 Z. +b0 [. +b0 b. +b11 o. +sError\x20(1) @3 +b0 C3 +b0 D3 +b0 E3 +b0 F3 +b0 G3 +b0 H3 +b0 I3 +b0 J3 +b0 Q3 +b11 ^3 +sError\x20(1) B4 +b0 E4 +b0 F4 +b0 G4 +b0 H4 +b0 I4 +b0 J4 +b0 K4 +b0 L4 +b0 S4 +b11 `4 +sError\x20(1) D5 +b0 G5 +b0 H5 +b0 I5 +b0 J5 +b0 K5 +b0 L5 +b0 M5 +b0 N5 +b0 U5 +b11 b5 +b10011111100001000 e5 +b10011111100010000 h5 +b10011111100011000 k5 +b11011 m5 +b0 n5 +b0 o5 +b0 p5 +b11 76 +sError\x20(1) J6 +b0 M6 +b0 N6 +b0 O6 +b0 P6 +b0 Q6 +b0 R6 +b0 S6 +b0 T6 +b0 [6 +b11 h6 +b10011111100001000 k6 +b10011111100010000 n6 +b10011111100011000 q6 +b11011 s6 +b0 t6 +b0 u6 +b0 v6 +b11 =7 +#81000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#81500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b0 R* +b1010100 U* +b1100101 V* +b1110011 W* +b1110100 X* +b100000 Y* +b1100100 Z* +b1100001 [* +b1110100 \* +b1100001 ]* +b101100 ^* +b100000 _* +b1110100 `* +b1100101 a* +b1110011 b* +b1110100 c* +b1101001 d* +b1101110 e* +b1100111 f* +b101110 g* +b101110 h* +b101110 i* +b1010 j* +b1010100 k* +b1100101 l* +b1110011 m* +b1110100 n* +b100000 o* +b1010100 p* +b1100101 q* +b1110011 r* +b1110100 s* +b100001 t* +sHdlSome\x20(1) u* +b1000 v* +0x* +b0 y* +b0 z* +b0 {* +b0 |* +b0 }* +b0 ~* +b0 !+ +b0 "+ +0>+ +0?+ +0@+ +0A+ +0B+ +0C+ +0D+ +0E+ +0^+ +sReadingCache\x20(1) W, +b10 -. +sHdlSome\x20(1) /. +b0 A/ +b1010100 D/ +b1100101 E/ +b1110011 F/ +b1110100 G/ +b100000 H/ +b1100100 I/ +b1100001 J/ +b1110100 K/ +b1100001 L/ +b101100 M/ +b100000 N/ +b1110100 O/ +b1100101 P/ +b1110011 Q/ +b1110100 R/ +b1101001 S/ +b1101110 T/ +b1100111 U/ +b101110 V/ +b101110 W/ +b101110 X/ +b1010 Y/ +b1010100 Z/ +b1100101 [/ +b1110011 \/ +b1110100 ]/ +b100000 ^/ +b1010100 _/ +b1100101 `/ +b1110011 a/ +b1110100 b/ +b100001 c/ +sHdlSome\x20(1) d/ +b1000 e/ +0g/ +b0 h/ +b0 i/ +b0 j/ +b0 k/ +b0 l/ +b0 m/ +b0 n/ +b0 o/ +0-0 +0.0 +0/0 +000 +010 +020 +030 +040 +0M0 +sReadingCache\x20(1) F1 +b10 z2 +sHdlSome\x20(1) |2 +b0 r +b10 "" +b0 t" +b10 $# +b0 r) +b10 "* +b0 a. +b10 o. +b0 P3 +b10 ^3 +b0 R4 +b10 `4 +b0 T5 +b10 b5 +b10011111100010000 e5 +b10011111100011000 h5 +b11010 j5 +b0 k5 +b0 l5 +b0 m5 +b10 76 +b0 Z6 +b10 h6 +b10011111100010000 k6 +b10011111100011000 n6 +b11010 p6 +b0 q6 +b0 r6 +b0 s6 +b10 =7 +#82000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#82500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b1 R* +b1010 U* +b1010011 V* +b1100101 W* +b1100011 X* +b1101111 Y* +b1101110 Z* +b1100100 [* +b100000 \* +b1000011 ]* +b1100001 ^* +b1100011 _* +b1101000 `* +b100000 b* +b1001100 c* +b1100101 f* +b1010 g* +b1010100 h* +b1100101 i* +b1110011 j* +b1110100 k* +b1101001 l* +b1101110 m* +b1100111 n* +b101110 o* +b101110 p* +b101110 q* +b101110 r* +b101110 s* +b1010 t* +sReturning\x20(5) W, +b1101110 Z, +b1100111 [, +b101110 \, +b101110 ], +b101110 ^, +b1010 _, +b1010100 `, +b1100101 a, +sReadingCache\x20(1) e, +b11 -. +b1 A/ +b1010 D/ +b1010011 E/ +b1100101 F/ +b1100011 G/ +b1101111 H/ +b1101110 I/ +b1100100 J/ +b100000 K/ +b1000011 L/ +b1100001 M/ +b1100011 N/ +b1101000 O/ +b100000 Q/ +b1001100 R/ +b1100101 U/ +b1010 V/ +b1010100 W/ +b1100101 X/ +b1110011 Y/ +b1110100 Z/ +b1101001 [/ +b1101110 \/ +b1100111 ]/ +b101110 ^/ +b101110 _/ +b101110 `/ +b101110 a/ +b101110 b/ +b1010 c/ +sReturning\x20(5) F1 +b1101110 I1 +b1100111 J1 +b101110 K1 +b101110 L1 +b101110 M1 +b1010 N1 +b1010100 O1 +b1100101 P1 +sReadingCache\x20(1) T1 +b11 z2 +sHdlNone\x20(0) a +sSuccess\x20(0) b +b0 q +b1 "" +sHdlNone\x20(0) c" +sSuccess\x20(0) d" +b0 s" +b1 $# +sHdlNone\x20(0) a) +sSuccess\x20(0) b) +b0 q) +b1 "* +sHdlNone\x20(0) P. +sSuccess\x20(0) Q. +b0 `. +b1 o. +sHdlNone\x20(0) ?3 +sSuccess\x20(0) @3 +b0 O3 +b1 ^3 +sHdlNone\x20(0) A4 +sSuccess\x20(0) B4 +b0 Q4 +b1 `4 +sHdlNone\x20(0) C5 +sSuccess\x20(0) D5 +b0 S5 +b1 b5 +b10011111100011000 e5 +b11001 g5 +b0 h5 +b0 i5 +b0 j5 +b1 76 +sHdlNone\x20(0) I6 +sSuccess\x20(0) J6 +b0 Y6 +b1 h6 +b10011111100011000 k6 +b11001 m6 +b0 n6 +b0 o6 +b0 p6 +b1 =7 +#83000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#83500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b0 R* +b1010100 U* +b1100101 V* +b1110011 W* +b1110100 X* +b100000 Y* +b1100100 Z* +b1100001 [* +b1110100 \* +b1100001 ]* +b101100 ^* +b100000 _* +b1110100 `* +b1110011 b* +b1110100 c* +b1100111 f* +b101110 g* +b101110 h* +b101110 i* +b1010 j* +b1010100 k* +b1100101 l* +b1110011 m* +b1110100 n* +b100000 o* +b1010100 p* +b1100101 q* +b1110011 r* +b1110100 s* +b100001 t* +sReturning\x20(5) e, +b1010 h, +b1010011 i, +b1100101 j, +b1100011 k, +b1101111 l, +b1101110 m, +b1100100 n, +b100000 o, +sReadingCache\x20(1) s, +b0 A/ +b1010100 D/ +b1100101 E/ +b1110011 F/ +b1110100 G/ +b100000 H/ +b1100100 I/ +b1100001 J/ +b1110100 K/ +b1100001 L/ +b101100 M/ +b100000 N/ +b1110100 O/ +b1110011 Q/ +b1110100 R/ +b1100111 U/ +b101110 V/ +b101110 W/ +b101110 X/ +b1010 Y/ +b1010100 Z/ +b1100101 [/ +b1110011 \/ +b1110100 ]/ +b100000 ^/ +b1010100 _/ +b1100101 `/ +b1110011 a/ +b1110100 b/ +b100001 c/ +sReturning\x20(5) T1 +b1010 W1 +b1010011 X1 +b1100101 Y1 +b1100011 Z1 +b1101111 [1 +b1101110 \1 +b1100100 ]1 +b100000 ^1 +sReadingCache\x20(1) b1 +b11000 g5 +b11000 m6 +#84000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#84500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlSome\x20(1) S +b10000000000000 U +b1110 ^ +sHdlSome\x20(1) U" +b10000000000000 W" +b1110 `" +sHdlSome\x20(1) S) +b10000000000000 U) +b1110 ^) +sCacheMiss\x20(2) s, +sReadingCache\x20(1) #- +b10000000000000 2. +b1110 3. +sHdlSome\x20(1) 4. +sHdlSome\x20(1) 7. +b10 =. +sHdlSome\x20(1) B. +b10000000000000 D. +b1110 M. +sCacheMiss\x20(2) b1 +sReadingCache\x20(1) p1 +b10000000000000 !3 +b1110 "3 +sHdlSome\x20(1) #3 +sHdlSome\x20(1) &3 +b10 ,3 +sHdlSome\x20(1) 13 +b10000000000000 33 +b1110 <3 +sHdlSome\x20(1) 34 +b10000000000000 54 +b1110 >4 +sHdlSome\x20(1) 55 +b10000000000000 75 +b1110 @5 +sHdlSome\x20(1) ;6 +b10000000000000 =6 +b1110 F6 +b10111 g5 +b10111 m6 +#85000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#85500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10000000001000 U +b10000000001000 W" +b10000000001000 U) +sCacheMiss\x20(2) #- +sReadingCache\x20(1) 1- +b1 5. +b10000000001000 D. +sCacheMiss\x20(2) p1 +sReadingCache\x20(1) ~1 +b1 $3 +b10000000001000 33 +b10000000001000 54 +b10000000001000 75 +b10000000001000 =6 +b1110 q +b10 "" +b1110 s" +b10 $# +b1110 q) +b10 "* +b1110 `. +b10 o. +b1110 O3 +b10 ^3 +b1110 Q4 +b10 `4 +b1110 S5 +b10 b5 +b10110 g5 +b10000000000000 h5 +b1110 i5 +b100 j5 +b10 76 +b1110 Y6 +b10 h6 +b10110 m6 +b10000000000000 n6 +b1110 o6 +b100 p6 +b10 =7 +#86000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#86500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10000000010000 U +b10000000010000 W" +b10000000010000 U) +sCacheMiss\x20(2) 1- +sReadingCache\x20(1) ?- +b10 5. +b10000000010000 D. +sCacheMiss\x20(2) ~1 +sReadingCache\x20(1) .2 +b10 $3 +b10000000010000 33 +b10000000010000 54 +b10000000010000 75 +b10000000010000 =6 +b1110 r +b11 "" +b1110 t" +b11 $# +b1110 r) +b11 "* +b1110 a. +b11 o. +b1110 P3 +b11 ^3 +b1110 R4 +b11 `4 +b1110 T5 +b11 b5 +b10101 g5 +b11 j5 +b10000000001000 k5 +b1110 l5 +b100 m5 +b11 76 +b1110 Z6 +b11 h6 +b10101 m6 +b11 p6 +b10000000001000 q6 +b1110 r6 +b100 s6 +b11 =7 +#87000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#87500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +b10000000011000 U +b10000000011000 W" +b10000000011000 U) +sCacheMiss\x20(2) ?- +sReadingCache\x20(1) M- +b11 5. +b10000000011000 D. +sCacheMiss\x20(2) .2 +sReadingCache\x20(1) <2 +b11 $3 +b10000000011000 33 +b10000000011000 54 +b10000000011000 75 +b10000000011000 =6 +b1110 s +b100 "" +b1110 u" +b100 $# +b1110 s) +b100 "* +b1110 b. +b100 o. +b1110 Q3 +b100 ^3 +b1110 S4 +b100 `4 +b1110 U5 +b100 b5 +b10100 g5 +b10 j5 +b11 m5 +b10000000010000 n5 +b1110 o5 +b100 p5 +b100 76 +b1110 [6 +b100 h6 +b10100 m6 +b10 p6 +b11 s6 +b10000000010000 t6 +b1110 u6 +b100 v6 +b100 =7 +#88000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#88500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sHdlNone\x20(0) S +b0 U +b0 ^ +sHdlNone\x20(0) U" +b0 W" +b0 `" +sHdlNone\x20(0) S) +b0 U) +b0 ^) +sCacheMiss\x20(2) M- +sReadingCache\x20(1) [- +sHdlNone\x20(0) 4. +b0 5. +sHdlNone\x20(0) B. +b0 D. +b0 M. +sCacheMiss\x20(2) <2 +sReadingCache\x20(1) J2 +sHdlNone\x20(0) #3 +b0 $3 +sHdlNone\x20(0) 13 +b0 33 +b0 <3 +sHdlNone\x20(0) 34 +b0 54 +b0 >4 +sHdlNone\x20(0) 55 +b0 75 +b0 @5 +sHdlNone\x20(0) ;6 +b0 =6 +b0 F6 +b1110 t +b101 "" +b1110 v" +b101 $# +b1110 t) +b101 "* +b1110 c. +b101 o. +b1110 R3 +b101 ^3 +b1110 T4 +b101 `4 +b1110 V5 +b101 b5 +b10011 g5 +b1 j5 +b10 m5 +b11 p5 +b10000000011000 q5 +b1110 r5 +b100 s5 +b101 76 +b1110 \6 +b101 h6 +b10011 m6 +b1 p6 +b10 s6 +b11 v6 +b10000000011000 w6 +b1110 x6 +b100 y6 +b101 =7 +#89000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#89500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sCacheMiss\x20(2) [- +sReadingCache\x20(1) i- +sCacheMiss\x20(2) J2 +sReadingCache\x20(1) X2 +b10010 g5 +b0 j5 +b1 m5 +b10 p5 +b11 s5 +b10010 m6 +b0 p6 +b1 s6 +b10 v6 +b11 y6 +#90000000 +0! +0Q +0S" +0Q) +0@. +0/3 +014 +035 +096 +#90500000 +1! +1Q +1S" +1Q) +1@. +1/3 +114 +135 +196 +sCacheMiss\x20(2) i- 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MemoryOperationErrorKind, MemoryOperationFinish, MemoryOperationFinishKind, + MemoryOperationKind, MemoryOperationStart, fetch, + }, + next_pc::{NextPcToFetchInterface, NextPcToFetchInterfaceInner}, + unit::UnitKind, + util::array_vec::ArrayVec, +}; +use fayalite::{ + prelude::*, + sim::vcd::VcdWriterDecls, + util::{DebugAsDisplay, RcWriter}, +}; +use std::{cell::RefCell, collections::VecDeque, fmt, num::NonZeroUsize}; + +struct Random { + index: u64, +} + +impl Random { + fn next(&mut self) -> u64 { + let index = self.index; + self.index = self.index.wrapping_add(1); + // make a pseudo-random number deterministically based on index + index + .wrapping_add(1) + .wrapping_mul(0x18C49126EABE7A0D) // random prime + .rotate_left(32) + .wrapping_mul(0x92B38C197608A6B) // random prime + .rotate_right(60) + } +} + +const MEMORY_QUEUE_SIZE: usize = 16; + +#[hdl] +struct MemoryQueueEntry { + addr: UInt<64>, + fetch_block_id: UInt<8>, + cycles_left: UInt<8>, +} + +impl MemoryQueueEntry { + #[hdl] + fn default_sim(self) -> SimValue { + #[hdl(sim)] + Self { + addr: 0u64, + fetch_block_id: 0u8, + cycles_left: 0u8, + } + } + fn get_next_delay(random: &mut Random) -> u8 { + if random.next() % 32 == 0 { 30 } else { 5 } + } +} + +const MEMORY_DATA: &str = "Test data, testing...\nTest Test!\nSecond Cache Line\nTesting.....\n"; +const MEMORY_START: u64 = 0x1000; +const MEMORY_RANGE2: std::ops::Range = 0x2000..0x3000; +const MEMORY_ERROR_RANGE: std::ops::Range = 0x10F00..0x20F00; +const MEMORY_ERROR_STEP: u64 = 0x1000; + +fn read_memory(start: u64, len: usize) -> Option<&'static [u8]> { + if MEMORY_ERROR_RANGE.contains(&start) { + let start = start - MEMORY_ERROR_RANGE.start; + let fail_at = start / MEMORY_ERROR_STEP; + let offset = start % MEMORY_ERROR_STEP; + return if offset < fail_at { + [0xFFu8; MEMORY_DATA.len()].get(..len) + } else { + None + }; + } + if MEMORY_RANGE2.contains(&start) { + return [0xF2u8; MEMORY_DATA.len()].get(..len); + } + MEMORY_DATA + .as_bytes() + .get(start.checked_sub(MEMORY_START)?.try_into().ok()?..)? + .get(..len) +} + +#[hdl_module(extern)] +fn mock_memory(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let memory_interface: MemoryInterface> = + m.input(MemoryInterface[config]); + #[hdl] + let queue_debug: ArrayVec> = m.output(); + m.register_clock_for_past(cd.clk); + m.extern_module_simulation_fn( + (cd, memory_interface, queue_debug), + |(cd, memory_interface, queue_debug), mut sim| async move { + // intentionally have a different sequence each time we're reset + let random = RefCell::new(Random { index: 0 }); + sim.resettable( + cd, + async |mut sim| { + #[hdl] + let MemoryInterface::<_> { + start, + finish, + next_fetch_block_ids, + config: _, + } = memory_interface; + sim.write(start.ready, false).await; + sim.write(finish.data, finish.ty().data.HdlNone()).await; + sim.write(next_fetch_block_ids, next_fetch_block_ids.ty().HdlNone()) + .await; + sim.write( + queue_debug, + queue_debug.ty().new_sim(MemoryQueueEntry.default_sim()), + ) + .await; + }, + |sim, ()| run_fn(cd, memory_interface, queue_debug, &random, sim), + ) + .await; + }, + ); + #[hdl] + async fn run_fn( + cd: Expr, + memory_interface: Expr>>, + queue_debug: Expr>>, + random: &RefCell, + mut sim: ExternModuleSimulationState, + ) { + let mut random = random.borrow_mut(); + let config = memory_interface.config.ty(); + let finish_data_ty = memory_interface.finish.data.ty(); + let next_fetch_block_ids_ty = memory_interface.next_fetch_block_ids.ty(); + let mut queue: VecDeque> = VecDeque::new(); + loop { + for entry in &mut queue { + entry.cycles_left = entry.cycles_left.as_int().saturating_sub(1).to_sim_value(); + } + let sim_queue = queue_debug + .ty() + .from_iter_sim(MemoryQueueEntry.default_sim(), &queue) + .ok() + .expect("queue is known to be small enough"); + sim.write(queue_debug, sim_queue).await; + sim.write_bool( + memory_interface.start.ready, + queue.len() < MEMORY_QUEUE_SIZE && random.next() % 32 != 0, + ) + .await; + sim.write( + memory_interface.next_fetch_block_ids, + #[hdl(sim)] + next_fetch_block_ids_ty.HdlSome( + next_fetch_block_ids_ty + .HdlSome + .from_iter_sim(0u8, queue.iter().map(|entry| &entry.fetch_block_id)) + .ok() + .expect("queue is known to be small enough"), + ), + ) + .await; + let finish_data = if let Some(entry) = queue + .front() + .filter(|entry| entry.cycles_left.as_int() == 0) + { + #[hdl(sim)] + let MemoryQueueEntry { + addr, + fetch_block_id: _, + cycles_left: _, + } = entry; + let addr = addr.as_int(); + let mut read_data = + repeat(0u8, finish_data_ty.HdlSome.read_data.len()).to_sim_value(); + let kind = if let Some(data) = read_memory(addr, read_data.len()) { + for (l, r) in read_data.iter_mut().zip(data) { + *l = r.to_sim_value(); + } + #[hdl(sim)] + MemoryOperationFinishKind.Success( + #[hdl(sim)] + MemoryOperationKind.Read(), + ) + } else { + #[hdl(sim)] + MemoryOperationFinishKind.Error( + #[hdl(sim)] + MemoryOperationErrorKind.Generic(), + ) + }; + #[hdl(sim)] + finish_data_ty.HdlSome( + #[hdl(sim)] + MemoryOperationFinish::<_> { + kind, + read_data, + config, + }, + ) + } else { + #[hdl(sim)] + finish_data_ty.HdlNone() + }; + sim.write(memory_interface.finish.data, &finish_data).await; + sim.wait_for_clock_edge(cd.clk).await; + println!( + "Dump mock memory queue: {:#?}", + Vec::from_iter(queue.iter().map(|v| { + DebugAsDisplay(format!( + "fid={:#x} addr={:#x}", + v.fetch_block_id.as_int(), + v.addr.as_int(), + )) + })) + ); + if sim + .read_past_bool(memory_interface.start.ready, cd.clk) + .await + { + #[hdl(sim)] + if let HdlSome(memory_operation_start) = + sim.read_past(memory_interface.start.data, cd.clk).await + { + #[hdl(sim)] + let MemoryOperationStart::<_> { + kind, + addr, + write_data: _, + fetch_block_id, + config: _, + } = memory_operation_start; + #[hdl(sim)] + match kind { + MemoryOperationKind::Read => {} + MemoryOperationKind::Write => unreachable!(), + } + let entry = #[hdl(sim)] + MemoryQueueEntry { + addr, + fetch_block_id, + cycles_left: MemoryQueueEntry::get_next_delay(&mut random), + }; + println!("mock memory start: {entry:#?}"); + queue.push_back(entry); + } + } + if sim + .read_past_bool(memory_interface.finish.ready, cd.clk) + .await + { + #[hdl(sim)] + if let HdlSome(finish_data) = finish_data { + let Some(entry) = queue.pop_front() else { + unreachable!(); + }; + #[hdl(sim)] + let MemoryOperationFinish::<_> { + kind, + read_data, + config: _, + } = finish_data; + let kind = #[hdl(sim)] + match kind { + MemoryOperationFinishKind::Error(_) => Err(()), + MemoryOperationFinishKind::Success(_) => Ok(()), + }; + println!( + "mock memory finish: kind={kind:?} read_data={read_data:?} {entry:#?}" + ); + } + } + } + } +} + +#[hdl_module] +fn dut(config: PhantomConst) { + #[hdl] + let cd: ClockDomain = m.input(); + #[hdl] + let from_next_pc: NextPcToFetchInterface> = + m.input(NextPcToFetchInterface[config]); + #[hdl] + let to_decode: FetchToDecodeInterface> = + m.output(FetchToDecodeInterface[config]); + #[hdl] + let fetch = instance(fetch(config)); + #[hdl] + let fetch { + cd: fetch_cd, + memory_interface: fetch_memory_interface, + from_next_pc: fetch_from_next_pc, + to_decode: fetch_to_decode, + } = fetch; + connect(fetch_cd, cd); + connect(fetch_from_next_pc, from_next_pc); + connect(to_decode, fetch_to_decode); + #[hdl] + let mock_memory = instance(mock_memory(config)); + #[hdl] + let mock_memory { + cd: mock_memory_cd, + memory_interface: mock_memory_interface, + queue_debug: _, + } = mock_memory; + connect(mock_memory_cd, cd); + connect(mock_memory_interface, fetch_memory_interface); +} + +#[derive(Clone)] +struct FetchTestOperation { + start_pc: u64, + fetch_block_id: u8, + fetch_block_data: [u8; FETCH_WIDTH_IN_BYTES], + error: Option>, +} + +impl PartialEq for FetchTestOperation { + #[hdl] + fn eq(&self, other: &Self) -> bool { + let Self { + start_pc, + fetch_block_id, + fetch_block_data, + ref error, + } = *self; + if let Some(error) = error { + #[hdl(sim)] + match error { + MemoryOperationErrorKind::Generic => {} + } + } + start_pc == other.start_pc + && fetch_block_id == other.fetch_block_id + && fetch_block_data == other.fetch_block_data + && error.is_some() == other.error.is_some() + } +} + +impl fmt::Debug for FetchTestOperation { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + let Self { + start_pc, + fetch_block_id, + fetch_block_data, + error, + } = self; + let mut debug_struct = f.debug_struct("FetchTestOperation"); + debug_struct.field("start_pc", &format_args!("{start_pc:#x}")); + debug_struct.field("fetch_block_id", &format_args!("{fetch_block_id:#x}")); + if fetch_block_data.iter().all(|v| *v == fetch_block_data[0]) { + debug_struct.field( + "fetch_block_data", + &format_args!( + "[b'{}'; {FETCH_WIDTH_IN_BYTES}]", + fetch_block_data[0].escape_ascii(), + ), + ); + } else { + debug_struct.field( + "fetch_block_data", + &format_args!("b\"{}\"", fetch_block_data.escape_ascii()), + ); + } + debug_struct.field("error", error).finish() + } +} + +const LOG2_FETCH_WIDTH_IN_BYTES: u8 = 3; +const FETCH_WIDTH_IN_BYTES: usize = 1 << LOG2_FETCH_WIDTH_IN_BYTES; +const LOG2_CACHE_LINE_SIZE_IN_BYTES: u8 = 5; +const CACHE_LINE_SIZE_IN_BYTES: usize = 1 << LOG2_CACHE_LINE_SIZE_IN_BYTES; + +// needs to be a multiple of the cache line size +const _: [(); CACHE_LINE_SIZE_IN_BYTES * 2] = [(); MEMORY_DATA.len()]; + +fn fetch_test_operations() -> Vec { + #[track_caller] + fn mem_data(r: std::ops::RangeFrom) -> [u8; FETCH_WIDTH_IN_BYTES] { + *MEMORY_DATA[r] + .as_bytes() + .first_chunk() + .expect("start should be in-range") + } + #[hdl] + fn generic_error() -> SimValue { + #[hdl(sim)] + MemoryOperationErrorKind.Generic() + } + let mut last_fetch_block_id = 0u8.wrapping_sub(1); + macro_rules! op { + { + $($field:ident: $value:expr,)* + } => { + FetchTestOperation { + fetch_block_id: { + last_fetch_block_id = last_fetch_block_id.wrapping_add(1); + last_fetch_block_id + }, + $($field: $value,)* + } + }; + } + vec![ + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1010, + fetch_block_data: mem_data(0x10..), + error: None, + }, + op! { + start_pc: 0x1020, + fetch_block_data: mem_data(0x20..), + error: None, + }, + op! { + start_pc: 0x100, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP * 2, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: MEMORY_ERROR_RANGE.start + MEMORY_ERROR_STEP * 3, + fetch_block_data: [0; _], + error: Some(generic_error()), + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1010, + fetch_block_data: mem_data(0x10..), + error: None, + }, + op! { + start_pc: 0x1020, + fetch_block_data: mem_data(0x20..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1010, + fetch_block_data: mem_data(0x10..), + error: None, + }, + op! { + start_pc: 0x1020, + fetch_block_data: mem_data(0x20..), + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: MEMORY_RANGE2.start, + fetch_block_data: [0xF2; _], + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + op! { + start_pc: 0x1000, + fetch_block_data: mem_data(0..), + error: None, + }, + ] +} + +#[test] +#[hdl] +fn test_fetch() { + let _n = SourceLocation::normalize_files_for_tests(); + let mut config = CpuConfig::new( + vec![ + UnitConfig::new(UnitKind::AluBranch), + UnitConfig::new(UnitKind::AluBranch), + ], + NonZeroUsize::new(20).unwrap(), + ); + config.fetch_width = NonZeroUsize::new(2).unwrap(); + config.log2_fetch_width_in_bytes = LOG2_FETCH_WIDTH_IN_BYTES; + config.log2_cache_line_size_in_bytes = LOG2_CACHE_LINE_SIZE_IN_BYTES; + config.log2_l1_i_cache_line_count = 4; + let m = dut(PhantomConst::new_sized(config)); + let mut sim = Simulation::new(m); + let writer = RcWriter::default(); + sim.add_trace_writer(VcdWriterDecls::new(writer.clone())); + struct DumpVcdOnDrop { + writer: Option, + } + impl Drop for DumpVcdOnDrop { + fn drop(&mut self) { + if let Some(mut writer) = self.writer.take() { + let vcd = String::from_utf8(writer.take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + } + } + } + let mut writer = DumpVcdOnDrop { + writer: Some(writer), + }; + let from_next_pc_ty = sim.io().from_next_pc.ty(); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, true); + sim.write( + sim.io().from_next_pc.cancel.data, + from_next_pc_ty.cancel.data.HdlNone(), + ); + sim.write( + sim.io().from_next_pc.fetch.data, + from_next_pc_ty.fetch.data.HdlNone(), + ); + sim.write(sim.io().to_decode.fetched.ready, true); + let operations = fetch_test_operations(); + let mut started_operations = 0; + let mut finished_operations = 0; + for cycle in 0..500 { + sim.write( + sim.io().from_next_pc.fetch.data, + if let Some(op) = operations.get(started_operations) { + #[hdl(sim)] + HdlSome( + #[hdl(sim)] + NextPcToFetchInterfaceInner { + start_pc: op.start_pc, + fetch_block_id: op.fetch_block_id, + }, + ) + } else { + #[hdl(sim)] + HdlNone() + }, + ); + sim.advance_time(SimDuration::from_nanos(500)); + if sim.read_bool(sim.io().from_next_pc.fetch.ready) { + #[hdl(sim)] + if let HdlSome(_) = sim.read(sim.io().from_next_pc.fetch.data) { + println!("started fetch: {:#?}", operations[started_operations]); + started_operations += 1; + } + } + if sim.read_bool(sim.io().to_decode.fetched.ready) { + #[hdl(sim)] + if let HdlSome(fetched) = sim.read(sim.io().to_decode.fetched.data) { + #[hdl(sim)] + let FetchToDecodeInterfaceInner::<_> { + start_pc, + fetch_block_id, + fetch_block_data, + error, + config: _, + } = &fetched; + let Some(expected_op) = operations.get(finished_operations) else { + panic!("too many finished operations: {fetched:#?}"); + }; + let op = FetchTestOperation { + start_pc: start_pc.as_int(), + fetch_block_id: fetch_block_id.as_int(), + error: #[hdl(sim)] + match error { + HdlSome(e) => Some(e.clone()), + HdlNone => None, + }, + fetch_block_data: std::array::from_fn(|i| fetch_block_data[i].as_int()), + }; + println!("finished fetch: op={op:#?}"); + assert_eq!( + op, *expected_op, + "cycle={cycle} finished_operations={finished_operations}", + ); + finished_operations += 1; + } + } + println!("clock tick: {cycle}"); + sim.write_clock(sim.io().cd.clk, true); + sim.advance_time(SimDuration::from_nanos(500)); + sim.write_clock(sim.io().cd.clk, false); + sim.write_reset(sim.io().cd.rst, false); + } + assert_eq!(finished_operations, operations.len()); + // FIXME: vcd is just whatever fetch does now, which isn't known to be correct + let vcd = String::from_utf8(writer.writer.take().unwrap().take()).unwrap(); + println!("####### VCD:\n{vcd}\n#######"); + if vcd != include_str!("expected/fetch.vcd") { + panic!(); + } +}